OpenCores
URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

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  • This comparison shows the changes necessary to convert path 
    /y80e
    from Rev 5 to Rev 6
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  •

Rev 5 → Rev 6

/trunk/asm/int_opsd.s
50,8 → 50,8
db 029h
 
 
org 0ff32h
dw 03cceh ;ff32h
org 0ff2eh
dw 0d747h, 0d633h, 03cceh ;ff2eh
dw 08421h, 0edb7h, 0ff92h, 0d610h, 09678h ;ff34h
dw 02e00h, 00100h, 0001fh, 05a44h, 05a44h ;ff3eh
dw 06900h, 02e00h, 00100h, 0001fh, 0de00h ;ff48h
77,3 → 77,4
dw 05000h, 00004h, 05000h, 00003h ;fff0h
dw 0c202h, 00002h, 0c102h, 00001h ;fff8h
 
end
/trunk/asm/180_ops.s
0,0 → 1,174
;**********************************************************************************
;* *
;* checks all z180 instructions *
;* *
;**********************************************************************************
aseg
 
org 00h
jp 100h
 
org 038h
jp (hl)
org 066h
jp (ix)
org 80h
db 00h, 01h, 2dh, 03h, 04h, 05h, 06h, 07h
db 0fh, 1eh, 02h, 3ch, 4bh, 5ah, 69h, 78h
 
org 0c0h ;pattern finish location
nop
jr 0c0h
 
org 0100h
di
ld sp, 0fffeh ;point sp at result table
xor a
ld hl, 01234h
ld de, 05678h
ld bc, 09abch
mlt sp
push af ;0044h @ fd00h
mlt hl
push hl ;03a8h @ fcfeh
mlt de
push de ;2850h @ fcfch
mlt bc
push bc ;7118h @ fcfah
push af ;0044h @ fcf8h
;
add a,1
in0 a,(080h) ;read 00h @ 0080h
push af ;0044h @ fcf6h
out0 (030h),b ;071 @ 0030h
push af ;0044h @ fcf4h
in0 a,(08ah) ;read 02h @ 008ah
push af ;0200h @ fcf2h
out0 (031h),c ;018 @ 0031h
push af ;0200h @ fcf0h
in0 b,(81h)
in0 c,(82h)
in0 d,(83h)
in0 e,(84h)
in0 h,(85h)
in0 l,(86h) ;read 06h @ 0086h
push af ;0204h @ fceeh
push bc ;012dh @ fcech
push de ;0304h @ fceah
push hl ;0506h @ fce8h
;
out0 (032h),l ;06h @ 0032h
out0 (033h),h ;05h @ 0033h
out0 (034h),a ;02h @ 0034h
out0 (035h),d ;03h @ 0035h
out0 (036h),e ;04h @ 0036h
push af ;0204h @ fce6h
;
ld a, 0a9h
tst b ;a9h & 01h = 01h
push af ;a910h @ fce4h
tst c ;a9h & 2dh = 29h
push af ;a910h @ fce2h
tst d ;a9h & 03h = 01h
push af ;a910h @ fce0h
scf
tst e ;a9h & 04h = 00h
push af ;a954h @ fcdeh
tst h ;a9h & 05h = 01h
push af ;a910h @ fcdch
ld l, 0f7h
tst l ;a9h & f7h = a1h
push af ;a990h @ fcdah
tst a ;a9h & a9h = a9h
push af ;a994h @ fcd8h
scf
ld hl, 01000h
tst (hl) ;a9h & b7h = a1h
push af ;a990h @ fcd6h
tst 056h ;a9h & 56h = 00h
push af ;a954h @ fcd4h
ld c, 08ch
scf
tstio 0aah ;a9h & 4bh = 09h
push af ;a914h @ fcd2h
;
xor a
ld hl, 02000h
ld bc, 00630h
otim ;read 71h @ 2000h
;write 71h @ 0030h
push af ;0006h @ fcd0h
push bc ;0531h @ fcceh
push hl ;2001h @ fccch
otimr ;read 18h @ 2001h
;write 18h @ 0031h
;read 06h @ 2002h
;write 06h @ 0032h
;read 05h @ 2003h
;write 05h @ 0033h
;read 02h @ 2004h
;write 02h @ 0034h
;read 03h @ 2005h
;write 03h @ 0035h
push af ;0046h @ fccah
push bc ;0036h @ fcc8h
push hl ;2006h @ fcc6h
ld b,1
otimr ;read 04h @ 2006h
;write 04h @ 0036h
push af ;0046h @ fcc4h
push bc ;0037h @ fcc2h
push hl ;2007h @ fcc0h
inc b
otim ;read aah @ 2007h
;write aah @ 0037h
push af ;0042h @ fcbeh
push bc ;0038h @ fcbch
push hl ;2008h @ fcbah
ld hl, 02007h
ld bc, 00637h
otdm ;read aah @ 2007h
;write aah @ 0037h
push af ;0002h @ fcb8h
push bc ;0536h @ fcb6h
push hl ;2006h @ fcb4h
otdmr ;read 04h @ 2006h
;write 04h @ 0036h
;read 03h @ 2005h
;write 03h @ 0035h
;read 02h @ 2004h
;write 02h @ 0034h
;read 05h @ 2003h
;write 05h @ 0033h
;read 06h @ 2002h
;write 06h @ 0032h
push af ;0042h @ fcb2h
push bc ;0031h @ fcb0h
push hl ;2001h @ fcaeh
inc b
xor 0aah
otdmr ;read 18h @ 2001h
;write 18h @ 0031h
push af ;aac6h @ fcach
push bc ;0030h @ fcaah
push hl ;2000h @ fca8h
inc b
otdm ;read 71h @ 2000h
;write 71h @ 0030h
push af ;aa42h @ fca6h
push bc ;002fh @ fca4h
push de ;0304h @ fca2h
push hl ;1fffh @ fca0h
;
ld hl, 00100h
jp 0c0h
org 01000h
db 0b7h
 
org 02000h
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah
end
/trunk/asm/180_opsd.s
0,0 → 1,24
;**********************************************************************************
;* *
;* 180_ops compare data *
;* *
;**********************************************************************************
org 030h
db 071h, 018h, 006h, 005h, 002h, 003h, 004h, 0aah
 
org 0fca0h
dw 01fffh, 00304h, 0002fh, 0aa42h ;fca0h
dw 02000h, 00030h, 0aac6h, 02001h ;fca8h
dw 00031h, 00042h, 02006h, 00536h ;fcb0h
dw 00002h, 02008h, 00038h, 00042h ;fcb8h
dw 02007h, 00037h, 00046h, 02006h ;fcc0h
dw 00036h, 00046h, 02001h, 00531h ;fcc8h
dw 00006h, 0a914h, 0a954h, 0a990h ;fcd0h
dw 0a994h, 0a990h, 0a910h, 0a954h ;fcd8h
dw 0a910h, 0a910h, 0a910h, 00204h ;fce0h
dw 00506h, 00304h, 0012dh, 00204h ;fce8h
dw 00200h, 00200h, 00044h, 00044h ;fcf0h
dw 00044h, 07118h, 02850h, 003a8h ;fcf8h
dw 00044h ;fd00h
end
/trunk/asm/int_opss.s
50,8 → 50,8
db 029h
 
 
org 0ff32h
dw 03cceh ;ff32h
org 0ff2eh
dw 0d747h, 0d633h, 03cceh ;ff2eh
dw 08421h, 0edb7h, 0ff92h, 0d610h, 09678h ;ff34h
dw 02e00h, 00100h, 0001fh, 05a44h, 05a44h ;ff3eh
dw 06900h, 02e00h, 00100h, 0001fh, 0de00h ;ff48h
77,3 → 77,4
dw 05000h, 00004h, 05000h, 00003h ;fff0h
dw 0c202h, 00002h, 0c101h, 00001h ;fff8h
 
end
/trunk/asm/ihex2vm.cpp
0,0 → 1,94
#include <iostream>
#include <fstream>
#include <iomanip>
#include <sstream>
#include <string>
#include <vector>
#include <cstring>
#include <cerrno>
 
int main(int argc, char *argv[])
{
std::istream *src = &std::cin;
std::ostream *dst = &std::cout;
std::cerr << "Intel HEX to Verilog readmemh converter" << std::endl;
if (argc > 1) {
std::fstream *file = new std::fstream(argv[1], std::ios::in);
src = file;
if (!file->is_open()) {
const char *err = strerror(errno);
std::cerr << "Failed to open input file: " << err << std::endl;
return 1;
}
if (argc > 2) {
file = new std::fstream(argv[2], std::ios::out);
dst = file;
if (!file->is_open()) {
const char *err = strerror(errno);
std::cerr << "Failed to open output file: " << err << std::endl;
return 1;
}
}
} else
std::cerr << "Usage:\n\t" << argv[0] << "[<input file> [<output file>]]\n" << "By default standard input and output are used" << std::endl;
 
std::string line;
std::vector<unsigned char> buffer;
int nline = 0;
*dst << std::uppercase;
while(std::getline(*src, line)) {
++nline;
if (line.empty())
continue;
char c[3];
std::istringstream str(line);
str >> c[0];
if (c[0] != ':') {
std::cerr << "Line " << nline << " has invalid format:\n'" << line << '\'' << std::endl;
return 1;
}
buffer.clear();
unsigned crc = 0;
str.clear();
c[2] = '\0';
c[0] = '\0';
while(str >> c[1]) {
if (c[0] == '\0') {
c[0] = c[1];
continue;
}
std::istringstream str(c);
unsigned x;
if (!(str >> std::hex >> x)) {
std::cerr << "Invalid entry size at line " << nline << std::endl;
return 1;
}
buffer.push_back((unsigned char)x);
crc += x;
c[0] = '\0';
}
std::cerr << std::endl;
if ((char)crc) {
std::cerr << "Invalid CRC of line " << nline << std::endl;
return 1;
}
if (buffer.size() < 5) {
std::cerr << "Invalid size of line " << nline << std::endl;
return 1;
}
if (buffer[3] == 1) //end of file
break;
int size = buffer[0];
int address = (buffer[1] << 8) + buffer[2];
*dst << '@' << std::hex << std::setw(4) << std::setfill('0') << address;
for(std::vector<unsigned char>::iterator i = buffer.begin() + 4, e = buffer.end()-1; i != e; ++i)
*dst << ' ' << std::hex << std::setw(2) << std::setfill('0') << unsigned(*i);
*dst << '\n';
}
 
if (dst != &std::cout)
delete dst;
if (src != &std::cin)
delete src;
return 0;
}
trunk/asm/ihex2vm.cpp Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/x-c++src \ No newline at end of property Index: trunk/asm/build.bat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/x-msdos-program Index: trunk/asm/int_ops.s =================================================================== --- trunk/asm/int_ops.s (revision 5) +++ trunk/asm/int_ops.s (revision 6) @@ -496,6 +496,19 @@ push de push hl exx + + di + nop + slp + nop + + ld hl,0d740h + ei ;int next + slp ;d633h @ ff30h + rst 00h ;not executed + + org 0d640h + di ld hl, 0100h jp 0c0h @@ -503,6 +516,13 @@ nop ;int next xor c ;d700 @ ff96h + org 0d740h + di + ld hl,0d640h + nop ;nmi next + slp ;d747h @ ff2eh + rst 00h + org 0d7feh nop ;nmi next xor h ;d800 @ ff8ch @@ -510,12 +530,12 @@ org 0d8feh nop ;int next - adc h ;d900 @ ff82h + adc a,h ;d900 @ ff82h nop org 0d9feh nop ;nmi next - sbc h ;da00 @ ff78h + sbc a,h ;da00 @ ff78h nop org 0dafeh @@ -537,3 +557,5 @@ nop ;nmi next dec hl ;de00 @ ff50h nop + + end
/trunk/rtl/aluamux.v
1,12 → 1,13
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** alu a input multiplexer module Rev 0.0 07/24/2011 **/
/** alu a input multiplexer module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module aluamux (adda_in, alua_in, alua_reg, aa_reg_out, bit_mask, daa_out, hl_reg_out,
ii_reg, int_addr, ix_reg, iy_reg, pc_reg, rr_reg, rst_addr);
ii_reg, int_addr, ix_reg, iy_reg, pc_reg, rr_reg, rst_addr, tmp_reg);
 
input [7:0] aa_reg_out; /* a register output */
input [7:0] bit_mask; /* bit mask for bit operations */
19,6 → 20,7
input [15:0] ix_reg; /* ix register output */
input [15:0] iy_reg; /* iy register output */
input [15:0] pc_reg; /* pc register output */
input [15:0] tmp_reg; /* tmp register output */
input [`ALUA_IDX:0] alua_reg; /* pipelined alu input a mux control */
output [15:0] adda_in; /* address alu a input bus */
output [15:0] alua_in; /* alu a input bus */
31,11 → 33,11
reg [15:0] alua_in;
reg [15:0] alua_in_0, alua_in_1, alua_in_2, alua_in_3, alua_in_4, alua_in_5;
reg [15:0] alua_in_6, alua_in_7, alua_in_8, alua_in_9, alua_in_10, alua_in_11;
reg [15:0] alua_in_12, alua_in_13;
reg [15:0] alua_in_12, alua_in_13, alua_in_14;
 
wire [15:0] adda_in;
wire [15:0] adda_in_0, adda_in_1, adda_in_2, adda_in_4, adda_in_5, adda_in_12;
wire [15:0] adda_in_13;
wire [15:0] adda_in_14;
 
/*****************************************************************************************/
/* */
58,6 → 60,7
alua_in_11 = 16'h0;
alua_in_12 = 16'h0;
alua_in_13 = 16'h0;
alua_in_14 = 16'h0;
if (alua_reg[`AA_ONE]) alua_in_0 = 16'h0001;
if (alua_reg[`AA_M1]) alua_in_1 = 16'hffff;
if (alua_reg[`AA_M2]) alua_in_2 = 16'hfffe;
71,15 → 74,16
if (alua_reg[`AA_II]) alua_in_10 = {8'h00, ii_reg};
if (alua_reg[`AA_RR]) alua_in_11 = {8'h00, rr_reg};
if (alua_reg[`AA_INT]) alua_in_12 = int_addr;
if (alua_reg[`AA_RST]) alua_in_13 = {8'h00, rst_addr};
if (alua_reg[`AA_TMP]) alua_in_13 = tmp_reg;
if (alua_reg[`AA_RST]) alua_in_14 = {8'h00, rst_addr};
end
 
always @ (alua_in_0 or alua_in_1 or alua_in_2 or alua_in_3 or alua_in_4 or
alua_in_5 or alua_in_6 or alua_in_7 or alua_in_8 or alua_in_9 or
alua_in_10 or alua_in_11 or alua_in_12 or alua_in_13) begin
alua_in_10 or alua_in_11 or alua_in_12 or alua_in_13 or alua_in_14) begin
alua_in = alua_in_0 | alua_in_1 | alua_in_2 | alua_in_3 | alua_in_4 |
alua_in_5 | alua_in_6 | alua_in_7 | alua_in_8 | alua_in_9 |
alua_in_10 | alua_in_11 | alua_in_12 | alua_in_13;
alua_in_10 | alua_in_11 | alua_in_12 | alua_in_13 | alua_in_14;
end
 
/*****************************************************************************************/
93,10 → 97,10
assign adda_in_4 = (alua_reg[`AA_IX]) ? ix_reg : 16'h0000;
assign adda_in_5 = (alua_reg[`AA_IY]) ? iy_reg : 16'h0000;
assign adda_in_12 = (alua_reg[`AA_INT]) ? int_addr : 16'h0000;
assign adda_in_13 = (alua_reg[`AA_RST]) ? {8'h00, rst_addr} : 16'h0000;
assign adda_in_14 = (alua_reg[`AA_RST]) ? {8'h00, rst_addr} : 16'h0000;
 
assign adda_in = adda_in_0 | adda_in_1 | adda_in_2 | adda_in_4 | adda_in_5 |
adda_in_12 | adda_in_13;
adda_in_12 | adda_in_14;
 
endmodule
 
/trunk/rtl/defines.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** define file to make the code more readable Rev 0.0 07/29/2011 **/
/** define file to make the code more readable Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
 
41,17 → 42,19
/* address bus select: add_sel */
/* */
/*****************************************************************************************/
`define ADCTL_IDX 3
`define ADD_RSTVAL 4'b0000 //Pipeline register reset value
`define ADD_PC 4'b0001 //Select address register from PC
`define ADD_HL 4'b0010 //Select address register from HL
`define ADD_SP 4'b0100 //Select address register from SP
`define ADD_ALU 4'b1000 //Select address register from ALU
`define ADCTL_IDX 4
`define ADD_RSTVAL 5'b00000 //Pipeline register reset value
`define ADD_PC 5'b00001 //Select address register from PC
`define ADD_HL 5'b00010 //Select address register from HL
`define ADD_SP 5'b00100 //Select address register from SP
`define ADD_ALU 5'b01000 //Select address register from ALU
`define ADD_ALU8 5'b10000 //Select address register from {8'h0, ALU[7:0]}
 
`define AD_PC 0 //Address from PC
`define AD_HL 1 //Address from HL
`define AD_SP 2 //Address from SP
`define AD_ALU 3 //Address from ALU
`define AD_ALU8 4 //Address from {8'h0, ALU[7:0]}
 
/*****************************************************************************************/
/* */
220,23 → 223,24
/* ALU input A control: alua_sel */
/* */
/*****************************************************************************************/
`define ALUA_IDX 13
`define ALUA_RSTVAL 14'h0000 //Reset value for pipeline controls
`define ALUA_ZER 14'h0000 //Select 16'h0000 (default)
`define ALUA_ONE 14'h0001 //Select 16'h0001
`define ALUA_M1 14'h0002 //Select 16'hFFFF
`define ALUA_M2 14'h0004 //Select 16'hFFFE
`define ALUA_HL 14'h0008 //Select HL register
`define ALUA_IX 14'h0010 //Select IX register
`define ALUA_IY 14'h0020 //Select IY register
`define ALUA_PC 14'h0040 //Select PC register
`define ALUA_AA 14'h0080 //Select A register
`define ALUA_BIT 14'h0100 //Select bit select constant
`define ALUA_DAA 14'h0200 //Select decimal adjust constant
`define ALUA_II 14'h0400 //Select I register
`define ALUA_RR 14'h0800 //Select R register
`define ALUA_INT 14'h1000 //Select interrupt address
`define ALUA_RST 14'h2000 //Select restart address
`define ALUA_IDX 14
`define ALUA_RSTVAL 15'h0000 //Reset value for pipeline controls
`define ALUA_ZER 15'h0000 //Select 16'h0000 (default)
`define ALUA_ONE 15'h0001 //Select 16'h0001
`define ALUA_M1 15'h0002 //Select 16'hFFFF
`define ALUA_M2 15'h0004 //Select 16'hFFFE
`define ALUA_HL 15'h0008 //Select HL register
`define ALUA_IX 15'h0010 //Select IX register
`define ALUA_IY 15'h0020 //Select IY register
`define ALUA_PC 15'h0040 //Select PC register
`define ALUA_AA 15'h0080 //Select A register
`define ALUA_BIT 15'h0100 //Select bit select constant
`define ALUA_DAA 15'h0200 //Select decimal adjust constant
`define ALUA_II 15'h0400 //Select I register
`define ALUA_RR 15'h0800 //Select R register
`define ALUA_INT 15'h1000 //Select interrupt address
`define ALUA_TMP 15'h2000 //Select TMP register
`define ALUA_RST 15'h4000 //Select restart address
 
`define AA_ONE 0 //alua one
`define AA_M1 1 //alua -1
251,7 → 255,8
`define AA_II 10 //alua ii
`define AA_RR 11 //alua rr
`define AA_INT 12 //alua interrupt
`define AA_RST 13 //alua restart
`define AA_TMP 13 //alua tmp
`define AA_RST 14 //alua restart
 
/*****************************************************************************************/
/* */
344,6 → 349,7
`define ALUOP_SRL 8'b10100000 //ALU shft: shift right logical
`define ALUOP_SRA 8'b10101000 //ALU shft: shift right arithmetic
 
`define ALUOP_MLT 8'b11000000 //ALU mult: 8 bit multiplication
/*****************************************************************************************/
/* */
/* ALU operation control: 6 encoded */
387,6 → 393,7
`define AOP_SRL 6'b100000 //ALU shft: shift right logical
`define AOP_SRA 6'b101000 //ALU shft: shift right arithmetic
 
`define AOP_MLT 6'b000000 //ALU mult: 8 bit multiplication
/*****************************************************************************************/
/* */
/* machine state - pseudo-one-hot */
/trunk/rtl/control.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** control module Rev 0.0 08/22/2011 **/
/** control module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
11,11 → 12,12
page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, rreg_en, sflg_en, state_nxt,
tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg,
intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int,
xhlt_reg, zero_bit);
xhlt_reg, zero_bit, int_req);
 
input carry_bit; /* carry flag */
input dmar_reg; /* latched dma request */
input intr_reg; /* latched interrupt request */
input int_req; /* interrupt request (for SLP) */
input par_bit; /* parity flag */
input sign_bit; /* sign flag */
input tflg_reg; /* temporary flag */
41,7 → 43,7
output rd_frst; /* read first cycle */
output rd_nxt; /* read cycle identifier */
output reti_nxt; /* reti identifier */
output rreg_en; /* update refresh register */
output rreg_en; /* update refresh register */
output sflg_en; /* sign flag control */
output wr_frst; /* write first cycle */
output zflg_en; /* zero flag control */
83,9 → 85,9
reg output_inh; /* disable cpu outputs */
reg rd_frst; /* first clock of read */
reg rd_nxt; /* read trans next */
reg reti_nxt; /* reti trans next */
`ifdef RREG_EMU
reg rreg_en; /* update refresh register */
reg reti_nxt; /* reti trans next */
`ifdef RREG_EMU
reg rreg_en; /* update refresh register */
`endif
reg sflg_en; /* sign flag control */
reg wr_frst; /* first clock of write */
107,40 → 109,40
reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
reg [`TTYPE_IDX:0] tran_sel; /* transaction type */
reg [`WREG_IDX:0] wr_addr; /* register write address bus */
 
/*****************************************************************************************/
/* */
/* refresh register control */
/* */
/*****************************************************************************************/
`ifdef RREG_EMU
always @ (inst_reg or page_reg or state_reg or dmar_reg) begin
casex (state_reg) //sysnopsys parallel_case
`IF1B,
`IF2B,
`IF3B: rreg_en = 1'b1;
`WR1B,
`WR2B: begin
casex ({page_reg, inst_reg}) //sysnopsys parallel_case
12'b1xxx10111001,
12'b1xxx10110001,
12'b1xxx10111010,
12'b1xxx10110010,
12'b1xxx10111000,
12'b1xxx10110000,
12'b1xxx10111011,
12'b1xxx10110011,
12'b0001xxxxxxxx: rreg_en = 1'b1;
default: rreg_en = 1'b0;
endcase
end
default: rreg_en = 1'b0;
endcase
end
`endif
 
/*****************************************************************************************/
/* */
/* refresh register control */
/* */
/*****************************************************************************************/
`ifdef RREG_EMU
always @ (inst_reg or page_reg or state_reg or dmar_reg) begin
casex (state_reg) //sysnopsys parallel_case
`IF1B,
`IF2B,
`IF3B: rreg_en = 1'b1;
`WR1B,
`WR2B: begin
casex ({page_reg, inst_reg}) //sysnopsys parallel_case
12'b1xxx10111001,
12'b1xxx10110001,
12'b1xxx10111010,
12'b1xxx10110010,
12'b1xxx10111000,
12'b1xxx10110000,
12'b1xxx10111011,
12'b1xxx10110011,
12'b0001xxxxxxxx: rreg_en = 1'b1;
default: rreg_en = 1'b0;
endcase
end
default: rreg_en = 1'b0;
endcase
end
`endif
 
/*****************************************************************************************/
/* */
/* exchange instruction control */
/* */
/*****************************************************************************************/
316,10 → 318,15
12'b010x11100001,
12'b010x11100011,
12'b010x11100101,
12'b1xxx00xxx11x, //ld (hl),rr; ld (hl),ii; ld rr,(hl); ld ii,(hl)
12'b1xxx0100x101,
12'b1xxx0110x111,
12'b1xxx01xxx00x,
12'b1xxx01110110, //slp
12'b1xxx100xx01x, //indm,indmr,inim,inimr, otdm,otdmr,otim,otimr
12'b1xxx101xx0xx,
12'b1xxx10xxx100, //ind2,ind2r,ini2,ini2r, outd2,otd2r,outi2,oti2r
12'b1xxx1100x01x, //indrx,inirx, otdrx,otirx
12'b010x11101001: ld_wait = 1'b0;
default: ld_wait = 1'b1;
endcase
466,7 → 473,7
end
`IF2B: state_nxt = `sDEC2;
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b001000110110,
12'b001000000110,
12'b001000001110,
484,6 → 491,7
12'b010111100001,
12'b010111100011,
12'b010111100101,
12'b1xxx00110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01100111,
490,6 → 498,10
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx10000011,
12'b1xxx10001011,
12'b1xxx10010011,
12'b1xxx10011011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
505,55 → 517,55
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: state_nxt = `sADR2;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b1xxx10111011: state_nxt = `sADR2;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b001000110xxx,
12'b001000000xxx,
12'b001000001xxx,
573,6 → 585,7
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
582,9 → 595,11
12'b1xxx01011110,
12'b1xxx01011111,
12'b1xxx01xx0010,
12'b1xxx01xx1010: state_nxt = `sIF1B;
12'b1xxx01xx1010,
12'b1xxx01xx1100: state_nxt = `sIF1B;
12'b010011101001,
12'b010111101001: state_nxt = `sPCO;
12'b010111101001,
12'b1xxx01110110: state_nxt = `sPCO;
default: state_nxt = `sOF1B;
endcase
end
615,10 → 630,13
12'b010110100110,
12'b010110101110,
12'b010110110110,
12'b010110111110: state_nxt = `sADR1;
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010110111110,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01110100: state_nxt = `sADR1;
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b0000000xx110,12'b00000010x110,12'b000000111110,
12'b000011000110,
628,7 → 646,8
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110: state_nxt = `sIF1A;
12'b000011111110,
12'b1xxx01100100: state_nxt = `sIF1A;
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
707,6 → 726,7
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx1011,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
738,6 → 758,7
12'b000011010011,
12'b010001110xxx,
12'b010101110xxx,
12'b1xxx00xxx001,
12'b1xxx01xxx001: state_nxt = `sWR2A;
default: state_nxt = `sRD2A;
endcase
749,6 → 770,7
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: state_nxt = `sBLK1;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
818,6 → 840,8
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxx000,
12'b1xxx0x110100,
12'b1xxx01xxx000,
12'b1xxx01xx1011: state_nxt = `sIF1A;
12'b000011001001,
834,6 → 858,7
`WR1A: state_nxt = `sWR1B;
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
840,6 → 865,7
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10101011: state_nxt = `sIF1A;
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
852,6 → 878,7
`WR2A: state_nxt = `sWR2B;
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10111010,
12'b1xxx10110011,
873,11 → 900,12
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: state_nxt = `sHLTA;
12'b1xxx01110110: state_nxt = `sHLTA;
default: state_nxt = `sIF1A;
endcase
end
`HLTA: state_nxt = `sHLTB;
`HLTB: state_nxt = (xhlt_reg) ? `sIF1A : `sHLTA;
`HLTB: state_nxt = (xhlt_reg || (int_req && page_reg[3])) ? `sIF1A : `sHLTA;
`IF1A: state_nxt = `sIF1B;
`IF1B: state_nxt = `sDEC1;
`INTA: state_nxt = `sINTB;
960,8 → 988,11
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011010011,
12'b000011011011,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx01110100,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
986,6 → 1017,7
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: tran_sel = `TRAN_IDL;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
1050,8 → 1082,10
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx01110100,
12'b1xxx01xxx000,
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
1067,6 → 1101,7
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
1088,6 → 1123,7
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx10110010,
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10111000,
12'b1xxx10110011,
1104,7 → 1140,8
end
`PCO: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: tran_sel = `TRAN_IDL;
12'b000001110110,
12'b1xxx01110110: tran_sel = `TRAN_IDL;
default: tran_sel = `TRAN_IF;
endcase
end
1118,7 → 1155,7
(intr_reg) ? `TRAN_IAK : `TRAN_IF;
endcase
end
`HLTB: tran_sel = (xhlt_reg) ? `TRAN_IF : `TRAN_IDL;
`HLTB: tran_sel = (xhlt_reg || (page_reg[3] && int_req)) ? `TRAN_IF : `TRAN_IDL;
`INTB: tran_sel = (vector_int) ? `TRAN_IDL : `TRAN_MEM;
`DMA2: tran_sel = (dmar_reg) ? `TRAN_IDL : `TRAN_IF;
`RSTE: tran_sel = `TRAN_IF;
1135,8 → 1172,9
casex (state_reg)
`PCO,
`HLTB: begin
casex ({page_reg, inst_reg})
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: halt_nxt = !xhlt_reg;
12'b1xxx01110110: halt_nxt = !int_req;
default: halt_nxt = 1'b0;
endcase
end
1175,8 → 1213,9
`DMA2: output_inh = dmar_reg;
`PCO,
`HLTB: begin
casex ({page_reg, inst_reg})
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000001110110: output_inh = !xhlt_reg;
12'b1xxx01110110: output_inh = !int_req;
default: output_inh = 1'b0;
endcase
end
1240,6 → 1279,7
12'b010111101001,
12'b1xxx01xxx000,
12'b1xxx01xxx001,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
1255,7 → 1295,7
12'b1xxx10111000,
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b1xxx10111011: add_sel = `ADD_ALU;
12'b001000000110,
12'b001000001110,
12'b001000010110,
1262,11 → 1302,12
12'b001000011110,
12'b001000100110,
12'b001000101110,
12'b001000110110,
12'b001000110110,
12'b001000111110,
12'b001001xxx110,
12'b001010xxx110,
12'b001011xxx110,
12'b1xxx00110100,
12'b1xxx01100111,
12'b1xxx01101111: add_sel = `ADD_HL;
12'b010011100001,
1294,9 → 1335,21
default: add_sel = `ADD_PC;
endcase
end
`IF3A,
`ADR1,
`RD1A: add_sel = `ADD_ALU;
`IF3A: add_sel = `ADD_ALU;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100,
12'b1xxx00xxx000,
12'b1xxx00xxx001: add_sel = `ADD_ALU8;
default: add_sel = `ADD_ALU;
endcase
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011: add_sel = `ADD_ALU8;
default: add_sel = `ADD_ALU;
endcase
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011100011,
1308,7 → 1361,7
12'b010100110101,
12'b010111100011,
12'b011x00xxxxxx,
12'b011x1xxxxxxx,
12'b011x1xxxxxxx,
12'b1xxx10100000,
12'b1xxx10100001,
12'b1xxx10100010,
1325,6 → 1378,8
12'b1xxx10111001,
12'b1xxx10111010,
12'b1xxx10111011: add_sel = `ADD_ALU;
//12'b1xxx01110100,
12'b1xxx100xx011: add_sel = `ADD_ALU8;
12'b000000110100,
12'b000000110101,
12'b000000xxx100,
1341,8 → 1396,8
12'b001000100xxx,
12'b001000101110,
12'b001000101xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000110110,
12'b001000110xxx,
12'b001000111110,
12'b001000111xxx,
12'b001010xxx110,
1356,6 → 1411,7
end
`WR1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1000x011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
1371,6 → 1427,7
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
1409,6 → 1466,7
end
`IF1A: add_sel = `ADD_PC;
`INTA: add_sel = (vector_int) ? `ADD_PC : `ADD_ALU;
`HLTA: add_sel = `ADD_PC;
`DMA1: add_sel = `ADD_PC;
default: add_sel = `ADD_RSTVAL;
endcase
1485,10 → 1543,10
endcase
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010000100110,
12'b010000101110,
12'b010100100110,
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b010000100110,
12'b010000101110,
12'b010100100110,
12'b010100101110,
12'b010011001011, //DD+CB prefix
12'b010111001011, //FD+CB prefix
1526,58 → 1584,62
12'b010110110110,
12'b010110111110,
12'b010111101001,
12'b1xxx00xxx000,
12'b1xxx00xxx001,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01000101,
12'b1xxx01001101,
12'b1xxx01xx0011,
12'b1xxx01xx1011: pc_sel = `PC_LD;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101,
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100,
12'b0100011000xx,12'b01000110010x,12'b010001100111,
12'b0100011010xx,12'b01000110110x,12'b010001101111,
12'b0101011000xx,12'b01010110010x,12'b010101100111,
12'b0101011010xx,12'b01010110110x,12'b010101101111,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101,
12'b0010000000xx,12'b00100000010x,12'b001000000111,
12'b0010000010xx,12'b00100000110x,12'b001000001111,
12'b0010000100xx,12'b00100001010x,12'b001000010111,
1584,7 → 1646,7
12'b0010000110xx,12'b00100001110x,12'b001000011111,
12'b0010001000xx,12'b00100010010x,12'b001000100111,
12'b0010001010xx,12'b00100010110x,12'b001000101111,
12'b0010001100xx,12'b00100011010x,12'b001000110111,
12'b0010001100xx,12'b00100011010x,12'b001000110111,
12'b0010001110xx,12'b00100011110x,12'b001000111111,
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,
1597,6 → 1659,8
12'b010100101011,
12'b010100xx1001,
12'b010111111001,
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
12'b1xxx01xx1100,
12'b1xxx01000100,
12'b1xxx01000110,
12'b1xxx01000111,
1640,18 → 1704,10
default: pc_sel = `PC_NUL;
endcase
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`RD1B,
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
1663,6 → 1719,15
default: pc_sel = `PC_NUL;
endcase
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011001101,
12'b000011xxx100,
12'b000011xxx111,
12'b0001xxxxxxxx: pc_sel = `PC_LD;
default: pc_sel = `PC_NUL;
endcase
end
`PCA: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD;
1682,6 → 1747,7
12'b000011101001,
12'b010011101001,
12'b010111101001,
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
1698,6 → 1764,7
12'b1xxx01000101,
12'b1xxx01001101,
12'b0001xxxxxxxx: pc_sel = `PC_LD;
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110001,
12'b1xxx10110010,
1805,6 → 1872,7
12'b000011xx0101,
12'b000011xxx111,
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
1820,9 → 1888,8
12'b000011100011,
12'b1xxx01xx0011: do_ctl = `DO_MSB;
12'b000011010011,
12'b1xxx0x0xx001,
12'b1xxx0x10x001,
12'b1xxx0x111001,
12'b1xxx0xxxx001,
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
1886,50 → 1953,52
12'b010111100101: aluop_sel = `ALUOP_ADD;
12'b1xxx01010111,
12'b1xxx01011111: aluop_sel = `ALUOP_APAS;
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101: aluop_sel = `ALUOP_BADC;
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100: aluop_sel = `ALUOP_BADD;
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b010010001100,
12'b010010001101,
12'b010110001100,
12'b010110001101: aluop_sel = `ALUOP_BADC;
12'b010010000100,
12'b010010000101,
12'b010110000100,
12'b010110000101,
12'b010000100100,
12'b010000101100,
12'b010100100100,
12'b010100101100: aluop_sel = `ALUOP_BADD;
12'b010010100100,
12'b010010100101,
12'b010110100100,
12'b010110100101,
12'b001001xxxxxx,
12'b001010xxxxxx: aluop_sel = `ALUOP_BAND;
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101: aluop_sel = `ALUOP_BDEC;
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b001010xxxxxx,
12'b1xxx00xxx100: aluop_sel = `ALUOP_BAND;
12'b010000100101,
12'b010000101101,
12'b010100100101,
12'b010100101101: aluop_sel = `ALUOP_BDEC;
12'b010010110100,
12'b010010110101,
12'b010110110100,
12'b010110110101,
12'b001011xxxxxx: aluop_sel = `ALUOP_BOR;
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101: aluop_sel = `ALUOP_BSBC;
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b010010011100,
12'b010010011101,
12'b010110011100,
12'b010110011101: aluop_sel = `ALUOP_BSBC;
12'b010010111100,
12'b010010111101,
12'b010110111100,
12'b010110111101,
12'b010010010100,
12'b010010010101,
12'b010110010100,
12'b010110010101,
12'b1xxx01000100: aluop_sel = `ALUOP_BSUB;
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101: aluop_sel = `ALUOP_BXOR;
12'b010010101100,
12'b010010101101,
12'b010110101100,
12'b010110101101: aluop_sel = `ALUOP_BXOR;
12'b1xxx01xx1100: aluop_sel = `ALUOP_MLT;
12'b001000010xxx: aluop_sel = `ALUOP_RL;
12'b001000000xxx: aluop_sel = `ALUOP_RLC;
12'b001000011xxx: aluop_sel = `ALUOP_RR;
1936,7 → 2005,7
12'b001000001xxx: aluop_sel = `ALUOP_RRC;
12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC;
12'b001000100xxx: aluop_sel = `ALUOP_SLA;
12'b001000110xxx: aluop_sel = `ALUOP_SLL;
12'b001000110xxx: aluop_sel = `ALUOP_SLL;
12'b001000101xxx: aluop_sel = `ALUOP_SRA;
12'b001000111xxx: aluop_sel = `ALUOP_SRL;
default: aluop_sel = `ALUOP_PASS;
1950,6 → 2019,7
12'b000000111000: aluop_sel = ( carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
12'b000000010000,
12'b000000011000: aluop_sel = `ALUOP_ADS;
12'b1xxx01110100,
12'b000000110110: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADD;
endcase
1988,6 → 2058,7
`IF3A: aluop_sel = `ALUOP_ADS;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx00xxx00x,
12'b000000100010,
12'b000000101010,
12'b000000110010,
1999,6 → 2070,8
12'b010000101010,
12'b010100100010,
12'b010100101010,
12'b1xxx01100100,
12'b1xxx01110100,
12'b1xxx01xx0011,
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
default: aluop_sel = `ALUOP_ADS;
2014,6 → 2087,7
12'b1xxx10110001,
12'b1xxx10111000,
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
2027,6 → 2101,7
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
2048,6 → 2123,7
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
2073,6 → 2149,7
12'b1xxx10110010,
12'b1xxx10111000,
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011: aluop_sel = `ALUOP_BADD;
default: aluop_sel = `ALUOP_PASS;
endcase
end
2106,20 → 2183,22
12'b010111100011,
12'b1xxx01000101,
12'b1xxx01001101,
//12'b1xxx01110100,
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
12'b0x1x00011xxx: aluop_sel = `ALUOP_RR;
12'b0x1x00100xxx: aluop_sel = `ALUOP_SLA;
12'b0x1x00101xxx: aluop_sel = `ALUOP_SRA;
12'b0x1x00110xxx: aluop_sel = `ALUOP_SLL;
12'b0x1x00101xxx: aluop_sel = `ALUOP_SRA;
12'b0x1x00110xxx: aluop_sel = `ALUOP_SLL;
12'b0x1x00111xxx: aluop_sel = `ALUOP_SRL;
12'b1xxx01101111: aluop_sel = `ALUOP_RLD1;
12'b1xxx01100111: aluop_sel = `ALUOP_RRD1;
12'b1xxx01101111: aluop_sel = `ALUOP_RLD1;
12'b1xxx01100111: aluop_sel = `ALUOP_RRD1;
default: aluop_sel = `ALUOP_ADD;
endcase
end
2142,6 → 2221,7
12'b1xxx10101011,
12'b1xxx10110000,
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
12'b1xxx100xx011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
2151,6 → 2231,7
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
2166,6 → 2247,7
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2193,6 → 2275,7
12'b000010000xxx,
12'b000011000110,
12'b010x10000110,
12'b1xxx100xx011,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
2201,6 → 2284,9
12'b0x1x01xxxxxx,
12'b010x10100110,
12'b000011100110,
12'b1xxx00110100,
12'b1xxx00xxx000,
12'b1xxx011x0100,
12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND;
12'b000010110xxx,
12'b010x10110110,
2258,27 → 2344,27
end
`DEC2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx: alua_sel = `ALUA_BIT;
12'b001001xxxxxx,
12'b001010xxxxxx,
12'b001011xxxxxx: alua_sel = `ALUA_BIT;
12'b1xxx01xx0010,
12'b1xxx01xx1010: alua_sel = `ALUA_HL;
12'b1xxx01010111: alua_sel = `ALUA_II;
12'b010000xx1001: alua_sel = `ALUA_IX;
12'b010100xx1001: alua_sel = `ALUA_IY;
12'b010000100101,
12'b010000100101,
12'b010000101011,
12'b010000101101,
12'b010000101101,
12'b010011100101,
12'b010100100101,
12'b010100100101,
12'b010100101011,
12'b010100101101,
12'b010100101101,
12'b010111100101: alua_sel = `ALUA_M1;
12'b010000100100,
12'b010000101100,
12'b010000100100,
12'b010000101100,
12'b010000100011,
12'b010100100100,
12'b010100101100,
12'b010100100100,
12'b010100101100,
12'b010100100011: alua_sel = `ALUA_ONE;
12'b1xxx01011111: alua_sel = `ALUA_RR;
12'b1xxx01000100: alua_sel = `ALUA_ZER;
2318,6 → 2404,7
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx,
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101010,
12'b1xxx10111000,
2357,6 → 2444,7
12'b010100100010,
12'b010111100011,
12'b1xxx01xx0011,
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10110000,
2366,6 → 2454,7
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110000,
12'b1xxx10110010,
12'b1xxx10110011,
2378,6 → 2467,7
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
12'b1xxx100x1011,
12'b1xxx10101000,
12'b1xxx10101011,
12'b1xxx10111000,
2388,6 → 2478,7
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10100011,
2413,7 → 2504,9
`IF1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
12'b1xxx00xxx000,
12'b1xxx01xxx000,
12'b1xxx100x1011,
12'b1xxx10100011,
12'b1xxx10101000,
12'b1xxx10101010,
2422,10 → 2515,12
12'b1xxx10111000,
12'b1xxx10111010,
12'b1xxx10111011: alua_sel = `ALUA_M1;
12'b1xxx100x0011,
12'b1xxx10100000,
12'b1xxx10100010,
12'b1xxx10110000,
12'b1xxx10110010: alua_sel = `ALUA_ONE;
12'b1xxx01110100: alua_sel = `ALUA_TMP;
default: alua_sel = `ALUA_AA;
endcase
end
2512,50 → 2607,50
12'b010000101011,
12'b010011101001,
12'b010011111001: alub_sel = `ALUB_IX;
12'b010000100100,
12'b010000100101,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b010010000100,
12'b010010001100,
12'b010010010100,
12'b010010011100,
12'b010010100100,
12'b010010101100,
12'b010010110100,
12'b010010111100: alub_sel = `ALUB_IXH;
12'b010100100100,
12'b010100100101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b010110000100,
12'b010110001100,
12'b010110010100,
12'b010110011100,
12'b010110100100,
12'b010110101100,
12'b010110110100,
12'b010110111100: alub_sel = `ALUB_IYH;
12'b010000101100,
12'b010000101101,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b010010000101,
12'b010010001101,
12'b010010010101,
12'b010010011101,
12'b010010100101,
12'b010010101101,
12'b010010110101,
12'b010010111101: alub_sel = `ALUB_IXL;
12'b010100101100,
12'b010100101101,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010110000101,
12'b010110001101,
12'b010110010101,
12'b010110011101,
12'b010110100101,
12'b010110101101,
12'b010110110101,
12'b010110111101: alub_sel = `ALUB_IYL;
12'b010000100100,
12'b010000100101,
12'b0100010xx100,12'b01000110x100,12'b010001111100,
12'b010010000100,
12'b010010001100,
12'b010010010100,
12'b010010011100,
12'b010010100100,
12'b010010101100,
12'b010010110100,
12'b010010111100: alub_sel = `ALUB_IXH;
12'b010100100100,
12'b010100100101,
12'b0101010xx100,12'b01010110x100,12'b010101111100,
12'b010110000100,
12'b010110001100,
12'b010110010100,
12'b010110011100,
12'b010110100100,
12'b010110101100,
12'b010110110100,
12'b010110111100: alub_sel = `ALUB_IYH;
12'b010000101100,
12'b010000101101,
12'b0100010xx101,12'b01000110x101,12'b010001111101,
12'b010010000101,
12'b010010001101,
12'b010010010101,
12'b010010011101,
12'b010010100101,
12'b010010101101,
12'b010010110101,
12'b010010111101: alub_sel = `ALUB_IXL;
12'b010100101100,
12'b010100101101,
12'b0101010xx101,12'b01010110x101,12'b010101111101,
12'b010110000101,
12'b010110001101,
12'b010110010101,
12'b010110011101,
12'b010110100101,
12'b010110101101,
12'b010110110101,
12'b010110111101: alub_sel = `ALUB_IYL;
12'b010100100011,
12'b010100101011,
12'b010111101001,
2562,20 → 2657,30
12'b010111111001: alub_sel = `ALUB_IY;
12'b1xxx01000101,
12'b1xxx01001101: alub_sel = `ALUB_PC;
12'b010x0110x000,
12'b010x0110x000,
12'b1xxx00000100,
12'b0010xxxxx000: alub_sel = `ALUB_BB;
12'b010x0110x001,
12'b010x0110x001,
12'b1xxx00001100,
12'b0010xxxxx001: alub_sel = `ALUB_CC;
12'b010x0110x010,
12'b010x0110x010,
12'b1xxx00010100,
12'b0010xxxxx010: alub_sel = `ALUB_DD;
12'b010x0110x011,
12'b010x0110x011,
12'b1xxx00011100,
12'b0010xxxxx011: alub_sel = `ALUB_EE;
12'b1xxx00100100,
12'b0010xxxxx100: alub_sel = `ALUB_HH;
12'b1xxx00101100,
12'b0010xxxxx101: alub_sel = `ALUB_LL;
12'b010x0110x111,
12'b010x0110x111,
12'b1xxx00111100,
12'b0010xxxxx111: alub_sel = `ALUB_AA;
12'b1xxx01001100,
12'b1xxx0100x010: alub_sel = `ALUB_BC;
12'b1xxx01011100,
12'b1xxx0101x010: alub_sel = `ALUB_DE;
12'b1xxx01111100,
12'b1xxx0111x010: alub_sel = `ALUB_SP;
12'b010011100101,
12'b010111100101: alub_sel = `ALUB_SP;
2582,7 → 2687,7
12'b010x00001001: alub_sel = `ALUB_BC;
12'b010x00011001: alub_sel = `ALUB_DE;
12'b010000101001: alub_sel = `ALUB_IX;
12'b010100101001: alub_sel = `ALUB_IY;
12'b010100101001: alub_sel = `ALUB_IY;
12'b010x00111001: alub_sel = `ALUB_SP;
default: alub_sel = `ALUB_HL;
endcase
2589,6 → 2694,7
end
`OF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100,
12'b000000010000,
12'b000000011000,
12'b000000110110: alub_sel = `ALUB_DIN;
2634,6 → 2740,7
`IF3A: alub_sel = `ALUB_DIN;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100: alub_sel = `ALUB_CC;
12'b000011010011,
12'b000011011011: alub_sel = `ALUB_IO;
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
2646,6 → 2753,7
12'b000000010010,
12'b000000110010,
12'b000011010011: alub_sel = `ALUB_AA;
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2669,24 → 2777,32
12'b000011xxx111: alub_sel = `ALUB_PCH;
12'b000001xxx000,
12'b010x01110000,
12'b1xxx00000001,
12'b1xxx01000001: alub_sel = `ALUB_BB;
12'b000001xxx001,
12'b010x01110001,
12'b1xxx01110100,
12'b1xxx00001001,
12'b1xxx01001001: alub_sel = `ALUB_CC;
12'b000001xxx010,
12'b010x01110010,
12'b1xxx00010001,
12'b1xxx01010001: alub_sel = `ALUB_DD;
12'b000001xxx011,
12'b010x01110011,
12'b1xxx00011001,
12'b1xxx01011001: alub_sel = `ALUB_EE;
12'b000001xxx100,
12'b010x01110100,
12'b1xxx00100001,
12'b1xxx01100001: alub_sel = `ALUB_HH;
12'b000001xxx101,
12'b010x01110101,
12'b1xxx00101001,
12'b1xxx01101001: alub_sel = `ALUB_LL;
12'b000001xxx111,
12'b010x01110111,
12'b1xxx00111001,
12'b1xxx01111001: alub_sel = `ALUB_AA;
12'b1xxx01000011: alub_sel = `ALUB_BC;
12'b1xxx01010011: alub_sel = `ALUB_DE;
2704,6 → 2820,7
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
2731,6 → 2848,8
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BC;
12'b1xxx01110100,
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
2804,7 → 2923,10
12'b010111100001,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxx000,
12'b1xxx00xxx100,
12'b1xxx01xxx000,
12'b1xxx01xxx100,
12'b1xxx01xx1011: alub_sel = `ALUB_PC;
12'b0001xxxxxxxx: alub_sel = `ALUB_PCH;
default: alub_sel = `ALUB_DIN;
2816,6 → 2938,7
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: alub_sel = `ALUB_BC;
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
2833,6 → 2956,7
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx1001x011,
12'b1xxx10110010,
12'b1xxx10110011,
12'b1xxx10111010,
2871,6 → 2995,7
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2896,6 → 3021,7
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: alub_sel = `ALUB_BB;
12'b1xxx100xx011: alub_sel = `ALUB_CC;
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
2942,6 → 3068,12
endcase
end
`IF3B: wr_addr = `WREG_TMP;
`ADR1: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01110100: wr_addr = `WREG_TMP;
default: wr_addr = `WREG_NUL;
endcase
end
`ADR2: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000011xxx111,
2965,6 → 3097,7
end
`RD1A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
2998,6 → 3131,7
end
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
3019,6 → 3153,7
end
`RD2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011: wr_addr = `WREG_CC;
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
3040,6 → 3175,7
end
`WR1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
3060,6 → 3196,7
end
`WR2B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100000,
12'b1xxx10100011,
12'b1xxx10101000,
3082,220 → 3219,225
end
`IF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000000111,
12'b000000001010,
12'b000000001111,
12'b000000010111,
12'b000000011010,
12'b000000011111,
12'b000000100111,
12'b000000101111,
12'b000000111010,
12'b00000011110x,
12'b000000111110,
12'b000001111xxx,
12'b000010000xxx,
12'b000010001xxx,
12'b000010010xxx,
12'b000010011xxx,
12'b000010100xxx,
12'b000010101xxx,
12'b000010110xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011011,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b001000xxx111,
12'b00101xxxx111,
//12'b011x00xxx111,
//12'b011x1xxxx111,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b010x0111110x,
12'b010x01111110,
12'b1xxx01000100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx0x111000: wr_addr = `WREG_AA;
12'b000011110001: wr_addr = `WREG_AF;
12'b00000000010x,
12'b000000000110,
12'b000001000xxx,
12'b001000xxx000,
12'b00101xxxx000,
//12'b011x00xxx000,
// 12'b011x1xxxx000,
12'b010x0100010x,
12'b010x01000110,
12'b1xxx0x000000,
12'b000000000111,
12'b000000001010,
12'b000000001111,
12'b000000010111,
12'b000000011010,
12'b000000011111,
12'b000000100111,
12'b000000101111,
12'b000000111010,
12'b00000011110x,
12'b000000111110,
12'b000001111xxx,
12'b000010000xxx,
12'b000010001xxx,
12'b000010010xxx,
12'b000010011xxx,
12'b000010100xxx,
12'b000010101xxx,
12'b000010110xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011011,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b001000xxx111,
12'b00101xxxx111,
//12'b011x00xxx111,
//12'b011x1xxxx111,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b010x0111110x,
12'b010x01111110,
12'b1xxx01000100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx0x111000: wr_addr = `WREG_AA;
12'b000011110001: wr_addr = `WREG_AF;
12'b00000000010x,
12'b000000000110,
12'b000001000xxx,
12'b001000xxx000,
12'b00101xxxx000,
//12'b011x00xxx000,
// 12'b011x1xxxx000,
12'b010x0100010x,
12'b010x01000110,
12'b1xxx0x000000,
12'b1xxx10100011,
12'b1xxx10101011,
12'b1xxx10110011,
12'b1xxx10111011: wr_addr = `WREG_BB;
12'b000000000001,
12'b00000000x011,
12'b000011000001,
12'b00000000x011,
12'b000011000001,
12'b1xxx01001100,
12'b1xxx01001011: wr_addr = `WREG_BC;
12'b00000000110x,
12'b000000001110,
12'b000001001xxx,
12'b001000xxx001,
12'b00101xxxx001,
//12'b011x00xxx001,
//12'b011x1xxxx001,
12'b010x0100110x,
12'b010x01001110,
12'b1xxx0x001000: wr_addr = `WREG_CC;
12'b00000001010x,
12'b000000010110,
12'b000001010xxx,
12'b001000xxx010,
12'b00101xxxx010,
//12'b011x00xxx010,
//12'b011x1xxxx010,
12'b010x0101010x,
12'b010x01010110,
12'b1xxx0x010000: wr_addr = `WREG_DD;
12'b000011010001,
12'b00000001x011,
12'b00000000110x,
12'b000000001110,
12'b000001001xxx,
12'b001000xxx001,
12'b00101xxxx001,
//12'b011x00xxx001,
//12'b011x1xxxx001,
12'b010x0100110x,
12'b010x01001110,
12'b1xxx100xx011,
12'b1xxx0x001000: wr_addr = `WREG_CC;
12'b00000001010x,
12'b000000010110,
12'b000001010xxx,
12'b001000xxx010,
12'b00101xxxx010,
//12'b011x00xxx010,
//12'b011x1xxxx010,
12'b010x0101010x,
12'b010x01010110,
12'b1xxx0x010000: wr_addr = `WREG_DD;
12'b000011010001,
12'b00000001x011,
12'b000000010001,
12'b1xxx01011100,
12'b1xxx01011011,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: wr_addr = `WREG_DE;
12'b000011101011: wr_addr = `WREG_DEHL;
12'b00000001110x,
12'b000000011110,
12'b000001011xxx,
12'b001000xxx011,
12'b00101xxxx011,
//12'b011x00xxx011,
//12'b011x1xxxx011,
12'b010x0101110x,
12'b010x01011110,
12'b1xxx0x011000: wr_addr = `WREG_EE;
12'b00000010010x,
12'b000000100110,
12'b000001100xxx,
12'b001000xxx100,
12'b00101xxxx100,
//12'b011x00xxx100,
//12'b011x1xxxx100,
12'b010x01100110,
12'b1xxx0x100000: wr_addr = `WREG_HH;
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: wr_addr = `WREG_DE;
12'b000011101011: wr_addr = `WREG_DEHL;
12'b00000001110x,
12'b000000011110,
12'b000001011xxx,
12'b001000xxx011,
12'b00101xxxx011,
//12'b011x00xxx011,
//12'b011x1xxxx011,
12'b010x0101110x,
12'b010x01011110,
12'b1xxx0x011000: wr_addr = `WREG_EE;
12'b00000010010x,
12'b000000100110,
12'b000001100xxx,
12'b001000xxx100,
12'b00101xxxx100,
//12'b011x00xxx100,
//12'b011x1xxxx100,
12'b010x01100110,
12'b1xxx0x100000: wr_addr = `WREG_HH;
12'b000000100001,
12'b000000101010,
12'b00000010x011,
12'b000000xx1001,
12'b000011100001,
12'b000011100011,
12'b1xxx01101011,
12'b1xxx01xx0010,
12'b1xxx01xx1010,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx01000111: wr_addr = `WREG_II;
12'b010000100001,
12'b010000100011,
12'b010000101010,
12'b010000101011,
12'b010000xx1001,
12'b010011100001,
12'b010011100011: wr_addr = `WREG_IX;
12'b010000100100,
12'b010000100101,
12'b010000100110,
12'b0100011000xx,
12'b01000110010x,
12'b010001100111: wr_addr = `WREG_IXH;
12'b010000101100,
12'b010000101101,
12'b010000101110,
12'b0100011010xx,
12'b01000110110x,
12'b010001101111: wr_addr = `WREG_IXL;
12'b010100100001,
12'b010100100011,
12'b010100101010,
12'b010100101011,
12'b010100xx1001,
12'b010111100001,
12'b010111100011: wr_addr = `WREG_IY;
12'b010100100100,
12'b010100100101,
12'b010100100110,
12'b0101011000xx,
12'b01010110010x,
12'b010101100111: wr_addr = `WREG_IYH;
12'b010100101100,
12'b010100101101,
12'b010100101110,
12'b0101011010xx,
12'b01010110110x,
12'b010101101111: wr_addr = `WREG_IYL;
12'b00000010110x,
12'b000000101110,
12'b000001101xxx,
12'b001000xxx101,
12'b00101xxxx101,
//12'b011x00xxx101,
//12'b011x1xxxx101,
12'b010x01101110,
12'b1xxx0x101000: wr_addr = `WREG_LL;
12'b1xxx01001111: wr_addr = `WREG_RR;
12'b000000101010,
12'b00000010x011,
12'b000000xx1001,
12'b000011100001,
12'b000011100011,
12'b1xxx01101100,
12'b1xxx01101011,
12'b1xxx01xx0010,
12'b1xxx01xx1010,
12'b1xxx10100010,
12'b1xxx10101010,
12'b1xxx10110010,
12'b1xxx10111010: wr_addr = `WREG_HL;
12'b1xxx01000111: wr_addr = `WREG_II;
12'b010000100001,
12'b010000100011,
12'b010000101010,
12'b010000101011,
12'b010000xx1001,
12'b010011100001,
12'b010011100011: wr_addr = `WREG_IX;
12'b010000100100,
12'b010000100101,
12'b010000100110,
12'b0100011000xx,
12'b01000110010x,
12'b010001100111: wr_addr = `WREG_IXH;
12'b010000101100,
12'b010000101101,
12'b010000101110,
12'b0100011010xx,
12'b01000110110x,
12'b010001101111: wr_addr = `WREG_IXL;
12'b010100100001,
12'b010100100011,
12'b010100101010,
12'b010100101011,
12'b010100xx1001,
12'b010111100001,
12'b010111100011: wr_addr = `WREG_IY;
12'b010100100100,
12'b010100100101,
12'b010100100110,
12'b0101011000xx,
12'b01010110010x,
12'b010101100111: wr_addr = `WREG_IYH;
12'b010100101100,
12'b010100101101,
12'b010100101110,
12'b0101011010xx,
12'b01010110110x,
12'b010101101111: wr_addr = `WREG_IYL;
12'b00000010110x,
12'b000000101110,
12'b000001101xxx,
12'b001000xxx101,
12'b00101xxxx101,
//12'b011x00xxx101,
//12'b011x1xxxx101,
12'b010x01101110,
12'b1xxx0x101000: wr_addr = `WREG_LL;
12'b1xxx01001111: wr_addr = `WREG_RR;
12'b000000110001,
12'b00000011x011,
12'b000011111001,
12'b010x11111001,
12'b00000011x011,
12'b000011111001,
12'b010x11111001,
12'b1xxx01111100,
12'b1xxx01111011: wr_addr = `WREG_SP;
default: wr_addr = `WREG_NUL;
endcase
3314,13 → 3456,13
casex (state_reg) //synopsys parallel_case
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000110100,
12'b000000110101,
12'b001000xxxxxx,
12'b010000110100,
12'b010000110101,
12'b010100110100,
12'b010100110101,
12'b000000110100,
12'b000000110101,
12'b001000xxxxxx,
12'b010000110100,
12'b010000110101,
12'b010100110100,
12'b010100110101,
12'b011x00xxxxxx: sflg_en = 1'b1;
default: sflg_en = 1'b0;
endcase
3339,96 → 3481,99
12'b000000100111,
12'b0000000xx100,12'b00000010x100,12'b000000111100,
12'b0000000xx101,12'b00000010x101,12'b000000111101,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b001000xxx0xx,
12'b001000xxx10x,
12'b001000xxx111,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xx0010,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000011111110,
12'b001000xxx0xx,
12'b001000xxx10x,
12'b001000xxx111,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx00110100,
12'b1xxx00xxxx00,
12'b1xxx011x0100,
12'b1xxx01000100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xx0010,
12'b1xxx01xx1010: sflg_en = 1'b1;
default: sflg_en = 1'b0;
endcase
3447,6 → 3592,7
`RD1A,
`RD2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx100xx011,
12'b1xxx10100010,
12'b1xxx10100011,
12'b1xxx10101010,
3460,13 → 3606,13
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000110100,
12'b000000110101,
12'b001000xxxxxx,
12'b010000110100,
12'b010000110101,
12'b010100110100,
12'b010100110101,
12'b000000110100,
12'b000000110101,
12'b001000xxxxxx,
12'b010000110100,
12'b010000110101,
12'b010100110100,
12'b010100110101,
12'b011x00xxxxxx: zflg_en = 1'b1;
default: zflg_en = 1'b0;
endcase
3570,11 → 3716,13
12'b010110111110,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxxx00,
12'b1xxx01000100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx011x0100,
12'b1xxx01xxx000,
12'b1xxx01xx0010,
12'b1xxx01xx1010,
3620,120 → 3768,123
end
`IF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000110111,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011101110,
12'b000011110110,
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000110xxx,
12'b001000111xxx,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01xxx000,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000110111,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011101110,
12'b000011110110,
12'b001000000xxx,
12'b001000001xxx,
12'b001000010xxx,
12'b001000011xxx,
12'b001000100xxx,
12'b001000101xxx,
12'b001000110xxx,
12'b001000111xxx,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b1xxx00xxx000,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01xxx000,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: hflg_ctl = `HFLG_0;
12'b000000101111,
12'b000010100110,
12'b000010100xxx,
12'b000011100110,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b011001xxx110,
12'b011101xxx110: hflg_ctl = `HFLG_1;
12'b000000101111,
12'b000010100110,
12'b000010100xxx,
12'b000011100110,
12'b001001xxx110,
12'b001001xxxxxx,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b011001xxx110,
12'b011101xxx110,
12'b1xxx00xxx100,
12'b1xxx011x0100: hflg_ctl = `HFLG_1;
12'b000000111111,
12'b000000100111,
12'b000000100111,
12'b0000000xx100,12'b00000010x100,12'b000000111100,
12'b0000000xx101,12'b00000010x101,12'b000000111101,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b1xxx01xx1010: hflg_ctl = `HFLG_H;
default: hflg_ctl = `HFLG_NUL;
endcase
3765,7 → 3916,7
end
`WR2A: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b001000xxxxxx,
12'b001000xxxxxx,
12'b011x00xxxxxx: pflg_ctl = `PFLG_P;
12'b000000110100,
12'b000000110101,
3780,95 → 3931,98
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b1xxx01010111,
12'b1xxx01011111: pflg_ctl = `PFLG_F;
12'b000000100111,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b000000100111,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b1xxx01100111,
12'b1xxx01101111,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b1xxx00xxxx00,
12'b1xxx00110100,
12'b1xxx011x0100,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000: pflg_ctl = `PFLG_P;
12'b0000000xx100,12'b00000010x100,12'b000000111100,
12'b0000000xx101,12'b00000010x101,12'b000000111101,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100100,
12'b010000100101,
12'b010000101100,
12'b010000101101,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100100,
12'b010100100101,
12'b010100101100,
12'b010100101101,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b1xxx01xx1010: pflg_ctl = `PFLG_V;
default: pflg_ctl = `PFLG_NUL;
endcase
3900,121 → 4054,125
end
`IF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000110100,
12'b000000110111,
12'b000000111111,
12'b000000xxx100,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011000110,
12'b000011001110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b010000100100,
12'b010000101100,
12'b010000110100,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010100100100,
12'b010100101100,
12'b010100110100,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b00100xxxxxxx,
12'b011x0xxxxxxx,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xx1010,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000110100,
12'b000000110111,
12'b000000111111,
12'b000000xxx100,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011000110,
12'b000011001110,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b010000100100,
12'b010000101100,
12'b010000110100,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010100100100,
12'b010100101100,
12'b010100110100,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b00100xxxxxxx,
12'b011x0xxxxxxx,
12'b1xxx00xxxx00,
12'b1xxx00110100,
12'b1xxx011x0100,
12'b1xxx01010111,
12'b1xxx01011111,
12'b1xxx01100111,
12'b1xxx01101111,
12'b1xxx01xxx000,
12'b1xxx01xx1010,
12'b1xxx10100000,
12'b1xxx10101000,
12'b1xxx10110000,
12'b1xxx10111000: nflg_ctl = `NFLG_0;
12'b000000101111,
12'b000000110101,
12'b000000xxx101,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100101,
12'b010000101101,
12'b010000110101,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100101,
12'b010100101101,
12'b010100110101,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b000000101111,
12'b000000110101,
12'b000000xxx101,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b010000100101,
12'b010000101101,
12'b010000110101,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100100101,
12'b010100101101,
12'b010100110101,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b1xxx100xx011,
12'b1xxx10100001,
12'b1xxx10101001,
12'b1xxx10110001,
12'b1xxx10111001: nflg_ctl = `NFLG_1;
default: nflg_ctl = `NFLG_NUL;
endcase
4039,91 → 4197,94
end
`IF1B: begin
casex ({page_reg, inst_reg}) //synopsys parallel_case
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b000000110111,
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000100111,
12'b000000111111,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b000010100110,
12'b000010100xxx,
12'b000010101110,
12'b000010101xxx,
12'b000010110110,
12'b000010110xxx,
12'b000011100110,
12'b000011101110,
12'b000011110110,
12'b010010100100,
12'b010010100101,
12'b010010100110,
12'b010010101100,
12'b010010101101,
12'b010010101110,
12'b010010110100,
12'b010010110101,
12'b010010110110,
12'b010110100100,
12'b010110100101,
12'b010110100110,
12'b010110101100,
12'b010110101101,
12'b010110101110,
12'b010110110100,
12'b010110110101,
12'b010110110110,
12'b000000110111,
12'b000000000111,
12'b000000001111,
12'b000000010111,
12'b000000011111,
12'b000000100111,
12'b000000111111,
12'b000000xx1001,
12'b000010000110,
12'b000010000xxx,
12'b000010001110,
12'b000010001xxx,
12'b000010010110,
12'b000010010xxx,
12'b000010011110,
12'b000010011xxx,
12'b000010111110,
12'b000010111xxx,
12'b000011000110,
12'b000011001110,
12'b000011010110,
12'b000011011110,
12'b000011111110,
12'b001000xxx0xx,12'b001000xxx10x,12'b001000xxx111,
12'b010000xx1001,
12'b010010000100,
12'b010010000101,
12'b010010000110,
12'b010010001100,
12'b010010001101,
12'b010010001110,
12'b010010010100,
12'b010010010101,
12'b010010010110,
12'b010010011100,
12'b010010011101,
12'b010010011110,
12'b010010111100,
12'b010010111101,
12'b010010111110,
12'b010100xx1001,
12'b010110000100,
12'b010110000101,
12'b010110000110,
12'b010110001100,
12'b010110001101,
12'b010110001110,
12'b010110010100,
12'b010110010101,
12'b010110010110,
12'b010110011100,
12'b010110011101,
12'b010110011110,
12'b010110111100,
12'b010110111101,
12'b010110111110,
12'b1xxx00xxxx00,
12'b1xxx00110100,
12'b1xxx011x0100,
12'b1xxx01000100,
12'b1xxx01xx0010,
12'b1xxx01xx1010: cflg_en = 1'b1;
default: cflg_en = 1'b0;
endcase
/trunk/rtl/y80_top.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** processor top level Rev 0.0 08/03/2011 **/
/** processor top level Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module y80_top (dma_ack, halt_tran, iack_tran, io_addr_out, io_data_out, io_read, io_strobe,
165,7 → 166,8
.carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg),
.intr_reg(intr_reg), .page_reg(page_reg), .par_bit(par_bit),
.sign_bit(sign_bit), .state_reg(state_reg), .tflg_reg(tflg_reg),
.vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit) );
.vector_int(vector_int), .xhlt_reg(xhlt_reg), .zero_bit(zero_bit),
.int_req(int_req) );
 
/*****************************************************************************************/
/* */
/trunk/rtl/top_levl.v
1,535 → 1,563
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** **/
/** Y80 processor test bench Rev 0.0 08/20/2011 **/
/** **/
/*******************************************************************************************/
`timescale 1ns / 10ps /* set time scale */
`include "version.v" /* select version */
`include "hierarchy.v" /* include sources */
 
module top_levl;
 
wire DMA_ACK; /* dma acknowledge */
wire HALT_TRAN; /* halt transaction */
wire IACK_TRAN; /* int ack transaction */
wire IO_READ; /* i/o read/write status */
wire IO_STROBE; /* i/o strobe */
wire IO_TRAN; /* i/o transaction */
wire IVEC_RD; /* int vector read strobe */
wire MEM_RD; /* mem read strobe */
wire MEM_TRAN; /* mem transaction */
wire MEM_WR; /* mem write strobe */
wire RETI_TRAN; /* reti transaction */
wire T1; /* first clock of transaction */
wire [7:0] IO_DATA_OUT; /* i/o data output bus */
wire [7:0] MEM_DATA_OUT; /* mem data output bus */
wire [15:0] IO_ADDR; /* i/o address bus */
wire [15:0] MEM_ADDR; /* mem address bus */
 
reg CLEARB; /* master (test) reset */
reg CLKC; /* clock */
reg DMA_REQ; /* dma request */
reg INT_REQ; /* interrupt request */
reg NMI_REQ; /* non-maskable interrupt req */
reg RESETB; /* internal (user) reset */
reg WAIT_REQ; /* wait request */
reg [7:0] IO_DATA_IN; /* i/o data input bus */
reg [7:0] IVEC_DATA_IN; /* vector input bus */
reg [7:0] MEM_DATA_IN; /* mem data input bus */
 
/*****************************************************************************************/
/* */
/* testbench internal variables */
/* */
/*****************************************************************************************/
reg CLR_INT; /* deassert interrupt */
reg CLR_NMI; /* deassert nmi */
reg DISABLE_BREQ; /* bus req generator control */
reg DISABLE_INT; /* interrupt generator control */
reg DISABLE_WAIT; /* wait generator control */
reg INT_TYPE; /* int type during bus req */
reg PAT_DONE; /* pattern done flag */
reg TRIG_INT; /* assert interrupt */
reg TRIG_NMI; /* assert nmi */
reg [2:0] PAT_CNT; /* counter to track patterns */
reg [15:0] CMP_ERR_L; /* error counter */
 
reg wait_dly; /* wait request state machine */
reg [5:0] breq_mach; /* bus request state machine */
 
reg TREF0, TREF1, TREF2, TREF3, TREF4; /* timing generator */
reg TREF5, TREF6, TREF7, TREF8, TREF9;
 
/*****************************************************************************************/
/* */
/* read memory and write data compare memory */
/* */
/*****************************************************************************************/
reg [7:0] rdmem [0:65535];
reg [7:0] wrmem [0:65535];
 
wire [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :
(IO_TRAN) ? wrmem[IO_ADDR] : 8'hxx;
 
wire [7:0] rd_data = rdmem[MEM_ADDR];
wire [7:0] iord_data = rdmem[IO_ADDR];
 
always @ (posedge TREF6) begin
IO_DATA_IN = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;
MEM_DATA_IN = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;
end
 
always @ (posedge TREF6) begin
IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;
end
 
always @ (posedge TREF0) begin
IO_DATA_IN = 8'hxx;
MEM_DATA_IN = 8'hxx;
IVEC_DATA_IN = 8'hxx;
end
 
/*****************************************************************************************/
/* */
/* instantiate the design */
/* */
/*****************************************************************************************/
y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),
.io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),
.io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),
.mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),
.mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),
.clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),
.io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),
.mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),
.wait_req(WAIT_REQ) );
 
/*****************************************************************************************/
/* */
/* timing generator */
/* */
/*****************************************************************************************/
initial begin
TREF0 = 1;
CLKC = 1;
end
 
always begin
#10 TREF0 <= 1'b0;
TREF1 <= 1'b1;
#10 TREF1 <= 1'b0;
TREF2 <= 1'b1;
#10 TREF2 <= 1'b0;
TREF3 <= 1'b1;
#10 TREF3 <= 1'b0;
TREF4 <= 1'b1;
#10 TREF4 <= 1'b0;
TREF5 <= 1'b1;
#10 TREF5 <= 1'b0;
TREF6 <= 1'b1;
#10 TREF6 <= 1'b0;
TREF7 <= 1'b1;
#10 TREF7 <= 1'b0;
TREF8 <= 1'b1;
#10 TREF8 <= 1'b0;
TREF9 <= 1'b1;
#10 TREF9 <= 1'b0;
TREF0 <= 1'b1;
end
 
always @ (posedge TREF3) CLKC = 0;
always @ (posedge TREF8) CLKC = 1;
 
/*****************************************************************************************/
/* */
/* initialize input signals */
/* */
/*****************************************************************************************/
initial begin
CLEARB = 1;
DMA_REQ = 0;
INT_REQ = 0;
NMI_REQ = 0;
RESETB = 1;
WAIT_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* initialize testbench variables */
/* */
/*****************************************************************************************/
initial begin
breq_mach = 6'b000000;
CMP_ERR_L = 16'h0000;
CLR_INT = 0;
CLR_NMI = 0;
DISABLE_BREQ = 1;
DISABLE_INT = 1;
DISABLE_WAIT = 1;
INT_TYPE = 0;
PAT_DONE = 0;
TRIG_INT = 0;
TRIG_NMI = 0;
end
 
/*****************************************************************************************/
/* */
/* reset and clear task */
/* */
/*****************************************************************************************/
task resettask;
begin
wait(TREF6);
RESETB = 0;
wait(TREF0);
wait(TREF6);
wait(TREF0);
wait(TREF6);
RESETB = 1;
CLR_INT = 1;
CLR_NMI = 1;
wait(TREF0);
PAT_DONE = 0;
end
endtask
 
task cleartask;
begin
wait(TREF6);
CLEARB = 0;
RESETB = 0;
wait(TREF0);
wait(TREF6);
wait(TREF0);
wait(TREF6);
CLEARB = 1;
RESETB = 1;
CLR_INT = 1;
CLR_NMI = 1;
wait(TREF0);
PAT_DONE = 0;
end
endtask
 
/*****************************************************************************************/
/* */
/* error log */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
if (MEM_WR) CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);
if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT != wr_data);
end
 
/*****************************************************************************************/
/* */
/* end-of-pattern detect */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
PAT_DONE = (MEM_ADDR[15:0] == 16'h00c3);
end
 
/*****************************************************************************************/
/* */
/* interrupt/nmi request generator */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) ||
DISABLE_INT || |breq_mach;
TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) ||
DISABLE_INT || |breq_mach;
CLR_INT = (MEM_ADDR[15:13] == 3'b111);
CLR_NMI = (MEM_ADDR[15:13] == 3'b111);
if (T1) INT_TYPE = MEM_ADDR[8];
end
 
always @ (negedge TRIG_NMI) begin
NMI_REQ = 1;
end
 
always @ (posedge CLR_NMI) begin
NMI_REQ = 0;
end
 
always @ (negedge TRIG_INT) begin
INT_REQ = 1;
end
 
always @ (posedge CLR_INT) begin
wait(TREF0);
wait(TREF4);
wait(TREF0);
wait(TREF4);
INT_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* interrupt request generator (during Halt) */
/* */
/*****************************************************************************************/
integer j;
 
always @ (posedge HALT_TRAN) begin
for (j=0; j < 10; j=j+1) begin
wait (TREF6);
wait (TREF0);
end
wait (TREF6);
INT_REQ = HALT_TRAN && !INT_TYPE;
NMI_REQ = HALT_TRAN && INT_TYPE;
wait (TREF0);
for (j=0; j < 12; j=j+1) begin
wait (TREF6);
wait (TREF0);
end
INT_REQ = 0;
NMI_REQ = 0;
wait (TREF6);
wait (TREF0);
wait (TREF6);
NMI_REQ = HALT_TRAN && INT_TYPE;
wait (TREF0);
wait (TREF6);
wait (TREF0);
NMI_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* wait request generator */
/* */
/*****************************************************************************************/
always @ (posedge CLKC) begin
wait_dly <= T1;
end
 
always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 || wait_dly);
always @ (posedge TREF9) WAIT_REQ = 1'b0;
 
/*****************************************************************************************/
/* */
/* bus request generator */
/* */
/*****************************************************************************************/
always @ (posedge CLKC) begin
breq_mach <= (DISABLE_BREQ) ? 6'b000000 :
(T1) ? 6'b000001 : {breq_mach[4:0], wait_dly};
end
 
always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&
(T1 || |breq_mach[2:0] || (HALT_TRAN && |breq_mach));
 
/*****************************************************************************************/
/* */
/* run the test patterns */
/* */
/*****************************************************************************************/
initial begin
$readmemh("setup_hl.vm", rdmem);
cleartask;
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_WAIT = 0; /* wait generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_BREQ = 0; /* bus req generator on */
DISABLE_WAIT = 1; /* wait generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opss.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
$stop;
end
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*******************************************************************************************/
/** **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** Y80 processor test bench Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
`timescale 1ns / 10ps /* set time scale */
`include "version.v" /* select version */
`include "hierarchy.v" /* include sources */
 
module top_levl;
 
wire DMA_ACK; /* dma acknowledge */
wire HALT_TRAN; /* halt transaction */
wire IACK_TRAN; /* int ack transaction */
wire IO_READ; /* i/o read/write status */
wire IO_STROBE; /* i/o strobe */
wire IO_TRAN; /* i/o transaction */
wire IVEC_RD; /* int vector read strobe */
wire MEM_RD; /* mem read strobe */
wire MEM_TRAN; /* mem transaction */
wire MEM_WR; /* mem write strobe */
wire RETI_TRAN; /* reti transaction */
wire T1; /* first clock of transaction */
wire [7:0] IO_DATA_OUT; /* i/o data output bus */
wire [7:0] MEM_DATA_OUT; /* mem data output bus */
wire [15:0] IO_ADDR; /* i/o address bus */
wire [15:0] MEM_ADDR; /* mem address bus */
 
reg CLEARB; /* master (test) reset */
reg CLKC; /* clock */
reg DMA_REQ; /* dma request */
reg INT_REQ; /* interrupt request */
reg NMI_REQ; /* non-maskable interrupt req */
reg RESETB; /* internal (user) reset */
reg WAIT_REQ; /* wait request */
reg [7:0] IO_DATA_IN; /* i/o data input bus */
reg [7:0] IVEC_DATA_IN; /* vector input bus */
reg [7:0] MEM_DATA_IN; /* mem data input bus */
 
/*****************************************************************************************/
/* */
/* testbench internal variables */
/* */
/*****************************************************************************************/
reg CLR_INT; /* deassert interrupt */
reg CLR_NMI; /* deassert nmi */
reg DISABLE_BREQ; /* bus req generator control */
reg DISABLE_INT; /* interrupt generator control */
reg DISABLE_WAIT; /* wait generator control */
reg INT_TYPE; /* int type during bus req */
reg PAT_DONE; /* pattern done flag */
reg TRIG_INT; /* assert interrupt */
reg TRIG_NMI; /* assert nmi */
reg [2:0] PAT_CNT; /* counter to track patterns */
reg [15:0] CMP_ERR_L; /* error counter */
 
reg wait_dly; /* wait request state machine */
reg [5:0] breq_mach; /* bus request state machine */
 
reg TREF0, TREF1, TREF2, TREF3, TREF4; /* timing generator */
reg TREF5, TREF6, TREF7, TREF8, TREF9;
 
/*****************************************************************************************/
/* */
/* read memory and write data compare memory */
/* */
/*****************************************************************************************/
reg [7:0] rdmem [0:65535];
reg [7:0] wrmem [0:65535];
 
wire [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :
(IO_TRAN) ? wrmem[IO_ADDR] : 8'hxx;
 
wire [7:0] rd_data = rdmem[MEM_ADDR];
wire [7:0] iord_data = rdmem[IO_ADDR];
 
always @ (posedge TREF6) begin
IO_DATA_IN = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;
MEM_DATA_IN = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;
end
 
always @ (posedge TREF6) begin
IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;
end
 
always @ (posedge TREF0) begin
IO_DATA_IN = 8'hxx;
MEM_DATA_IN = 8'hxx;
IVEC_DATA_IN = 8'hxx;
end
 
/*****************************************************************************************/
/* */
/* instantiate the design */
/* */
/*****************************************************************************************/
y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),
.io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),
.io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),
.mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),
.mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),
.clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),
.io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),
.mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),
.wait_req(WAIT_REQ) );
 
/*****************************************************************************************/
/* */
/* timing generator */
/* */
/*****************************************************************************************/
initial begin
TREF0 = 1;
CLKC = 1;
end
 
always begin
#10 TREF0 <= 1'b0;
TREF1 <= 1'b1;
#10 TREF1 <= 1'b0;
TREF2 <= 1'b1;
#10 TREF2 <= 1'b0;
TREF3 <= 1'b1;
#10 TREF3 <= 1'b0;
TREF4 <= 1'b1;
#10 TREF4 <= 1'b0;
TREF5 <= 1'b1;
#10 TREF5 <= 1'b0;
TREF6 <= 1'b1;
#10 TREF6 <= 1'b0;
TREF7 <= 1'b1;
#10 TREF7 <= 1'b0;
TREF8 <= 1'b1;
#10 TREF8 <= 1'b0;
TREF9 <= 1'b1;
#10 TREF9 <= 1'b0;
TREF0 <= 1'b1;
end
 
always @ (posedge TREF3) CLKC = 0;
always @ (posedge TREF8) CLKC = 1;
 
/*****************************************************************************************/
/* */
/* initialize input signals */
/* */
/*****************************************************************************************/
initial begin
CLEARB = 1;
DMA_REQ = 0;
INT_REQ = 0;
NMI_REQ = 0;
RESETB = 1;
WAIT_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* initialize testbench variables */
/* */
/*****************************************************************************************/
initial begin
breq_mach = 6'b000000;
CMP_ERR_L = 16'h0000;
CLR_INT = 0;
CLR_NMI = 0;
DISABLE_BREQ = 1;
DISABLE_INT = 1;
DISABLE_WAIT = 1;
INT_TYPE = 0;
PAT_DONE = 0;
TRIG_INT = 0;
TRIG_NMI = 0;
end
 
/*****************************************************************************************/
/* */
/* reset and clear task */
/* */
/*****************************************************************************************/
task resettask;
begin
wait(TREF6);
RESETB = 0;
wait(TREF0);
wait(TREF6);
wait(TREF0);
wait(TREF6);
RESETB = 1;
CLR_INT = 1;
CLR_NMI = 1;
wait(TREF0);
PAT_DONE = 0;
end
endtask
 
task cleartask;
begin
wait(TREF6);
CLEARB = 0;
RESETB = 0;
wait(TREF0);
wait(TREF6);
wait(TREF0);
wait(TREF6);
CLEARB = 1;
RESETB = 1;
CLR_INT = 1;
CLR_NMI = 1;
wait(TREF0);
PAT_DONE = 0;
end
endtask
 
/*****************************************************************************************/
/* */
/* error log */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
if (MEM_WR) CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);
if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT != wr_data);
end
 
/*****************************************************************************************/
/* */
/* end-of-pattern detect */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
PAT_DONE = (MEM_ADDR[15:0] == 16'h00c3);
end
 
/*****************************************************************************************/
/* */
/* interrupt/nmi request generator */
/* */
/*****************************************************************************************/
always @ (posedge TREF4) begin
TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) ||
DISABLE_INT || |breq_mach;
TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) ||
DISABLE_INT || |breq_mach;
CLR_INT = (MEM_ADDR[15:13] == 3'b111);
CLR_NMI = (MEM_ADDR[15:13] == 3'b111);
if (T1) INT_TYPE = MEM_ADDR[8];
end
 
always @ (negedge TRIG_NMI) begin
NMI_REQ = 1;
end
 
always @ (posedge CLR_NMI) begin
NMI_REQ = 0;
end
 
always @ (negedge TRIG_INT) begin
INT_REQ = 1;
end
 
always @ (posedge CLR_INT) begin
wait(TREF0);
wait(TREF4);
wait(TREF0);
wait(TREF4);
INT_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* interrupt request generator (during Halt) */
/* */
/*****************************************************************************************/
integer j;
 
always @ (posedge HALT_TRAN) begin
for (j=0; j < 10; j=j+1) begin
wait (TREF6);
wait (TREF0);
end
wait (TREF6);
INT_REQ = HALT_TRAN && !INT_TYPE;
NMI_REQ = HALT_TRAN && INT_TYPE;
wait (TREF0);
for (j=0; j < 12; j=j+1) begin
wait (TREF6);
wait (TREF0);
end
INT_REQ = 0;
NMI_REQ = 0;
wait (TREF6);
wait (TREF0);
wait (TREF6);
NMI_REQ = HALT_TRAN && INT_TYPE;
wait (TREF0);
wait (TREF6);
wait (TREF0);
NMI_REQ = 0;
end
 
/*****************************************************************************************/
/* */
/* wait request generator */
/* */
/*****************************************************************************************/
always @ (posedge CLKC) begin
wait_dly <= T1;
end
 
always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 || wait_dly);
always @ (posedge TREF9) WAIT_REQ = 1'b0;
 
/*****************************************************************************************/
/* */
/* bus request generator */
/* */
/*****************************************************************************************/
always @ (posedge CLKC) begin
breq_mach <= (DISABLE_BREQ) ? 6'b000000 :
(T1) ? 6'b000001 : {breq_mach[4:0], wait_dly};
end
 
always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&
(T1 || |breq_mach[2:0] || (HALT_TRAN && |breq_mach));
 
/*****************************************************************************************/
/* */
/* run the test patterns */
/* */
/*****************************************************************************************/
initial begin
$readmemh("setup_hl.vm", rdmem);
cleartask;
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_WAIT = 0; /* wait generator on */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 0; /* interrupt generator on */
DISABLE_BREQ = 0; /* bus req generator on */
DISABLE_WAIT = 1; /* wait generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h1;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("int_ops.vm", rdmem);
$readmemh("int_opss.vm", wrmem);
wait (PAT_DONE);
 
DISABLE_INT = 1; /* interrupt generator off */
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h2;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("alu_ops.vm", rdmem);
$readmemh("alu_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h3;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("dat_mov.vm", rdmem);
$readmemh("dat_movd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h4;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("bit_ops.vm", rdmem);
$readmemh("bit_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h5;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("jmp_ops.vm", rdmem);
$readmemh("jmp_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h6;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("io_ops.vm", rdmem);
$readmemh("io_opsd.vm", wrmem);
wait (PAT_DONE);
 
resettask;
CMP_ERR_L = 16'h0000;
PAT_CNT = 4'h7;
$readmemh("blank_xx.vm", rdmem);
$readmemh("blank_xx.vm", wrmem);
$readmemh("180_ops.vm", rdmem);
$readmemh("180_opsd.vm", wrmem);
wait (PAT_DONE);
 
$stop;
end
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/alu_shft.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** alu shifter module Rev 0.0 07/17/2011 **/
/** alu shifter module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module alu_shft (shft_c, shft_out, alub_in, aluop_reg, carry_bit);
/trunk/rtl/version.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2010, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2010, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** version definition file Rev 0.0 03/28/2010 **/
/** version definition file Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
 
/trunk/rtl/datapath.v
1,8 → 1,9
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** data path module Rev 0.0 08/22/2010 **/
/** data path module Rev 0.0 05/13/2012 **/
/** **/
/*******************************************************************************************/
module datapath (addr_reg_in, carry_bit, dmar_reg, dout_io_reg, dout_mem_reg, inst_reg,
120,7 → 121,7
wire [15:8] bsign_ext; /* address alu b sign extend */
wire [15:0] adda_in, addb_in; /* address alu inputs */
wire [15:0] adder_out; /* math result */
wire [15:0] addr_alu, addr_hl, addr_pc, addr_sp; /* address mux terms */
wire [15:0] addr_alu8, addr_alu, addr_hl, addr_pc, addr_sp; /* address mux terms */
wire [15:0] addr_reg_in; /* address register input */
wire [15:0] alua_in, alub_in; /* alu inputs */
wire [15:0] data_bus; /* alu output */
597,7 → 598,7
.aa_reg_out(aa_reg_out), .bit_mask(bit_mask), .daa_out(daa_out),
.hl_reg_out(hl_reg_out), .ii_reg(ii_reg), .int_addr(int_addr),
.ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .rr_reg(rr_reg),
.rst_addr(rst_addr) );
.rst_addr(rst_addr), .tmp_reg(tmp_reg) );
 
alubmux BMUX ( .addb_in(addb_in), .alub_in(alub_in), .alub_reg(alub_reg),
.af_reg_out(af_reg_out), .bc_reg_out(bc_reg_out), .de_reg_out(de_reg_out),
621,13 → 622,13
 
alu_shft ALUSHFT ( .shft_c(shft_c), .shft_out(shft_out), .alub_in(alub_in[7:0]),
.aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit) );
 
wire [15:0] mult_out = alub_in[15:8] * alub_in[7:0];
aluout ALUOUT ( .cry_nxt(cry_nxt), .data_bus(data_bus), .hcar_nxt(hcar_nxt),
.one_nxt(one_nxt), .par_nxt(par_nxt), .sign_nxt(sign_nxt),
.zero_nxt(zero_nxt), .adder_c(adder_c), .adder_hc(adder_hc),
.adder_out(adder_out), .hi_byte(hi_byte), .logic_c(logic_c),
.logic_hc(logic_hc), .logic_out(logic_out), .shft_c(shft_c),
.shft_out(shft_out), .unit_sel(aluop_reg[7:6]), .word_op(word_op) );
.shft_out(shft_out), .mult_out(mult_out), .unit_sel(aluop_reg[7:6]), .word_op(word_op) );
 
/*****************************************************************************************/
/* */
672,6 → 673,7
always @ (aluop_reg or adda_in or addb_in or bsign_ext) begin
case (aluop_reg)
`ALUOP_ADS: adda_out = adda_in + {bsign_ext[15:8], addb_in[7:0]};
`ALUOP_BADD,
`ALUOP_ADD: adda_out = adda_in + addb_in;
`ALUOP_APAS: adda_out = adda_in;
default: adda_out = addb_in;
678,12 → 680,13
endcase
end
 
assign addr_alu8 = (addsel_reg[`AD_ALU8]) ? {8'h00, adda_out[7:0]} : 16'h0000;
assign addr_alu = (addsel_reg[`AD_ALU]) ? adda_out : 16'h0000;
assign addr_hl = (addsel_reg[`AD_HL]) ? hl_reg_out : 16'h0000;
assign addr_pc = (addsel_reg[`AD_PC]) ? pc_reg : 16'h0000;
assign addr_sp = (addsel_reg[`AD_SP]) ? sp_reg : 16'h0000;
 
assign addr_reg_in = addr_alu | addr_hl | addr_pc | addr_sp;
assign addr_reg_in = addr_alu8 | addr_alu | addr_hl | addr_pc | addr_sp;
 
endmodule
 
/trunk/rtl/aluout.v
1,12 → 1,14
/*******************************************************************************************/
/** **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
/** **/
/** alu function unit combiner module Rev 0.0 07/24/2011 **/
/** alu function unit combiner module Rev 0.0 06/13/2012 **/
/** **/
/*******************************************************************************************/
module aluout (cry_nxt, data_bus, hcar_nxt, one_nxt, par_nxt, sign_nxt, zero_nxt, adder_c,
adder_hc, adder_out, hi_byte, logic_c, logic_hc, logic_out, shft_c, shft_out,
mult_out,
unit_sel, word_op);
 
input adder_c; /* math carry result */
20,6 → 22,7
input [7:0] shft_out; /* shift unit result */
input [15:0] adder_out; /* math unit result */
input [15:0] logic_out; /* logic unit result */
input [15:0] mult_out; /* multiplier unit result */
output cry_nxt; /* carry flag next */
output hcar_nxt; /* half-carry flag next */
output one_nxt; /* one flag next */
44,10 → 47,11
/* alu function unit combination */
/* */
/*****************************************************************************************/
always @ (unit_sel or adder_out or logic_out or shft_out) begin
always @ (unit_sel or adder_out or logic_out or shft_out or mult_out) begin
casex (unit_sel)
2'b01: alu_result = adder_out;
2'b1x: alu_result = {8'h00, shft_out};
2'b10: alu_result = {8'h00, shft_out};
2'b11: alu_result = mult_out;
default: alu_result = logic_out;
endcase
end
/trunk/doc/execute.xls Cannot display: file marked as a binary type. svn:mime-type = application/vnd.ms-excel
/trunk/doc/execute.xls
trunk/doc/execute.xls Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/vnd.ms-excel \ No newline at end of property Index: trunk/doc/execute.ods =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/vnd.oasis.opendocument.spreadsheet

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