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URL https://opencores.org/ocsvn/yac/yac/trunk

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  • This comparison shows the changes necessary to convert path 
    /yac/trunk
    from Rev 10 to Rev 11
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  •

Rev 10 → Rev 11

/c_octave/cordic_iterative.c
123,7 → 123,7
int A_WIDTH,
int GUARD_BITS,
int RM_GAIN );
int cordic_int_dbg ( long long int x,
void cordic_int_dbg ( long long int x,
long long int y,
long long int a,
int mode,
582,7 → 582,7
 
 
 
int cordic_int_dbg( long long int x,
void cordic_int_dbg( long long int x,
long long int y,
long long int a,
int mode,
/test_sys/sw/pc/serial.c
0,0 → 1,3
 
 
 
/test_sys/sw/pc/main.o
0,0 → 1,254
 
 
 
 
 
+EEEEEE࿉EE%EHUEt'HHǸEHMdH3 %(tUsage: TODO timeoutcrc error( %d <-> %d ) +%dError: failed to sync +Error: failed to do test1 +Error: Failed to open serial port %s +TTTcrcT;  +7_mm<TT T!T ">#$I4%I8> tgF1111 1(10181@1H1P1X` +: ; I8 I !I/ + .symtab.strtab.shstrtab.rela.text.data.bss.rodata.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame @x!P&Y,`41`>.9( +main.c__bswap_32global_out_bufglobal_in_bufprint_usage_and_exitputsexitsnd_rcvcrcwritereaddo_syncdo_testcordic_intprintfmain__isoc99_sscanfmemsetinit_serial_portstderrfwriteopenfprintftcgetattr__errno_locationcfsetospeedcfsetispeedtcsetattr__stack_chk_fail +"n + +"  + w}  +   +,$ +,+(2 +,<B T$f( +< +' 9 +?>!]h z +V!"  +x#$%! & +3#N&_'(%  +#) + + +g + +) + 0 +7 +S< +CP +5U +b +i +)p +w +| +( + + + + +l + + + +C% +: +(? +J +U +` +l +Kx + +D + +1 +N + + +] + + +  + +o$ +0 +< + I +V +c +p +Q} +A + +< +! +a +u + + + +> +u  +Y +`& +3 +@ +M +iZ +h +o +{ +S +o +T + + + +K +) +3&W +e +s +} +- + + +L +d T + +> + +j +8 + + +Y0 +8? +N +l +| + +}  + +  @\&| \ No newline at end of file
/test_sys/sw/pc/main.c
0,0 → 1,382
/***************************************************************************
* *
* File : main.c *
* Project : YAC (Yet Another CORDIC Core) *
* Creation : Jun. 2015 *
* Limitations : *
* Platform : Linux *
* Target : Linux-Os *
* *
* Author(s): : Christian Haettich *
* Email : feddischson@opencores.org *
* *
* *
** **
* *
* Description *
* C implementation for a test system: PC part. *
* This implementation sends messages via serial line. *
* Each message contains a calculation request, and each answer *
* contains the calculation result *
* All messages have the same size, starting with a synchronization *
* byte and a header byte. *
* *
* *
****************************************************************************
* *
* Copyright Notice *
* *
* This file is part of YAC - Yet Another CORDIC Core *
* Copyright (c) 2015, Author(s), All rights reserved. *
* *
* YAC is free software; you can redistribute it and/or *
* modify it under the terms of the GNU Lesser General Public *
* License as published by the Free Software Foundation; either *
* version 3.0 of the License, or (at your option) any later version. *
* *
* YAC is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
* Lesser General Public License for more details. *
* *
* You should have received a copy of the GNU Lesser General Public *
* License along with this library. If not, download it from *
* http://www.gnu.org/licenses/lgpl *
* *
***************************************************************************/
 
#include <errno.h>
#include <termios.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <endian.h>
#include <math.h>
 
#include "msg.h"
#include "yac.h"
#include "crc.h"
 
 
/**
* Some error numbers used by this little tool
*/
#define ERR_NONE 0 /* no error */
#define ERR_CRC 1 /* CRC error */
#define ERR_TIMEOUT 2 /* Timeout error */
#define ERR_CALC 3 /* Calculation error */
#define ERR_SYNC 4 /* Synchronization error */
#define ERR_SERIAL 5 /* Serial comm. error */
 
#if 0
#define VERBOSE
#endif
 
 
/*
* implemented in cordic_iterative.c
*/
extern
void cordic_int( long long int x_i,
long long int y_i,
long long int a_i,
long long int * x_o,
long long int * y_o,
long long int * a_o,
int * it_o,
int mode,
int XY_WIDTH,
int A_WIDTH,
int GUARD_BITS,
int RM_GAIN );
 
 
/*
* global message buffers
*/
static Msg global_out_buf;
static Msg global_in_buf;
 
 
/*
* local functions
*/
uint8_t do_test ( int fd, int x, int y, int z, int mode );
uint8_t do_sync ( int fd );
uint8_t run_random_test ( int fd, uint32_t n_test );
int init_serial_port ( char* portname, int baud, int timeout );
void print_usage_and_exit( void );
 
 
 
 
int main( int argc, char* argv[] )
{
int i;
char* portname ;
int baud;
int serial_fd;
int n_tests;
 
if( argc != 4 )
print_usage_and_exit( );
 
if( 1 != sscanf( argv[3], "%d", &n_tests ) )
print_usage_and_exit( );
if( 1 != sscanf( argv[2], "%d", &baud ) )
print_usage_and_exit( );
portname = argv[1];
 
 
 
memset( global_out_buf.bytes, 0, sizeof( Msg ) );
global_out_buf.fields.sync = SYNC_BYTE;
 
 
serial_fd = init_serial_port( portname, baud, 10 );
if( -1 == serial_fd )
return -1;
 
if( ERR_NONE != do_sync( serial_fd ) )
fprintf( stderr, "Error: failed to sync\n" );
 
run_random_test( serial_fd, n_tests );
 
return 0;
}
 
/*
* Prints some usage message
*/
void print_usage_and_exit( void )
{
printf( "Usage: TODO <port> <baud> <n-tests>\n" );
exit( -1 );
}
 
 
 
/**
* Initializes the serial port
*/
int init_serial_port( char* portname, int baud, int timeout )
{
 
struct termios tty;
int serial_fd = open ( portname, O_RDWR | O_NOCTTY | O_SYNC );
if( serial_fd == -1 )
{
fprintf( stderr, "Error: Failed to open serial port %s\n", portname );
return -1;
}
 
memset (&tty, 0, sizeof( tty ) );
if (tcgetattr ( serial_fd, &tty ) != 0)
{
fprintf( stderr, "Error %d from tcgetattr", errno );
return -1;
}
 
cfsetospeed (&tty, baud);
cfsetispeed (&tty, baud);
 
tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8;
tty.c_iflag &= ~IGNBRK;
tty.c_lflag = 0;
 
tty.c_oflag = 0;
tty.c_cc[VMIN] = 0; /* non blocking */
tty.c_cc[VTIME] = 1;
 
tty.c_iflag &= ~(IXON | IXOFF | IXANY); /* shut off xon/xoff ctrl */
tty.c_cflag |= (CLOCAL | CREAD);
tty.c_cflag &= ~(PARENB | PARODD);
tty.c_cflag |= 0; /* parity */
tty.c_cflag &= ~CSTOPB;
tty.c_cflag &= ~CRTSCTS;
 
if (tcsetattr ( serial_fd, TCSANOW, &tty ) != 0)
{
fprintf( stderr, "Error %d from tcsetattr", errno);
return -1;
}
 
return serial_fd;
}
 
 
/**
* Function to send and receive one message.
*
*/
uint8_t snd_rcv( int fd, Msg out_buf, Msg * in_buf, int fail_cnt )
{
int w_bytes, r_bytes;
uint8_t *ptr;
uint8_t crc_in;
out_buf.fields.payload[ 0 ] = htobe32( out_buf.fields.payload[ 0 ] );
out_buf.fields.payload[ 1 ] = htobe32( out_buf.fields.payload[ 1 ] );
out_buf.fields.payload[ 2 ] = htobe32( out_buf.fields.payload[ 2 ] );
 
out_buf.fields.crc = crc( out_buf.bytes, sizeof( Msg )-1 );
 
w_bytes = write( fd, out_buf.bytes, sizeof( Msg ) );
 
if( w_bytes != sizeof( Msg ) )
return ERR_SERIAL;
 
ptr = &in_buf->bytes[ 0 ];
while( w_bytes )
{
r_bytes = read( fd, ptr, w_bytes );
ptr += r_bytes;
w_bytes -= r_bytes;
 
if( --fail_cnt == 0 )
{
#if 0
printf( "timeout\n" );
#endif
return ERR_TIMEOUT;
}
}
crc_in = crc( in_buf->bytes, sizeof( Msg )-1 );
in_buf->fields.payload[ 0 ] = be32toh( in_buf->fields.payload[ 0 ] );
in_buf->fields.payload[ 1 ] = be32toh( in_buf->fields.payload[ 1 ] );
in_buf->fields.payload[ 2 ] = be32toh( in_buf->fields.payload[ 2 ] );
if( crc_in != in_buf->fields.crc )
{
#if 0
printf( "crc error (%x <-> %x )\n", crc_in, in_buf->fields.crc );
#endif
return ERR_CRC;
}
 
if( in_buf->fields.sync == out_buf.fields.sync )
return ERR_NONE;
else
return ERR_SYNC;
}
 
/**
* Send and receive a synchronization message
* ( empty NOP message )
*/
uint8_t do_sync( int fd )
{
uint8_t res;
 
global_out_buf.fields.header = CMD_NOP;
res = snd_rcv( fd, global_out_buf, &global_in_buf, 40 );
if( res != ERR_NONE )
return res;
 
 
if( global_in_buf.fields.sync == global_out_buf.fields.sync &&
global_in_buf.fields.header == global_out_buf.fields.header )
return ERR_NONE;
else
return ERR_SYNC;
}
 
 
 
 
 
/**
* Function to run n_test tests
*
*/
uint8_t run_random_test( int fd, uint32_t n_test )
{
 
uint8_t res;
uint32_t test_cnt = 0;
uint32_t calc_cnt = 0;
uint32_t crc_cnt = 0;
uint32_t othr_cnt = 0;
 
srand( 1234 );
uint32_t i;
for( i=0; i < n_test; i++, test_cnt++ )
{
int32_t y = ( rand() % ( (int32_t) pow( 2, YAC_XY_WIDTH ) ) ) - pow( 2, YAC_XY_WIDTH-1 );
int32_t x = ( rand() % ( (int32_t) pow( 2, YAC_XY_WIDTH ) ) ) - pow( 2, YAC_XY_WIDTH-1 );
 
res = do_test( fd, x, y, 0, YAC_FLAG_VEC_ROT | YAC_MODE_CIR );
 
if( ERR_NONE != res )
{
if( res == ERR_CALC )
calc_cnt++;
else if( res == ERR_CRC )
crc_cnt++;
else
othr_cnt++;
 
}
}
 
printf(" %d of %d tests failed, (crc-errors: %d, other errors: %d )\n",
calc_cnt,
test_cnt,
crc_cnt,
othr_cnt );
 
return ERR_NONE;
}
 
 
/**
* Run one single test
*
*/
uint8_t do_test( int fd, int x, int y, int z, int mode )
{
long long int xo;
long long int yo;
long long int zo;
uint8_t res;
int it;
 
/* local calculation */
cordic_int(
x, y, z, &xo, &yo, &zo, &it, mode,
YAC_XY_WIDTH,
YAC_A_WIDTH,
2,
YAC_RM_GAIN
);
 
 
/* remote calculation */
global_out_buf.fields.header = CMD_CALC;
global_out_buf.fields.payload[ 0 ] = x;
global_out_buf.fields.payload[ 1 ] = y;
global_out_buf.fields.payload[ 2 ] = z;
global_out_buf.fields.mode = mode;
res = snd_rcv( fd, global_out_buf, &global_in_buf, 10 );
if( ERR_NONE != res )
return res;
 
# if defined (VERBOSE)
printf("( %d <-> %d ) \n", global_in_buf.fields.payload[0], (int)xo );
printf("( %d <-> %d ) \n", global_in_buf.fields.payload[1], (int)yo );
printf("( %d <-> %d ) \n", global_in_buf.fields.payload[2], (int)zo );
#endif
 
/* result comparions */
if ( (xo == global_in_buf.fields.payload[0]) &&
(yo == global_in_buf.fields.payload[1]) &&
(zo == global_in_buf.fields.payload[2]) )
return ERR_NONE;
else
return ERR_CALC;
 
}
 
 
/test_sys/sw/pc/serial.h --- test_sys/sw/pc/SConscript (nonexistent) +++ test_sys/sw/pc/SConscript (revision 11) @@ -0,0 +1,13 @@ + +env = Environment( tools = [ 'default' ], + CPPDEFINES = ['OR32_TARGET'], + CPPPATH = [ "../inc", '../../../sw/inc'], + LINKFLAGS = "-lm", + OBJSUFFIX = ['.opc' ], + CCFLAGS = "-Wall -g -Wno-unused-variable" + ) + +target = env.Program( "../test_tool", [ "main.c", "../../../c_octave/cordic_iterative.c", "../src/crc.c" ] ) + + +# vim: filetype=python et ts=3 sw=3
/test_sys/sw/or32/interrupts.c
0,0 → 1,16
// Dummy or32 except vectors
void buserr_except(){}
void dpf_except(){}
void ipf_except(){}
void align_except(){}
void illegal_except(){}
void dtlbmiss_except(){}
void itlbmiss_except(){}
void range_except(){}
void syscall_except(){}
void res1_except(){}
void trap_except(){}
void res2_except(){}
void tick_except(){}
void ext_except(){}
 
/test_sys/sw/or32/interconnect.h
0,0 → 1,10
#ifndef _INTERCONNECT_H_
#define _INTERCONNECT_H_
 
#define UART_BASE 0x90000000
#define UART_IRQ 2
 
#define YAC_BASE 0x9f000000
 
 
#endif
/test_sys/sw/or32/uart.h
0,0 → 1,128
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER 1 /* Out: Interrupt Enable Register */
#define UART_IIR 2 /* In: Interrupt ID Register */
#define UART_FCR 2 /* Out: FIFO Control Register */
#define UART_EFR 2 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 3 /* Out: Line Control Register */
#define UART_MCR 4 /* Out: Modem Control Register */
#define UART_LSR 5 /* In: Line Status Register */
#define UART_MSR 6 /* In: Modem Status Register */
#define UART_SCR 7 /* I/O: Scratch Register */
 
/*
* These are the definitions for the FIFO Control Register
* (16650 only)
*/
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
 
/* 16650 redefinitions */
#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
 
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_LCR_SBC 0x40 /* Set break control */
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
#define UART_LCR_EPAR 0x10 /* Even parity select */
#define UART_LCR_PARITY 0x08 /* Parity Enable */
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
 
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
#define UART_LSR_FE 0x08 /* Frame error indicator */
#define UART_LSR_PE 0x04 /* Parity error indicator */
#define UART_LSR_OE 0x02 /* Overrun error indicator */
#define UART_LSR_DR 0x01 /* Receiver data ready */
 
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
 
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_TOI 0x0c /* Receive time out interrupt */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
 
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
 
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2 0x08 /* Out2 complement */
#define UART_MCR_OUT1 0x04 /* Out1 complement */
#define UART_MCR_RTS 0x02 /* RTS complement */
#define UART_MCR_DTR 0x01 /* DTR complement */
 
/*
* These are the definitions for the Modem Status Register
*/
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 
/*
* These are the definitions for the Extended Features Register
* (StarTech 16C660 only, when DLAB=1)
*/
#define UART_EFR_CTS 0x80 /* CTS flow control */
#define UART_EFR_RTS 0x40 /* RTS flow control */
#define UART_EFR_SCD 0x20 /* Special character detect */
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
 
void uart_init(unsigned long);
void empty_RX( void );
void uart_write( char * p, size_t len );
void uart_putc(char);
char uart_getc(void);
void uart_print_str(char *);
void uart_print_long(unsigned long);
void uart_interrupt();
void uart_print_short(unsigned long ul);
/test_sys/sw/or32/support.h
0,0 → 1,33
/* Support file for or32 tests. This file should is included
in each test. It calls main() function and add support for
basic functions */
 
#ifndef SUPPORT_H
#define SUPPORT_H
 
#include <stdarg.h>
#include <stddef.h>
#include <limits.h>
 
/* Register access macros */
#define REG8(add) *((volatile unsigned char *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG32(add) *((volatile unsigned long *)(add))
 
/* For writing into SPR. */
void mtspr(unsigned long spr, unsigned long value);
 
/* For reading SPR. */
unsigned long mfspr(unsigned long spr);
 
/* Function to be called at entry point - not defined here. */
int main ();
 
/* Prints out a value */
void report(unsigned long value);
 
/* return value by making a syscall */
extern void or32_exit (int i) __attribute__ ((__noreturn__));
 
 
#endif /* SUPPORT_H */
/test_sys/sw/or32/reset.S
0,0 → 1,112
/* Support file for c based tests */
#include "or1200.h"
#include "board.h"
 
.section .stack
.space STACK_SIZE
_stack:
 
.section .reset, "ax"
 
.org 0x100
_reset_vector:
l.nop
l.nop
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
l.addi r9,r0,0x0
l.addi r10,r0,0x0
l.addi r11,r0,0x0
l.addi r12,r0,0x0
l.addi r13,r0,0x0
l.addi r14,r0,0x0
l.addi r15,r0,0x0
l.addi r16,r0,0x0
l.addi r17,r0,0x0
l.addi r18,r0,0x0
l.addi r19,r0,0x0
l.addi r20,r0,0x0
l.addi r21,r0,0x0
l.addi r22,r0,0x0
l.addi r23,r0,0x0
l.addi r24,r0,0x0
l.addi r25,r0,0x0
l.addi r26,r0,0x0
l.addi r27,r0,0x0
l.addi r28,r0,0x0
l.addi r29,r0,0x0
l.addi r30,r0,0x0
l.addi r31,r0,0x0
 
/*
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,MC_BA_MASK
l.addi r5,r0,0x00
l.sw 0(r3),r5
*/
l.movhi r3,hi(_start)
l.ori r3,r3,lo(_start)
l.jr r3
l.nop
 
.section .text
 
_start:
 
.if IC | DC
/* Flush IC and/or DC */
l.addi r10,r0,0
l.addi r11,r0,0
l.addi r12,r0,0
.if IC
l.addi r11,r0,IC_SIZE
.endif
.if DC
l.addi r12,r0,DC_SIZE
.endif
l.sfleu r12,r11
l.bf loop
l.nop
l.add r11,r0,r12
loop:
.if IC
l.mtspr r0,r10,SPR_ICBIR
.endif
.if DC
l.mtspr r0,r10,SPR_DCBIR
.endif
l.sfne r10,r11
l.bf loop
l.addi r10,r10,16
 
/* Enable IC and/or DC */
l.addi r10,r0,(SPR_SR_SM)
.if IC
l.ori r10,r10,(SPR_SR_ICE)
.endif
.if DC
l.ori r10,r10,(SPR_SR_DCE)
.endif
l.mtspr r0,r10,SPR_SR
l.nop
l.nop
l.nop
l.nop
l.nop
.endif
 
/* Set stack pointer */
l.movhi r1,hi(_stack)
l.ori r1,r1,lo(_stack)
 
/* Jump to main */
l.movhi r2,hi(CLABEL(reset))
l.ori r2,r2,lo(CLABEL(reset))
l.jr r2
l.nop
 
/test_sys/sw/or32/main.c
0,0 → 1,184
/***************************************************************************
* *
* File : main.c *
* Project : YAC (Yet Another CORDIC Core) *
* Creation : Jun. 2015 *
* Limitations : *
* Platform : Linux *
* Target : Open Risc MCU (test-system) *
* *
* Author(s): : Christian Haettich *
* Email : feddischson@opencores.org *
* *
* *
** **
* *
* Description *
* C implementation for a test system: Or32 part. *
* This implementation receives messages via serial line. *
* Each message contains a calculation request, and each answer *
* contains the calculation result *
* All messages have the same size, starting with a synchronization *
* byte and a header byte. *
* *
* *
****************************************************************************
* *
* Copyright Notice *
* *
* This file is part of YAC - Yet Another CORDIC Core *
* Copyright (c) 2015, Author(s), All rights reserved. *
* *
* YAC is free software; you can redistribute it and/or *
* modify it under the terms of the GNU Lesser General Public *
* License as published by the Free Software Foundation; either *
* version 3.0 of the License, or (at your option) any later version. *
* *
* YAC is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
* Lesser General Public License for more details. *
* *
* You should have received a copy of the GNU Lesser General Public *
* License along with this library. If not, download it from *
* http://www.gnu.org/licenses/lgpl *
* *
***************************************************************************/
#include "interconnect.h"
#include "support.h"
#include "or1200.h"
 
#include "uart.h"
#include "board.h"
#include <stdint.h>
#include "msg.h"
#include "yac.h"
#include "crc.h"
 
 
static uint8_t byte_cnt;
static uint8_t in_sync;
static void update_buf( uint8_t c );
static void proceed_msg( Msg * m );
 
 
/* our yac instance */
static YAC yac;
 
 
 
int main()
{
uart_init( UART_BASE );
empty_RX( );
 
in_sync = 0;
byte_cnt = 0;
 
yac_init( &yac,
YAC_BASE,
YAC_XY_WIDTH,
YAC_A_WIDTH,
YAC_RM_GAIN,
YAC_N_ENTRIES );
 
 
while(1)
{
update_buf( uart_getc() );
}
}
 
 
/* serial decoding and synchronization */
void update_buf( uint8_t c )
{
/* input buffer */
static Msg buf;
 
 
if( 0 == in_sync && SYNC_BYTE == c )
{
in_sync = 1;
byte_cnt = 1;
buf.bytes[ 0 ] = c;
}
else
if( 1 == in_sync && byte_cnt < sizeof( Msg ) )
{
buf.bytes[ byte_cnt ] = c;
byte_cnt++;
}
else
if( 1 == in_sync && 0 == byte_cnt )
{
byte_cnt++;
if( SYNC_BYTE == c )
buf.bytes[ 0 ] = c;
else
in_sync = 0;
}
 
 
/* we are synchronized and have a full message */
if( in_sync && byte_cnt == sizeof( Msg ) )
{
byte_cnt = 0;
proceed_msg( &buf );
}
 
}
 
void proceed_msg( Msg * m )
{
uint8_t crc_in = crc( m->bytes, sizeof( Msg )-1 );
if( crc_in != m->fields.crc )
{
/* Ignore message!
* The pc will handle the situation, that
* he doesn't get a response!
*/
}
else
if( CMD_NOP == m->fields.header )
{
/* simple echo */
uart_write( (char*)m->bytes, sizeof( Msg ) );
}
 
else
if( CMD_CALC == m->fields.header )
{
 
/* please note: we extract the message fields to the stack
* because of some "Program received signal SIGBUS, Bus error. ... incomplete sequence"
* problem. It seems there is some problem with the alignment
* (or maybe something else, but the problem does not occur if there is no pragma pack in msg.h)
*
* */
int32_t x, xx, y, yy, a, aa;
uint8_t mode;
 
/* extract */
x = m->fields.payload[0];
y = m->fields.payload[1];
a = m->fields.payload[3];
mode = m->fields.mode;
 
/* do the calculation */
yac_single( &yac,
&x, &y, &a, &xx, &yy, &aa, &mode );
 
/* put back the result */
m->fields.payload[ 0 ] = xx;
m->fields.payload[ 1 ] = yy;
m->fields.payload[ 2 ] = aa;
 
/* calculate the crc*/
m->fields.crc = crc( m->bytes, sizeof( Msg )-1 );
 
/* write out the message */
uart_write( (char*)&m->bytes[0], sizeof( Msg ) );
}
 
}
/test_sys/sw/or32/SConscript
0,0 → 1,35
import os
 
env = Environment( ENV = { 'PATH' : os.environ['PATH'] },
tools = [ 'default', 'gcc', 'gnulink' ],
CC = 'or32-elf-gcc',
CXX = 'or32-elf-g++',
LINK = 'or32-elf-ld',
AS = 'or32-elf-as',
AR = 'or32-elf-ar',
CPPPATH = ["./", '../inc', '../../../sw/inc' ],
OBJSUFFIX = ['.oor32' ],
CCFLAGS = "-Wall -mhard-mul -mhard-div -nostdlib -g -O0 -mnewlib",
ASFLAGS = "-Wall -mhard-mul -mhard-div -nostdlib -g -O0 -mnewlib",
LINKFLAGS = "-L /opt_fpga/or32-toolchain/or32-linux/lib -lm -T or32/orp.ld ",
CPPDEFINES = [ 'OR32_TARGET']
)
 
env2 = env.Clone()
env2.Append( ASFLAGS = " -DIC=0 -DDC=0 " )
 
 
src =[
File( "support.c" ),
File( "main.c" ),
File( "uart.c" ),
File( "interrupts.c" ),
File( "except.S" ),
File( "../../../sw/src/yac.c" ),
File( "../src/crc.c" )
]
 
obj = env.Object( src ) + env2.Object( File( "reset.S" ) )
target = env.Program( '../test_sys_sw.or32', obj )
 
# vim: filetype=python et ts=3 sw=3
/test_sys/sw/or32/except.S
0,0 → 1,152
#include "or1200.h"
 
// Linked from 0x200, so subtract 0x200 from each .org
.section .vectors, "ax"
 
/*
.org 0x100
 
_reset:
l.nop
l.j _reset_except
l.nop
*/
 
/* This cannot be a regular function because it would waste the return register r9 of the interrupted procedure. */
/* Furthermore, if this would be a function and l.j handler would be outside of this, the return register set here would be use upon return of this function. */
/* However, the desired behavior is to finish the handler and let the return of the service routine simply restore the registers and return to the interrupted procedure. */
#define intr_handler(handler) \
l.nop ;\
l.addi r1,r1,-244 /*free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1)*/;\
/*plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) */;\
l.sw 0x18(r1),r9 /*save register r9(return addr) to stack*/;\
l.jal store_regs /*save registers r3-r31 (except r9) to stack (r9 is changed here)*/;\
l.nop ;\
;\
l.movhi r9,hi(end_except) /*set return addr to end_except instruction*/;\
l.ori r9,r9,lo(end_except)/*set return addr to end_except instruction*/;\
l.j CLABEL(handler) ;\
l.nop
 
.org 0x000
_except_200:
intr_handler(buserr_except)
 
.org 0x100
_except_300:
intr_handler(dpf_except)
 
.org 0x200
_except_400:
intr_handler(ipf_except)
 
.org 0x300
_except_500:
intr_handler(tick_except)
 
.org 0x400
_except_600:
intr_handler(align_except)
 
.org 0x500
_except_700:
intr_handler(illegal_except)
 
.org 0x600
_except_800:
intr_handler(ext_except)
 
.org 0x700
_except_900:
intr_handler(dtlbmiss_except)
 
.org 0x800
_except_a00:
intr_handler(itlbmiss_except)
 
.org 0x900
_except_b00:
intr_handler(range_except)
 
.org 0xa00
_except_c00:
intr_handler(syscall_except)
 
.org 0xb00
_except_d00:
intr_handler(res1_except)
 
.org 0xc00
_except_e00:
intr_handler(trap_except)
 
.org 0xd00
_except_f00:
intr_handler(res2_except)
 
store_regs: //save registers r3-r31 (except r9) to stack
l.sw 0x00(r1),r3
l.sw 0x04(r1),r4
l.sw 0x08(r1),r5
l.sw 0x0c(r1),r6
l.sw 0x10(r1),r7
l.sw 0x14(r1),r8
l.sw 0x1c(r1),r10
l.sw 0x20(r1),r11
l.sw 0x24(r1),r12
l.sw 0x28(r1),r13
l.sw 0x2c(r1),r14
l.sw 0x30(r1),r15
l.sw 0x34(r1),r16
l.sw 0x38(r1),r17
l.sw 0x3c(r1),r18
l.sw 0x40(r1),r19
l.sw 0x44(r1),r20
l.sw 0x48(r1),r21
l.sw 0x4c(r1),r22
l.sw 0x50(r1),r23
l.sw 0x54(r1),r24
l.sw 0x58(r1),r25
l.sw 0x5c(r1),r26
l.sw 0x60(r1),r27
l.sw 0x64(r1),r28
l.sw 0x68(r1),r29
l.sw 0x6c(r1),r30
l.sw 0x70(r1),r31
l.jr r9
l.nop
 
end_except: //load back registers from stack r3-r31
l.lwz r3,0x00(r1)
l.lwz r4,0x04(r1)
l.lwz r5,0x08(r1)
l.lwz r6,0x0c(r1)
l.lwz r7,0x10(r1)
l.lwz r8,0x14(r1)
l.lwz r9,0x18(r1)
l.lwz r10,0x1c(r1)
l.lwz r11,0x20(r1)
l.lwz r12,0x24(r1)
l.lwz r13,0x28(r1)
l.lwz r14,0x2c(r1)
l.lwz r15,0x30(r1)
l.lwz r16,0x34(r1)
l.lwz r17,0x38(r1)
l.lwz r18,0x3c(r1)
l.lwz r19,0x40(r1)
l.lwz r20,0x44(r1)
l.lwz r21,0x48(r1)
l.lwz r22,0x4c(r1)
l.lwz r23,0x50(r1)
l.lwz r24,0x54(r1)
l.lwz r25,0x58(r1)
l.lwz r26,0x5c(r1)
l.lwz r27,0x60(r1)
l.lwz r28,0x64(r1)
l.lwz r29,0x68(r1)
l.lwz r30,0x6c(r1)
l.lwz r31,0x70(r1)
l.addi r1,r1,244 //free stack places
l.rfe //recover SR register and prior PC (jumps back to program)
l.nop
 
/test_sys/sw/or32/or1200.h
0,0 → 1,454
/* or1200.h -- Defines OR1K architecture specific special-purpose registers
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This file is also used by microkernel test bench. Among
others it is also used in assembly file(s). */
 
#define __CLABEL(prefix, label) prefix ## label
#define _CLABEL(prefix, label) __CLABEL(prefix, label)
#define CLABEL(label) _CLABEL(__USER_LABEL_PREFIX__, label)
 
/* Definition of special-purpose registers (SPRs) */
 
#define MAX_GRPS (32)
#define MAX_SPRS_PER_GRP_BITS (11)
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
#define MAX_SPRS (0x10000)
 
/* Base addresses for the groups */
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
 
/* System control and status group */
#define SPR_VR (SPRGROUP_SYS + 0)
#define SPR_UPR (SPRGROUP_SYS + 1)
#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
#define SPR_DCCFGR (SPRGROUP_SYS + 5)
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
 
#if 0
/* Data MMU group */
#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
 
/* Instruction MMU group */
#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
#else
 
/* Data MMU group */
#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
 
/* Instruction MMU group */
#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
#endif
/* Data cache group */
#define SPR_DCCR (SPRGROUP_DC + 0)
#define SPR_DCBPR (SPRGROUP_DC + 1)
#define SPR_DCBFR (SPRGROUP_DC + 2)
#define SPR_DCBIR (SPRGROUP_DC + 3)
#define SPR_DCBWR (SPRGROUP_DC + 4)
#define SPR_DCBLR (SPRGROUP_DC + 5)
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
 
/* Instruction cache group */
#define SPR_ICCR (SPRGROUP_IC + 0)
#define SPR_ICBPR (SPRGROUP_IC + 1)
#define SPR_ICBIR (SPRGROUP_IC + 2)
#define SPR_ICBLR (SPRGROUP_IC + 3)
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
 
/* MAC group */
#define SPR_MACLO (SPRGROUP_MAC + 1)
#define SPR_MACHI (SPRGROUP_MAC + 2)
 
/* Debug group */
#define SPR_DVR(N) (SPRGROUP_D + (N))
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
#define SPR_DMR1 (SPRGROUP_D + 16)
#define SPR_DMR2 (SPRGROUP_D + 17)
#define SPR_DWCR0 (SPRGROUP_D + 18)
#define SPR_DWCR1 (SPRGROUP_D + 19)
#define SPR_DSR (SPRGROUP_D + 20)
#define SPR_DRR (SPRGROUP_D + 21)
 
/* Performance counters group */
#define SPR_PCCR(N) (SPRGROUP_PC + (N))
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
 
/* Power management group */
#define SPR_PMR (SPRGROUP_PM + 0)
 
/* PIC group */
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICPR (SPRGROUP_PIC + 1)
#define SPR_PICSR (SPRGROUP_PIC + 2)
 
/* Tick Timer group */
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTCR (SPRGROUP_TT + 1)
 
/*
* Bit definitions for the Version Register
*
*/
#define SPR_VR_VER 0xffff0000 /* Processor version */
#define SPR_VR_REV 0x0000003f /* Processor revision */
 
/*
* Bit definitions for the Unit Present Register
*
*/
#define SPR_UPR_UP 0x00000001 /* UPR present */
#define SPR_UPR_DCP 0x00000002 /* Data cache present */
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
#define SPR_UPR_PMP 0x00002000 /* Power management present */
#define SPR_UPR_PICP 0x00004000 /* PIC present */
#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
#define SPR_UPR_CUST 0xff000000 /* Custom units */
 
/*
* Bit definitions for the Supervision Register
*
*/
#define SPR_SR_CID 0xf0000000 /* Context ID */
#define SPR_SR_FO 0x00008000 /* Fixed one */
#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
#define SPR_SR_OV 0x00000800 /* Overflow flag */
#define SPR_SR_CY 0x00000400 /* Carry flag */
#define SPR_SR_F 0x00000200 /* Condition Flag */
#define SPR_SR_CE 0x00000100 /* CID Enable */
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
 
/*
* Bit definitions for the Data MMU Control Register
*
*/
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
 
/*
* Bit definitions for the Instruction MMU Control Register
*
*/
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
 
/*
* Bit definitions for the Data TLB Match Register
*
*/
#define SPR_DTLBMR_V 0x00000001 /* Valid */
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
 
/*
* Bit definitions for the Data TLB Translate Register
*
*/
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
#define SPR_DTLBTR_A 0x00000010 /* Accessed */
#define SPR_DTLBTR_D 0x00000020 /* Dirty */
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
SPR_DTLBTR_UWE | \
SPR_DTLBTR_SRE | \
SPR_DTLBTR_SWE )
/*
* Bit definitions for the Instruction TLB Match Register
*
*/
#define SPR_ITLBMR_V 0x00000001 /* Valid */
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
 
/*
* Bit definitions for the Instruction TLB Translate Register
*
*/
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A 0x00000010 /* Accessed */
#define SPR_ITLBTR_D 0x00000020 /* Dirty */
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
SPR_ITLBTR_UXE )
 
 
/*
* Bit definitions for Data Cache Control register
*
*/
#define SPR_DCCR_EW 0x000000ff /* Enable ways */
 
/*
* Bit definitions for Insn Cache Control register
*
*/
#define SPR_ICCR_EW 0x000000ff /* Enable ways */
 
/*
* Bit definitions for Debug Control registers
*
*/
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
#define SPR_DCR_CC 0x0000000e /* Compare condition */
#define SPR_DCR_SC 0x00000010 /* Signed compare */
#define SPR_DCR_CT 0x000000e0 /* Compare to */
 
/* Bit results with SPR_DCR_CC mask */
#define SPR_DCR_CC_MASKED 0x00000000
#define SPR_DCR_CC_EQUAL 0x00000001
#define SPR_DCR_CC_LESS 0x00000002
#define SPR_DCR_CC_LESSE 0x00000003
#define SPR_DCR_CC_GREAT 0x00000004
#define SPR_DCR_CC_GREATE 0x00000005
#define SPR_DCR_CC_NEQUAL 0x00000006
 
/* Bit results with SPR_DCR_CT mask */
#define SPR_DCR_CT_DISABLED 0x00000000
#define SPR_DCR_CT_IFEA 0x00000020
#define SPR_DCR_CT_LEA 0x00000040
#define SPR_DCR_CT_SEA 0x00000060
#define SPR_DCR_CT_LD 0x00000080
#define SPR_DCR_CT_SD 0x000000a0
#define SPR_DCR_CT_LSEA 0x000000c0
 
/*
* Bit definitions for Debug Mode 1 register
*
*/
#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
#define SPR_DMR1_BT 0x00800000 /* Branch trace */
#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
 
/*
* Bit definitions for Debug Mode 2 register
*
*/
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
 
/*
* Bit definitions for Debug watchpoint counter registers
*
*/
#define SPR_DWCR_COUNT 0x0000ffff /* Count */
#define SPR_DWCR_MATCH 0xffff0000 /* Match */
 
/*
* Bit definitions for Debug stop register
*
*/
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */
#define SPR_DSR_AE 0x00000020 /* Alignment exception */
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
#define SPR_DSR_RE 0x00000400 /* Range exception */
#define SPR_DSR_SCE 0x00000800 /* System call exception */
#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
#define SPR_DSR_TE 0x00002000 /* Trap exception */
 
/*
* Bit definitions for Debug reason register
*
*/
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
#define SPR_DRR_AE 0x00000020 /* Alignment exception */
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
#define SPR_DRR_RE 0x00000400 /* Range exception */
#define SPR_DRR_SCE 0x00000800 /* System call exception */
#define SPR_DRR_TE 0x00001000 /* Trap exception */
 
/*
* Bit definitions for Performance counters mode registers
*
*/
#define SPR_PCMR_CP 0x00000001 /* Counter present */
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
#define SPR_PCMR_LA 0x00000010 /* Load access event */
#define SPR_PCMR_SA 0x00000020 /* Store access event */
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
 
/*
* Bit definitions for the Power management register
*
*/
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
 
/*
* Bit definitions for PICMR
*
*/
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
 
/*
* Bit definitions for PICPR
*
*/
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
 
/*
* Bit definitions for PICSR
*
*/
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
 
/*
* Bit definitions for Tick Timer Control Register
*
*/
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
#define SPR_TTMR_RT 0x40000000 /* Restart tick */
#define SPR_TTMR_SR 0x80000000 /* Single run */
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
#define SPR_TTMR_M 0xc0000000 /* Tick mode */
 
/*
* l.nop constants
*
*/
#define NOP_NOP 0x0000 /* Normal nop instruction */
#define NOP_EXIT 0x0001 /* End of simulation */
#define NOP_REPORT 0x0002 /* Simple report */
#define NOP_PRINTF 0x0003 /* Simprintf instruction */
#define NOP_REPORT_FIRST 0x0400 /* Report with number */
#define NOP_REPORT_LAST 0x03ff /* Report with number */
/test_sys/sw/or32/uart.c
0,0 → 1,161
#include "board.h"
#include "support.h"
#include "uart.h"
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(uart_base + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
{\
unsigned char lsr; \
do { \
lsr = REG8(uart_base + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR); \
}
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
static unsigned long uart_base = 0;
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(unsigned long base)
{
int divisor;
uart_base = base;
/* Reset receiver and transmiter */
/* Set RX interrupt for each byte */
REG8(uart_base + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
 
/* Enable RX interrupt
REG8(uart_base + UART_IER) = UART_IER_RDI | UART_IER_THRI; */
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(uart_base + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
/* Set baud rate */
divisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(uart_base + UART_LCR) |= UART_LCR_DLAB;
REG8(uart_base + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(uart_base + UART_DLL) = divisor & 0x000000ff;
REG8(uart_base + UART_LCR) &= ~(UART_LCR_DLAB);
 
return;
}
 
void uart_putc(char c)
{
unsigned char lsr;
 
WAIT_FOR_THRE;
REG8(uart_base + UART_TX) = c;
WAIT_FOR_XMITR;
}
 
 
void empty_RX( void )
{
char c;
while( CHECK_FOR_CHAR )
c = REG8(uart_base + UART_RX);
 
}
 
 
char uart_getc()
{
char c;
unsigned char lsr;
do {
lsr = REG8(uart_base + UART_LSR);
} while ((lsr & UART_LSR_DR) != UART_LSR_DR);
 
c = REG8(uart_base + UART_RX);
return c;
}
 
 
void uart_interrupt()
{
char lala;
unsigned char interrupt_id;
interrupt_id = REG8(uart_base + UART_IIR);
if ( interrupt_id & UART_IIR_RDI )
{
lala = uart_getc();
uart_putc(lala+1);
}
 
}
 
 
void uart_write( char * p, size_t len )
{
while( len-- )
{
uart_putc(*p++);
}
}
 
void uart_print_str(char *p)
{
while(*p != 0) {
uart_putc(*p);
p++;
}
}
 
void uart_print_long(unsigned long ul)
{
int i;
char c;
 
 
uart_print_str("0x");
for(i=0; i<8; i++) {
 
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
uart_putc(c);
}
 
}
 
void uart_print_short(unsigned long ul)
{
int i;
char c;
char flag=0;
 
 
uart_print_str("0x");
for(i=0; i<8; i++) {
 
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
if ((c != '0') || (i==7))
flag=1;
if(flag)
uart_putc(c);
}
 
}
/test_sys/sw/or32/board.h
0,0 → 1,14
#ifndef _BOARD_H_
#define _BOARD_H_
 
#define MC_ENABLED 0
#define IC_ENABLE 0
#define IC_SIZE 8192
#define DC_ENABLE 0
#define DC_SIZE 8192
#define IN_CLK 50000000
#define STACK_SIZE 0x00100
#define UART_BAUD_RATE 115200
 
 
#endif
/test_sys/sw/or32/support.c
0,0 → 1,124
/* Support */
 
#ifndef OR32
#include <sys/time.h>
#endif
 
#include "or1200.h"
#include "support.h"
 
#ifdef UART_PRINTF
#include <uart.h>
#endif
 
#if OR32
void int_main();
 
#if 0
void ext_except()
{
int_main();
}
#endif
 
/* Start function, called by reset exception handler. */
void reset ()
{
int i = main();
or32_exit (i);
}
 
/* return value by making a syscall */
void or32_exit (int i)
{
asm("l.add r3,r0,%0": : "r" (i));
asm("l.nop %0": :"K" (NOP_EXIT));
while (1);
}
 
#ifdef UART_PRINTF
 
static int uart_init_done = 0;
 
#define PRINTFBUFFER_SIZE 512
char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer
 
void minsoc_printf(const char *fmt, ...)
{
// init uart if not done already
if (!uart_init_done)
{
uart_init();
uart_init_done = 1;
}
 
va_list args;
va_start(args, fmt);
 
//int str_l = vsnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
int str_l = vfnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
 
if (!str_l) return; // no length string - just return
 
int c=0;
// now print each char via the UART
while (c < str_l)
uart_putc(PRINTFBUFFER[c++]);
 
va_end(args);
}
 
#else
/* activate printf support in simulator */
void minsoc_printf(const char *fmt, ...)
{
va_list args;
va_start(args, fmt);
__asm__ __volatile__ (" l.addi\tr3,%1,0\n \
l.addi\tr4,%2,0\n \
l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args));
}
 
#endif
 
 
 
 
/* print long */
void report(unsigned long value)
{
asm("l.addi\tr3,%0,0": :"r" (value));
asm("l.nop %0": :"K" (NOP_REPORT));
}
 
/* just to satisfy linker */
void __main()
{
}
 
/* start_TIMER */
void start_timer(int x)
{
}
 
/* For writing into SPR. */
void mtspr(unsigned long spr, unsigned long value)
{
asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
}
 
/* For reading SPR. */
unsigned long mfspr(unsigned long spr)
{
unsigned long value;
asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
return value;
}
 
#else
void report(unsigned long value)
{
printf("report(0x%x);\n", (unsigned) value);
}
 
#endif
/test_sys/sw/or32/orp.ld
0,0 → 1,60
MEMORY
{
reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
}
 
SECTIONS
{
.reset :
{
*(.reset)
} > reset
 
 
.vectors :
{
_vec_start = .;
*(.vectors)
_vec_end = .;
} > vectors
 
.text :
{
*(.text)
} > ram
 
.rodata :
{
*(.rodata)
*(.rodata.*)
} > ram
.icm :
{
_icm_start = .;
*(.icm)
_icm_end = .;
} > ram
 
.data :
{
_dst_beg = .;
*(.data)
_dst_end = .;
} > ram
.bss :
{
*(.bss)
} > ram
.stack (NOLOAD) :
{
*(.stack)
_src_addr = .;
} > ram
 
}
/test_sys/sw/SConstruct
0,0 → 1,5
 
SConscript( [ 'pc/SConscript',
'or32/SConscript' ])
 
# vim: set filetype=python
/test_sys/sw/src/crc.o
0,0 → 1,23
+d .symtab.strtab.shstrtab.text.data.bss.rela.debug_info.debug_abbrev.rela.debug_aranges.rela.debug_line.debug_str.comment.note.GNU-stack.rela.eh_frame@i!'1, +  + icrc.ccrc + + Q +% +, + 3 + A + F + S + Z + a + h + ?w + +  +n  \ No newline at end of file
/test_sys/sw/src/crc.c
0,0 → 1,21
#include <stdint.h>
 
/*
* Message size up to 2^8 byte only!
*/
uint8_t crc( uint8_t *data, uint8_t l, uint8_t crc_init )
{
uint8_t i, j;
uint8_t crc = 0;
 
for ( i = 0; i<l; i++ ) {
crc ^= ( *data );
for(j = 0; j<8; j++) {
if (crc & 0x80)
crc ^= 0x07;
crc <<= 1;
}
data++;
}
return (uint8_t)crc;
}
/test_sys/sw/inc/msg.h
0,0 → 1,26
#ifndef _MSG_H_
#define _MSG_H_
#include <stdint.h>
 
#define SYNC_BYTE 0x55
 
#define CMD_NOP 0x00
#define CMD_CALC 0x10
 
 
#pragma pack( push, 1 )
typedef union _MSG_ {
struct _fields_ {
uint8_t sync;
uint8_t header;
uint8_t mode;
int32_t payload[ 3 ];
uint8_t crc;
}fields;
 
uint8_t bytes[ sizeof( struct _fields_ ) ];
 
}Msg;
#pragma pack( pop )
 
#endif
/test_sys/sw/inc/crc.h
0,0 → 1,7
#ifndef _CRC_H_
#define _CRC_H_
 
uint8_t crc( uint8_t *data, uint8_t l );
 
 
#endif
/test_sys/sw/gdb.cmd
0,0 → 1,4
target remote localhost:9999
load
set $pc=0x100
c
/test_sys/README.txt
1,5 → 1,36
 
 
---------------------------------------
Author: C. Hättich (feddischson@gmx.com)
Date: 22 June 2015
---------------------------------------
 
Introduction
============
A simple test system is used to test the YAC core on a
Spartan 3an starter kit (Xilinx). This test system
is based on a or32 CPU with some on-chip ram and an uart.
 
The system is created with the tool
soc_maker (see https://github.com/feddischson/soc_maker),
which takes the configuration file test_sys.yaml and generates
all the required files.
The result is placed in ./build.
 
The software contains two parts, a PC part and a embedded part.
Both are build with SCons (see www.scons.org),
a replacement for make.
 
The PC part creates test patterns and sends them to the test-system
on the FPGA. The test system calculates the CORDIC result and sends it back.
This result is compared with a software based calculation.
 
 
 
 
 
Dependencies:
=============
- SVN / Git
- SOC-Maker
- SCons
11,24 → 42,46
the procedure below needs to be adapted)
 
 
Description
===========
 
Do the following to get the test system working:
 
 
 
# replace <Version> in order to match your SOC-Maker version
git clone --branch <Version> https://github.com/feddischson/soc_maker_lib.git
 
# initialize the soc_maker_lib
soc_maker -i -l soc_maker_lib
 
# create the system
soc_maker test_system.yaml
soc_maker -l ./ test_system.yaml
 
 
 
# create a Xilinx project file and synthesize all files
# from ./rtl and ./build
 
# program your FPGA
 
# Build the software
# todo ...
# program your FPGA and start the adv_jtag_bridge
#
 
impact # and do the programming
./adv_jtag_bridge -t -b <PATH_TO_BSDLS_FILES> -x 1 xpc_usb
 
 
#
# Build and run the software
#
 
# in terminal 1:
cd sw
scons
or32-elf-gdb test_sys_sw.or32 -x gdb.cmd
 
 
#in terminal 2:
cd sw
./test_tool /dev/ttyUSB0 115200 2000 #replace /dev/ttyUSB0 with our serial port
 
 

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