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URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /yifive/trunk
    from Rev 16 to Rev 15
    Reverse comparison

Rev 16 → Rev 15

/caravel_yifive/verilog/rtl/syntacore_scr1/src/ahb_top.files
0,0 → 1,8
top/scr1_dmem_router.sv
top/scr1_imem_router.sv
top/scr1_dp_memory.sv
top/scr1_tcm.sv
top/scr1_timer.sv
top/scr1_dmem_ahb.sv
top/scr1_imem_ahb.sv
top/scr1_top_ahb.sv
/caravel_yifive/verilog/rtl/syntacore_scr1/src/axi_top.files
0,0 → 1,7
top/scr1_dmem_router.sv
top/scr1_imem_router.sv
top/scr1_dp_memory.sv
top/scr1_tcm.sv
top/scr1_timer.sv
top/scr1_mem_axi.sv
top/scr1_top_axi.sv
/caravel_yifive/verilog/rtl/syntacore_scr1/src/core.files
0,0 → 1,21
core/pipeline/scr1_pipe_hdu.sv
core/pipeline/scr1_pipe_tdu.sv
core/pipeline/scr1_ipic.sv
core/pipeline/scr1_pipe_csr.sv
core/pipeline/scr1_pipe_exu.sv
core/pipeline/scr1_pipe_ialu.sv
core/pipeline/scr1_pipe_idu.sv
core/pipeline/scr1_pipe_ifu.sv
core/pipeline/scr1_pipe_lsu.sv
core/pipeline/scr1_pipe_mprf.sv
core/pipeline/scr1_pipe_top.sv
core/primitives/scr1_reset_cells.sv
core/primitives/scr1_cg.sv
core/scr1_clk_ctrl.sv
core/scr1_tapc_shift_reg.sv
core/scr1_tapc.sv
core/scr1_tapc_synchronizer.sv
core/scr1_core_top.sv
core/scr1_dm.sv
core/scr1_dmi.sv
core/scr1_scu.sv
/caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim
0,0 → 1,2
vlib work
vlog -f wb_top.files -f core.files +incdir+includes -sv
caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files =================================================================== --- caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files (nonexistent) +++ caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files (revision 15) @@ -0,0 +1,9 @@ +top/scr1_dmem_router.sv +top/scr1_imem_router.sv +top/scr1_dp_memory.sv +top/scr1_tcm.sv +top/scr1_timer.sv +top/scr1_dmem_wb.sv +top/scr1_imem_wb.sv +top/scr1_top_wb.sv +../../lib/sync_fifo.sv

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