Subversion Repositories yifive

/trunk/caravel_yifive/openlane/spi_master/pin_order.cfg File deleted

/trunk/caravel_yifive/openlane/spi_master/config.tcl File deleted

trunk/caravel_yifive/openlane/spi_master/config.tcl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/caravel_yifive/openlane/syntacore/config.tcl =================================================================== --- trunk/caravel_yifive/openlane/syntacore/config.tcl (revision 18) +++ trunk/caravel_yifive/openlane/syntacore/config.tcl (revision 17) @@ -3,7 +3,7 @@ set script_dir [file dirname [file normalize [info script]]] # Name -set ::env(DESIGN_NAME) scr1_top_wb +set ::env(DESIGN_NAME) scr1_top_axi # This is macro set ::env(DESIGN_IS_CORE) 0 @@ -26,36 +26,34 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \ - $script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \ - $script_dir/../../verilog/rtl/lib/sync_fifo.sv " + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv \ + $script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore_scr1/src/includes ] #set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_rx.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_tx.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/filelist.f File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_top.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_fifo.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_clkgen.sv File deleted

/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_ctrl.sv File deleted

/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv