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Rev 5 → Rev 6

/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/axi_tb.files File deleted \ No newline at end of file
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv
58,12 → 58,12
//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef struct {
typedef struct packed { // cp.6
logic vd;
logic idx;
} type_scr1_search_one_2_s;
 
typedef struct {
typedef struct packed { // cp.6
logic vd;
logic [SCR1_IRQ_VECT_WIDTH-1:0] idx;
} type_scr1_search_one_16_s;
93,9 → 93,9
begin
tmp.vd = |din;
tmp.idx = ~din[0];
return tmp;
scr1_search_one_2 = tmp;
end
endfunction : scr1_search_one_2
endfunction
 
function automatic type_scr1_search_one_16_s scr1_search_one_16(
input logic [15:0] din
109,10 → 109,9
logic [1:0] stage2_idx [3:0];
logic [2:0] stage3_idx [1:0];
type_scr1_search_one_16_s result;
 
integer i; // cp.17
// Stage 1
for (int unsigned i=0; i<8; ++i) begin
type_scr1_search_one_2_s tmp;
for (i=0; i<8; i=i+1) begin
tmp = scr1_search_one_2(din[(i+1)*2-1-:2]);
stage1_vd[i] = tmp.vd;
stage1_idx[i] = tmp.idx;
119,8 → 118,7
end
 
// Stage 2
for (int unsigned i=0; i<4; ++i) begin
type_scr1_search_one_2_s tmp;
for (i=0; i<4; i=i+1) begin
tmp = scr1_search_one_2(stage1_vd[(i+1)*2-1-:2]);
stage2_vd[i] = tmp.vd;
stage2_idx[i] = (~tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
127,8 → 125,7
end
 
// Stage 3
for (int unsigned i=0; i<2; ++i) begin
type_scr1_search_one_2_s tmp;
for (i=0; i<2; i=i+1) begin
tmp = scr1_search_one_2(stage2_vd[(i+1)*2-1-:2]);
stage3_vd[i] = tmp.vd;
stage3_idx[i] = (~tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
138,9 → 135,9
result.vd = |stage3_vd;
result.idx = (stage3_vd[0]) ? {1'b0, stage3_idx[0]} : {1'b1, stage3_idx[1]};
 
return result;
scr1_search_one_16 = result;
end
endfunction : scr1_search_one_16
endfunction
 
//------------------------------------------------------------------------------
// Local signals declaration
466,10 → 463,10
 
assign ipic_ipr_clr_cond = ~irq_lvl | ipic_imr_next;
assign ipic_ipr_clr = ipic_ipr_clr_req & ipic_ipr_clr_cond;
 
integer i;
always_comb begin
ipic_ipr_next = '0;
for (int unsigned i=0; i<SCR1_IRQ_VECT_NUM; ++i) begin
for (i=0; i<SCR1_IRQ_VECT_NUM; i=i+1) begin
ipic_ipr_next[i] = ipic_ipr_clr[i] ? 1'b0
: ~ipic_imr_ff[i] ? irq_lvl[i]
: ipic_ipr_ff[i] | irq_edge_detected[i];
586,14 → 583,68
 
assign irq_req_v = ipic_ipr_ff & ipic_ier_ff;
 
/*** Modified for Yosys handing typedef in function - dinesha
assign irr_priority = scr1_search_one_16(irq_req_v);
assign irq_req_vd = irr_priority.vd;
assign irq_req_idx = irr_priority.idx;
****/
 
always_comb
begin
casex(irq_req_v)
16'bxxxx_xxxx_xxxx_xxx1 : irq_req_idx = 0;
16'bxxxx_xxxx_xxxx_xx10 : irq_req_idx = 1;
16'bxxxx_xxxx_xxxx_x100 : irq_req_idx = 2;
16'bxxxx_xxxx_xxxx_1000 : irq_req_idx = 3;
16'bxxxx_xxxx_xxx1_0000 : irq_req_idx = 4;
16'bxxxx_xxxx_xx10_0000 : irq_req_idx = 5;
16'bxxxx_xxxx_x100_0000 : irq_req_idx = 6;
16'bxxxx_xxxx_1000_0000 : irq_req_idx = 7;
16'bxxxx_xxx1_0000_0000 : irq_req_idx = 8;
16'bxxxx_xx10_0000_0000 : irq_req_idx = 9;
16'bxxxx_x100_0000_0000 : irq_req_idx = 10;
16'bxxxx_1000_0000_0000 : irq_req_idx = 11;
16'bxxx1_0000_0000_0000 : irq_req_idx = 12;
16'bxx10_0000_0000_0000 : irq_req_idx = 13;
16'bx100_0000_0000_0000 : irq_req_idx = 14;
16'b1000_0000_0000_0000 : irq_req_idx = 15;
16'b0000_0000_0000_0000 : irq_req_idx = 16;
default : irq_req_idx = 16;
endcase
irq_req_vd = |irq_req_v;
end
 
/*** Modified for Yosys handing typedef in function - dinesha
assign isvr_priority_eoi = scr1_search_one_16(ipic_isvr_eoi);
assign irq_eoi_req_vd = isvr_priority_eoi.vd;
assign irq_eoi_req_idx = isvr_priority_eoi.idx;
*************************************************/
 
always_comb
begin
casex(ipic_isvr_eoi)
16'bxxxx_xxxx_xxxx_xxx1 : irq_eoi_req_idx = 0;
16'bxxxx_xxxx_xxxx_xx10 : irq_eoi_req_idx = 1;
16'bxxxx_xxxx_xxxx_x100 : irq_eoi_req_idx = 2;
16'bxxxx_xxxx_xxxx_1000 : irq_eoi_req_idx = 3;
16'bxxxx_xxxx_xxx1_0000 : irq_eoi_req_idx = 4;
16'bxxxx_xxxx_xx10_0000 : irq_eoi_req_idx = 5;
16'bxxxx_xxxx_x100_0000 : irq_eoi_req_idx = 6;
16'bxxxx_xxxx_1000_0000 : irq_eoi_req_idx = 7;
16'bxxxx_xxx1_0000_0000 : irq_eoi_req_idx = 8;
16'bxxxx_xx10_0000_0000 : irq_eoi_req_idx = 9;
16'bxxxx_x100_0000_0000 : irq_eoi_req_idx = 10;
16'bxxxx_1000_0000_0000 : irq_eoi_req_idx = 11;
16'bxxx1_0000_0000_0000 : irq_eoi_req_idx = 12;
16'bxx10_0000_0000_0000 : irq_eoi_req_idx = 13;
16'bx100_0000_0000_0000 : irq_eoi_req_idx = 14;
16'b1000_0000_0000_0000 : irq_eoi_req_idx = 15;
16'b0000_0000_0000_0000 : irq_eoi_req_idx = 16;
default : irq_eoi_req_idx = 16;
endcase
irq_eoi_req_vd = |ipic_isvr_eoi;
end
 
assign irq_hi_prior_pnd = irq_req_idx < irq_serv_idx;
 
assign ipic2csr_irq_m_req_o = irq_req_vd & (~irq_serv_vd | irq_hi_prior_pnd);
602,4 → 653,4
 
endmodule : scr1_ipic
 
`endif // SCR1_IPIC_EN
`endif // SCR1_IPIC_EN
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv
302,10 → 302,10
// IRQ exception codes priority
always_comb begin
case (1'b1)
csr_eirq_pnd_en: csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_EXTERNAL);
csr_sirq_pnd_en: csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_SOFTWARE);
csr_tirq_pnd_en: csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_TIMER);
default : csr_mcause_ec_new = type_scr1_exc_code_e'(SCR1_EXC_CODE_IRQ_M_EXTERNAL);
csr_eirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_EXTERNAL; // cp.7
csr_sirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_SOFTWARE; // cp.7
csr_tirq_pnd_en: csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_TIMER; // cp.7
default : csr_mcause_ec_new = SCR1_EXC_CODE_IRQ_M_EXTERNAL; // cp.7
endcase
end
 
348,7 → 348,7
// Machine Trap Handling (read-write)
SCR1_CSR_ADDR_MSCRATCH : csr_r_data = csr_mscratch_ff;
SCR1_CSR_ADDR_MEPC : csr_r_data = csr_mepc;
SCR1_CSR_ADDR_MCAUSE : csr_r_data = {csr_mcause_i_ff, type_scr1_csr_mcause_ec_v'(csr_mcause_ec_ff)};
SCR1_CSR_ADDR_MCAUSE : csr_r_data = {csr_mcause_i_ff, (`SCR1_XLEN-1)'(csr_mcause_ec_ff)};
SCR1_CSR_ADDR_MTVAL : csr_r_data = csr_mtval_ff;
SCR1_CSR_ADDR_MIP : csr_r_data = csr_mip;
 
794,7 → 794,7
always_ff @(negedge rst_n, posedge clk) begin
if (~rst_n) begin
csr_mcause_i_ff <= 1'b0;
csr_mcause_ec_ff <= type_scr1_exc_code_e'(SCR1_EXC_CODE_RESET);
csr_mcause_ec_ff <= SCR1_EXC_CODE_RESET; // cp.7
end else begin
csr_mcause_i_ff <= csr_mcause_i_next;
csr_mcause_ec_ff <= csr_mcause_ec_next;
813,7 → 813,7
end
csr_mcause_upd: begin
csr_mcause_i_next = csr_w_data[`SCR1_XLEN-1];
csr_mcause_ec_next = type_scr1_exc_code_e'(csr_w_data[SCR1_EXC_CODE_WIDTH_E-1:0]);
csr_mcause_ec_next = csr_w_data[SCR1_EXC_CODE_WIDTH_E-1:0]; // cp.7
end
default : begin
csr_mcause_i_next = csr_mcause_i_ff;
1089,6 → 1089,7
 
// Behavior checks
 
`ifndef VERILATOR
SCR1_SVA_CSR_MRET : assert property (
@(negedge clk) disable iff (~rst_n)
e_mret |=> ($stable(csr_mepc_ff) & $stable(csr_mtval_ff))
1110,7 → 1111,7
(~csr_mstatus_mie_ff & (~csr_mcause_i_ff)
& (exu2csr_pc_curr_i=={csr_mtvec_base, SCR1_CSR_MTVEC_BASE_ZERO_BITS'(0)}))
) else $error("CSR Error: wrong EXC+IRQ");
 
`endif // VERILATOR
SCR1_SVA_CSR_EVENTS : assert property (
@(negedge clk) disable iff (~rst_n)
$onehot0({e_irq, e_exc, e_mret})
1121,14 → 1122,16
csr2exu_rw_exc_o |-> (exu2csr_w_req_i | exu2csr_r_req_i)
) else $error("CSR Error: impossible exception");
 
`ifndef VERILATOR
SCR1_SVA_CSR_MSTATUS_MIE_UP : assert property (
@(negedge clk) disable iff (~rst_n)
csr2exu_mstatus_mie_up_o |=> ~csr2exu_mstatus_mie_up_o
) else $error("CSR Error: csr2exu_mstatus_mie_up_o can only be high for one mcycle");
`endif // VERILATOR
 
 
`ifndef SCR1_CSR_REDUCED_CNT
 
`ifndef VERILATOR
SCR1_SVA_CSR_CYCLE_INC : assert property (
@(
`ifndef SCR1_CLKCTRL_EN
1154,7 → 1157,7
(csr_minstret == $past(csr_minstret + 1'b1))
`endif // SCR1_MCOUNTEN_EN
) else $error("CSR Error: INSTRET increment wrong behavior");
 
`endif
SCR1_SVA_CSR_CYCLE_INSTRET_UP : assert property (
@(negedge clk) disable iff (~rst_n)
~(&csr_minstret_upd | &csr_mcycle_upd)
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv
487,16 → 487,17
//-------------------------------------------------------------------------------
// MDU adder
//-------------------------------------------------------------------------------
logic sgn;
logic inv;
 
always_comb begin
mdu_sum_sub = 1'b0;
mdu_sum_op1 = '0;
mdu_sum_op2 = '0;
sgn = '0; // yosys - latch fix
inv = '0; // yosys - latch fix
case (mdu_cmd)
SCR1_IALU_MDU_DIV : begin
logic sgn;
logic inv;
 
sgn = mdu_fsm_corr ? div_op1_is_neg ^ mdu_res_c_ff
: mdu_fsm_idle ? 1'b0
: ~mdu_res_lo_ff[0];
683,6 → 684,7
$onehot0({~exu2ialu_rvm_cmd_vd_i, mdu_fsm_iter, mdu_fsm_corr})
) else $error("IALU Error: illegal state");
 
`ifndef VERILATOR
SCR1_SVA_IALU_JUMP_FROM_IDLE : assert property (
@(negedge clk) disable iff (~rst_n)
(mdu_fsm_idle & (~exu2ialu_rvm_cmd_vd_i | ~mdu_iter_req)) |=> mdu_fsm_idle
712,6 → 714,7
@(negedge clk) disable iff (~rst_n)
mdu_fsm_corr |=> mdu_fsm_idle
) else $error("EXU Error: illegal state stay in CORR");
`endif // VERILATOR
 
`endif // SCR1_RVM_EXT
 
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv
80,10 → 80,10
assign instr = ifu2idu_instr_i;
 
// RVI / RVC
assign instr_type = type_scr1_instr_type_e'(instr[1:0]);
assign instr_type = instr[1:0];
 
// RVI / RVC fields
assign rvi_opcode = type_scr1_rvi_opcode_e'(instr[6:2]); // RVI
assign rvi_opcode = instr[6:2]; // RVI
assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
assign funct7 = instr[31:25]; // RVI
assign funct12 = instr[31:20]; // RVI (SYSTEM)
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv
420,8 → 420,10
 
always_ff @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
`ifdef SCR1_MPRF_RST_EN // Two dimensional array init not allowed in YOSYS - cp.13
q_data <= '{SCR1_IFU_Q_SIZE_HALF{'0}};
q_err <= '{SCR1_IFU_Q_SIZE_HALF{1'b0}};
`endif
end else if (q_wr_en) begin
case (q_wr_size)
SCR1_IFU_QUEUE_WR_HI : begin
777,12 → 779,12
) else $error("IFU Error: unknown {ifu2imem_addr_o, ifu2imem_cmd_o}");
 
// Behavior checks
 
`ifndef VERILATOR
SCR1_SVA_IFU_DRC_UNDERFLOW : assert property (
@(negedge clk) disable iff (~rst_n)
~imem_resp_discard_req |=> ~(imem_resp_discard_cnt == SCR1_TXN_CNT_W'('1))
) else $error("IFU Error: imem_resp_discard_cnt underflow");
 
`endif // VERILATOR
SCR1_SVA_IFU_DRC_RANGE : assert property (
@(negedge clk) disable iff (~rst_n)
(imem_resp_discard_cnt >= 0) & (imem_resp_discard_cnt <= imem_pnd_txns_cnt)
795,6 → 797,7
: (q_wr_size == SCR1_IFU_QUEUE_WR_NONE))
) else $error("IFU Error: queue overflow");
 
`ifndef VERILATOR
SCR1_SVA_IFU_IMEM_ERR_BEH : assert property (
@(negedge clk) disable iff (~rst_n)
(imem_resp_er & ~imem_resp_discard_req & ~exu2ifu_pc_new_req_i) |=>
805,17 → 808,18
@(negedge clk) disable iff (~rst_n)
exu2ifu_pc_new_req_i |=> q_is_empty
) else $error("IFU Error: incorrect behavior after exu2ifu_pc_new_req_i");
 
`endif // VERILATOR
SCR1_SVA_IFU_IMEM_ADDR_ALIGNED : assert property (
@(negedge clk) disable iff (~rst_n)
ifu2imem_req_o |-> ~|ifu2imem_addr_o[1:0]
) else $error("IFU Error: unaligned IMEM access");
 
`ifndef VERILATOR
SCR1_SVA_IFU_STOP_FETCH : assert property (
@(negedge clk) disable iff (~rst_n)
pipe2ifu_stop_fetch_i |=> (ifu_fsm_curr == SCR1_IFU_FSM_IDLE)
) else $error("IFU Error: fetch not stopped");
 
`endif // VERILATOR
SCR1_SVA_IFU_IMEM_FAULT_RVI_HI : assert property (
@(negedge clk) disable iff (~rst_n)
ifu2idu_err_rvi_hi_o |-> ifu2idu_imem_err_o
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv
154,7 → 154,7
 
// TDATA2 register
logic [MTRIG_NUM-1:0] csr_tdata2_upd;
logic [MTRIG_NUM-1:0] [SCR1_TDU_DATA_W-1:0] csr_tdata2_ff;
logic [MTRIG_NUM-1:0] csr_tdata2_ff [SCR1_TDU_DATA_W-1:0];
 
//------------------------------------------------------------------------------
// CSR read/write interface
164,8 → 164,9
//------------------------------------------------------------------------------
 
assign tdu2csr_resp_o = csr2tdu_req_i ? SCR1_CSR_RESP_OK : SCR1_CSR_RESP_ER;
 
integer i;
always_comb begin
i = 0; // yosys latch warning fix
tdu2csr_rdata_o = '0;
if (csr2tdu_req_i) begin
case (csr2tdu_addr_i)
173,7 → 174,7
tdu2csr_rdata_o = {'0, csr_tselect_ff};
end
SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
if(csr_tselect_ff == ALLTRIG_W'(i)) begin
tdu2csr_rdata_o = csr_tdata2_ff[i];
end
180,7 → 181,7
end
end
SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
if(csr_tselect_ff == ALLTRIG_W'(i)) begin
tdu2csr_rdata_o[SCR1_TDU_TDATA1_TYPE_HI:
SCR1_TDU_TDATA1_TYPE_LO] = SCR1_TDU_MCONTROL_TYPE_VAL;
221,7 → 222,7
`endif // SCR1_TDU_ICOUNT_EN
end
SCR1_CSR_ADDR_TDU_OFFS_TINFO : begin
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
for(i = 0; i < MTRIG_NUM; i=i+1) begin // cp.4
if(csr_tselect_ff == ALLTRIG_W'(i)) begin
tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TYPE_VAL] = 1'b1;
end
265,8 → 266,9
 
// Register selection
//------------------------------------------------------------------------------
 
integer k;
always_comb begin
k = 0; // yosys latch warning fix
csr_addr_tselect = 1'b0;
csr_addr_tdata2 = '0;
csr_addr_mcontrol = '0;
280,9 → 282,9
csr_addr_tselect = 1'b1;
end
SCR1_CSR_ADDR_TDU_OFFS_TDATA1 : begin
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
if(csr_tselect_ff == ALLTRIG_W'(i)) begin
csr_addr_mcontrol[i] = 1'b1;
for(k = 0; k < MTRIG_NUM; k=k+1) begin
if(csr_tselect_ff == ALLTRIG_W'(k)) begin
csr_addr_mcontrol[k] = 1'b1;
end
end
`ifdef SCR1_TDU_ICOUNT_EN
292,9 → 294,9
`endif // SCR1_TDU_ICOUNT_EN
end
SCR1_CSR_ADDR_TDU_OFFS_TDATA2 : begin
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
if(csr_tselect_ff == ALLTRIG_W'(i) ) begin
csr_addr_tdata2[i] = 1'b1;
for(k = 0; k < MTRIG_NUM; k=k+1) begin // cp.4
if(csr_tselect_ff == ALLTRIG_W'(k) ) begin
csr_addr_tdata2[k] = 1'b1;
end
end
end
398,7 → 400,7
 
genvar trig;
generate
for (trig = 0; $unsigned(trig) < MTRIG_NUM; ++trig) begin : gblock_mtrig
for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_mtrig
 
assign csr_mcontrol_wr_req[trig] = csr_addr_mcontrol[trig] & csr_wr_req;
assign csr_mcontrol_clk_en[trig] = clk_en
490,7 → 492,7
//------------------------------------------------------------------------------
 
generate
for (trig = 0; $unsigned(trig) < MTRIG_NUM; ++trig) begin : gblock_break_trig
for (trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1) begin : gblock_break_trig
assign csr_mcontrol_exec_hit[trig] = ~tdu_dsbl_i
& csr_mcontrol_m_ff[trig]
& csr_mcontrol_exec_ff[trig]
509,7 → 511,7
//------------------------------------------------------------------------------
 
generate
for( trig = 0; $unsigned(trig) < MTRIG_NUM; ++trig ) begin : gblock_watch_trig
for( trig = 0; $unsigned(trig) < MTRIG_NUM; trig=trig+1 ) begin : gblock_watch_trig
assign csr_mcontrol_ldst_hit[trig] = ~tdu_dsbl_i
& csr_mcontrol_m_ff[trig]
& lsu2tdu_dmon_i.vd
529,12 → 531,12
//------------------------------------------------------------------------------
// TDU <-> HDU interface
//------------------------------------------------------------------------------
 
integer j;
always_comb begin
tdu2hdu_dmode_req_o = 1'b0;
 
for(int unsigned i = 0; i < MTRIG_NUM; ++i) begin
tdu2hdu_dmode_req_o |= (csr_mcontrol_action_ff[i] & exu2tdu_bp_retire_i[i]);
for(j = 0; j < MTRIG_NUM; j=j+1) begin
tdu2hdu_dmode_req_o |= (csr_mcontrol_action_ff[j] & exu2tdu_bp_retire_i[j]);
end
`ifdef SCR1_TDU_ICOUNT_EN
tdu2hdu_dmode_req_o |= (csr_icount_action_ff & exu2tdu_bp_retire_i[ALLTRIG_NUM-1]);
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv
1131,9 → 1131,9
 
ABS_STATE_ERR: begin
if (dmi_req_abstractcs & dmi2dm_wr_i) begin
abstractcs_cmderr_next = type_scr1_abs_err_e'(logic'(abstractcs_cmderr_ff)
abstractcs_cmderr_next = abstractcs_cmderr_ff // cp.7
& (~dmi2dm_wdata_i[SCR1_DBG_ABSTRACTCS_CMDERR_HI:
SCR1_DBG_ABSTRACTCS_CMDERR_LO]));
SCR1_DBG_ABSTRACTCS_CMDERR_LO]);
end
end
 
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv
187,7 → 187,7
end
 
assign tapc_shift_next = tapc_dr_cap_req ? tapc_shadow_ff
: tapc_dr_shft_req ? {tapcsync2scu_ch_tdi_i, tapc_shift_ff[$bits(type_scr1_scu_sysctrl_dr_s)-1:1]}
: tapc_dr_shft_req ? {tapcsync2scu_ch_tdi_i, tapc_shift_ff[SCR1_SCU_DR_SYSCTRL_WIDTH-1:1]}// cp.5
: tapc_shift_ff;
 
// TAPC shadow register
319,12 → 319,12
// STICKY_STATUS register
//------------------------------------------------------------------------------
// For every output reset signal shows if it was asserted since the last bit clearing
 
integer i;
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
if (~pwrup_rst_n_sync) begin
scu_sticky_sts_ff <= '0;
end else begin
for (int unsigned i = 0; i < $bits(type_scr1_scu_sysctrl_status_reg_s); ++i) begin
for (i = 0; i < SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH ; i=i+1) begin // cp.4
if (scu_status_ff_posedge[i]) begin
scu_sticky_sts_ff[i] <= 1'b1;
end else if (scu_sticky_sts_wr_req) begin
483,6 → 483,7
!$isunknown({pwrup_rst_n, rst_n, cpu_rst_n, ndm_rst_n_i, hart_rst_n_i})
) else $error("SCU resets error: unknown values of input resets");
 
`ifndef VERILATOR
// Qualifiers checks
SCR1_SVA_SCU_SYS2SOC_QLFY_CHECK : assert property (
@(negedge clk) disable iff (~pwrup_rst_n)
508,7 → 509,7
@(negedge clk) disable iff (~pwrup_rst_n)
$fell(hdu_rst_n_o) |-> $fell($past(hdu2dm_rdc_qlfy_o))
) else $error("SCU hdu2dm qlfy error: qlfy wasn't raised prior to reset");
 
`endif // VERILATOR
`endif // SCR1_TRGT_SIMULATION
 
endmodule : scr1_scu
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_arch_description.svh
59,7 → 59,7
 
// Uncomment one of these defines to set the recommended configuration:
 
//`define SCR1_CFG_RV32IMC_MAX
`define SCR1_CFG_RV32IMC_MAX
//`define SCR1_CFG_RV32IC_BASE
//`define SCR1_CFG_RV32EC_MIN
 
74,15 → 74,15
parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26;
`define SCR1_MTVEC_MODE_EN
`define SCR1_FAST_MUL
`define SCR1_MPRF_RST_EN
//`define SCR1_MPRF_RST_EN - yosys fix, two dimensional array init not allowed
`define SCR1_MCOUNTEN_EN
`define SCR1_DBG_EN
// `define SCR1_DBG_EN
`define SCR1_TDU_EN
parameter int unsigned SCR1_TDU_TRIG_NUM = 4;
`define SCR1_TDU_ICOUNT_EN
`define SCR1_IPIC_EN
`define SCR1_IPIC_SYNC_EN
`define SCR1_TCM_EN
// `define SCR1_TCM_EN
`elsif SCR1_CFG_RV32IC_BASE
`define SCR1_RVI_EXT
`define SCR1_RVC_EXT
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_hdu.svh
17,7 → 17,7
// Parameters
//==============================================================================
//localparam int unsigned SCR1_HDU_DEBUGCSR_BASE_ADDR = 12'h7B0;
localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN = SCR1_CSR_ADDR_HDU_MSPAN;
localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN = 4; // YOSYS FIX
localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_WIDTH = $clog2(SCR1_HDU_DEBUGCSR_ADDR_SPAN);
localparam bit [3:0] SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER = 4'h4;
localparam int unsigned SCR1_HDU_PBUF_ADDR_SPAN = 8;
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_search_ms1.svh
9,12 → 9,12
//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef struct {
typedef struct packed {
logic vd;
logic idx;
} type_scr1_search_one_2_s;
 
typedef struct {
typedef struct packed {
logic vd;
logic [4:0] idx;
} type_scr1_search_one_32_s;
29,9 → 29,9
begin
tmp.vd = |din;
tmp.idx = ~din[1];
return tmp;
scr1_lead_zeros_cnt_2 = tmp;
end
endfunction : scr1_lead_zeros_cnt_2
endfunction
 
function automatic logic [4:0] scr1_lead_zeros_cnt_32(
input logic [31:0] din
48,9 → 48,10
logic [3:0] stage4_idx [1:0];
type_scr1_search_one_32_s tmp;
logic [4:0] res;
integer i;
 
// Stage 1
for (int unsigned i=0; i<16; ++i) begin
for (i=0; i<16; i=i+1) begin // cp.4
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
stage1_vd[i] = tmp.vd;
58,7 → 59,7
end
 
// Stage 2
for (int unsigned i=0; i<8; ++i) begin
for (i=0; i<8;i=i+1) begin // cp.4
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
stage2_vd[i] = tmp.vd;
66,7 → 67,7
end
 
// Stage 3
for (int unsigned i=0; i<4; ++i) begin
for (i=0; i<4; i=i+1) begin // cp.4
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
stage3_vd[i] = tmp.vd;
74,7 → 75,7
end
 
// Stage 4
for (int unsigned i=0; i<2; ++i) begin
for (i=0; i<2; i=i+1) begin // cp.4
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
stage4_vd[i] = tmp.vd;
87,8 → 88,8
 
res = tmp.idx;
 
return res;
scr1_lead_zeros_cnt_32 = res;
end
endfunction : scr1_lead_zeros_cnt_32
endfunction
 
`endif // SCR1_SEARCH_MS1_SVH
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_ahb.sv
96,9 → 96,9
tmp = SCR1_HSIZE_ERR;
end
endcase
return tmp;
scr1_conv_mem2ahb_width = tmp; // cp.11
end
endfunction : scr1_conv_mem2ahb_width
endfunction
 
function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_mem2ahb_wdata (
input logic [1:0] dmem_addr,
145,9 → 145,9
default : begin
end
endcase
return tmp;
scr1_conv_mem2ahb_wdata = tmp;
end
endfunction : scr1_conv_mem2ahb_wdata
endfunction
 
function automatic logic[SCR1_AHB_WIDTH-1:0] scr1_conv_ahb2mem_rdata (
input logic [2:0] hwidth,
182,9 → 182,9
default : begin
end
endcase
return tmp;
scr1_conv_ahb2mem_rdata = tmp;
end
endfunction : scr1_conv_ahb2mem_rdata
endfunction
 
//-------------------------------------------------------------------------------
// Local signal declaration
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv
90,9 → 90,9
default: axsize = 'x;
endcase
 
return axsize;
width2axsize = axsize; // cp.11
end
endfunction: width2axsize
endfunction
 
typedef struct packed {
type_scr1_mem_width_e axi_width;
108,9 → 108,21
} type_scr1_req_status_s;
 
 
type_scr1_request_s [SCR1_REQ_BUF_SIZE-1:0] req_fifo;
type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status;
type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status_new;
//type_scr1_request_s [SCR1_REQ_BUF_SIZE-1:0] req_fifo;
logic [1:0] req_fifo_axi_width[SCR1_REQ_BUF_SIZE-1:0];
logic [SCR1_ADDR_WIDTH-1:0] req_fifo_axi_addr [SCR1_REQ_BUF_SIZE-1:0];
logic [31:0] req_fifo_axi_wdata [SCR1_REQ_BUF_SIZE-1:0];
//type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_write ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_addr ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_data ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_req_resp ;
//type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status_new;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_write ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_addr ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_data ;
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_new_req_resp ;
 
logic [SCR1_REQ_BUF_SIZE-1:0] req_status_en;
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_aval_ptr;
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_proc_ptr;
124,30 → 136,30
 
 
assign core_req_ack = ~axi_reinit &
~req_status[req_aval_ptr].req_resp &
~req_status_req_resp[req_aval_ptr] &
core_resp!=SCR1_MEM_RESP_RDY_ER;
 
 
assign rready = ~req_status[req_done_ptr].req_write;
assign bready = req_status[req_done_ptr].req_write;
assign rready = ~req_status_req_write[req_done_ptr];
assign bready = req_status_req_write[req_done_ptr];
 
 
assign force_read = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_RD;
assign force_write = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_WR;
assign force_read = SCR1_AXI_REQ_BP & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_RD;
assign force_write = SCR1_AXI_REQ_BP & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_WR;
 
 
integer i;
always_comb begin: idle_status
core_idle = 1'b1;
for (int unsigned i=0; i<SCR1_REQ_BUF_SIZE; ++i) begin
core_idle &= req_status[i].req_resp==1'b0;
for (i=0; i<SCR1_REQ_BUF_SIZE; i=i+1) begin
core_idle &= req_status_req_resp[i]==1'b0;
end
end
 
always_ff @(posedge clk) begin
if (core_req & core_req_ack) begin
req_fifo[req_aval_ptr].axi_width <= core_width;
req_fifo[req_aval_ptr].axi_addr <= core_addr;
req_fifo[req_aval_ptr].axi_wdata <= core_wdata;
req_fifo_axi_width[req_aval_ptr] <= core_width;
req_fifo_axi_addr[req_aval_ptr] <= core_addr;
req_fifo_axi_wdata[req_aval_ptr] <= core_wdata;
end
end
 
158,19 → 170,22
always_comb begin
// Default
req_status_en = '0; // No update
req_status_new = req_status; // Hold request info
req_status_new_req_write = req_status_req_write; // Hold request info
req_status_new_req_addr = req_status_req_addr; // Hold request info
req_status_new_req_data = req_status_req_data; // Hold request info
req_status_new_req_resp = req_status_req_resp; // Hold request info
 
// Update status on new core request
if( core_req & core_req_ack ) begin
req_status_en[req_aval_ptr] = 1'd1;
 
req_status_new[req_aval_ptr].req_resp = 1'd1;
req_status_new[req_aval_ptr].req_write = core_cmd == SCR1_MEM_CMD_WR;
req_status_new_req_resp[req_aval_ptr] = 1'd1;
req_status_new_req_write[req_aval_ptr] = core_cmd == SCR1_MEM_CMD_WR;
 
req_status_new[req_aval_ptr].req_addr = ~( (force_read & arready) |
req_status_new_req_addr[req_aval_ptr] = ~( (force_read & arready) |
(force_write & awready) );
 
req_status_new[req_aval_ptr].req_data = ~( (force_write & wready & awlen == 8'd0) |
req_status_new_req_data[req_aval_ptr] = ~( (force_write & wready & awlen == 8'd0) |
(~force_write & core_cmd == SCR1_MEM_CMD_RD) );
end
 
177,30 → 192,37
// Update status on AXI address phase
if ( (awvalid & awready) | (arvalid & arready) ) begin
req_status_en[req_proc_ptr] = 1'd1;
req_status_new[req_proc_ptr].req_addr = 1'd0;
req_status_new_req_addr[req_proc_ptr] = 1'd0;
end
 
// Update status on AXI data phase
if ( wvalid & wready & wlast ) begin
req_status_en[req_proc_ptr] = 1'd1;
req_status_new[req_proc_ptr].req_data = 1'd0;
req_status_new_req_data[req_proc_ptr] = 1'd0;
end
 
// Update status when AXI finish transaction
if ( (bvalid & bready) | (rvalid & rready & rlast) ) begin
req_status_en[req_done_ptr] = 1'd1;
req_status_new[req_done_ptr].req_resp = 1'd0;
req_status_new_req_resp[req_done_ptr] = 1'd0;
end
end
 
// Request Status Queue register
integer j;
always_ff @(negedge rst_n, posedge clk) begin
if (~rst_n) begin
req_status <= '0;
req_status_req_write <= '0;
req_status_req_addr <= '0;
req_status_req_data <= '0;
req_status_req_resp <= '0;
end else begin
for (int unsigned i = 0; i < SCR1_REQ_BUF_SIZE; ++i) begin
if ( req_status_en[i] ) begin
req_status[i] <= req_status_new[i];
for (j = 0; j < SCR1_REQ_BUF_SIZE; j = j+1) begin // cp.4
if ( req_status_en[j] ) begin
req_status_req_write[j] <= req_status_new_req_write[j];
req_status_req_addr[j] <= req_status_new_req_addr[j];
req_status_req_data[j] <= req_status_new_req_data[j];
req_status_req_resp[j] <= req_status_new_req_resp[j];
end
end
end
216,9 → 238,9
req_proc_ptr <= '0;
end else begin
if (( awvalid & awready & wvalid & wready & wlast) |
(~force_write & ~req_status[req_proc_ptr].req_data & awvalid & awready ) |
(~force_write & ~req_status[req_proc_ptr].req_addr & wvalid & wready & wlast) |
( ~req_status[req_proc_ptr].req_data & arvalid & arready ) ) begin
(~force_write & ~req_status_req_data[req_proc_ptr] & awvalid & awready ) |
(~force_write & ~req_status_req_addr[req_proc_ptr] & wvalid & wready & wlast) |
( ~req_status_req_data[req_proc_ptr] & arvalid & arready ) ) begin
 
req_proc_ptr <= req_proc_ptr + 1'b1;
end
229,7 → 251,7
if (~rst_n) begin
req_done_ptr <= '0;
end else begin
if ((bvalid & bready | rvalid & rready & rlast) & req_status[req_done_ptr].req_resp) begin
if ((bvalid & bready | rvalid & rready & rlast) & req_status_req_resp[req_done_ptr]) begin
 
req_done_ptr <= req_done_ptr + 1'b1;
end
238,19 → 260,19
 
 
 
assign arvalid = req_status[req_proc_ptr].req_addr & ~req_status[req_proc_ptr].req_write | force_read;
assign awvalid = req_status[req_proc_ptr].req_addr & req_status[req_proc_ptr].req_write | force_write;
assign wvalid = req_status[req_proc_ptr].req_data & req_status[req_proc_ptr].req_write | force_write;
assign arvalid = req_status_req_addr[req_proc_ptr] & ~req_status_req_write[req_proc_ptr] | force_read;
assign awvalid = req_status_req_addr[req_proc_ptr] & req_status_req_write[req_proc_ptr] | force_write;
assign wvalid = req_status_req_data[req_proc_ptr] & req_status_req_write[req_proc_ptr] | force_write;
 
assign araddr = (~force_read )? req_fifo[req_proc_ptr].axi_addr : core_addr;
assign awaddr = (~force_write)? req_fifo[req_proc_ptr].axi_addr : core_addr;
assign araddr = (~force_read )? req_fifo_axi_addr[req_proc_ptr] : core_addr;
assign awaddr = (~force_write)? req_fifo_axi_addr[req_proc_ptr] : core_addr;
 
always_comb begin
if (bvalid & bready & req_status[req_done_ptr].req_resp) begin
if (bvalid & bready & req_status_req_resp[req_done_ptr]) begin
rcvd_resp = (bresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
SCR1_MEM_RESP_RDY_ER;
end else begin
if (rvalid & rready & rlast & req_status[req_done_ptr].req_resp) begin
if (rvalid & rready & rlast & req_status_req_resp[req_done_ptr]) begin
rcvd_resp = (rresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
SCR1_MEM_RESP_RDY_ER;
end else begin
260,8 → 282,9
end
 
 
wire [SCR1_ADDR_WIDTH-1:0] CurAddr1 = req_fifo_axi_addr[req_proc_ptr];
wire [1:0] bShift1 = CurAddr1[1:0];
 
 
// Write data signals adaptation
always_comb begin
if (force_write)
272,10 → 295,10
default: wstrb = 'x;
endcase
else
case (req_fifo[req_proc_ptr].axi_width)
SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << req_fifo[req_proc_ptr].axi_addr[1:0];
SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << req_fifo[req_proc_ptr].axi_addr[1:0];
SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << req_fifo[req_proc_ptr].axi_addr[1:0];
case (req_fifo_axi_width[req_proc_ptr])
SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << bShift1;
SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << bShift1;
SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << bShift1;
default: wstrb = 'x;
endcase
end
283,17 → 306,17
 
 
assign wdata = (force_write)? core_wdata << (8* core_addr[1:0]) :
req_fifo[req_proc_ptr].axi_wdata << (8* req_fifo[req_proc_ptr].axi_addr[1:0]);
req_fifo_axi_wdata[req_proc_ptr] << (8* bShift1);
 
 
// Read data adaptation
always_comb begin
case (req_fifo[req_done_ptr].axi_width)
SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
SCR1_MEM_WIDTH_HWORD: rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
SCR1_MEM_WIDTH_WORD : rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
default: rcvd_rdata = 'x;
endcase
case (req_fifo_axi_width[req_done_ptr])
SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*bShift2);
SCR1_MEM_WIDTH_HWORD: rcvd_rdata = rdata >> (8*bShift2);
SCR1_MEM_WIDTH_WORD : rcvd_rdata = rdata >> (8*bShift2);
default: rcvd_rdata = 'x;
endcase
end
 
 
317,7 → 340,7
// AXI interface assignments
assign awid = SCR1_AXI_IDWIDTH'(1);
assign awlen = 8'd0;
assign awsize = (force_write) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
assign awsize = (force_write) ? width2axsize(core_width) : width2axsize(req_fifo_axi_width[req_proc_ptr]);
assign awburst = 2'd1;
assign awcache = 4'd2;
assign awlock = '0;
328,7 → 351,7
 
assign arid = SCR1_AXI_IDWIDTH'(0);
assign arlen = 8'd0;
assign arsize = (force_read) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
assign arsize = (force_read) ? width2axsize(core_width) : width2axsize(req_fifo_axi_width[req_proc_ptr]);
assign arburst = 2'd1;
assign arcache = 4'd2;
assign arprot = '0;
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/Makefile
0,0 → 1,71
#------------------------------------------------------------------------------
# Makefile for Synthesis
#------------------------------------------------------------------------------
 
# Paths
export ROOT_DIR := $(shell pwd)
export DESIGN_FILE := $(ROOT_DIR)/pyfive.sv
export SYNTH_LOG := $(ROOT_DIR)/synth.log
export REPORT_DIR := $(ROOT_DIR)/reports
export NETLIST_DIR := $(ROOT_DIR)/netlist
export TMP_DIR := $(ROOT_DIR)/tmp
 
 
# Targets
.PHONY: clean create merge synth
 
default: clean create merge synth
 
synth: clean create merge
yosys -g -c synth.tcl -l synth.log
 
create:
mkdir -p ./tmp/synthesis;
mkdir -p ./reports;
mkdir -p ./netlist;
$(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
 
merge:
################################################
# yosys has issue in propgating the golbal parameter from one file to other file
# to fix this issue, we have concatinated all the rtl file into single file before starting synthesis
# only memory are exclded from this list
# ################################################
cat ../src/core/pipeline/scr1_pipe_top.sv > pyfive.sv;
cat ../src/core/scr1_core_top.sv >> pyfive.sv;
cat ../src/core/scr1_dm.sv >> pyfive.sv;
cat ../src/core/scr1_tapc_synchronizer.sv >> pyfive.sv;
cat ../src/core/scr1_clk_ctrl.sv >> pyfive.sv;
cat ../src/core/scr1_scu.sv >> pyfive.sv;
cat ../src/core/scr1_tapc.sv >> pyfive.sv;
cat ../src/core/scr1_tapc_shift_reg.sv >> pyfive.sv;
cat ../src/core/scr1_dmi.sv >> pyfive.sv;
cat ../src/core/primitives/scr1_reset_cells.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_ifu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_idu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_exu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_mprf.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_csr.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_ialu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_lsu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_hdu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_pipe_tdu.sv >> pyfive.sv;
cat ../src/core/pipeline/scr1_ipic.sv >> pyfive.sv;
cat ../src/top/scr1_dmem_router.sv >> pyfive.sv;
cat ../src/top/scr1_imem_router.sv >> pyfive.sv;
#cat ../src/top/scr1_dp_memory.sv >> pyfive.sv;
cat ../src/top/scr1_tcm.sv >> pyfive.sv;
cat ../src/top/scr1_timer.sv >> pyfive.sv;
#cat ../src/top/scr1_dmem_ahb.sv >> pyfive.sv;
#cat ../src/top/scr1_imem_ahb.sv >> pyfive.sv;
cat ../src/top/scr1_top_axi.sv >> pyfive.sv;
cat ../src/top/scr1_mem_axi.sv>> pyfive.sv;
 
 
 
clean:
$(RM) $(DESIGN_FILE)
$(RM) $(SYNTH_LOG)
$(RM) -R $(REPORT_DIR)
$(RM) -R $(NETLIST_DIR)
$(RM) -R $(TMP_DIR)
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/run_synth
0,0 → 1,49
#####################################################
# Clean up old file and freshly create the directory
####################################################
\rm -rf pyfive.sv
\rm -rf ./tmp
\rm -rf ./reports
\rm -rf ./netlist
mkdir -p ./tmp/synthesis
mkdir -p ./reports
mkdir -p ./netlist
 
################################################
# yosys has issue in propgating the golbal parameter from one file to other file
# to fix this issue, we have concatinated all the rtl file into single file before starting synthesis
# only memory are exclded from this list
################################################
 
cat ../src/core/pipeline/scr1_pipe_top.sv > pyfive.sv
cat ../src/core/scr1_core_top.sv >> pyfive.sv
cat ../src/core/scr1_dm.sv >> pyfive.sv
cat ../src/core/scr1_tapc_synchronizer.sv >> pyfive.sv
cat ../src/core/scr1_clk_ctrl.sv >> pyfive.sv
cat ../src/core/scr1_scu.sv >> pyfive.sv
cat ../src/core/scr1_tapc.sv >> pyfive.sv
cat ../src/core/scr1_tapc_shift_reg.sv >> pyfive.sv
cat ../src/core/scr1_dmi.sv >> pyfive.sv
cat ../src/core/primitives/scr1_reset_cells.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_ifu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_idu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_exu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_mprf.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_csr.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_ialu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_lsu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_hdu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_pipe_tdu.sv >> pyfive.sv
cat ../src/core/pipeline/scr1_ipic.sv >> pyfive.sv
cat ../src/top/scr1_dmem_router.sv >> pyfive.sv
cat ../src/top/scr1_imem_router.sv >> pyfive.sv
#cat ../src/top/scr1_dp_memory.sv >> pyfive.sv
cat ../src/top/scr1_tcm.sv >> pyfive.sv
cat ../src/top/scr1_timer.sv >> pyfive.sv
cat ../src/top/scr1_dmem_ahb.sv >> pyfive.sv
cat ../src/top/scr1_imem_ahb.sv >> pyfive.sv
cat ../src/top/scr1_top_axi.sv >> pyfive.sv
cat ../src/top/scr1_mem_axi.sv>> pyfive.sv
 
yosys -g -c synth.tcl -l synth.log
 
yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/run_synth Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl =================================================================== --- yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl (nonexistent) +++ yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl (revision 6) @@ -0,0 +1,388 @@ +# Copyright 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# inputs expected as env vars +#set opt $::env(SYNTH_OPT) +########### config.tcl ################## +# User config + +# User config +set ::env(DESIGN_DIR) ../ + +set ::env(PROJ_DIR) ../../../../ + +# User config +set ::env(DESIGN_NAME) scr1_top_axi + +# Change if needed +set ::env(VERILOG_FILES) [glob \ + $::env(DESIGN_DIR)/synth/pyfive.sv ] + +#set ::env(VERILOG_FILES_BLACKBOX) [glob \ +# $::env(DESIGN_DIR)/src/top/scr1_dp_memory.sv ] + +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/src/includes] + +#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN SCR1_MPRF_RAM ] + + +set ::env(LIB_SYNTH) ./tmp/trimmed.lib + + +#set ::env(SDC_FILE) "./designs/aes128/src/aes128.sdc" + +# Fill this +set ::env(CLOCK_PERIOD) "10" +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(RUN_SIMPLE_CTS) 0 +set ::env(SYNTH_BUFFERING) 0 +set ::env(SYNTH_SIZING) 0 + +set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" +set ::env(SYNTH_CAP_LOAD) "17.65" +set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]" + +set ::env(SYNTH_MAX_FANOUT) 6 +set ::env(FP_CORE_UTIL) 50 +set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ] +set ::env(CELL_PAD) 4 + +set ::env(SYNTH_NO_FLAT) "0" + + +set ::env(SYNTH_STRATEGY) "AREA 0" +set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO" +set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI" +set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X" + + +set ::env(CLOCK_NET) $::env(CLOCK_PORT) + + + +set ::env(yosys_tmp_file_tag) "./tmp/" +set ::env(TMP_DIR) "./tmp/" +set ::env(yosys_netlist_dir) "./netlist" +set ::env(yosys_report_file_tag) "./reports/yosys" +set ::env(yosys_result_file_tag) "./reports/yosys.synthesis" + +set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv + + + +########### End of config.tcl +set buffering $::env(SYNTH_BUFFERING) +set sizing $::env(SYNTH_SIZING) + +yosys -import + +set vtop $::env(DESIGN_NAME) +#set sdc_file $::env(SDC_FILE) +set sclib $::env(LIB_SYNTH) + +if { [info exists ::env(SYNTH_DEFINES) ] } { + foreach define $::env(SYNTH_DEFINES) { + log "Defining $define" + verilog_defines -D$define + } +} + +set vIdirsArgs "" +if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} { + foreach dir $::env(VERILOG_INCLUDE_DIRS) { + log "Adding include file -I$dir " + lappend vIdirsArgs "-I$dir" + } + set vIdirsArgs [join $vIdirsArgs] +} + + + +if { [info exists ::env(EXTRA_LIBS) ] } { + foreach lib $::env(EXTRA_LIBS) { + read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib + } +} + + + +# ns expected (in sdc as well) +set clock_period [expr {$::env(CLOCK_PERIOD)*1000}] + +set driver $::env(SYNTH_DRIVING_CELL) +set cload $::env(SYNTH_CAP_LOAD) +# input pin cap of IN_3VX8 +set max_FO $::env(SYNTH_MAX_FANOUT) +if {![info exist ::env(SYNTH_MAX_TRAN)]} { + set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}] +} else { + set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}] +} +set max_Tran $::env(SYNTH_MAX_TRAN) + + +# Mapping parameters +set A_factor 0.00 +set B_factor 0.88 +set F_factor 0.00 + +# Don't change these unless you know what you are doing +set stat_ext ".stat.rpt" +set chk_ext ".chk.rpt" +set gl_ext ".gl.v" +set constr_ext ".$clock_period.constr" +set timing_ext ".timing.txt" +set abc_ext ".abc" + + +# get old sdc, add library specific stuff for abc scripts +set sdc_file $::env(yosys_tmp_file_tag).sdc +set outfile [open ${sdc_file} w] +#puts $outfile $sdc_data +puts $outfile "set_driving_cell ${driver}" +puts $outfile "set_load ${cload}" +close $outfile + + +# ABC Scrips +set abc_rs_K "resub,-K," +set abc_rs "resub" +set abc_rsz "resub,-z" +set abc_rw_K "rewrite,-K," +set abc_rw "rewrite" +set abc_rwz "rewrite,-z" +set abc_rf "refactor" +set abc_rfz "refactor,-z" +set abc_b "balance" + +set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}" +set abc_share "strash; multi,-m; ${abc_resyn2}" +set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}" +set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance" +set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}" + +set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore" +set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore" + +set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0" +set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0" +set abc_retime_area "retime,-D,{D},-M,5" +set abc_retime_dly "retime,-D,{D},-M,6" +set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000" + +set abc_area_recovery_1 "${abc_choice}; map;" +set abc_area_recovery_2 "${abc_choice2}; map;" + +set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0" +set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0" +set abc_retime_area "retime,-D,{D},-M,5" +set abc_retime_dly "retime,-D,{D},-M,6" +set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000" + +if {$buffering==1} { + set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}" +} elseif {$sizing} { + set abc_fine_tune "upsize,{D};dnsize,{D}" +} else { + set abc_fine_tune "" +} + + +set delay_scripts [list \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + ] + +set area_scripts [list \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + \ + "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \ + ] + +set all_scripts [list {*}$delay_scripts {*}$area_scripts] + +set strategy_parts [split $::env(SYNTH_STRATEGY)] + +proc synth_strategy_format_err { } { + upvar area_scripts area_scripts + upvar delay_scripts delay_scripts + log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")." + log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"." + exit 1 +} + +if { [llength $strategy_parts] != 2 } { + synth_strategy_format_err +} + +set strategy_type [lindex $strategy_parts 0] +set strategy_type_idx [lindex $strategy_parts 1] + +if { $strategy_type != "AREA" && $strategy_type != "DELAY" } { + log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)" + synth_strategy_format_err +} + +if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } { + log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high." + synth_strategy_format_err +} + +if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } { + log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high." + synth_strategy_format_err +} + +if { $strategy_type == "DELAY" } { + set strategy $strategy_type_idx +} else { + set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}] +} + + +for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } { + read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i] +} + +if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } { + foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) { + read_verilog -sv {*}$vIdirsArgs -lib $verilog_file + } +} +select -module $vtop +show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy +select -clear + +hierarchy -check -top $vtop + +# Infer tri-state buffers. +set tbuf_map false +if { [info exists ::env(TRISTATE_BUFFER_MAP)] } { + if { [file exists $::env(TRISTATE_BUFFER_MAP)] } { + set tbuf_map true + tribuf + } else { + log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)" + } +} + +if { $::env(SYNTH_NO_FLAT) } { + synth -top $vtop +} else { + synth -top $vtop -flatten +} + +share -aggressive +opt +opt_clean -purge + +tee -o "$::env(yosys_report_file_tag)_pre.stat" stat + +# Map tri-state buffers. +if { $tbuf_map } { + log {mapping tbuf} + techmap -map $::env(TRISTATE_BUFFER_MAP) + simplemap +} + +# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes +if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } { + muxcover -mux4 + techmap -map $::env(SYNTH_MUX4_MAP) + simplemap +} + +# handle technology mapping of 2-MUX +if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } { + techmap -map $::env(SYNTH_MUX_MAP) + simplemap +} + +# handle technology mapping of latches +if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } { + techmap -map $::env(SYNTH_LATCH_MAP) + simplemap +} + +dfflibmap -liberty $sclib +tee -o "$::env(yosys_report_file_tag)_dff.stat" stat + +if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } { + design -save myDesign + + for { set index 0 } { $index < [llength $all_scripts] } { incr index } { + log "\[INFO\]: ABC: WireLoad : S_$index" + design -load myDesign + + abc -D $clock_period \ + -constr "$sdc_file" \ + -liberty $sclib \ + -script [lindex $all_scripts $index] + + setundef -zero + + hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT) + + # get rid of the assignments that make verilog2def fail + splitnets + opt_clean -purge + insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT) + + tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check + write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v" + design -reset + } +} else { + + log "\[INFO\]: ABC: WireLoad : S_$strategy" + + abc -D $clock_period \ + -constr "$sdc_file" \ + -liberty $sclib \ + -script [lindex $all_scripts $strategy] \ + -showtmp; + + setundef -zero + + hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT) + + # get rid of the assignments that make verilog2def fail + splitnets + opt_clean -purge + insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT) + + tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check + write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)" +} + +if { $::env(SYNTH_NO_FLAT) } { + design -reset + file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v + read_verilog -sv $::env(SAVE_NETLIST) + synth -top $vtop -flatten + splitnets + opt_clean -purge + insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT) + write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)" + tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check +}
yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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