OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

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/zap/trunk/ZAP/docs/zap2_doc.docx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/zap/trunk/ZAP/docs/zap2_doc.docx
zap/trunk/ZAP/docs/zap2_doc.docx Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zap/trunk/ZAP/docs/zap2_doc.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zap/trunk/ZAP/hw/rtl/wb/zap_wb_merger.v =================================================================== --- zap/trunk/ZAP/hw/rtl/wb/zap_wb_merger.v (revision 14) +++ zap/trunk/ZAP/hw/rtl/wb/zap_wb_merger.v (nonexistent) @@ -1,129 +0,0 @@ -// Merges two Wishbone busses onto a single bus. Released under GPL V2. -// (C)2017 Revanth Kamaraj. - -`default_nettype none - -module zap_wb_merger ( - -input wire i_clk, -input wire i_reset, - -input wire i_c_wb_stb, -input wire i_c_wb_cyc, -input wire i_c_wb_wen, -input wire [3:0] i_c_wb_sel, -input wire [31:0] i_c_wb_dat, -input wire [31:0] i_c_wb_adr, -input wire [2:0] i_c_wb_cti, -output reg o_c_wb_ack, - -input wire i_d_wb_stb, -input wire i_d_wb_cyc, -input wire i_d_wb_wen, -input wire [3:0] i_d_wb_sel, -input wire [31:0] i_d_wb_dat, -input wire [31:0] i_d_wb_adr, -input wire [2:0] i_d_wb_cti, -output reg o_d_wb_ack, - -output reg o_wb_cyc, -output reg o_wb_stb, -output reg o_wb_wen, -output reg [3:0] o_wb_sel, -output reg [31:0] o_wb_dat, -output reg [31:0] o_wb_adr, -output reg [2:0] o_wb_cti, -input wire i_wb_ack - -); - -`include "zap_defines.vh" -`include "zap_localparams.vh" - -localparam CODE = 1'd0; -localparam DATA = 1'd1; - -reg sel_ff, sel_nxt; - -always @ (posedge i_clk) -begin - if ( i_reset ) - sel_ff <= CODE; - else - sel_ff <= sel_nxt; -end - -always @* -begin - if ( sel_ff == CODE ) - begin - o_c_wb_ack = i_wb_ack; - o_d_wb_ack = 1'd0; - end - else - begin - o_d_wb_ack = i_wb_ack; - o_c_wb_ack = 1'd0; - end -end - -always @* -begin - case(sel_ff) - CODE: - begin - if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_d_wb_stb ) - sel_nxt = DATA; - else if ( !i_c_wb_stb && i_d_wb_stb ) - sel_nxt = DATA; - else - sel_nxt = sel_ff; - end - - DATA: - begin - if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_c_wb_stb ) - sel_nxt = CODE; - else if ( i_c_wb_stb && !i_d_wb_stb ) - sel_nxt = CODE; - else - sel_nxt = sel_ff; - end - endcase -end - -always @ (posedge i_clk) -begin - if ( i_reset ) - begin - o_wb_cyc <= 0; - o_wb_stb <= 0; - o_wb_wen <= 0; - o_wb_sel <= 0; - o_wb_dat <= 0; - o_wb_adr <= 0; - o_wb_cti <= 0; - end - else if ( sel_nxt == CODE ) - begin - o_wb_cyc <= i_c_wb_cyc; - o_wb_stb <= i_c_wb_stb; - o_wb_wen <= i_c_wb_wen; - o_wb_sel <= i_c_wb_sel; - o_wb_dat <= i_c_wb_dat; - o_wb_adr <= i_c_wb_adr; - o_wb_cti <= i_c_wb_cti; - end - else - begin - o_wb_cyc <= i_d_wb_cyc; - o_wb_stb <= i_d_wb_stb; - o_wb_wen <= i_d_wb_wen; - o_wb_sel <= i_d_wb_sel; - o_wb_dat <= i_d_wb_dat; - o_wb_adr <= i_d_wb_adr; - o_wb_cti <= i_d_wb_cti; - end -end - -endmodule Index: zap/trunk/ZAP/hw/rtl/TOP/zap_top.v =================================================================== --- zap/trunk/ZAP/hw/rtl/TOP/zap_top.v (revision 14) +++ zap/trunk/ZAP/hw/rtl/TOP/zap_top.v (revision 13) @@ -26,6 +26,7 @@ module zap_top #( // Enable cache and MMU. +parameter [0:0] CACHE_MMU_ENABLE = 1'd1, parameter BP_ENTRIES = 1024, // Predictor depth. parameter FIFO_DEPTH = 4, // FIFO depth. @@ -64,17 +65,32 @@ input wire i_fiq, // --------------------- - // Wishbone interface. + // Code interface. // --------------------- - output wire o_wb_cyc, - output wire o_wb_stb, - output wire [31:0] o_wb_adr, - output wire o_wb_we, - output wire [31:0] o_wb_dat, - output wire [3:0] o_wb_sel, - output wire [2:0] o_wb_cti, - input wire i_wb_ack, - input wire [31:0] i_wb_dat + output wire o_instr_wb_cyc, + output wire o_instr_wb_stb, + output wire [31:0] o_instr_wb_adr, + output wire o_instr_wb_we, + input wire i_instr_wb_err, + input wire [31:0] i_instr_wb_dat, // Wishbone data port. + input wire i_instr_wb_ack, + output wire [3:0] o_instr_wb_sel, + output wire [2:0] o_instr_wb_cti, + + // --------------------- + // Data interface. + // --------------------- + output wire o_data_wb_cyc, + output wire o_data_wb_stb, + output wire [31:0] o_data_wb_adr, + output wire o_data_wb_we, + input wire i_data_wb_err, + input wire [31:0] i_data_wb_dat, // Wishbone instr port. + output wire [31:0] o_data_wb_dat, + input wire i_data_wb_ack, + output wire [3:0] o_data_wb_sel, + output wire [2:0] o_data_wb_cti + ); localparam COMPRESSED_EN = 1'd1; @@ -87,6 +103,113 @@ zap_reset_sync U_RST_SYNC ( .i_clk(i_clk), .i_reset(i_reset), .o_reset(rst_sync) ); +generate +begin +if ( CACHE_MMU_ENABLE == 1'd0 ) begin:cmmu_dis // Raw processor core without cache+MMU. + +assign o_data_wb_cti = 0; +assign o_instr_wb_cti = 0; + +// ------------------- +// Processor core. +// ------------------- +zap_core #( + .BP_ENTRIES(BP_ENTRIES), + .FIFO_DEPTH(FIFO_DEPTH) +) u_zap_core +( +.i_clk (i_clk), +.i_clk_multipump (i_clk_multipump), +.i_reset (rst_sync), + + +// Code related. +.o_instr_wb_adr (o_instr_wb_adr), +.o_instr_wb_cyc (o_instr_wb_cyc), +.o_instr_wb_stb (o_instr_wb_stb), +.o_instr_wb_we (o_instr_wb_we), +.o_instr_wb_sel (o_instr_wb_sel), + +// Code related. +.i_instr_wb_dat_cache (128'd0), +.i_instr_wb_dat_nocache (i_instr_wb_dat), +.i_instr_src (1'd0), + +.i_instr_wb_ack (i_instr_wb_ack), +.i_instr_wb_err (i_instr_wb_err), + +// Data related. +.o_data_wb_we (o_data_wb_we), +.o_data_wb_adr (o_data_wb_adr), +.o_data_wb_sel (o_data_wb_sel), +.o_data_wb_dat (o_data_wb_dat), +.o_data_wb_cyc (o_data_wb_cyc), +.o_data_wb_stb (o_data_wb_stb), + +// Data related. +.i_data_wb_ack (i_data_wb_ack), +.i_data_wb_err (i_data_wb_err), +.i_data_wb_dat_cache (128'd0), +.i_data_wb_dat_uncache (i_data_wb_dat), +.i_data_src (1'd0), + +// Interrupts. +.i_fiq (i_fiq), +.i_irq (i_irq), + +// These ports are irrelevant as no MMU, cache is present. +.o_mem_translate (), +.i_fsr (32'd0), +.i_far (32'd0), +.o_dac (), +.o_baddr (), +.o_mmu_en (), +.o_sr (), +.o_dcache_inv (), +.o_icache_inv (), +.o_dcache_clean (), +.o_icache_clean (), +.o_dtlb_inv (), +.o_itlb_inv (), +.i_dcache_inv_done (1'd1), +.i_icache_inv_done (1'd1), +.i_dcache_clean_done (1'd1), +.i_icache_clean_done (1'd1), +.o_dcache_en (), +.o_icache_en (), + +// Cache read enables. +.o_instr_cache_rd_en (), +.o_data_cache_rd_en (), + +// Combo Outputs - UNUSED. +.o_clear_from_alu (), +.o_stall_from_shifter (), +.o_stall_from_issue (), +.o_stall_from_decode (), +.o_clear_from_decode (), +.o_clear_from_writeback (), + +// Data IF nxt. +.o_address_nxt (), // Data addr nxt. Used to drive address of data tag RAM. +.o_data_wb_we_nxt (), +.o_data_wb_cyc_nxt (), +.o_data_wb_stb_nxt (), +.o_data_wb_dat_nxt (), +.o_data_wb_sel_nxt (), + +// Code access prpr. +.o_pc_nxt (), // PC addr nxt. Drives read address of code tag RAM. +.o_instr_wb_stb_nxt (), + +.o_cpsr () + +); + +end +else // Cache and MMU enabled. +begin: cmmu_en + wire cpu_mmu_en; wire [31:0] cpu_cpsr; wire cpu_mem_translate; @@ -116,24 +239,6 @@ wire cpu_dc_we, cpu_dc_stb; wire [3:0] cpu_dc_sel; -wire c_wb_stb; -wire c_wb_cyc; -wire c_wb_wen; -wire [3:0] c_wb_sel; -wire [31:0] c_wb_dat; -wire [31:0] c_wb_adr; -wire [2:0] c_wb_cti; -wire c_wb_ack; - -wire d_wb_stb; -wire d_wb_cyc; -wire d_wb_wen; -wire [3:0] d_wb_sel; -wire [31:0] d_wb_dat; -wire [31:0] d_wb_adr; -wire [2:0] d_wb_cti; -wire d_wb_ack; - zap_core #( .BP_ENTRIES(BP_ENTRIES), .FIFO_DEPTH(FIFO_DEPTH) @@ -259,25 +364,15 @@ .i_baddr (cpu_baddr), .i_dac_reg (cpu_dac_reg), .i_tlb_inv (cpu_dtlb_inv), - -.o_wb_stb (), -.o_wb_cyc (), -.o_wb_wen (), -.o_wb_sel (), -.o_wb_dat (), -.o_wb_adr (), -.o_wb_cti (), - -.i_wb_dat (i_wb_dat), -.i_wb_ack (d_wb_ack), - -.o_wb_stb_nxt (d_wb_stb), -.o_wb_cyc_nxt (d_wb_cyc), -.o_wb_wen_nxt (d_wb_wen), -.o_wb_sel_nxt (d_wb_sel), -.o_wb_dat_nxt (d_wb_dat), -.o_wb_adr_nxt (d_wb_adr), -.o_wb_cti_nxt (d_wb_cti) +.o_wb_stb (o_data_wb_stb), +.o_wb_cyc (o_data_wb_cyc), +.o_wb_wen (o_data_wb_we), +.o_wb_sel (o_data_wb_sel), +.o_wb_dat (o_data_wb_dat), +.o_wb_adr (o_data_wb_adr), +.o_wb_cti (o_data_wb_cti), +.i_wb_dat (i_data_wb_dat), +.i_wb_ack (i_data_wb_ack) ); zap_cache #( @@ -312,60 +407,19 @@ .i_baddr (cpu_baddr), .i_dac_reg (cpu_dac_reg), .i_tlb_inv (cpu_itlb_inv), - -.o_wb_stb (), -.o_wb_cyc (), -.o_wb_wen (), -.o_wb_sel (), +.o_wb_stb (o_instr_wb_stb), +.o_wb_cyc (o_instr_wb_cyc), +.o_wb_wen (o_instr_wb_we), +.o_wb_sel (o_instr_wb_sel), .o_wb_dat (), -.o_wb_adr (), -.o_wb_cti (), - -.i_wb_dat (i_wb_dat), -.i_wb_ack (c_wb_ack), - -.o_wb_stb_nxt (c_wb_stb), -.o_wb_cyc_nxt (c_wb_cyc), -.o_wb_wen_nxt (c_wb_wen), -.o_wb_sel_nxt (c_wb_sel), -.o_wb_dat_nxt (c_wb_dat), -.o_wb_adr_nxt (c_wb_adr), -.o_wb_cti_nxt (c_wb_cti) +.o_wb_adr (o_instr_wb_adr), +.o_wb_cti (o_instr_wb_cti), +.i_wb_dat (i_instr_wb_dat), +.i_wb_ack (i_instr_wb_ack) ); -zap_wb_merger u_zap_wb_merger ( +end +end +endgenerate -.i_clk(i_clk), -.i_reset(i_reset), - -.i_c_wb_stb(c_wb_stb), -.i_c_wb_cyc(c_wb_cyc), -.i_c_wb_wen(c_wb_wen), -.i_c_wb_sel(c_wb_sel), -.i_c_wb_dat(c_wb_dat), -.i_c_wb_adr(c_wb_adr), -.i_c_wb_cti(c_wb_cti), -.o_c_wb_ack(c_wb_ack), - -.i_d_wb_stb(d_wb_stb), -.i_d_wb_cyc(d_wb_cyc), -.i_d_wb_wen(d_wb_wen), -.i_d_wb_sel(d_wb_sel), -.i_d_wb_dat(d_wb_dat), -.i_d_wb_adr(d_wb_adr), -.i_d_wb_cti(d_wb_cti), -.o_d_wb_ack(d_wb_ack), - -.o_wb_cyc(o_wb_cyc), -.o_wb_stb(o_wb_stb), -.o_wb_wen(o_wb_we), -.o_wb_sel(o_wb_sel), -.o_wb_dat(o_wb_dat), -.o_wb_adr(o_wb_adr), -.o_wb_cti(o_wb_cti), -//.i_wb_dat(i_wb_dat), -.i_wb_ack(i_wb_ack) - -); - -endmodule // zap_top_single_if.v +endmodule // zap_top.v
/zap/trunk/ZAP/hw/rtl/cache/zap_cache.v
63,13 → 63,13
input wire i_tlb_inv,
 
// Wishbone. Signals from all 4 modules are ORed.
output reg o_wb_stb, o_wb_stb_nxt,
output reg o_wb_cyc, o_wb_cyc_nxt,
output reg o_wb_wen, o_wb_wen_nxt,
output reg [3:0] o_wb_sel, o_wb_sel_nxt,
output reg [31:0] o_wb_dat, o_wb_dat_nxt,
output reg [31:0] o_wb_adr, o_wb_adr_nxt,
output reg [2:0] o_wb_cti, o_wb_cti_nxt,
output reg o_wb_stb,
output reg o_wb_cyc,
output reg o_wb_wen,
output reg [3:0] o_wb_sel,
output reg [31:0] o_wb_dat,
output reg [31:0] o_wb_adr,
output reg [2:0] o_wb_cti,
input wire [31:0] i_wb_dat,
input wire i_wb_ack
 
284,18 → 284,6
end
end
 
// Combo signals for external MUXing.
always @*
begin
o_wb_stb_nxt = wb_stb[0] | wb_stb[1] | wb_stb[2];
o_wb_cyc_nxt = wb_cyc[0] | wb_cyc[1] | wb_cyc[2];
o_wb_adr_nxt = wb_adr[0] | wb_adr[1] | wb_adr[2];
o_wb_cti_nxt = wb_cti[0] | wb_cti[1] | wb_cti[2];
o_wb_sel_nxt = wb_sel[0] | wb_sel[1] | wb_sel[2];
o_wb_dat_nxt = wb_dat[0] | wb_dat[1] | wb_dat[2];
o_wb_wen_nxt = wb_wen[0] | wb_wen[1] | wb_wen[2];
end
 
// synopsys translate_off
reg xerr;
initial xerr = 0;
/zap/trunk/ZAP/hw/rtl/cpu/zap_alu_main.v
184,7 → 184,7
// Wires to emulate an adder.
reg [31:0] op1, op2;
reg cin;
wire [32:0] sum = {1'd0, op1} + {1'd0, op2} + {32'd0, cin};
wire [32:0] sum = {1'd0, op1} + {1'd0, op2} + {31'd0, cin};
 
reg [31:0] tmp_flags, tmp_sum;
 
/zap/trunk/ZAP/hw/rtl/cpu/zap_predecode_coproc.v
123,8 → 123,8
 
case ( state_ff )
IDLE:
// Activate only if no thumb, not in USER mode and CP15 access is requested.
casez ( (!i_cpsr_ff_t && (i_cpsr_ff_mode != USR) & (i_instruction[11:8] == 4'b1111)) ? i_instruction : 32'd0 )
// Activate only if no thumb.
casez ( (!i_cpsr_ff_t && (i_cpsr_ff_mode != USR)) ? i_instruction : 32'd0 )
MRC, MCR, LDC, STC, CDP:
begin
// Send ANDNV R0, R0, R0 instruction.
/zap/trunk/ZAP/hw/rtl/rtl_files.list
25,7 → 25,6
${ZAP_HOME}/hw/rtl/cache/zap_cache_fsm.v
${ZAP_HOME}/hw/rtl/cache/zap_cache_tag_ram.v
${ZAP_HOME}/hw/rtl/cache/zap_cache.v
${ZAP_HOME}/hw/rtl/wb/zap_wb_merger.v
 
+libdir+${ZAP_HOME}/hw/rtl/lib/
+incdir+${ZAP_HOME}/hw/rtl/inc
/zap/trunk/ZAP/hw/sim/run_sim.pl
17,6 → 17,7
[+seed+<seed_value>] -- Force a specific seed for simulation.
[+sim] -- Force register file debug and some extra error messages.
+test+<test_case> -- Run a specific test case. only +test+factorial is available, you may add new tests (see sw folder).
[+cmmu_en] -- Enable cache and MMU (highly unstable)
+ram_size+<ram_size> -- Set size of RAM in bench.
+dump_start+<start_addr_of_dump>+<number_of_words_in_dump> -- Starting memory address to start logging and number of words to log.
[+cache_size+<data_cache_size>+<code_cache_size>] -- Specify data and I-cache size in bytes.
44,6 → 45,7
my $ZAP_HOME = "";
my $SEED = int rand (0xffffffff);
my $SIM = 0;
my $CACHE_MMU_ENABLE = 0;
my $RAM_SIZE = 32768;
my $DUMP_START = 2000;
my $DUMP_SIZE = 200;
81,6 → 83,7
elsif (/^\+seed\+(.*)/) { $SEED = $1; }
elsif (/^\+sim/) { $SIM = 1; }
elsif (/^\+test\+(.*)/) { $TEST = $1; }
elsif (/^\+cmmu_en/) { $CACHE_MMU_ENABLE = 1; }
elsif (/^\+ram_size\+(.*)/) { $RAM_SIZE = $1; }
elsif (/^\+dump_start\+(.*)\+(.*)/) { $DUMP_START = $1; $DUMP_SIZE = $2; }
elsif (/^\+cache_size\+(.*)\+(.*)/) {
127,7 → 130,7
$IVL_OPTIONS .= "-DVCD_FILE_PATH=\\\"/dev/null\\\" ";
}
 
$IVL_OPTIONS .= "-Pzap_test.RAM_SIZE=$RAM_SIZE -Pzap_test.START=$DUMP_START -Pzap_test.COUNT=$DUMP_SIZE -DLINUX ";
$IVL_OPTIONS .= "-Pzap_test.CACHE_MMU_ENABLE=$CACHE_MMU_ENABLE -Pzap_test.RAM_SIZE=$RAM_SIZE -Pzap_test.START=$DUMP_START -Pzap_test.COUNT=$DUMP_SIZE -DLINUX ";
$IVL_OPTIONS .= "-Pzap_test.BP_ENTRIES=$BP -Pzap_test.FIFO_DEPTH=$FIFO ";
$IVL_OPTIONS .= "-Pzap_test.DATA_SECTION_TLB_ENTRIES=$DATA_SECTION_TLB_ENTRIES -Pzap_test.DATA_LPAGE_TLB_ENTRIES=$DATA_LPAGE_TLB_ENTRIES -Pzap_test.DATA_SPAGE_TLB_ENTRIES=$DATA_SPAGE_TLB_ENTRIES -Pzap_test.DATA_CACHE_SIZE=$DATA_CACHE_SIZE ";
$IVL_OPTIONS .= "-Pzap_test.CODE_SECTION_TLB_ENTRIES=$CODE_SECTION_TLB_ENTRIES -Pzap_test.CODE_LPAGE_TLB_ENTRIES=$CODE_LPAGE_TLB_ENTRIES -Pzap_test.CODE_SPAGE_TLB_ENTRIES=$CODE_SPAGE_TLB_ENTRIES -Pzap_test.CODE_CACHE_SIZE=$CODE_CACHE_SIZE ";
/zap/trunk/ZAP/hw/sim/run_sim_gui.pl
25,7 → 25,7
"Seed" 2 1 "0 " 2 25 25 30\
"Define SIM(Y/N)?" 3 1 "Y " 3 25 25 30\
"Testcase" 4 1 "factorial " 4 25 25 30\
"<UNUSED>" 5 1 "Y " 5 25 25 30\
"Cache/MMU Enable(Y/N)?" 5 1 "Y " 5 25 25 30\
"External RAM size(bytes)" 6 1 "32768 " 6 25 25 30\
"dump start addr+words" 7 1 "1992+100 " 7 25 25 30\
"DTLB(sect+small+large)" 8 1 "8+8+8 " 8 25 25 30\
54,6 → 54,7
my $seed ;
my $sim ;
my $testcase ;
my $cmmu ;
my $ram_size ;
my $memdumpstart;
my $dtlb ;
79,6 → 80,7
$seed = $2;
$sim = $3;
$testcase = $4;
$cmmu = $5;
$ram_size = $6;
$memdumpstart = $7;
$dtlb = $8;
101,6 → 103,7
seed = $seed
sim = $sim
testcase = $testcase
cmmu = $cmmu
ram_size = $ram_size
memdumpstart = $memdumpstart
dtlb = $dtlb
124,15 → 127,15
print "Zenity ERROR. Form not entered correctly!";
}
 
if ( $cmmu =~ m/Y/ ) { $command .= " +cmmu_en "; }
if ( $seed =~ m/^\s*[0-9]+\s*$/ ) { $command .= " +seed+$seed"; }
if ( $sim =~ m/Y/ ) { $command .= " +sim "; }
 
if ( 1 ) {
if ( $cmmu =~ m/Y/ ) {
$command .= " +cmmu_en ";
$command .= " +cache_size+$csize ";
$command .= " +dtlb+$dtlb ";
$command .= " +itlb+$itlb ";
}
 
if ( $irq =~ m/Y/ ) { $command .= " +irq_en "; }
if ( $fiq =~ m/Y/ ) { $command .= " +fiq_en "; }
if ( $tlbdebug =~ m/Y/ ) { $command .= " +tlbdebug "; }
/zap/trunk/ZAP/hw/tb/zap_tb.v
11,7 → 11,6
input [3:0] i_wb_sel,
input i_wb_we,
 
// unused.
input i_wb_cyc2,
input i_wb_stb2,
input [31:0] i_wb_adr2,
20,10 → 19,10
input i_wb_we2,
 
output reg [31:0] o_wb_dat,
output reg [31:0] o_wb_dat2, // unused.
output reg [31:0] o_wb_dat2,
 
output reg o_wb_ack,
output reg o_wb_ack2 // unused.
output reg o_wb_ack2
 
);
 
128,6 → 127,7
parameter RAM_SIZE = 32768;
parameter START = 1992;
parameter COUNT = 120;
parameter CACHE_MMU_ENABLE = 0;
parameter DATA_SECTION_TLB_ENTRIES = 4;
parameter DATA_LPAGE_TLB_ENTRIES = 8;
parameter DATA_SPAGE_TLB_ENTRIES = 16;
195,6 → 195,7
 
// CPU config.
 
$display("parameter CACHE_MMU_ENABLE = %d", CACHE_MMU_ENABLE ) ;
$display("parameter DATA_SECTION_TLB_ENTRIES = %d", DATA_SECTION_TLB_ENTRIES ) ;
$display("parameter DATA_LPAGE_TLB_ENTRIES = %d", DATA_LPAGE_TLB_ENTRIES ) ;
$display("parameter DATA_SPAGE_TLB_ENTRIES = %d", DATA_SPAGE_TLB_ENTRIES ) ;
229,11 → 230,23
end
endtask
 
always @*
begin
if ( instr_wb_dat[0] === 1'dx )
begin
$display("*E: Wishbone reporting x...! Terminating simulation...");
$finish;
end
end
 
// =========================
// Processor core.
// =========================
zap_top #(
 
// enable cache and mmu.
.CACHE_MMU_ENABLE(CACHE_MMU_ENABLE),
 
// Configure FIFO depth and BP entries.
.FIFO_DEPTH(FIFO_DEPTH),
.BP_ENTRIES(BP_ENTRIES),
258,16 → 271,30
.i_irq(i_irq),
.i_fiq(i_fiq),
 
.o_wb_cyc(data_wb_cyc),
.o_wb_stb(data_wb_stb),
.o_wb_adr(data_wb_adr),
.o_wb_we(data_wb_we),
//.i_wb_err(1'd0),
.i_wb_dat(data_wb_din[0][31:0]),
.o_wb_dat(data_wb_dout),
.i_wb_ack(data_wb_ack),
.o_wb_sel(data_wb_sel)
.o_instr_wb_cyc(instr_wb_cyc),
.o_instr_wb_stb(instr_wb_stb),
.o_instr_wb_adr(instr_wb_adr),
.o_instr_wb_we(instr_wb_we),
.i_instr_wb_err(1'd0),
.i_instr_wb_dat(instr_wb_dat[0][31:0]),
 
 
.i_instr_wb_ack(instr_wb_ack),
.o_instr_wb_sel(instr_wb_sel),
.o_data_wb_cyc(data_wb_cyc),
.o_data_wb_stb(data_wb_stb),
.o_data_wb_adr(data_wb_adr),
.o_data_wb_we(data_wb_we),
.i_data_wb_err(1'd0),
.i_data_wb_dat(data_wb_din[0][31:0]),
 
 
 
 
.o_data_wb_dat(data_wb_dout),
.i_data_wb_ack(data_wb_ack),
.o_data_wb_sel(data_wb_sel)
 
);
 
// ===============================
290,14 → 317,14
.o_wb_ack(data_wb_ack),
.i_wb_sel(data_wb_sel),
 
.i_wb_cyc2(0),
.i_wb_stb2(0),
.i_wb_adr2(0),
.i_wb_we2 (0),
.o_wb_dat2(),
.o_wb_ack2(),
.i_wb_sel2(0),
.i_wb_dat2(0)
.i_wb_cyc2(instr_wb_cyc),
.i_wb_stb2(instr_wb_stb),
.i_wb_adr2(instr_wb_adr),
.i_wb_we2(instr_wb_we),
.o_wb_dat2(instr_wb_dat[0][31:0]),
.o_wb_ack2(instr_wb_ack),
.i_wb_sel2(instr_wb_sel),
.i_wb_dat2(32'd0)
);
 
// ===========================
/zap/trunk/ZAP/README.md
21,7 → 21,7
### Features
 
Can execute 32-bit ARMv4 and 16 bit Thumb v1 code.
Wishbone B3 compatible interface. Cache unit supports burst access.
Wishbone B3 compatible I and D interfaces. Cache unit supports burst access.
9-stage pipeline design.
Branch prediction is supported.
Split I and D writeback cache (Size can be configured using parameters).

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