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URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

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  • This comparison shows the changes necessary to convert path 
    /zap/trunk
    from Rev 34 to Rev 33
    ↔ Reverse comparison
  •

Rev 34 → Rev 33

/doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/src/doc/zap_ug.tex
227,7 → 227,6
# from a synthesis perspective.
 
# Testbench configuration.
UART_TX_TERMINAL => 0, # 1 Enables UART TX terminal. 0 disables it.
EXT_RAM_SIZE => 32768, # External RAM size in bytes.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/rtl/cpu/zap_fetch_main.v
173,9 → 173,8
// PC is pumped down the pipeline.
o_pc_ff <= i_pc_ff;
 
// Instruction. If 16-bit aligned address, move data from
// cache by 16-bit to focus on the instruction.
o_instruction <= i_pc_ff[1] ? i_instruction >> 16 : i_instruction;
// Instruction.
o_instruction <= i_instruction;
end
else
begin
184,19 → 183,6
end
end
 
`ifndef SYNTHESIS
 
always @ (negedge i_clk)
begin
if ( i_pc_ff[0] != 1'd0 )
begin
$display($time, ": Error: PC LSB isn't zero. This is not legal! (Module_Src = %m)");
$finish;
end
end
 
`endif
 
// ----------------------------------------------------------------------------
 
//
/src/rtl/cpu/zap_thumb_decoder.v
172,16 → 172,5
end
end
 
`ifndef SYNTHESIS
 
// Helpful for debug.
zap_decompile u_zap_decompile (
.i_instruction(o_instruction),
.i_dav(o_instruction_valid),
.o_decompile()
);
 
`endif
 
endmodule
`default_nettype wire
/src/rtl/cpu/zap_top.v
296,8 → 296,8
u_code_cache (
.i_clk (i_clk),
.i_reset (reset),
.i_address (cpu_iaddr & 32'hFFFF_FFFC), // Cut off lower 2 bits.
.i_address_nxt (cpu_iaddr_nxt & 32'hFFFF_FFFC), // Cut off lower 2 bits.
.i_address (cpu_iaddr),
.i_address_nxt (cpu_iaddr_nxt),
 
.i_rd (cpu_instr_stb),
.i_wr (1'd0),
/src/scripts/Config.cfg_template
16,7 → 16,6
SYNTHESIS => 1, # Make this to 1 to simulate compile from a synthesis perspective.
 
# Testbench configuration.
UART_TX_TERMINAL => 1, # 1 Enables UART TX terminal. 0 disables it.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/scripts/run_sim.pl
29,7 → 29,6
my $MAX_CLOCK_CYCLES = $Config{'MAX_CLOCK_CYCLES'};
my $TLB_DEBUG = $Config{'DEFINE_TLB_DEBUG'};
my $STALL = $Config{'ALLOW_STALLS'};
my $TX_TERM = $Config{'UART_TX_TERMINAL'};
 
# System configuration.
my $DATA_CACHE_SIZE = $Config{'DATA_CACHE_SIZE'};
93,13 → 92,7
$IVL_OPTIONS .= " $ZAP_HOME/src/rtl/*/*.v $ZAP_HOME/src/testbench/cpu/*.v -o $VVP_PATH -gstrict-ca-eval -Wall -g2001 -Winfloop -DSEED=$SEED -DMEMORY_IMAGE=\\\"$PROG_PATH\\\" ";
 
$IVL_OPTIONS .= " -DVCD_FILE_PATH=\\\"$VCD_PATH\\\" ";
 
if ( $TX_TERM) {
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"$UART_PATH\\\" ";
} else {
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"/dev/null\\\" ";
}
 
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"$UART_PATH\\\" ";
$IVL_OPTIONS .= " -Pzap_test.RAM_SIZE=$RAM_SIZE -Pzap_test.START=$DUMP_START -Pzap_test.COUNT=$DUMP_SIZE -DLINUX -Pzap_test.STORE_BUFFER_DEPTH=$SBUF_DEPTH ";
$IVL_OPTIONS .= " -Pzap_test.BP_ENTRIES=$BP -Pzap_test.FIFO_DEPTH=$FIFO ";
$IVL_OPTIONS .= " -Pzap_test.DATA_SECTION_TLB_ENTRIES=$DATA_SECTION_TLB_ENTRIES ";
141,19 → 134,15
print "*I: Rand is $SEED...\n";
print "iverilog $IVL_OPTIONS\n";
 
if ( $TX_TERM ) {
system("rm -f $UART_PATH"); # Remove UART file.
system("mknod $UART_PATH p"); # Create a UART output FIFO file.
}
system("rm -f $UART_PATH"); # Remove UART file.
system("mknod $UART_PATH p"); # Create a UART output FIFO file.
 
# UART output monitor.
die "Error: XTerm could not be found!" if system("which xterm");
die "Error: Icarus Verilog could not be found!" if system("which iverilog");
 
if ( $TX_TERM == 1 ) {
print "Setting up UART output monitor\n";
system("xterm -T 'TB UART Output' -hold -e 'cat $UART_PATH ; echo ; echo ------------------ ; echo UART_Output_Complete ; echo ------------------' &");
}
print "Setting up UART output monitor";
system("xterm -T 'TB UART Output' -hold -e 'cat $UART_PATH ; echo ; echo ------------------ ; echo UART_Output_Complete ; echo ------------------' &");
 
die "*E: Verilog Compilation Failed!\n" if system("iverilog $IVL_OPTIONS");
die "*E: VVP execution error!\n" if system("vvp $VVP_PATH | tee $LOG_FILE_PATH");
/src/ts/arm_test/Config.cfg
16,7 → 16,6
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
UART_TX_TERMINAL => 0, # Disable UART TX terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/ts/factorial/Config.cfg
16,7 → 16,6
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
UART_TX_TERMINAL => 0,
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/ts/uart/Config.cfg
0,0 → 1,31
# TC config.
 
%Config = (
# CPU configuration.
DATA_CACHE_SIZE => 4096, # Data cache size in bytes
CODE_CACHE_SIZE => 4096, # Instruction cache size in bytes
CODE_SECTION_TLB_ENTRIES => 8, # Instruction section TLB entries.
CODE_SPAGE_TLB_ENTRIES => 32, # Instruction small page TLB entries.
CODE_LPAGE_TLB_ENTRIES => 16, # Instruction large page TLB entries.
DATA_SECTION_TLB_ENTRIES => 8, # Data section TLB entries.
DATA_SPAGE_TLB_ENTRIES => 32, # Data small page TLB entries.
DATA_LPAGE_TLB_ENTRIES => 16, # Data large page TLB entries.
BP_DEPTH => 1024, # Branch predictor depth.
INSTR_FIFO_DEPTH => 4, # Instruction buffer depth.
STORE_BUFFER_DEPTH => 16, # Store buffer depth.
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
DUMP_SIZE => 200, # Length of dump in bytes.
IRQ_EN => 0, # Make this 1 to enable IRQ signal from TB.
FIQ_EN => 0, # Make this 1 to enable FIQ signal from TB.
MAX_CLOCK_CYCLES => 150000, # Clock cycles to run the simulation for.
ALLOW_STALLS => 1, # Make this 1 to allow external RAM to signal a stall.
DEFINE_TLB_DEBUG => 0, # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
REG_CHECK => {},
FINAL_CHECK => {}
);
 
/src/ts/uart/Description.txt
0,0 → 1,31
This test displays a string to the TB UART output console.
/src/ts/uart/main.c
0,0 → 1,12
#include "uart.h"
 
char* str = "Hello World";
 
int main(void)
{
UARTInit();
UARTWrite(str);
return 0;
}
 
 
/src/ts/uart/makefile
0,0 → 1,2
# Execute the main Makefile.
include ../../scripts/makefile
/src/ts/uart/uart.c
0,0 → 1,38
#include "uart.h"
 
void UARTInit()
{
*UART_LCR = (*UART_LCR) | (1 << 7);
*UART_DLAB1 = 1;
*UART_DLAB2 = 0;
*UART_LCR = (*UART_LCR) & ~(1 << 7);
return 0;
}
 
void UARTWrite(char* s)
{
int len;
 
len = strlen(s);
 
for(int i=0;i<len;i++)
{
UARTWriteByte(s[i]);
}
}
 
void UARTWriteByte(char c)
{
*UART_THR = c;
}
 
int strlen(char* s)
{
int i;
i = 0;
 
while(s[i] != '\0')
i++;
 
return i;
}
/src/ts/uart/uart.h
0,0 → 1,14
#ifndef UART_H
 
#define UART_H
#define UART_DLAB1 ((char*)0xFFFFFFE0)
#define UART_DLAB2 ((char*)0xFFFFFFE1)
#define UART_THR ((char*)0xFFFFFFE0)
#define UART_LCR ((char*)0xFFFFFFE3)
 
void UARTInit(void);
void UARTWrite(char*);
void UARTWriteByte(char c);
int strlen(char*);
 
#endif
/src/ts/uart/uart.ld
0,0 → 1,16
 
/* Linker Script */
 
ENTRY(_Reset) /* _Reset is the entry point. This is the entry point in the bootstrap assembler */
 
/* Define how sections of the program are organized. */
SECTIONS
{
. = 0x00000; /* Location Counter. */
.text : { *(.text) } /* Text section is expected to be starting at 0x0.*/
.data : { *(.data) } /* Immediately followed by data section */
.bss : { *(.bss) *(COMMON) } /* Immediately followed by BSS section. Common sections are also included in BSS. */
. = ALIGN(8); /* Align the location counter. */
. = . + 0x1000; /* 4kB of descending stack memory */
stack_top = .; /* Make stack_top same as location counter. */
}
/src/ts/uart/uart.s
0,0 → 1,7
.text
.global _Reset
_Reset:
ldr sp, =#3500
bl main
here: b here
 

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