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zap/trunk/sw/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2 Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: zap/trunk/LICENSE.md =================================================================== --- zap/trunk/LICENSE.md (revision 42) +++ zap/trunk/LICENSE.md (nonexistent) @@ -1,339 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc., - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. 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Index: zap/trunk/src/doc/makefile =================================================================== --- zap/trunk/src/doc/makefile (revision 42) +++ zap/trunk/src/doc/makefile (nonexistent) @@ -1,39 +0,0 @@ -// --------------------------------------------------------------------------- -// -- -- -// -- (C) 2016-2018 Revanth Kamaraj. -- -// -- -- -// -- ------------------------------------------------------------------------ -// -- -- -// -- This program is free software; you can redistribute it and/or -- -// -- modify it under the terms of the GNU General Public License -- -// -- as published by the Free Software Foundation; either version 2 -- -// -- of the License, or (at your option) any later version. -- -// -- -- -// -- This program is distributed in the hope that it will be useful, -- -// -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -// -- GNU General Public License for more details. -- -// -- -- -// -- You should have received a copy of the GNU General Public License -- -// -- along with this program; if not, write to the Free Software -- -// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -// -- 02110-1301, USA. -- -// -- -- -// --------------------------------------------------------------------------- - -.DEFAULT_GOAL=view - -view: ../../doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf - evince ../../doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf - -../../doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf: zap_ug.tex - mkdir -p ../../doc/ ../../obj/doc/ - pdflatex -output-directory ../../obj/doc/ zap_ug.tex - mv ../../obj/doc/zap_ug.pdf ../../doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf - -clean: - rm -rfv ../../obj/doc/*zap_ug* ../../doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf - rm -rfv zap_ug.pdf zap_ug.log zap_ug.aux ZAP_PROCESSOR_CORE_DATASHEET.pdf - -.PHONY: view -.PHONY: clean Index: zap/trunk/src/doc/zap_ug.tex =================================================================== --- zap/trunk/src/doc/zap_ug.tex (revision 42) +++ zap/trunk/src/doc/zap_ug.tex (nonexistent) @@ -1,556 +0,0 @@ -% --------------------------------------------------------------------------- -% -- -- -% -- (C) 2016-2018 Revanth Kamaraj. -- -% -- -- -% -- ------------------------------------------------------------------------ -% -- -- -% -- This program is free software; you can redistribute it and/or -- -% -- modify it under the terms of the GNU General Public License -- -% -- as published by the Free Software Foundation; either version 2 -- -% -- of the License, or (at your option) any later version. -- -% -- -- -% -- This program is distributed in the hope that it will be useful, -- -% -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -% -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -% -- GNU General Public License for more details. -- -% -- -- -% -- You should have received a copy of the GNU General Public License -- -% -- along with this program; if not, write to the Free Software -- -% -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- -% -- 02110-1301, USA. -- -% -- -- -% --------------------------------------------------------------------------- - - - -\documentclass[10pt]{article} -\usepackage{graphicx} -\usepackage{tabularx} -\usepackage{verbatim} -\usepackage{listings} -\usepackage{longtable} - -\renewcommand{\familydefault}{\sfdefault} - -\title{ZAP Processor User Guide} -\author{Revanth Kamaraj} - -\begin{document} - -\lstset{language=Perl} -\maketitle - -\section{Introduction} - -ZAP is a synthesizable open source 32-bit RISC processor core capable of -executing ARM®v4T binaries at both the user and supervisor level. The processor -features a 10-stage pipeline that allows it to reach reasonable operating -frequencies. The processor supports standard I/D cache and memory management -that may be controlled using coprocessor \#15. Both the cache and TLB are direct -mapped. Caches, TLBs and branch memory are implemented as generic fully -synchronous RAMs that can efficiently map to native FPGA block RAM to save FPGA -resources. To simplify device integration, the memory bus is fully compliant -with Wishbone B3. A store buffer is implemented to improve performance. -\linebreak -\linebreak -NOTE: Please use pipeline retiming during synthesis for maximum timing performance. - -\subsection{CPU Clock and Reset} -ZAP uses a single clock called the core clock to drive the entire design. The -clock must be supplied to the port I\_CLK. ZAP expects a rising edge -synchronous I\_RESET (active high) to be applied i.e., -the reset signal must change only on the rising edges of clock. The reset -must be externally synchronized to the core clock before being applied to -the processor. - -\subsection{Block Digram} -\includegraphics{images/image004.png} - -\subsection{Pipeline Overview} - -\begin{tabularx} {\linewidth}{|r|X|} -\hline - -Stage & -Description \\ \hline - -Fetch & -Clocks data from I-cache into instruction register. Also branch predictor memory -is read out in this stage. \\ \hline - -FIFO & -Instructions and corresponding PC+8 values are clocked into a shallow buffer. - \\ \hline - -Thumb Decoder & -Converts 16-bit instructions to 32-bit ARM instructions. Instructions predicted -as taken cause the pipeline to change to the new predicted target. \\ \hline - -Predecode & -Handles coprocessor instructions, SWAP and LDM/STM. \\ \hline - -Decode & -Decodes ARM instructions. \\ \hline - -Issue & -Operand values are extracted here from the bypass network. In case data from -the bypass network is not available, the register file is read. \\ \hline - -Shift & -Performs shifts and multiplies. Contains a single level bypass network to -optimize away certain dependencies. Multiplication takes multiple clock cycles. \\ \hline - -Execute & -Contains the ALU. The ALU is single cycle and handles arithmetic and logical -operations. \\ \hline - -Memory & -Clocks data from the data cache into the pipeline. Aligns read data as -necessary. \\ \hline - -Writeback & -Writes to register file. Can sustain 2 writes per clock cycle although the -only use for the feature is accelerate LDR performance in the current -implementation. \\ \hline -\end{tabularx} -\\ -\\ -ZAP features a 10 stage pipeline. The pipeline has an extensive bypass network -to minimize pipeline stalls. A load accelerator allows data to be forwarded -from memory a cycle early. Most non-multiply instructions can be executed -within a single clock tick with no stalls. Exceptions to this rule are when -multiplies or non-trivial shifts are used. -\\ -\\ -The following code takes 3 cycles to execute because R1 needs to be shifted -and is not available until the first instruction enters the ALU: -\\ -\\ -ADD R1, R2, R3 \\ -ADD R4, R5, R1 LSL R2 \\ -\\ -\\ -If the second register is not source shifted by a register that depends on the -previous instruction, a data dependency check may be relaxed (Register R9 for -the second instruction can be obtained in issue itself so nothing is blocking -the second instruction from using the shifter) and thus the following code -takes 2 cycles to execute: -\\ -\\ -ADD R1, R2, R3 LSL R5 \\ -ADD R4, R1, R9 LSL R2 \\ -\\ -\\ -Another feature of the pipeline is that it can issue memory operations with -writeback in a single cycle. The following instructions takes 2 cycles to -execute assuming a perfect cache. -\\ -\\ -LDR R0, [R1, \#2]! \\ -ADD R1, R3, R4 LSL R1 \\ -\\ -\\ -The pipeline feedback unit is designed to reasonably minimize pipeline stalls. -Note however that pipeline bubble squashing is available only across the -instruction FIFO. - -\subsection{Features} - -\begin{itemize} -\item Fully synthesizable Verilog-2001 core. -\item Store buffer for improved performance. -\item Can execute ARMv4T code at both the user and supervisor level. -\item Wishbone B3 compatible interface. Cache unit supports burst access. -\item 10-stage pipeline design. Pipeline has bypass network to resolve - dependencies. -\item 2 write ports for the register file to allow LDR/STR with - writeback to execute as a single instruction. Note that the - register file is implemented using flip-flops. -\item Branch prediction supported. Uses a 2-bit state for each branch. -\item Split I and D writeback cache (Size can be configured using parameters). -\item Split I and D MMUs (TLB size can be configured using parameters). -\item Base restored abort model to simplify data abort handling. -\end{itemize} - -\subsection{Branch prediction mechanism} - -ZAP uses a relatively simple branch prediction mechanism (Note that the branch -table block RAM is read in Fetch). Note that when using ARM code, the amount of -branch table entries is cut by half since the lower 2 bits of PC are 0. A -simple state machine is used to reinforce or modify the status of a branch. The -pass and fail signals are generated from the ALU. - -\includegraphics{images/image008.png} -\\ -\includegraphics{images/image010.png} - -\subsection{Cache/TLB Overview} - -ZAP uses direct mapped cache (separate I/D) that is virtual. For decent -performance, the cache is writeback. To enable writeback, each cache line has -a dirty bit. The size of each cache line is fixed at 16 bytes. Since ARMv4 -specifies three kinds of paging schemes: section, large and small pages, 3 -TLB block RAMs are employed which are also direct mapped. ZAP has independent -instruction and data caches/TLBs. The cache/MMU setup is v4 compatible. The -cache should be enabled as soon as possible for good performance because the -memory subsystem is efficient for burst transactions. - -\includegraphics{images/image012.png} - -\subsection{Running Simulations} -\subsubsection{Creating and Simulating Test Cases} - -To create a test case, create a some assembly(.s extension) and -C files(.c extension) and a linker script(.ld extension) in the directory -\texttt{src/ts/$\langle$TestCase$\rangle$/} -\\ -\\ -Copy the \texttt{makefile} and \texttt{Config.cfg} from one of the existing test case directories -to the directory \texttt{src/ts/$\langle$TestCase$\rangle$/}. Edit the \texttt{Config.cfg} to suit the testcase. -\\ -\\ -To run simulations using the scripts provided, you will need Icarus -Verilog 10.0 or higher and 32-bit libraries installed. Object files and -waveform dumps can be found in the \texttt{obj/ts/$\langle$TestCase$\rangle$/} directory. -\\ -\\ -Enter \texttt{src/ts/$\langle$TestCase$\rangle$} and type \texttt{make}. -\\ -\\ -NOTE: Normally C files are directly converted to object files. To view the assembly code for a C file (say file.c), do \texttt{make c2asm X=file.c}. -This will create a file called \texttt{file.c.asm} in the corresponding object directory. -\\ -NOTE: To clean object files, enter \texttt{src/ts/$\langle$TestCase$\rangle$} and type \texttt{make clean}. -\\ -NOTE: To clean object files and the extracted GCC files, enter \texttt{src/ts/$\langle$TestCase$\rangle$} and type \texttt{make cleanall}. -\\ -\\ -NOTE: You can set the testbench and processor configuration in the \texttt{Config.cfg} -file that contains a Perl hash. This file is present in the same directory as -the test case. -\\ -\\ -Here's a sample of what the \texttt{Config.cfg} file should contain. -\\ -\\ -\begin{lstlisting}[frame=none] % Perl code block start. - -%Config = ( -# CPU configuration. -DATA_CACHE_SIZE => 4096,# Data cache size in bytes -CODE_CACHE_SIZE => 4096,# Instruction cache size in bytes -CODE_SECTION_TLB_ENTRIES => 8, # Instruction section TLB entries. -CODE_SPAGE_TLB_ENTRIES => 32, # Instruction small page TLB entries. -CODE_LPAGE_TLB_ENTRIES => 16, # Instruction large page TLB entries. -DATA_SECTION_TLB_ENTRIES => 8, # Data section TLB entries. -DATA_SPAGE_TLB_ENTRIES => 32, # Data small page TLB entries. -DATA_LPAGE_TLB_ENTRIES => 16, # Data large page TLB entries. -BP_DEPTH => 1024,# Branch predictor depth. -INSTR_FIFO_DEPTH => 4, # Instruction buffer depth. -STORE_BUFFER_DEPTH => 8, # Store buffer depth. -SYNTHESIS => 1, # Make this to 1 to simulate compile - # from a synthesis perspective. - -# Testbench configuration. -IRQ_EN => 1, # 1 Enables VIC connection to CPU in testbench. -UART_TX_TERMINAL => 0, # 1 Enables UART TX terminal. 0 disables it. -EXT_RAM_SIZE => 32768, # External RAM size in bytes. -SEED => -1, # Seed. Use -1 to use random seed. -DUMP_START => 2000, # Starting memory address from which to dump. -DUMP_SIZE => 200, # Length of dump in bytes. -MAX_CLOCK_CYCLES => 100000,# Clock cycles to run the simulation for. -ALLOW_STALLS => 1, # Make this 1 to allow - # external RAM to signal a stall. -DEFINE_TLB_DEBUG => 0, # Make this 1 to define - #TLB_DEBUG. Useful for debugging the TLB. - -# Make this an anonymous has with entries like -# "r10" => "32'h0" etc. These represent register -# values (expected) at the end of simulation. -REG_CHECK => {"r1" => "32'h4", - "r2" => "32'd3"}, - -# Make this an anonymous hash with entries like -# verilog_address => verilog_value etc. These -# represent expected memory values at the end of -# simulation. -FINAL_CHECK => {"32'h100" => "32'd4", - "32'h66" => "32'h4"} -); - -\end{lstlisting} - -\section{IO Ports and Configuration} - -\begin{tabularx} {\linewidth}{|r|r|X|} -\hline -Signal Name & IO & Description \\ \hline - -I\_CLK & -I & -Core clock. \\ \hline - -I\_RESET & -I & -Core reset. \\ \hline - -O\_WB\_CYC & -O & -Wishbone CYC signal. \\ \hline - -O\_WB\_STB & -O & -Wishbone STB signal. \\ \hline - -O\_WB\_ADR[31:0] & -O & -Wishbone 32-bit address. \\ \hline - -O\_WB\_SEL[3:0] & -O & -Wishbone byte lane enables. \\ \hline - -O\_WB\_WE & -O & -Wishbone write enable. \\ \hline - -O\_WB\_DAT[31:0] & -O & -Wishbone write data. \\ \hline - -O\_WB\_CTI[2:0] & -O & -Wishbone cycle type indicator. \newline -0b010 = Incrementing burst. \newline -0b111 = End of burst. \newline -The interface shall only generate one of the above 2 codes. -A single transfer is effectively a burst of length 1.\\ \hline - -O\_WB\_BTE[1:0] & -O & -Burst type extension tag. This always reads 0x0 to indicate that -the processor can only perform incrementing linear bursts (32-bit width). -\\ \hline - -I\_WB\_DAT[31:0] & -I & -Wishbone read data. \\ \hline - -I\_WB\_ACK & -I & -Wishbone acknowledge. \\ \hline - -I\_IRQ & -I & -IRQ Interrupt. \\ \hline - -I\_FIQ & -I & -FIQ Interrupt. \\ \hline -\end{tabularx} -\\ -\\ -Verilog parameters can be used to statically configure the processor instance -as shown in the table below. -\\ -\\ -\begin{tabularx}{\linewidth}{|r|X|X|} -\hline -Parameter & -Description & -Notes \\ \hline - -DATA\_CACHE\_SIZE[31:0] & -Data cache size in bytes. & -1 \\ \hline - -CODE\_CACHE\_SIZE[31:0] & -Instruction cache size in bytes. & -1 \\ \hline - -CODE\_SECTION\_TLB\_ENTRIES[31:0] & -Section TLB entries (CODE). & -2 \\ \hline - -CODE\_SPAGE\_TLB\_ENTRIES[31:0] & -Small page TLB entries (CODE). & -2 \\ \hline - -CODE\_LPAGE\_TLB\_ENTRIES[31:0] & -Large page TLB entries (CODE). & -2 \\ \hline - -DATA\_SECTION\_TLB\_ENTRIES[31:0] & -Section TLB entries (DATA). & -2 \\ \hline - -DATA\_SPAGE\_TLB\_ENTRIES[31:0] & -Small page TLB entries (DATA). & -2 \\ \hline - -DATA\_LPAGE\_TLB\_ENTRIES[31:0] & -Large page TLB entries (DATA). & -2 \\ \hline - -FIFO\_DEPTH[31:0] & -Depth of the fetch buffer in the pipeline. & -3 \\ \hline - -BP\_ENTRIES[31:0] & -Depth of the branch predictor memory. & -3 \\ \hline - -STORE\_BUFFER\_DEPTH[31:0] & -Set the depth of the store buffer. Do not set it to a value less than 16. & -4 \\ \hline -\end{tabularx} - -NOTE. \\ - -1. Should be a power of 2 and greater than 128 bytes. \\ - -2. Should be a power of 2 and must be at least 2 entries. \\ - -3. Should be a power of 2 and must be greater than 2. \\ - -4. Depth must be 16 or more and a power of 2. \\ -\\ - -\section{CP15 commands} - -ZAP features an ARMv4 compatible cache subsystem (cache and MMU). This subsystem -may be configured by issuing commands to specific CP \#15 registers using -coprocessor instructions. A list of supported CP \#15 commands/registers are -listed in the table below: -\\ -\\ -WARNING: In particular, cleaning and flushing of specific locations is not -supported. The OS should avoid issuing such commands. -\\ -\\ -\begin{longtable}{|p{0.5cm}|p{2cm}|p{6cm}|p{0.5cm}|} -\hline - -Reg. & Name & Description & Note \\ \hline - -0 & -ID & -[23:16] – Always reads 0x01 to indicate a v4 implementation. \newline -Other bits are UNDEFINED. & -1 \\ \hline - -1 & -CON & -[0] – MMU enable. \newline -[2] – Data cache enable. \newline -[8] – S bit. \newline -[9] – R bit. \newline -[12] – Instruction cache enable. \newline -READ ONLY bits are described in note 2. \newline -Bits other than the ones specified here and in note 2 are UNDEFINED. \newline -2 \\ \hline - -2 & -TRBASE & -Holds 16KB aligned base address of L1 table. & - \\ \hline - -3 & -DAC & -Domain Access Control Register. & - \\ \hline - -5 & -FSR & -Fault address register. & -4 \\ \hline - -6 & -FAR & -Fault status register. & -4 \\ \hline - -7 & -CACHECON & -Data written to this register should be zero else UNDEFINED operations can occur. \newline -\begin{tiny} -CACHECON control table. \newline - {\begin{tabularx}{\linewidth}{|X|X|X|} - \hline - Opcode2 & - CRm & - Description \\ \hline - \hline - 000 & - 0111 & - Flush all caches. \\ \hline - - 000 & - 0101 & - Flush I cache. \\ \hline - - 000 & - 0110 & - Flush D cache. \\ \hline - - 000 & - 1011 & - Clean all caches. \\ \hline - - 000 & - 1010 & - Clean D cache. \\ \hline - - 000 & - 1111 & - Clean and flush all caches. \\ \hline - - 000 & - 1110 & - Clean and flush D cache. \\ \hline - \end{tabularx}} \end{tiny} & - -3 \\ \hline - -8 & -TLBCON & -Data written to this register should be zero else UNDEFINED operations can occur. \newline -TLBCON Control table.\newline - {\begin{tabularx}{\linewidth}{|X|X|X|} - \hline - Opcode2 & - CRm & - Description \\ \hline - \hline - - 000 & - 0111 & - Flush all TLBs \\ \hline - - 000 & - 0101 & - Flush I TLB. \\ \hline - - 000 & - 0110 & - Flush D TLB. \\ \hline - \end{tabularx}} & - -3 \\ \hline -\end{longtable} - -NOTE: - -1. Read only. Writes have NO effect. \newline - -2. Processor does not check for address alignment ([1] reads 0), only supports -Little Endian access, full 32-bit, write buffer always enabled ([7:4] reads 0b0011), -does not support high vectors ([13] reads 0) and always has a predictable cache -strategy ([11] reads 1) i.e., direct mapped. \newline - -3. Reads are UNPREDICTABLE. \newline - -4. Only data MMU can update this. For debug purposes, these are RW registers. \newline - -\end{document} - Index: zap/trunk/src/doc/images/image010.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zap/trunk/src/doc/images/image010.png =================================================================== --- zap/trunk/src/doc/images/image010.png (revision 42) +++ zap/trunk/src/doc/images/image010.png (nonexistent)

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zap/trunk/src/doc/images/image002.jpg Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: zap/trunk/src/rtl/cpu/zap_alu_main.v =================================================================== --- zap/trunk/src/rtl/cpu/zap_alu_main.v (revision 42) +++ zap/trunk/src/rtl/cpu/zap_alu_main.v (revision 43) @@ -38,13 +38,6 @@ parameter [31:0] FLAG_WDT = 32'd32 // Width of active CPSR. ) ( - /********************************************************************** - * - * INPUTS - * - *********************************************************************/ - - // ------------------------------------------------------------------ // Decompile Interface. Only for debug. // ------------------------------------------------------------------ @@ -131,12 +124,6 @@ input wire [zap_clog2(ALU_OPS)-1:0] i_alu_operation_ff, // Operation to perform. input wire i_flag_update_ff, // Update flags if 1. - /********************************************************************** - * - * OUTPUTS - * - *********************************************************************/ - // ----------------------------------------------------------------- // ALU result // ----------------------------------------------------------------- @@ -202,40 +189,21 @@ ); // ---------------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------------- `include "zap_defines.vh" `include "zap_localparams.vh" `include "zap_functions.vh" -wire [31:0] mem_srcdest_value_nxt; -wire [3:0] ben_nxt; +// ----------------------------------------------------------------------------- +// Localparams +// ----------------------------------------------------------------------------- -// Address about to be output. Used to drive tag RAMs etc. -reg [31:0] mem_address_nxt; - /* - For memory stores, we must generate correct byte enables. This is done - by examining access type inputs. For loads, always 1111 is generated. - If there is neither a load or a store, the old value is preserved. -*/ -assign ben_nxt = /*i_mem_store_ff ?*/ generate_ben ( - i_mem_unsigned_byte_enable_ff, - i_mem_signed_byte_enable_ff, - i_mem_unsigned_halfword_enable_ff, - i_mem_unsigned_halfword_enable_ff, - mem_address_nxt) /*: i_mem_load_ff ? 4'b1111 : o_ben_ff*/; - -assign mem_srcdest_value_nxt = duplicate ( - i_mem_unsigned_byte_enable_ff, - i_mem_signed_byte_enable_ff, - i_mem_unsigned_halfword_enable_ff, - i_mem_unsigned_halfword_enable_ff, - i_mem_srcdest_value_ff ); - -/* - These override global N,Z,C,V definitions which are on CPSR. These params - are localized over the 4-bit flag structure. -*/ + * These override global N,Z,C,V definitions which are on CPSR. These params + * are localized over the 4-bit flag structure. + */ localparam [1:0] _N = 2'd3; localparam [1:0] _Z = 2'd2; localparam [1:0] _C = 2'd1; @@ -247,6 +215,19 @@ localparam [1:0] WT = 2'd2; localparam [1:0] ST = 2'd3; +// ------------------------------------------------------------------------------ +// Variables +// ------------------------------------------------------------------------------ + +// Memory srcdest value (i.e., data) +wire [31:0] mem_srcdest_value_nxt; + +// Byte enable generator. +wire [3:0] ben_nxt; + +// Address about to be output. Used to drive tag RAMs etc. +reg [31:0] mem_address_nxt; + /* Sleep flop. When 1 unit sleeps i.e., does not produce any output except on the first clock cycle where LR is calculated using the ALU. @@ -268,6 +249,58 @@ reg [5:0] clz_rm; // Count leading zeros in Rm. +// Destination index about to be output. +reg [zap_clog2(PHY_REGS)-1:0] o_destination_index_nxt; + +// 1s complement of Rm and Rn. +wire [31:0] not_rm = ~rm; +wire [31:0] not_rn = ~rn; + +// Wires which connect to an adder. +reg [31:0] op1, op2; +reg cin; + +// 32-bit adder with carry input and carry output. +wire [32:0] sum = {1'd0, op1} + {1'd0, op2} + {32'd0, cin}; + +reg [31:0] tmp_flags, tmp_sum; + +// Opcode. +wire [zap_clog2(ALU_OPS)-1:0] opcode = i_alu_operation_ff; + +// ------------------------------------------------------------------------------- +// Assigns +// ------------------------------------------------------------------------------- + +/* + For memory stores, we must generate correct byte enables. This is done + by examining access type inputs. For loads, always 1111 is generated. + If there is neither a load or a store, the old value is preserved. +*/ +assign ben_nxt = generate_ben ( + i_mem_unsigned_byte_enable_ff, + i_mem_signed_byte_enable_ff, + i_mem_unsigned_halfword_enable_ff, + i_mem_unsigned_halfword_enable_ff, + mem_address_nxt); + +assign mem_srcdest_value_nxt = duplicate ( + i_mem_unsigned_byte_enable_ff, + i_mem_signed_byte_enable_ff, + i_mem_unsigned_halfword_enable_ff, + i_mem_unsigned_halfword_enable_ff, + i_mem_srcdest_value_ff ); + +/* + Hijack interface. Data aborts use the hijack interface to find return + address. The writeback drives the ALU inputs to find the final output. +*/ +assign o_hijack_sum = sum; + +// ------------------------------------------------------------------------------- +// CLZ logic. +// ------------------------------------------------------------------------------- + always @* // CLZ implementation. begin casez(rm) @@ -307,32 +340,9 @@ endcase end -// Destination index about to be output. -reg [zap_clog2(PHY_REGS)-1:0] o_destination_index_nxt; - -// 1s complement of Rm and Rn. -wire [31:0] not_rm = ~rm; -wire [31:0] not_rn = ~rn; - -// Wires which connect to an adder. -reg [31:0] op1, op2; -reg cin; - -// 32-bit adder with carry input and carry output. -wire [32:0] sum = {1'd0, op1} + {1'd0, op2} + {32'd0, cin}; - -reg [31:0] tmp_flags, tmp_sum; - -// Opcode. -wire [zap_clog2(ALU_OPS)-1:0] opcode = i_alu_operation_ff; - -/* - Hijack interface. Data aborts use the hijack interface to find return - address. The writeback drives the ALU inputs to find the final output. -*/ -assign o_hijack_sum = sum; - // ---------------------------------------------------------------------------- +// Aliases +// ---------------------------------------------------------------------------- always @* begin @@ -342,15 +352,16 @@ o_flags_nxt = flags_nxt; end +// ----------------------------------------------------------------------------- // Sequential logic. +// ----------------------------------------------------------------------------- + always @ (posedge i_clk) begin if ( i_reset ) begin - // // On reset, processor enters supervisory mode with interrupts // masked. - // clear ( {1'd1,1'd1,1'd0,SVC} ); end else if ( i_clear_from_writeback ) @@ -415,7 +426,7 @@ // ---------------------------------------------------------------------------- -always @ (posedge i_clk) // Wishbone flops. +always @ ( posedge i_clk ) // Wishbone flops. begin // Wishbone updates. o_data_wb_cyc_ff <= o_data_wb_cyc_nxt; @@ -426,7 +437,11 @@ o_mem_address_ff <= o_address_nxt; end -always @* // Wishbone next state logic. +// ----------------------------------------------------------------------------- +// WB next state logic. +// ----------------------------------------------------------------------------- + +always @* begin // Preserve values. o_data_wb_cyc_nxt = o_data_wb_cyc_ff; @@ -446,9 +461,12 @@ o_data_wb_cyc_nxt = 0; o_data_wb_stb_nxt = 0; end - else if ( i_data_stall ) begin end + else if ( i_data_stall ) + begin + // Save state. + end else if ( i_data_mem_fault || sleep_ff ) - begin + begin o_data_wb_cyc_nxt = 0; o_data_wb_stb_nxt = 0; end @@ -464,61 +482,40 @@ end // ---------------------------------------------------------------------------- +// Used to generate access address. +// ---------------------------------------------------------------------------- -always @* -begin:pre_post_index - // Memory address output based on pre or post index. - if ( i_mem_pre_index_ff == 0 ) // Post-index. Update is done after memory access. - mem_address_nxt = rn; - else // Pre-index. Update is done before memory access. - mem_address_nxt = o_alu_result_nxt; - - // - // If a force 32 align is set, make the lower 2 bits as zero. - // Force 32 align is valid for Thumb. - // - if ( i_force32align_ff ) - mem_address_nxt[1:0] = 2'b00; - - // - // Do not change address if not needed. - // If not a load OR a store. Preserve this value. Power saving. - // +always @ (*) +begin:pre_post_index_address_generator + /* + * Do not change address if not needed. + * If not a load OR a store. Preserve this value. Power saving. + */ if (!( (i_mem_load_ff || i_mem_store_ff) && o_dav_nxt )) mem_address_nxt = o_mem_address_ff; + else + begin + /* + * Memory address output based on pre or post index. + * For post-index, update is done after memory access. + * For pre-index, update is done before memory access. + */ + if ( i_mem_pre_index_ff == 0 ) + mem_address_nxt = rn; // Postindex; + else + mem_address_nxt = o_alu_result_nxt; // Preindex. + + // If a force 32 align is set, make the lower 2 bits as zero. + if ( i_force32align_ff ) + mem_address_nxt[1:0] = 2'b00; + end end -// ---------------------------------------------------------------------------- +// --------------------------------------------------------------------------------- +// Used to generate ALU result + Flags +// --------------------------------------------------------------------------------- -`ifndef SYNTHESIS - -reg [64*8-1:0] OPCODE; - always @* -case(opcode) -AND:begin OPCODE = "AND"; end -EOR:begin OPCODE = "EOR"; end -MOV:begin OPCODE = "MOV"; end -MVN:begin OPCODE = "MVN"; end -BIC:begin OPCODE = "BIC"; end -ORR:begin OPCODE = "ORR"; end -TST:begin OPCODE = "TST"; end -TEQ:begin OPCODE = "TEQ"; end -CLZ:begin OPCODE = "CLZ"; end -FMOV:begin OPCODE = "FMOV"; end -ADD:begin OPCODE = "ADD"; end -ADC:begin OPCODE = "ADC"; end -SUB:begin OPCODE = "SUB"; end -RSB:begin OPCODE = "RSB"; end -SBC:begin OPCODE = "SBC"; end -RSC:begin OPCODE = "RSC"; end -CMP:begin OPCODE = "CMP"; end -CMN:begin OPCODE = "CMN"; end -endcase - -`endif - -always @* begin: alu_result // Default value. @@ -543,11 +540,11 @@ ); end - // - // Flag MOV i.e., MOV to CPSR or MMOV. - // FMOV moves to CPSR and flushes the pipeline. - // MMOV moves to SPSR and does not flush the pipeline. - // + /* + * Flag MOV(FMOV) i.e., MOV to CPSR and MMOV handler. + * FMOV moves to CPSR and flushes the pipeline. + * MMOV moves to SPSR and does not flush the pipeline. + */ else if ( opcode == FMOV || opcode == MMOV ) begin: fmov_mmov integer i; @@ -566,11 +563,11 @@ tmp_sum[i] = rm[i]; end - // - // FMOV moves to the CPSR in ALU and writeback. - // No register is changed. The MSR out of this will have - // a target to CPSR. - // + /* + * FMOV moves to the CPSR in ALU and writeback. + * No register is changed. The MSR out of this will have + * a target to CPSR. + */ if ( opcode == FMOV ) begin tmp_flags = tmp_sum; @@ -584,7 +581,7 @@ op = opcode; - // Assign output of adder to flags. + // Assign output of adder to flags after some minimal logic. c = sum[32]; z = (sum[31:0] == 0); n = sum[31]; @@ -591,21 +588,13 @@ // Overflow. if ( ( op == ADD || op == ADC || op == CMN ) && (rn[31] == rm[31]) && (sum[31] != rn[31]) ) - begin v = 1; - end else if ( (op == RSB || op == RSC) && (rm[31] == !rn[31]) && (sum[31] != rm[31] ) ) - begin v = 1; - end else if ( (op == SUB || op == SBC || op == CMP) && (rn[31] == !rm[31]) && (sum[31] != rn[31]) ) - begin v = 1; - end else - begin v = 0; - end // // If you choose not to update flags, do not change the flags. @@ -623,6 +612,8 @@ end // ---------------------------------------------------------------------------- +// Flag propagation and branch prediction feedback unit +// ---------------------------------------------------------------------------- always @* begin: flags_bp_feedback @@ -641,9 +632,8 @@ begin // // Any sign of an interrupt is present, put unit to sleep. - // The current instruction will not be executed ultimately - // but rather a SUB LR, PC, 4 will be which will be stored in - // the link register. + // The current instruction will not be executed ultimately. + // However o_dav_nxt = 1 since interrupt must be carried on. // o_dav_nxt = 1'd1; sleep_nxt = 1'd1; @@ -658,10 +648,10 @@ end else if ( i_destination_index_ff == ARCH_PC && (i_condition_code_ff != NV)) begin - if ( i_flag_update_ff && o_dav_nxt ) - // PC update with S bit. - // Will restore CPU mode from SPSR. USR no change. + if ( i_flag_update_ff && o_dav_nxt ) // PC update with S bit. Context restore. begin + $display($time, " - %m :: Saw PC update with S bit set. Context restore initiated."); + o_destination_index_nxt = PHY_RAZ_REGISTER; o_clear_from_alu = 1'd1; o_pc_from_alu = tmp_sum; @@ -670,16 +660,23 @@ end else if ( o_dav_nxt ) // Branch taken and no flag update. begin - if ( i_taken_ff == SNT || i_taken_ff == WNT ) - // Incorrectly predicted as not-taken. + if ( i_taken_ff == SNT || i_taken_ff == WNT ) // Incorrectly predicted. begin // Quick branches - Flush everything before. - - // Dumping ground since PC change is done. + // Dumping ground since PC change is done. Jump to branch target for fast switching. o_destination_index_nxt = PHY_RAZ_REGISTER; o_clear_from_alu = 1'd1; o_pc_from_alu = tmp_sum; - flags_nxt[T] = i_switch_ff ? tmp_sum[0] : flags_ff[T]; // Thumb/ARM state if i_switch_ff = 1. + + if ( i_switch_ff ) + begin + flags_nxt[T] = tmp_sum[0]; + + if ( tmp_sum[0] ) + $display($time, " - %m :: Entering T state."); + else + $display($time, " - %m :: Entering A state."); + end end else // Correctly predicted. begin @@ -686,31 +683,28 @@ // If thumb bit changes, flush everything before if ( i_switch_ff ) begin - // // Quick branches! PC goes to RAZ register since // change is done. - // + o_destination_index_nxt = PHY_RAZ_REGISTER; - o_clear_from_alu = 1'd1; - o_pc_from_alu = tmp_sum; - flags_nxt[T] = i_switch_ff ? tmp_sum[0] : flags_ff[T]; - // Thumb/ARM state if i_switch_ff = 1. + o_pc_from_alu = tmp_sum; // Jump to branch target. + flags_nxt[T] = tmp_sum[0]; + + if ( tmp_sum[0] ) + $display($time, " - %m :: Entering T state."); + else + $display($time, " - %m :: Entering A state."); end else begin - // - // No mode change, do not change - // anything. - // + // No mode change, do not change anything. + o_destination_index_nxt = PHY_RAZ_REGISTER; - o_clear_from_alu = 1'd0; - flags_nxt[T] = i_switch_ff ? tmp_sum[0]: flags_ff[T]; + o_clear_from_alu = 1'd0; - // - // Send confirmation message to branch - // predictor. - // + // Send confirmation message to branch predictor. + o_pc_from_alu = 32'd0; o_confirm_from_alu = 1'd1; end @@ -719,15 +713,16 @@ else // Branch not taken begin if ( i_taken_ff == WT || i_taken_ff == ST ) - // Wrong prediction as taken... + // Wrong prediction as taken. Go back to the same + // branch. Non branches are always predicted as not-taken. + // GO BACK TO THE SAME BRANCH AND INFORM PREDICTOR OF ITS + // MISTAKE - THE NEXT TIME THE PREDICTION WILL BE NOT-TAKEN. begin - // Go to the same branch. o_clear_from_alu = 1'd1; o_pc_from_alu = i_pc_ff; end - else + else // Correct prediction. begin - // Correct prediction. o_clear_from_alu = 1'd0; o_pc_from_alu = 32'd0; end @@ -736,6 +731,7 @@ else if ( i_mem_srcdest_index_ff == ARCH_PC && o_dav_nxt && i_mem_load_ff) begin // Loads to PC also puts the unit to sleep. + $display($time, " - %m :: ALU saw a load to R15. Sleeping to prevent further instructions from executing."); sleep_nxt = 1'd1; end @@ -745,6 +741,8 @@ end // ---------------------------------------------------------------------------- +// MUX structure on the inputs of the adder. +// ---------------------------------------------------------------------------- // These are adder connections. Data processing and FMOV use these. always @* @@ -774,6 +772,7 @@ // Target is not written. CMP: begin op1 = rn ; op2 = not_rm ; cin = 32'd1; end CMN: begin op1 = rn ; op2 = rm ; cin = 32'd0; end + default: begin op1 = 0; @@ -784,11 +783,18 @@ end // ---------------------------------------------------------------------------- +// Functions +// ---------------------------------------------------------------------------- // Process logical instructions. function [35:0] process_logical_instructions -( input [31:0] rn, rm, input [3:0] flags, input [zap_clog2(ALU_OPS)-1:0] op, - input i_flag_upd, input nozero ); +( + input [31:0] rn, + input [31:0] rm, + input [3:0] flags, + input [zap_clog2(ALU_OPS)-1:0] op, + input i_flag_upd, input nozero +); begin: blk2 reg [31:0] rd; reg [3:0] flags_out; @@ -825,10 +831,8 @@ flags_out[_C] = i_shift_carry_ff; if ( nozero ) - // // This specifically states that we must NOT set the // ZERO flag under any circumstance. - // flags_out[_Z] = 1'd0; else flags_out[_Z] = (rd == 0); @@ -840,8 +844,11 @@ end endfunction -// ---------------------------------------------------------------------------- - +/* + * This task clears out the flip-flops in this module. + * The flag input is used to preserve/force flags to + * a specific state. + */ task clear ( input [31:0] flags ); begin o_dav_ff <= 0; @@ -857,14 +864,18 @@ end endtask -// ---------------------------------------------------------------------------- +/* + * The reason we use the duplicate function is to copy value over the memory + * bus for memory stores. If we have a byte write to address 1, then the + * memory controller basically takes address 0 and byte enable 0010 and writes + * to address 1. This enables implementation of a 32-bit memory controller + * with byte enables to control updates as is commonly done. Basically this + * is to faciliate byte and halfword based writes on a 32-bit aligned memory + * bus using byte enables. The rules are simple: + * For a byte access - duplicate the lower byte of the register 4 times. + * For halfword access - duplicate the lower 16-bit of the register twice. + */ -// The reason we use the duplicate function is to copy value over the memory -// bus for memory stores. If we have a byte write to address 1, then the -// memory controller basically takes address 0 and byte enable 0010 and writes -// to address 1. This enables implementation of a 32-bit memory controller -// with byte enables to control updates as is common. - function [31:0] duplicate ( input ub, // Unsigned byte. input sb, // Signed byte. input uh, // Unsigned halfword. @@ -891,9 +902,19 @@ end endfunction -// ---------------------------------------------------------------------------- - -// Generate byte enables based on access mode. +/* + * Generate byte enables based on access mode. + * This function is similar in spirit to the previous one. The + * byte enables are generated in such a way that along with + * duplicate - byte and halfword accesses are possible. + * Rules - + * For a byte access, generate a byte enable with a 1 at the + * position that the lower 2-bits read (0,1,2,3). + * For a halfword access, based on lower 2-bits, if it is 00, + * make no change to byte enable (0011) else if it is 10, then + * make byte enable as (1100) which is basically the 32-bit + * address + 2 (and 3) which will be written. + */ function [3:0] generate_ben ( input ub, // Unsigned byte. input sb, // Signed byte. input uh, // Unsigned halfword. @@ -926,19 +947,48 @@ end endfunction // generate_ben -`ifndef SYNTHESIS +// assertions_start + /* + * This assertion ensures that no privilege escalation is possible. + * It does so by ensuring that the flag register cannot change out + * of USR during normal operation. + */ always @* begin if ( flags_nxt[`CPSR_MODE] != USR && flags_ff[`CPSR_MODE] == USR ) begin - $display($time, "Error: %m CPU is changing out of USR mode without an exception..."); + $display($time, " - %m :: Error: Privilege Escalation Error."); $stop; end end -`endif + reg [64*8-1:0] OPCODE; + + always @* + case(opcode) + AND:begin OPCODE = "AND"; end + EOR:begin OPCODE = "EOR"; end + MOV:begin OPCODE = "MOV"; end + MVN:begin OPCODE = "MVN"; end + BIC:begin OPCODE = "BIC"; end + ORR:begin OPCODE = "ORR"; end + TST:begin OPCODE = "TST"; end + TEQ:begin OPCODE = "TEQ"; end + CLZ:begin OPCODE = "CLZ"; end + FMOV:begin OPCODE = "FMOV"; end + ADD:begin OPCODE = "ADD"; end + ADC:begin OPCODE = "ADC"; end + SUB:begin OPCODE = "SUB"; end + RSB:begin OPCODE = "RSB"; end + SBC:begin OPCODE = "SBC"; end + RSC:begin OPCODE = "RSC"; end + CMP:begin OPCODE = "CMP"; end + CMN:begin OPCODE = "CMN"; end + endcase +// assertions_end + endmodule // zap_alu_main.v `default_nettype wire

/zap/trunk/src/rtl/cpu/zap_cache.v

/zap/trunk/src/rtl/cpu/zap_cache_fsm.v

/zap/trunk/src/rtl/cpu/zap_cache_tag_ram.v

/zap/trunk/src/rtl/cpu/zap_core.v

/zap/trunk/src/rtl/cpu/zap_cp15_cb.v

/zap/trunk/src/rtl/cpu/zap_decode.v