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URL https://opencores.org/ocsvn/zet86/zet86/trunk

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Rev 37 → Rev 36

/trunk/tests/i86/Makefile
1,9 → 1,8
#s3roms := $(patsubst %.s,%.s3rom,$(wildcard *.s))
s3roms := $(patsubst %.s,%.s3rom,$(wildcard *.s))
ml403roms := $(patsubst %.s,%.bin,$(wildcard *.s))
rtlroms := $(patsubst %.s,%.rtlrom,$(wildcard *s))
all: $(ml403roms) $(rtlroms)
 
all: $(ml403roms)
 
# altera: ../../altera/zet/simulation/modelsim/bios0.dat ../../altera/zet/simulation/modelsim/bios1.dat
 
# ../../altera/zet/simulation/modelsim/bios0.dat: bios0.out
/trunk/tests/i86/09_vdu.s
2,28 → 2,8
start:
movw $0xb800, %dx
movw %dx, %ds
movw $0x20, %cx
movw $11, %bx
 
b:
movw $0x4d03, (%bx)
addw $2, %bx
loop b
 
movb $0x36, %al
outb %al, $0xb7
 
movw $0x0, %dx
movw %dx, %ds
 
movw $0x1234, (2)
movb $0x56, (5)
movb $0x26, (6)
movw $0x4567, (9)
 
movw (5), %ax
movw %ax, (0)
 
movw $0x034d, (4)
movw (1), %cx
hlt
 
.org 65520
/trunk/rtl-model/exec.v
26,7 → 26,6
output [15:0] x,
output [15:0] y,
output [15:0] aluo,
output [15:0] sp,
`endif
input [`IR_SIZE-1:0] ir,
input [15:0] off,
72,11 → 71,7
// Module instances
alu alu0( {c, a }, bus_b, aluout, t, func, alu_iflags, oflags,
alu_word, s, off, clk, dive);
regfile reg0 (
`ifdef DEBUG
sp,
`endif
a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
regfile reg0( a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
~byteop, a_byte, b_byte, c_byte, cx_zero, wrip0);
jmp_cond jc0( logic_flags, addr_b, addr_c[0], c, jmp);
/trunk/rtl-model/cpu.v
31,7 → 31,6
output [15:0] y,
output [15:0] imm,
output [15:0] aluo,
output [15:0] sp,
`endif
 
// Wishbone master interface
102,7 → 101,6
.x (x),
.y (y),
.aluo (aluo),
.sp (sp),
`endif
.ir (ir),
.off (off),
/trunk/rtl-model/fetch.v
63,6 → 63,7
wire prefix, repz_pr, sovr_pr;
wire next_in_opco, next_in_exec;
wire need_modrm, need_off, need_imm, off_size, imm_size;
wire dive;
 
reg [7:0] opcode_l, modrm_l;
reg [15:0] off_l, imm_l;
72,7 → 73,7
// Module instantiation
decode decode0(opcode, modrm, off_l, imm_l, pref_l[1], clk, rst, block,
exec_st, div_exc, need_modrm, need_off, need_imm, off_size,
imm_size, rom_ir, off, imm_d, end_seq, sop_l);
imm_size, rom_ir, off, imm_d, end_seq, dive, sop_l);
next_or_not nn0(pref_l, opcode[7:1], cx_zero, zf, next_in_opco,
next_in_exec);
nstate ns0(state, prefix, need_modrm, need_off, need_imm, end_seq,
253,6 → 254,7
output [15:0] off_o,
output [15:0] imm_o,
output end_seq,
output reg dive,
 
input [2:0] sop_l
);
263,7 → 265,6
wire [3:0] src, dst, base, index;
wire [1:0] seg;
reg [`SEQ_ADDR_WIDTH-1:0] seq;
reg dive;
 
// Module instantiations
opcode_deco opcode_deco0 (opcode, modrm, rep, sop_l, base_addr, need_modrm,
/trunk/rtl-model/util/div_uu.v
34,10 → 34,10
 
// CVS Log
//
// $Id: div_uu.v,v 1.2 2008-10-20 00:48:28 zeus Exp $
// $Id: div_uu.v,v 1.1 2008-10-10 04:04:11 zeus Exp $
//
// $Date: 2008-10-20 00:48:28 $
// $Revision: 1.2 $
// $Date: 2008-10-10 04:04:11 $
// $Revision: 1.1 $
// $Author: zeus $
// $Locker: $
// $State: Exp $
149,7 → 149,7
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= d_pipe[n0-1];
d_pipe[n0] <= #1 d_pipe[n0-1];
 
// generate internal remainder pipe
always @(z)
158,16 → 158,16
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
 
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= 0;
q_pipe[0] <= #1 0;
 
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
 
 
// flags (divide_by_zero, overflow)
181,26 → 181,26
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= ovf_pipe[n3-1];
div0_pipe[n3] <= div0_pipe[n3-1];
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
 
// assign outputs
always @(posedge clk)
if(ena)
ovf <= ovf_pipe[d_width];
ovf <= #1 ovf_pipe[d_width];
 
always @(posedge clk)
if(ena)
div0 <= div0_pipe[d_width];
div0 <= #1 div0_pipe[d_width];
 
always @(posedge clk)
if(ena)
q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
 
always @(posedge clk)
if(ena)
s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
 
 
/trunk/rtl-model/util/div_su.v
35,10 → 35,10
 
// CVS Log
//
// $Id: div_su.v,v 1.2 2008-10-20 00:48:28 zeus Exp $
// $Id: div_su.v,v 1.1 2008-10-10 04:04:11 zeus Exp $
//
// $Date: 2008-10-20 00:48:28 $
// $Revision: 1.2 $
// $Date: 2008-10-10 04:04:11 $
// $Revision: 1.1 $
// $Author: zeus $
// $Locker: $
// $State: Exp $
100,17 → 100,17
always @(posedge clk)
if (ena)
if (d[d_width-1])
id <= ~d +1'h1;
id <= #1 ~d +1'h1;
else
id <= d;
id <= #1 d;
 
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= ~z +1'h1;
iz <= #1 ~z +1'h1;
else
iz <= z;
iz <= #1 z;
 
// generate szpipe (z sign bit pipe)
integer n;
117,10 → 117,10
always @(posedge clk)
if(ena)
begin
szpipe[0] <= z[z_width-1];
szpipe[0] <= #1 z[z_width-1];
 
for(n=1; n <= d_width+1; n=n+1)
szpipe[n] <= szpipe[n-1];
szpipe[n] <= #1 szpipe[n-1];
end
 
// generate sdpipe (d sign bit pipe)
128,10 → 128,10
always @(posedge clk)
if(ena)
begin
sdpipe[0] <= d[d_width-1];
sdpipe[0] <= #1 d[d_width-1];
 
for(m=1; m <= d_width+1; m=m+1)
sdpipe[m] <= sdpipe[m-1];
sdpipe[m] <= #1 sdpipe[m-1];
end
 
// hookup non-restoring divider
151,10 → 151,10
always @(posedge clk)
if(ena)
begin
q <= (szpipe[d_width+1]^sdpipe[d_width+1]) ?
((~iq) + 1'h1) : ({1'b0, iq});
s <= (szpipe[d_width+1]) ?
((~is) + 1'h1) : ({1'b0, is});
q <= #1 (szpipe[d_width+1]^sdpipe[d_width+1]) ?
((~iq) + 1'h1) : ({1'b0, iq});
s <= #1 (szpipe[d_width+1]) ?
((~is) + 1'h1) : ({1'b0, is});
end
 
// delay flags same as results
161,7 → 161,7
always @(posedge clk)
if(ena)
begin
div0 <= idiv0;
ovf <= iovf;
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule
/trunk/rtl-model/regfile.v
18,13 → 18,7
 
`timescale 1ns/10ps
 
`include "defines.v"
 
module regfile (
`ifdef DEBUG
output [15:0] sp,
`endif
 
output [15:0] a,
output [15:0] b,
output [15:0] c,
59,9 → 53,6
wire [7:0] a8, b8, c8;
 
// Assignments
`ifdef DEBUG
assign sp = r[4];
`endif
assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a[1:0]][15:8] : r[addr_a][7:0];
 
/trunk/rtl-model/alu.v
53,7 → 53,7
.x (x[15:0]),
.func (func),
.out (cnv),
.iflags ({afi, cfi}),
.iflags ({afi, ofi, cfi}),
.oflags ({af_cnv, of_cnv, cf_cnv})
);
 
157,7 → 157,7
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
input [ 2:0] iflags, // afi, ofi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
 
190,7 → 190,7
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
 
assign afi = iflags[1];
assign afi = iflags[2];
assign cfi = iflags[0];
 
assign afo = acond;
/trunk/rtl-model/defines.v
23,4 → 23,4
`define ADD_IP `IR_SIZE'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8'h90
 
`define DEBUG 1
// `define DEBUG 1
/trunk/impl/virtex4-ml403ep/kotku.v
6,14 → 6,13
output rw_,
output e_,
output [7:4] db_,
input but_,
 
`endif
 
output tft_lcd_clk_,
output [ 1:0] tft_lcd_r_,
output [ 1:0] tft_lcd_g_,
output [ 1:0] tft_lcd_b_,
output tft_lcd_r_,
output tft_lcd_g_,
output tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
 
29,7 → 28,7
output sram_adv_ld_n_,
output flash_ce2_,
 
output [ 8:0] leds_
input but_
);
 
// Net declarations
37,30 → 36,14
wire rst_lck;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [19:1] adr;
wire [19:0] adr;
wire we;
wire tga;
wire mio;
wire stb;
wire ack;
wire [15:0] io_dat_i;
wire [ 1:0] sel;
wire cyc;
wire [15:0] vdu_dat_o;
wire vdu_ack_o;
wire vdu_arena;
wire [15:0] flash_dat_o;
wire flash_stb;
wire flash_ack;
wire flash_arena;
wire io_ack;
wire [15:0] zbt_dat_o;
wire zbt_stb;
wire zbt_ack;
wire [20:0] flash_addr_;
wire [20:0] sram_addr_;
wire flash_we_n_;
wire sram_we_n_;
wire io_op;
wire byte_o;
wire [15:0] dat_io;
wire [15:0] dat_mem;
 
`ifdef DEBUG
wire [35:0] control0;
74,18 → 57,13
wire [19:0] pc;
wire [15:0] cs, ip;
wire [15:0] aluo;
wire [ 2:0] cnt;
wire op;
wire [15:0] sp;
reg rst;
`else
wire rst;
wire [ 2:0] curr_st;
reg dbg;
`endif
 
// Register declarations
reg [15:0] io_reg;
reg [ 1:0] vdu_stb_sync;
reg [ 1:0] vdu_ack_sync;
reg rst;
 
// Module instantiations
clock c0 (
98,70 → 76,41
.rst (rst_lck)
);
 
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (adr[11:1]),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_ack_o (vdu_ack_o),
 
mem_map mem_map0 (
`ifdef DEBUG
.curr_st (curr_st),
`endif
// VGA pad signals
.vdu_clk (tft_lcd_clk_),
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_)
);
.vert_sync (tft_lcd_vsync_),
 
flash_cntrl fc0 (
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_o (flash_dat_o),
.wb_adr_i ({adr[17], adr[15:1]}),
.wb_stb_i (flash_stb),
.wb_cyc_i (flash_stb),
.wb_ack_o (flash_ack),
// Wishbone signals
.clk_i (clk),
.rst_i (rst_lck),
.adr_i (adr),
.dat_i (dat_o),
.dat_o (dat_mem),
.we_i (we),
.ack_o (ack),
.stb_i (stb & !mio),
.byte_i (byte_o),
 
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (sram_flash_data_),
.flash_we_n_ (flash_we_n_),
.flash_ce2_ (flash_ce2_)
.sram_clk_ (sram_clk_),
.sram_flash_addr_ (sram_flash_addr_),
.sram_flash_data_ (sram_flash_data_),
.sram_flash_oe_n_ (sram_flash_oe_n_),
.sram_flash_we_n_ (sram_flash_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.sram_adv_ld_n_ (sram_adv_ld_n_),
.flash_ce2_ (flash_ce2_)
);
 
zbt_cntrl zbt0 (
`ifdef DEBUG
.cnt (cnt),
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (zbt_stb),
.wb_cyc_i (zbt_stb),
.wb_ack_o (zbt_ack),
 
// Pad signals
.sram_clk_ (sram_clk_),
.sram_addr_ (sram_addr_),
.sram_data_ (sram_flash_data_),
.sram_we_n_ (sram_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.sram_adv_ld_n_ (sram_adv_ld_n_)
);
 
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
173,24 → 122,22
.y (y),
.imm (imm),
.aluo (aluo),
.sp (sp),
`endif
 
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack)
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
.dat_i (dat_i),
.dat_o (dat_o),
.adr_o (adr),
.we_o (we),
.mio_o (mio),
.byte_o (byte_o),
.stb_o (stb),
.ack_i (ack)
);
 
//`ifdef DEBUG
`ifdef DEBUG
// Module instantiations
icon icon0 (
.CONTROL0 (control0)
202,7 → 149,7
.TRIG0 (adr),
.TRIG1 ({dat_o,dat_i}),
.TRIG2 (pc),
.TRIG3 ({clk,we,tga,cyc,stb,ack}),
.TRIG3 ({clk,we,mio,byte_o,stb,ack}),
.TRIG4 (funct),
.TRIG5 ({state,next_state}),
.TRIG6 (io_reg),
213,9 → 160,7
.TRIG11 (sram_flash_data_),
.TRIG12 ({sram_flash_oe_n_, sram_flash_we_n_, sram_bw_,
sram_cen_, sram_adv_ld_n_, flash_ce2_}),
.TRIG13 (cnt),
.TRIG14 ({vdu_arena,flash_arena,flash_stb,zbt_stb,op}),
.TRIG15 (sp)
.TRIG13 (curr_st)
);
 
lcd_display lcd0 (
225,7 → 170,6
.m2 (m2), // 2nd row mask
 
.clk (clk_100M), // 100 Mhz clock
.rst (rst_lck),
 
// Pad signals
.lcd_rs_ (rs_),
235,66 → 179,30
);
 
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, dat_i, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
assign f1 = { 3'b0, rst, 4'h0, dat_i, 4'h0, dat_o, 7'h0, mio, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, byte_o, 8'h0, pc };
assign m1 = 16'b1011110111101010;
assign m2 = 16'b1111101110011111;
 
assign pc = (cs << 4) + ip;
//`endif
`endif
 
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = tga ? io_dat_i
: (vdu_arena ? vdu_dat_o
: (flash_arena ? flash_dat_o : zbt_dat_o));
assign vdu_arena = (adr[19:12]==8'hb8);
assign flash_arena = (adr[19:16]==4'hc || adr[19:16]==4'hf);
assign flash_stb = flash_arena & stb & cyc;
assign zbt_stb = !vdu_arena & !flash_arena & stb & cyc;
assign dat_io = (adr[15:0]==16'hb7) ? io_reg : 16'd0;
assign dat_i = mio ? dat_io : dat_mem;
 
assign ack = tga ? io_ack
: (vdu_arena ? vdu_ack_sync[1]
: (flash_arena ? flash_ack : zbt_ack));
assign io_ack = stb;
assign io_op = cyc & stb & tga;
 
assign leds_ = io_reg[8:0];
assign sram_flash_oe_n_ = 1'b0;
assign sram_flash_addr_ = flash_arena ? flash_addr_
: sram_addr_;
assign sram_flash_we_n_ = flash_arena ? flash_we_n_
: sram_we_n_;
 
// Behaviour
// IO Stub
always @(posedge clk)
if (rst) io_reg <= 16'h0000;
else
if (adr[15:1]==15'h5b && sel[1] && io_op)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15'h5c && sel[0] && io_op)
io_reg[15:8] <= dat_o[7:0];
if (adr==20'hb7 & we & mio)
io_reg <= byte_o ? { io_reg[15:8], dat_o[7:0] } : dat_o;
 
// vdu_stb_sync[0]
always @(posedge tft_lcd_clk_)
vdu_stb_sync[0] <= stb & cyc & vdu_arena;
 
// vdu_stb_sync[1]
// rst
always @(posedge clk)
vdu_stb_sync[1] <= vdu_stb_sync[0];
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
 
// vdu_ack_sync[0]
always @(posedge clk) vdu_ack_sync[0] <= vdu_ack_o;
 
// vdu_ack_sync[1]
always @(posedge clk) vdu_ack_sync[1] <= vdu_ack_sync[0];
 
// dbg
`ifdef DEBUG
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
`else
assign rst = rst_lck;
dbg <= rst_lck ? 1'b1 : (pc==20'hf005a ? 1'b0 : dbg);
`endif
endmodule
/trunk/impl/virtex4-ml403ep/mult.xco
1,7 → 1,7
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Sat Oct 18 02:02:55 2008
# Date: Sun Oct 5 14:08:58 2008
#
##############################################################
#
/trunk/impl/virtex4-ml403ep/lcd_display/test_lcd_cntrl.v
4,14 → 4,12
output rs_,
output rw_,
output e_,
inout [7:4] db_,
input but_
inout [7:4] db_
);
 
// Module instantiations
lcd_display lcd0 (
.clk (sys_clk_in_),
.rst (but_),
.f1 (64'h123456f890abcde7),
.f2 (64'h7645321dcbaef987),
.m1 (16'b0101011101011111),
/trunk/impl/virtex4-ml403ep/lcd_display/lcd_display.v
5,7 → 5,6
input [15:0] m2, // 2nd row mask
 
input clk, // 100 Mhz clock
input rst,
 
// Pad signals
output reg lcd_rs_,
42,8 → 41,7
 
// Behaviour
always @(posedge clk)
if (rst) cnt <= 26'hfffffff;
else begin
begin
cnt <= cnt - 1;
casex (cnt[k+1+n:k+2])
8'hff: lcd <= 6'b000010; // function set
/trunk/impl/virtex4-ml403ep/lcd_display/ml403.ucf
13,4 → 13,3
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
NET but_ LOC = B6; # C Button
/trunk/impl/virtex4-ml403ep/vdu_test/test_vdu.v
19,14 → 19,14
//
//////////////////////////////////////////////////////////////////////////////////
module test_vdu (
input sys_clk_in,
output tft_lcd_clk,
output [1:0] tft_lcd_r,
output [1:0] tft_lcd_g,
output [1:0] tft_lcd_b,
output tft_lcd_hsync,
output tft_lcd_vsync,
 
input sys_clk_in,
output tft_lcd_clk,
output tft_lcd_r,
output tft_lcd_g,
output tft_lcd_b,
output tft_lcd_hsync,
output tft_lcd_vsync,
output led
);
 
41,8 → 41,8
);
vdu vdu0 (
.wb_rst_i (rst),
.wb_clk_i (tft_lcd_clk), // 25MHz VDU clock
.vdu_clk (tft_lcd_clk), // 25MHz VDU clock
.vdu_rst (rst),
.vga_red_o (tft_lcd_r),
.vga_green_o (tft_lcd_g),
.vga_blue_o (tft_lcd_b),
/trunk/impl/virtex4-ml403ep/vdu_test/ml403.ucf
22,8 → 22,7
#NET tft_lcd_b<5> LOC = F8; # VGA_B7
#NET tft_lcd_b<*> SLEW = FAST;
#NET tft_lcd_b<*> DRIVE = 8;
NET tft_lcd_b[0] LOC = G8; # VGA_B6
NET tft_lcd_b[1] LOC = F8; # VGA_B7
NET tft_lcd_b LOC = F8; # VGA_B7
#NET tft_lcd_b SLEW = FAST;
#NET tft_lcd_b DRIVE = 8;
 
42,8 → 41,7
#NET tft_lcd_g<5> LOC = C1; # VGA_G7
#NET tft_lcd_g<*> SLEW = FAST;
#NET tft_lcd_g<*> DRIVE = 8;
NET tft_lcd_g[0] LOC = H8; # VGA_G6
NET tft_lcd_g[1] LOC = C1; # VGA_G7
NET tft_lcd_g LOC = C1; # VGA_G7
#NET tft_lcd_g SLEW = FAST;
#NET tft_lcd_g DRIVE = 8;
 
60,8 → 58,7
#NET tft_lcd_r<5> LOC = E6; #VGA_R7
#NET tft_lcd_r<*> SLEW = FAST;
#NET tft_lcd_r<*> DRIVE = 8;
NET tft_lcd_r[0] LOC = E5; #VGA_R6
NET tft_lcd_r[1] LOC = E6; #VGA_R7
NET tft_lcd_r LOC = E6; #VGA_R7
#NET tft_lcd_r SLEW = FAST;
#NET tft_lcd_r DRIVE = 8;
 
/trunk/soc/vga/vdu.v
10,23 → 10,24
// 16 vertical scan lines / character (2 scan lines/row)
`timescale 1ns/10ps
 
module vdu (
module vdu
(
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input [11:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input clk_i, // 25 Mhz VDU clock
input rst_i,
input stb_i,
input cyc_i,
input we_i,
input [11:0] adr_i,
input [15:0] dat_i,
output reg [15:0] dat_o,
output reg ack_o,
input byte_i,
 
// VGA pad signals
output reg [ 1:0] vga_red_o,
output reg [ 1:0] vga_green_o,
output reg [ 1:0] vga_blue_o,
output reg vga_red_o,
output reg vga_green_o,
output reg vga_blue_o,
output reg horiz_sync,
output reg vert_sync
);
34,7 → 35,7
// Net, registers and parameters
 
// Synchronization constants
parameter HOR_DISP_END = 10'd640; // Last horizontal pixel displayed
parameter HOR_DISP_END = 10'd639; // Last horizontal pixel displayed
parameter HOR_SYNC_BEG = 10'd679; // Start of horizontal synch pulse
parameter HOR_SYNC_END = 10'd775; // End of Horizontal Synch pulse
parameter HOR_SCAN_END = 10'd799; // Last pixel in scan line
83,7 → 84,7
reg [6:0] hor_addr; // 0 to 79
reg [6:0] ver_addr; // 0 to 124
reg vga0_we;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw;
reg vga1_we;
reg vga2_we;
reg buff_we;
96,21 → 97,27
reg [10:0] buff0_addr;
reg buff0_we;
reg [10:0] attr_addr;
reg intense;
wire vga_cs;
wire [7:0] vga_data_out;
wire [7:0] attr_data_out;
wire [10:0] vga_addr; // 2K byte character buffer
wire a0;
wire [10:0] vdu_addr1;
wire byte1;
wire [15:0] out_data;
wire [15:0] ext_attr, ext_buff;
wire fg_or_bg;
wire stb;
wire brown_bg;
wire brown_fg;
 
// Character write handshake signals
reg req_write; // request character write
reg req_read;
reg one_more_cycle;
 
// Module instantiation
char_rom vdu_char_rom (
.clk (wb_clk_i),
.rst (wb_rst_i),
.clk (clk_i),
.rst (rst_i),
.cs (char_cs),
.we (char_we),
.addr (char_addr),
119,8 → 126,8
);
 
ram_2k char_buff_ram (
.clk (wb_clk_i),
.rst (wb_rst_i),
.clk (clk_i),
.rst (rst_i),
.cs (vga_cs),
.we (buff_we),
.addr (buff_addr),
129,8 → 136,8
);
 
ram_2k_attr attr_buff_ram (
.clk (wb_clk_i),
.rst (wb_rst_i),
.clk (clk_i),
.rst (rst_i),
.cs (vga_cs),
.we (attr_we),
.addr (attr_addr),
146,10 → 153,16
assign char_data_in = 8'b0;
assign char_addr = { vga_data_out, v_count[3:0] };
assign vga_addr = { 4'b0, hor_addr} + { ver_addr, 4'b0 };
assign out_data = {attr_data_out, vga_data_out};
assign a0 = adr_i[0];
assign vdu_addr1 = adr_i[11:1] + 11'd1;
assign byte1 = byte_i || (adr_i == 12'hfff);
assign out_data = a0 ? (byte_i ? ext_attr : {vga_data_out, attr_data_out} )
: (byte_i ? ext_buff : {attr_data_out, vga_data_out} );
assign ext_buff = { {8{vga_data_out[7]}}, vga_data_out };
assign ext_attr = { {8{attr_data_out[7]}}, attr_data_out };
 
assign vga_cs = 1'b1;
assign stb = wb_stb_i && wb_cyc_i;
assign stb = stb_i && cyc_i;
 
// Old control registers
assign reg_hcursor = 7'b0;
157,14 → 170,12
assign reg_voffset = 5'd0;
 
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign brown_fg = (vga_fg_colour==3'd6) && !intense;
assign brown_bg = (vga_bg_colour==3'd6);
 
// Behaviour
 
// CPU write interface
always @(posedge wb_clk_i)
if (wb_rst_i)
always @(posedge clk_i)
if (rst_i)
begin
attr0_addr <= 11'b0;
attr0_we <= 1'b0;
172,37 → 183,39
buff0_addr <= 11'b0;
buff0_we <= 1'b0;
buff_data_in <= 8'h0;
req_write <= 1'b0;
end
else
begin
if (stb)
begin
attr0_addr <= wb_adr_i;
attr0_we <= wb_we_i & wb_sel_i[1];
attr_data_in <= wb_dat_i[15:8];
buff0_addr <= wb_adr_i;
buff0_we <= wb_we_i & wb_sel_i[0];
buff_data_in <= wb_dat_i[7:0];
attr0_addr <= adr_i[11:1];
attr0_we <= we_i & (!byte1 | a0);
attr_data_in <= a0 ? dat_i[7:0] : dat_i[15:8];
buff0_addr <= (a0 && !byte1) ? vdu_addr1 : adr_i[11:1];
buff0_we <= we_i & (!byte1 | !a0);
buff_data_in <= a0 ? dat_i[15:8] : dat_i[7:0];
req_write <= we_i;
end
end
 
// CPU read interface
always @(posedge wb_clk_i)
if (wb_rst_i)
always @(posedge clk_i)
if (rst_i)
begin
wb_dat_o <= 16'h0;
wb_ack_o <= 16'h0;
dat_o <= 16'h0;
ack_o <= 16'h0;
end
else
begin
wb_dat_o <= vga3_rw ? out_data : wb_dat_o;
wb_ack_o <= vga3_rw ? 1'b1 : (wb_ack_o && stb);
dat_o <= vga3_rw ? out_data : dat_o;
ack_o <= vga3_rw ? 1'b1 : (ack_o && stb);
end
 
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(posedge wb_clk_i)
if (wb_rst_i)
always @(posedge clk_i)
if (rst_i)
begin
h_count <= 10'b0;
horiz_sync <= 1'b1;
233,8 → 246,8
end
 
// Video memory access
always @(posedge wb_clk_i)
if (wb_rst_i)
always @(posedge clk_i)
if (rst_i)
begin
vga0_we <= 1'b0;
vga0_rw <= 1'b1;
264,8 → 277,8
case (h_count[2:0])
3'b000: // pipeline character write
begin
vga0_we <= wb_we_i;
vga0_rw <= stb;
vga0_we <= we_i;
vga0_rw <= stb_i && cyc_i;
end
default: // other 6 cycles free
begin
301,48 → 314,47
end
 
// Video shift register
always @(posedge wb_clk_i)
if (wb_rst_i)
always @(posedge clk_i)
if (rst_i)
begin
video_on <= 1'b0;
cursor_on <= 1'b0;
vga_bg_colour <= 3'b000;
vga_fg_colour <= 3'b111;
vga_shift <= 8'b00000000;
vga_red_o <= 1'b0;
vga_green_o <= 1'b0;
vga_blue_o <= 1'b0;
video_on = 1'b0;
cursor_on = 1'b0;
vga_bg_colour = 3'b000;
vga_fg_colour = 3'b111;
vga_shift = 8'b00000000;
vga_red_o = 1'b0;
vga_green_o = 1'b0;
vga_blue_o = 1'b0;
end
else
begin
if (h_count[2:0] == 3'b000)
begin
video_on <= video_on1;
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_fg_colour <= attr_data_out[2:0];
vga_bg_colour <= attr_data_out[6:4];
intense <= attr_data_out[3];
vga_shift <= char_data_out;
video_on = video_on1;
cursor_on = (cursor_on1 | attr_data_out[3]) & blink_count[22];
vga_fg_colour = attr_data_out[2:0];
vga_bg_colour = attr_data_out[6:4];
if (!attr_data_out[7]) vga_shift = char_data_out;
else
case (v_count[3:2])
2'b00: vga_shift = { {4{vga_data_out[0]}}, {4{vga_data_out[1]}} };
2'b01: vga_shift = { {4{vga_data_out[2]}}, {4{vga_data_out[3]}} };
2'b10: vga_shift = { {4{vga_data_out[4]}}, {4{vga_data_out[5]}} };
default: vga_shift = { {4{vga_data_out[6]}}, {4{vga_data_out[7]}} };
endcase
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
else vga_shift = { vga_shift[6:0], 1'b0 };
 
//
// Colour mask is
// 7 6 5 4 3 2 1 0
// X BR BG BB X FR FG FB
// X BG BB BR X FG FB FR
//
vga_blue_o <= video_on ? (fg_or_bg ? { vga_fg_colour[0], intense }
: { vga_bg_colour[0], 1'b0 })
: 2'b0;
 
// Green color exception with color brown
// http://en.wikipedia.org/wiki/Color_Graphics_Adapter#With_an_RGBI_monitor
vga_green_o <= video_on ?
(fg_or_bg ? (brown_fg ? 2'b01 : { vga_fg_colour[1], intense })
: (brown_bg ? 2'b01 : { vga_bg_colour[1], 1'b0 }))
: 2'b0;
vga_red_o <= video_on ? (fg_or_bg ? { vga_fg_colour[2], intense }
: { vga_bg_colour[2], 1'b0 })
: 2'b0;
vga_red_o = fg_or_bg ? video_on & vga_fg_colour[0]
: video_on & vga_bg_colour[0];
vga_green_o = fg_or_bg ? video_on & vga_fg_colour[1]
: video_on & vga_bg_colour[1];
vga_blue_o = fg_or_bg ? video_on & vga_fg_colour[2]
: video_on & vga_bg_colour[2];
end
endmodule
/trunk/soc/vga/ram2k_b16.v
25,16 → 25,5
.WE (we));
 
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
/*
defparam ram.INIT_00 = 256'h3130393837363534333231303938373635343332313039383736353433323130;
defparam ram.INIT_01 = 256'h3332313039383736353433323130393837363534333231303938373635343332;
defparam ram.INIT_02 = 256'h3534333231303938373635343332313039383736353433323130393837363534;
defparam ram.INIT_03 = 256'h3736353433323130393837363534333231303938373635343332313039383736;
defparam ram.INIT_04 = 256'h3938373635343332313039383736353433323130393837363534333231303938;
defparam ram.INIT_05 = 256'h3130393837363534333231303938373635343332313039383736353433323130;
defparam ram.INIT_06 = 256'h3332313039383736353433323130393837363534333231303938373635343332;
defparam ram.INIT_07 = 256'h3534333231303938373635343332313039383736353433323130393837363534;
defparam ram.INIT_08 = 256'h3736353433323130393837363534333231303938373635343332313039383736;
defparam ram.INIT_09 = 256'h3938373635343332313039383736353433323130393837363534333231303938;
*/
 
endmodule
/trunk/soc/bios/rombios.c
792,7 → 792,7
}
}
 
static char bios_svn_version_string[] = "$Revision: 1.4 $ $Date: 2008-10-20 00:48:29 $";
static char bios_svn_version_string[] = "$Revision: 1.3 $ $Date: 2008-10-13 00:24:30 $";
 
//--------------------------------------------------------------------------
// print_bios_banner
801,7 → 801,7
void
print_bios_banner()
{
printf("Zet ROMBIOS - build: %s\n%s\n\n",
printf("Zet BIOS - build: %s\n%s\n",
BIOS_BUILD_DATE, bios_svn_version_string);
}
 
1205,6 → 1205,7
;--------
.org 0xe05b ; POST Entry Point
post:
 
xor ax, ax
 
normal_post:
1268,11 → 1269,10
 
mov cx, #0xc000 ;; init vga bios
mov ax, #0xc780
 
call rom_scan
 
call _print_bios_banner
 
hlt
call _init_boot_vectors
 
mov cx, #0xc800 ;; init option roms
/trunk/soc/bios/vgabios.c
64,7 → 64,7
jmp vgabios_init_func
 
vgabios_name:
.ascii "Zet/Bochs VGABios"
.ascii "Plex86/Bochs VGABios"
.ascii " "
.byte 0x00
 
102,8 → 102,6
.byte 0x0a,0x0d
;;.ascii " . http://www.plex86.org"
;;.byte 0x0a,0x0d
.ascii " . http://zet.aluzina.org"
.byte 0x0a,0x0d
.ascii " . http://bochs.sourceforge.net"
.byte 0x0a,0x0d
.ascii " . http://www.nongnu.org/vgabios"
127,7 → 125,7
 
;; display splash screen
call _display_splash_screen
 
hlt
;; init video mode and clear the screen
mov ax,#0x0003
int #0x10
165,7 → 163,6
;; We have to set ds to access the right data segment
mov bx, #0xc000
mov ds, bx
 
call _int10_func
 
; popa ; we do this instead:
265,8 → 262,28
*/
static void display_splash_screen()
{
/*
ASM_START
push dx
push ds
mov dx, #0xb800
mov ds, dx
mov [6], #0x0361
pop ds
pop dx
ASM_END
*/
 
write_byte (0xb800, 0x2, 'o');
write_byte (0xb800, 0x0, 'H');
// write_byte (0xb800, 0x2, 'o');
write_byte (0xb800, 0x4, 'l');
write_byte (0xb800, 0x6, 'a');
write_byte (0xb800, 0x8, ' ');
write_byte (0xb800, 0xa, 't');
write_byte (0xb800, 0xc, 'i');
write_byte (0xb800, 0xe, 'o');
write_byte (0xb800, 0x10, '!');
write_byte (0xb800, 0x12, '!');
}
 
// --------------------------------------------------------------------------------------------
283,7 → 300,7
call _display_string
mov si,#vgabios_version
call _display_string
 
;;mov si,#vgabios_copyright
;;call _display_string
;;mov si,#crlf
316,7 → 333,7
mov ax,#0x0300
mov bx,#0x0000
int #0x10
 
pop cx
mov ax,#0x1301
mov bx,#0x000b
332,6 → 349,7
static void int10_func(DI, SI, BP, SP, BX, DX, CX, AX, DS, ES, FLAGS)
Bit16u DI, SI, BP, SP, BX, DX, CX, AX, ES, DS, FLAGS;
{
 
// BIOS functions
switch(GET_AH())
{
338,7 → 356,7
case 0x00:
biosfn_set_video_mode(GET_AL());
switch(GET_AL()&0x7F)
{case 6:
{case 6:
SET_AL(0x3F);
break;
case 0:
354,9 → 372,6
SET_AL(0x20);
}
break;
case 0x02:
biosfn_set_cursor_pos(GET_BH(),DX);
break;
case 0x03:
biosfn_get_cursor_pos(GET_BH(),&CX,&DX);
break;
386,7 → 401,7
Bit16u i,twidth,theightm1,cheight;
Bit8u modeset_ctl,video_ctl,vga_switches;
Bit16u crtc_addr;
 
// The real mode
mode=mode&0x7f;
 
/trunk/soc/bios/Makefile
37,7 → 37,7
VGABIOS_DATE = "-DVGABIOS_DATE=\"$(RELDATE)\""
 
 
all: run
bios: bios.bin
 
bios.bin: vgabios.rom ff.rom zet-bios.rom
cat vgabios.rom ff.rom zet-bios.rom > $@
44,6 → 44,7
 
run: bios.bin
prf
kotku
 
%.rom: %.out
out2rom-ml403 < $< > $@
75,7 → 76,7
$(BCC) -o vgabios.s -C-c -D__i86__ -S -0 _vgabios_.c
sed -e 's/^\.text//' -e 's/^\.data//' vgabios.s > _vgabios_.s
$(AS86) _vgabios_.s -b vgabios.bin -u -w- -g -0 -j -O -l vgabios.txt
# rm -f _vgabios_.s _vgabios_.c vgabios.s
rm -f _vgabios_.s _vgabios_.c vgabios.s
mv vgabios.bin $@
./vgasums $@
 

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