OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 44 to Rev 43
    ↔ Reverse comparison
  •

Rev 44 → Rev 43

/trunk/rtl-model/defines.v
23,4 → 23,4
`define ADD_IP `IR_SIZE'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8'h90
 
`define DEBUG 1
//`define DEBUG 1
/trunk/impl/virtex4-ml403ep/dbg/hw_dbg.v File deleted
/trunk/impl/virtex4-ml403ep/syn/kotku.v
25,11 → 25,7
output rw_,
output e_,
output [7:4] db_,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
input but_,
`endif
 
output tft_lcd_clk_,
93,19 → 89,7
wire intr;
wire inta;
wire clk_100M;
wire rst;
wire [15:0] vdu_dat_i;
wire [11:1] vdu_adr_i;
wire vdu_we_i;
wire [ 1:0] vdu_sel_i;
wire vdu_stb_i;
wire vdu_tga_i;
 
wire [19:1] zbt_adr_i;
wire zbt_we_i;
wire [ 1:0] zbt_sel_i;
wire zbt_stb_i;
 
`ifdef DEBUG
wire [35:0] control0;
wire [ 5:0] funct;
120,18 → 104,9
wire [ 2:0] cnt;
wire op;
wire [15:0] r1, r2;
 
wire [15:0] dbg_vdu_dat_o;
wire [11:1] dbg_vdu_adr_o;
wire dbg_vdu_we_o;
wire dbg_vdu_stb_o;
wire [ 1:0] dbg_vdu_sel_o;
wire dbg_vdu_tga_o;
 
wire [19:1] dbg_zbt_adr_o;
wire dbg_zbt_we_o;
wire [ 1:0] dbg_zbt_sel_o;
wire dbg_zbt_stb_o;
reg rst;
`else
wire rst;
`endif
 
// Register declarations
151,13 → 126,13
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst_lck),
.wb_dat_i (vdu_dat_i),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (vdu_adr_i),
.wb_we_i (vdu_we_i),
.wb_tga_i (vdu_tga_i),
.wb_sel_i (vdu_sel_i),
.wb_adr_i (adr[11:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_sel_i (sel),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_ack_o (vdu_ack_o),
176,7 → 151,7
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (flash_dat_o),
.wb_adr_i (adr[16:1]),
.wb_adr_i (adr[17:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_stb_i (flash_stb),
196,14 → 171,14
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst_lck),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (zbt_adr_i),
.wb_we_i (zbt_we_i),
.wb_sel_i (zbt_sel_i),
.wb_stb_i (zbt_stb_i),
.wb_cyc_i (zbt_stb_i),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (zbt_stb),
.wb_cyc_i (zbt_stb),
.wb_ack_o (zbt_ack),
 
// Pad signals
307,32 → 282,6
.lcd_dat_ (db_)
);
 
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst_lck),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
.butw_ (butw_),
.butn_ (butn_),
.buts_ (buts_),
 
.vdu_dat_o (dbg_vdu_dat_o),
.vdu_adr_o (dbg_vdu_adr_o),
.vdu_we_o (dbg_vdu_we_o),
.vdu_stb_o (dbg_vdu_stb_o),
.vdu_sel_o (dbg_vdu_sel_o),
.vdu_tga_o (dbg_vdu_tga_o),
.vdu_ack_i (vdu_ack_sync[1]),
 
.zbt_dat_i (zbt_dat_o),
.zbt_adr_o (dbg_zbt_adr_o),
.zbt_we_o (dbg_zbt_we_o),
.zbt_sel_o (dbg_zbt_sel_o),
.zbt_stb_o (dbg_zbt_stb_o),
.zbt_ack_i (zbt_ack)
);
 
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
340,28 → 289,6
assign m2 = 16'b1111101110011111;
 
assign pc = (cs << 4) + ip;
 
assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o;
assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1];
assign vdu_we_i = rst ? dbg_vdu_we_o : we;
assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel;
assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena;
assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga;
assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr;
assign zbt_we_i = rst ? dbg_zbt_we_o : we;
assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel;
assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb;
`else
assign vdu_dat_i = dat_o;
assign vdu_adr_i = adr[11:1];
assign vdu_we_i = we;
assign vdu_sel_i = sel;
assign vdu_stb_i = stb & cyc & vdu_arena;
assign vdu_tga_i = tga;
assign zbt_adr_i = adr;
assign zbt_we_i = we;
assign zbt_sel_i = sel;
assign zbt_stb_i = zbt_stb;
`endif
 
assign io_dat_i = flash_io_arena ? flash_dat_o
403,7 → 330,7
// Behaviour
// vdu_stb_sync[0]
always @(posedge tft_lcd_clk_)
vdu_stb_sync[0] <= vdu_stb_i;
vdu_stb_sync[0] <= stb & cyc & vdu_arena;
 
// vdu_stb_sync[1]
always @(posedge clk)
421,7 → 348,11
: ((tga && stb && cyc && we && adr[15:8]==8'hf1) ?
dat_o : io_reg );
 
`ifndef DEBUG
`ifdef DEBUG
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
`else
assign rst = rst_lck;
`endif
endmodule
/trunk/impl/virtex4-ml403ep/syn/ml403.ucf
100,20 → 100,17
NET tft_lcd_vsync_ SLEW = FAST;
NET tft_lcd_vsync_ DRIVE = 8;
 
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
#NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
#NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
#NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
 
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
#NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
#NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
#NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
#NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
NET butc_ LOC = B6; # C Button
NET butw_ LOC = E9; # W Button
NET bute_ LOC = F10; # E Button
NET butn_ LOC = E7; # N Button
NET buts_ LOC = A6; # S Button
#NET but_ LOC = B6; # C Button
#NET but2_ LOC = A6; # S Button
 
#NET led_[0] LOC = G5; #GPLED0
#NET led_[1] LOC = G6; #GPLED1
/trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj
14,11 → 14,9
verilog work "../../../../rtl-model/fetch.v"
verilog work "../../../../rtl-model/exec.v"
verilog work "../../../../soc/vga/rtl/vdu.v"
verilog work "../../../../soc/keyb/rtl/ps2_keyb.v"
verilog work "../../../../rtl-model/cpu.v"
verilog work "../../mem/zbt_cntrl.v"
verilog work "../../mem/flash_cntrl.v"
verilog work "../../dbg/hw_dbg.v"
verilog work "../clock.v"
verilog work "../kotku.v"
verilog work "../../lcd/lcd_display.v"
/trunk/impl/virtex4-ml403ep/mem/flash_cntrl.v
22,7 → 22,7
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input [17:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
51,7 → 51,8
// flash_addr, 21 bits
always @(posedge wb_clk_i)
flash_addr_ <= wb_tga_i ? { 1'b1, base, wb_adr_i[8:1] }
: { 5'h0, wb_adr_i[16:1] };
: { 5'h0, wb_adr_i[17],
wb_adr_i[15:1] };
 
always @(posedge wb_clk_i) flash_ce2_ <= op;
always @(posedge wb_clk_i) wb_ack_o <= op;
/trunk/impl/virtex4-ml403ep/lcd/test_lcd_cntrl.v
1,20 → 1,16
module lcd_test (
// Pad signals
input clk_,
input sys_clk_in_,
output rs_,
output rw_,
output e_,
inout [3:0] db_,
input but_,
output [5:0] led_
inout [7:4] db_,
input but_
);
 
// Registers
reg [4:0] cnt;
 
// Module instantiations
lcd_display4 lcd0 (
.clk (cnt[4]),
lcd_display lcd0 (
.clk (sys_clk_in_),
.rst (but_),
.f1 (64'h123456f890abcde7),
.f2 (64'h7645321dcbaef987),
21,13 → 17,10
.m1 (16'b0101011101011111),
.m2 (16'b1110101110101111),
 
.rs_ (rs_),
.rw_ (rw_),
.e_ (e_),
.db_ (db_),
.st (led_)
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_(db_)
);
 
// Behaviour
always @(posedge clk_) cnt <= cnt + 5'b1;
endmodule
/trunk/impl/virtex4-ml403ep/lcd/ml403.ucf
1,27 → 1,16
NET clk_ TNM_NET = "clk_";
TIMESPEC "TSSYSCLK" = PERIOD "clk_" 9.9 ns HIGH 50 %;
NET sys_clk_in_ TNM_NET = "sys_clk_in_";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %;
 
NET clk_ LOC = AE14;
NET clk_ IOSTANDARD = LVCMOS33;
NET sys_clk_in_ LOC = AE14;
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
 
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
 
NET db_[3] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[2] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[1] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[0] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
NET but_ LOC = B6; # C Button
 
NET led_[0] LOC = G5; #GPLED0
NET led_[1] LOC = G6; #GPLED1
NET led_[2] LOC = A11; #GPLED2
NET led_[3] LOC = A12; #GPLED3
 
# North-East-South-West-Center LEDs
NET led_[4] LOC = C6; # C LED
NET led_[5] LOC = F9; # W LED
#NET led_[6] LOC = A5; # S LED
#NET led_[7] LOC = E10; # E LED
NET but_ LOC = B6; # C Button
/trunk/impl/virtex4-ml403ep/sim/test_kotku.v
37,9 → 37,7
.sram_bw_ (s_bw),
.sram_cen_ (s_ce),
.sram_adv_ld_n_ (s_adv),
.flash_ce2_ (f_ce),
 
.but_ (1'b0)
.flash_ce2_ (f_ce)
);
 
flash_stub fs0 (
/trunk/impl/virtex4-ml403ep/sim/t.do
1,7 → 1,7
vdel -all -lib work
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
vlib work
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../dbg/hw_dbg.v
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../kotku.v ../clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/vdu.v ../../../soc/vga/char_rom_b16.v ../../../soc/vga/ram2k_b16_attr.v ../../../soc/vga/ram2k_b16.v ../memory/flash_cntrl.v ../memory/zbt_cntrl.v CY7C1354BV25.v
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl
add wave -label clk100 /testbench/clk
49,8 → 49,6
add wave -label we /testbench/kotku/we
add wave -label ack /testbench/kotku/ack
add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec
add wave -divider vdu
add wave -divider zbt
add wave -radix hexadecimal /testbench/kotku/vdu0/*
add wave -divider hw_dbg
add wave -radix hexadecimal /testbench/kotku/dbg0/*
run 50us
/trunk/soc/bios/rombios.c
960,7 → 960,7
}
}
 
static char bios_svn_version_string[] = "$Revision: 1.10 $ $Date: 2009-02-19 19:06:56 $";
static char bios_svn_version_string[] = "$Revision: 1.9 $ $Date: 2009-02-06 03:48:27 $";
 
//--------------------------------------------------------------------------
// print_bios_banner
2101,7 → 2101,7
 
;; Keyboard
SET_INT_VECTOR(0x09, #0xF000, #int09_handler)
;SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
 
xor ax, ax
mov ds, ax

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.