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URL https://opencores.org/ocsvn/zet86/zet86/trunk

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Rev 20 → Rev 21

/trunk/rtl-model/alu.v
47,11 → 47,11
// conv cnv0(x[15:0], cnv, func[0]);
// muldiv mul0(x, y, mul, func[1:0], word_op, cf_mul, of_mul);
bitlog lo0(x[15:0], y, log, func, cf_log, of_log);
// shifts sh0(x[15:0], y, shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
shifts sh0(x[15:0], y, shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
// rotat rot0(x[15:0], y, rot, func[1:0], word_op, cfi, cf_rot, of_rot);
othop oth0(x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
 
mux8_16 m0(t, adj, add, cnv[15:0],
mux8_16 m0(t, /* adj */ {8'd0, y[7:0]}, add, cnv[15:0],
mul[15:0], log, shi, rot, oth[15:0], out[15:0]);
mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
276,7 → 276,7
assign cfo = 1'b0;
assign ofo = 1'b0;
endmodule
/*
 
//
// This module implements the instructions shl/sal, sar, shr
//
320,7 → 320,7
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
endmodule
 
/*
module rotat(x, y, out, func, word_op, cfi, cfo, ofo);
// IO ports
input [15:0] x, y;
/trunk/rtl-model/exec.v
20,23 → 20,31
 
`include "defines.v"
 
module exec(ir, off, imm, cs, ip, of, zf, cx_zero, clk, rst,
memout, wr_data, addr, we, m_io, byteop, mem_rdy);
// IO Ports
input [`IR_SIZE-1:0] ir;
input [15:0] off, imm;
input clk;
input rst;
input [15:0] memout;
input mem_rdy;
module exec (
// IO Ports
`ifdef DEBUG
output [15:0] x,
output [15:0] y,
`endif
input [`IR_SIZE-1:0] ir,
input [15:0] off,
input [15:0] imm,
output [15:0] cs,
output [15:0] ip,
output of,
output zf,
output cx_zero,
input clk,
input rst,
input [15:0] memout,
 
output [15:0] wr_data, ip;
output of;
output zf;
output cx_zero;
output we, m_io, byteop;
output [19:0] addr;
output [15:0] cs;
output [15:0] wr_data,
output [19:0] addr,
output we,
output m_io,
output byteop,
input mem_rdy
);
 
// Net declarations
wire [15:0] a, b, c, s, alu_iflags, omemalu, bus_b;
95,4 → 103,8
assign alu_iflags = { 4'b0, flags[8:3], 1'b0, flags[2], 1'b0, flags[1],
1'b1, flags[0] };
assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };
`ifdef DEBUG
assign x = a;
assign y = bus_b;
`endif
endmodule
/trunk/rtl-model/cpu.v
21,6 → 21,17
`include "defines.v"
 
module cpu (
`ifdef DEBUG
output [15:0] cs,
output [15:0] ip,
output [ 2:0] state,
output [ 2:0] next_state,
output [ 5:0] iralu,
output [15:0] x,
output [15:0] y,
output [15:0] imm,
`endif
 
// Wishbone signals
input clk_i,
input rst_i,
31,27 → 42,75
output mio_o,
output byte_o,
output stb_o,
input ack_i,
output [15:0] cs,
output [15:0] ip
input ack_i
);
 
// Net declarations
// wire [15:0] cs, ip;
`ifndef DEBUG
wire [15:0] cs, ip;
wire [15:0] imm;
`endif
wire [`IR_SIZE-1:0] ir;
wire [15:0] off, imm;
wire [15:0] off;
 
wire [19:0] addr_exec, addr_fetch;
wire byte_fetch, byte_exec, fetch_or_exec;
wire of, zf, cx_zero;
 
// Module instantiations
fetch fetch0(clk_i, rst_i, cs, ip, of, zf, cx_zero, dat_i, ir, off,
imm, addr_fetch, byte_fetch, fetch_or_exec, ack_i);
exec exec0(ir, off, imm, cs, ip, of, zf, cx_zero, clk_i, rst_i,
dat_i, dat_o, addr_exec, we_o, mio_o, byte_exec, ack_i);
fetch fetch0 (
`ifdef DEBUG
.state (state),
.next_state (next_state),
`endif
.clk (clk_i),
.rst (rst_i),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.data (dat_i),
.ir (ir),
.off (off),
.imm (imm),
.pc (addr_fetch),
 
// Assignments
assign adr_o = fetch_or_exec ? addr_exec : addr_fetch;
.cx_zero (cx_zero),
.bytefetch (byte_fetch),
.fetch_or_exec (fetch_or_exec),
.mem_rdy (ack_i)
);
 
exec exec0 (
`ifdef DEBUG
.x (x),
.y (y),
`endif
.ir (ir),
.off (off),
.imm (imm),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.cx_zero (cx_zero),
.clk (clk_i),
.rst (rst_i),
.memout (dat_i),
.wr_data (dat_o),
.addr (addr_exec),
.we (we_o),
.m_io (mio_o),
.byteop (byte_exec),
.mem_rdy (ack_i)
);
 
// Assignments
assign adr_o = fetch_or_exec ? addr_exec : addr_fetch;
assign byte_o = fetch_or_exec ? byte_exec : byte_fetch;
assign stb_o = rst_i ? 1'b1 : ir[`MEM_OP];
assign stb_o = rst_i ? 1'b1 : ir[`MEM_OP];
 
`ifdef DEBUG
assign iralu = ir[28:23];
`endif
endmodule
/trunk/rtl-model/fetch.v
21,6 → 21,10
`include "defines.v"
 
module fetch (
`ifdef DEBUG
output reg [2:0] state,
output [2:0] next_state,
`endif
input clk,
input rst,
input [15:0] cs,
45,17 → 49,20
parameter immed_st = 3'h3;
parameter execu_st = 3'h4;
 
`ifndef DEBUG
wire [2:0] next_state;
reg [2:0] state;
`endif
 
wire [`IR_SIZE-1:0] rom_ir;
wire [7:0] opcode, modrm;
wire exec_st, end_seq;
wire [15:0] imm_d;
wire [2:0] next_state;
wire prefix;
wire next_in_opco, next_in_exec;
wire block;
wire need_modrm, need_off, need_imm, off_size, imm_size;
 
reg [2:0] state;
reg [7:0] opcode_l, modrm_l;
reg [15:0] off_l, imm_l;
reg [1:0] pref_l;
316,7 → 323,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= { 2'b10, opcode[4:3] };
dst <= 4'b0;
end
 
8'b0000_100x: // or r->r, r->m
363,7 → 373,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
dst <= { 2'b10, opcode[4:3] };
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= { 2'b10, opcode[4:3] };
end
 
8'b0010_000x: // and r->r, r->m
448,7 → 461,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= { 1'b0, opcode[2:0] };
dst <= 4'b0;
end
 
8'b0101_1xxx: // pop reg
457,6 → 473,9
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= { 1'b0, opcode[2:0] };
end
 
466,8 → 485,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= { opcode[3:0] };
dst <= 4'b0;
end
 
8'b1000_000x: // and, or i->r, i->m
509,6 → 530,7
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
dst <= { 1'b0, dstm };
src <= { 1'b0, srcm };
end
570,7 → 592,9
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
src <= { 1'b0, srcm };
dst <= 4'b0;
end
 
8'b1000_1110: // mov: m->s, r->s
602,6 → 626,8
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= { 1'b0, rm };
end
 
611,6 → 637,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1001_0xxx: // xchg acum
619,6 → 649,8
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0000;
dst <= { 1'b0, opcode[2:0] };
end
631,6 → 663,8
off_size <= 1'b1;
need_imm <= 1'b1;
imm_size <= 1'b1;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1001_1100: // pushf
653,6 → 687,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1001_1110: // sahf
661,7 → 699,11
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1001_1111: // lahf
begin
669,6 → 711,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_000x: // mov: m->a
703,6 → 749,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_011x: // cmps
711,6 → 761,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_100x: // test i->r
731,6 → 785,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_110x: // lods
739,6 → 797,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_111x: // scas
747,6 → 809,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1011_xxxx: // mov: i->r
769,6 → 835,9
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b1;
off_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_0011: // ret near
777,6 → 846,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_0100: // les
786,7 → 859,9
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
src <= { 1'b0, srcm };
dst <= 4'b0;
end
 
8'b1100_0101: // lds
796,7 → 871,9
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
src <= { 1'b0, srcm };
dst <= 4'b0;
end
 
8'b1100_011x: // mov: i->m (or i->r non-standard)
819,7 → 896,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b1;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_1011: // ret far
828,6 → 908,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_1100: // int 3
836,6 → 920,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_1101: // int
844,7 → 932,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_1110: // into
853,6 → 944,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1100_1111: // iret
861,6 → 956,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1101_0111: // xlat
869,6 → 968,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_0000: // loopne
877,7 → 980,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_0001: // loope
886,7 → 992,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_0010: // loop
895,7 → 1004,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_0011: // jcxz
904,7 → 1016,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_010x: // in imm
913,7 → 1028,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_011x: // out imm
922,7 → 1040,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_1000: // call same segment
931,7 → 1052,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= 1'b1;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_10x1: // jmp direct
966,6 → 1090,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_111x: // out dx
974,6 → 1102,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_0100: // hlt
995,6 → 1127,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_011x: // test i->r, i->m
1019,6 → 1155,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1001: // stc
1027,6 → 1167,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1010: // cli
1035,6 → 1179,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1011: // sti
1043,6 → 1191,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1100: // cld
1051,6 → 1203,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1101: // std
1059,6 → 1215,10
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1111_1111:
/trunk/impl/virtex4-ml403ep/test/test_mem_ctrl.v
1,6 → 1,25
//
// Memory map test. It testes all kind of memory accesses in
// different RAM / ROM. RAM contents at the end:
//
// Mem[01:00] = xx07
// Mem[03:02] = 0607
// Mem[05:04] = Mem[09:08]
// Mem[07:06] = 0a0b
// Mem[0d:0c] = 06xx
// Mem[0f:0e] = xxMem[08]
// Mem[11:10] = ff83
// Mem[13:12] = 0007
// Mem[15:14] = 0062
// Mem[17:16] = ext(Mem[09])
// Mem[19:18] = Mem[09]xx
// Mem[1b:1a] = 0b06
// Mem[1d:1c] = Mem[08]06
//
 
module test_mem_ctrl (
input sys_clk_in_,
 
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [15:0] sram_flash_data_,
8,16 → 27,20
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output sram_adv_ld_n_,
output flash_ce2_,
output [ 8:0] leds_
 
input but_
);
 
// Net declarations
wire rst;
wire rst_lck;
wire clk;
wire [15:0] dada_ent;
wire ack;
wire [35:0] control;
wire clk_100M;
wire [ 3:0] cs;
 
// Register declarations
reg [ 7:0] estat;
28,18 → 51,38
reg we;
reg stb;
reg byte_o;
reg rst;
 
// Module instantiations
clock c0 (
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
.rst (rst)
.clk_100M (clk_100M),
.rst (rst_lck)
);
 
icon icon0 (
.CONTROL0 (control)
);
 
ila_mem ilmem0 (
.CONTROL (control),
.CLK (clk_100M),
.TRIG0 (adr),
.TRIG1 (dada_sor),
.TRIG2 (dada_ent),
.TRIG3 ({clk,rst,we,byte_o,ack,stb}),
.TRIG4 (sram_flash_addr_),
.TRIG5 (sram_flash_data_),
.TRIG6 ({sram_adv_ld_n_,sram_clk_,sram_flash_oe_n_,sram_flash_we_n_,sram_bw_,sram_cen_,flash_ce2_}),
.TRIG7 (cs),
.TRIG8 (estat)
);
 
mem_ctrl mem_ctrl0 (
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
.rst_i (rst),
.adr_i (adr),
.dat_i (dada_sor),
.dat_o (dada_ent),
56,14 → 99,21
.sram_flash_we_n_ (sram_flash_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.flash_ce2_ (flash_ce2_)
.sram_adv_ld_n_ (sram_adv_ld_n_),
.flash_ce2_ (flash_ce2_),
 
.cs (cs)
);
 
// Continuous assignments
assign leds_ = dada_sor[8:0];
//assign leds_ = estat[7:0];
 
// Behavioral description
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
 
always @(posedge clk)
if (rst)
begin // ROM word read (dada1 = 0607)
estat <= 8'd00;
243,15 → 293,70
byte_o <= 1'd1;
end
8'd110:
if (ack) begin
if (ack) begin // ROM word read odd (0b06)
estat <= 8'd115;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h19;
adr <= 20'hc0003;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd1;
byte_o <= 1'd0;
end
8'd115:
if (ack) begin // RAM word write (@13 = 0b06)
estat <= 8'd120;
dada_sor <= dada_ent;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h1a;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'd120:
if (ack) begin // RAM word read (odd)
estat <= 8'd125;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'h3;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'd125:
if (ack) begin // RAM word write (even)
estat <= 8'd130;
dada_sor <= dada_ent;
dada1 <= dada_ent;
dada2 <= dada2;
adr <= 20'h1c;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'd130:
if (ack) begin // RAM word write (odd)
estat <= 8'd135;
dada_sor <= dada1;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'd13;
we <= 1'd1;
stb <= 1'd1;
byte_o <= 1'd0;
end
8'd135:
if (ack) begin // RAM word write (even)
estat <= 8'd140;
dada_sor <= dada_sor;
dada1 <= dada1;
dada2 <= dada2;
adr <= 20'd13;
we <= 1'd0;
stb <= 1'd1;
byte_o <= 1'd0;
end
endcase
endmodule
/trunk/impl/virtex4-ml403ep/kotku.v
1,4 → 1,21
`include "defines.v"
 
module kotku_ml403 (
`ifdef DEBUG
output rs_,
output rw_,
output e_,
output [7:4] db_,
 
`endif
/*
output tft_lcd_clk_,
output tft_lcd_r_,
output tft_lcd_g_,
output tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
*/
input sys_clk_in_,
 
output sram_clk_,
8,24 → 25,15
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output sram_adv_ld_n_,
output flash_ce2_,
 
output tft_lcd_clk_,
output tft_lcd_r_,
output tft_lcd_g_,
output tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
 
output rs_,
output rw_,
output e_,
output [7:4] db_
input but_
);
 
// Net declarations
wire clk;
wire rst;
wire rst_lck;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [19:0] adr;
34,41 → 42,37
wire stb;
wire ack;
wire byte_o;
wire [15:0] dat_io;
wire [15:0] dat_mem;
 
`ifdef DEBUG
wire [35:0] control0;
wire [ 5:0] ir;
wire [ 2:0] state, next_state;
wire [15:0] x, y;
wire [15:0] imm;
wire clk_100M;
wire [63:0] f1, f2;
wire [15:0] m1, m2;
wire [19:0] pc;
wire [15:0] cs, ip;
wire [15:0] dat_io;
wire [15:0] dat_mem;
`endif
 
// Register declarations
reg [15:0] io_reg;
reg rst;
 
// Module instantiations
clock c0 (
`ifdef DEBUG
.clk_100M (clk_100M),
`endif
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
.clk_100M (clk_100M),
.vdu_clk (tft_lcd_clk_),
.rst (rst)
// .vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
 
lcd_display lcd0 (
.f1 (f1), // 1st row
.f2 (f2), // 2nd row
.m1 (m1), // 1st row mask
.m2 (m2), // 2nd row mask
 
.clk (clk_100M), // 100 Mhz clock
 
// Pad signals
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_ (db_)
);
 
mem_map mem_map0 (
// Wishbone signals
.clk_i (clk),
89,8 → 93,9
.sram_flash_we_n_ (sram_flash_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.flash_ce2_ (flash_ce2_),
 
.sram_adv_ld_n_ (sram_adv_ld_n_),
.flash_ce2_ (flash_ce2_)
/*
// VGA pad signals
.vdu_clk (tft_lcd_clk_),
.vga_red_o (tft_lcd_r_),
97,10 → 102,22
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_)
.vert_sync (tft_lcd_vsync_),
*/
);
 
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
.ip (ip),
.state (state),
.next_state (next_state),
.iralu (ir),
.x (x),
.y (y),
.imm (imm),
`endif
 
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
111,11 → 128,44
.mio_o (mio),
.byte_o (byte_o),
.stb_o (stb),
.ack_i (ack),
.cs (cs),
.ip (ip)
.ack_i (ack)
);
 
`ifdef DEBUG
// Module instantiations
icon icon0 (
.CONTROL0 (control0)
);
 
ila ila0 (
.CONTROL (control0),
.CLK (clk_100M),
.TRIG0 (adr),
.TRIG1 ({dat_o,dat_i}),
.TRIG2 (pc),
.TRIG3 ({clk,we,mio,byte_o,stb,ack}),
.TRIG5 (ir),
.TRIG6 ({state,next_state}),
.TRIG7 (io_reg),
.TRIG8 (imm),
.TRIG9 ({x,y})
);
 
lcd_display lcd0 (
.f1 (f1), // 1st row
.f2 (f2), // 2nd row
.m1 (m1), // 1st row mask
.m2 (m2), // 2nd row mask
 
.clk (clk_100M), // 100 Mhz clock
 
// Pad signals
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_ (db_)
);
 
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, dat_i, 4'h0, dat_o, 7'h0, mio, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, byte_o, 8'h0, pc };
123,6 → 173,7
assign m2 = 16'b1111101110011111;
 
assign pc = (cs << 4) + ip;
`endif
 
assign dat_io = (adr[15:0]==16'hb7) ? io_reg : 16'd0;
assign dat_i = mio ? dat_io : dat_mem;
133,4 → 184,8
if (adr==20'hb7 & we & mio)
io_reg <= byte_o ? { io_reg[15:8], dat_o[7:0] } : dat_o;
 
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
 
endmodule
/trunk/impl/virtex4-ml403ep/memory/mem_map.v
1,6 → 1,15
`timescale 1ns/10ps
 
module mem_map (
/*
// VGA pad signals
input vdu_clk, // 25MHz VDU clock
output vga_red_o,
output vga_green_o,
output vga_blue_o,
output horiz_sync,
output vert_sync,
*/
// Wishbone signals
input clk_i,
input rst_i,
21,17 → 30,7
output [ 3:0] sram_bw_,
output sram_cen_,
output sram_adv_ld_n_,
output flash_ce2_,
/*
// VGA pad signals
input vdu_clk, // 25MHz VDU clock
output vga_red_o,
output vga_green_o,
output vga_blue_o,
output horiz_sync,
output vert_sync,
*/
output [1:0] cnt
output flash_ce2_
);
 
// Net declarations
/trunk/tests/i86/.bochsrc
1,4 → 1,4
romimage: file=10_bitwise.out
romimage: file=11_shifts.out
cpu: count=1, ips=10000000, reset_on_triple_fault=1
megs: 2
vgaromimage: file=$BXSHARE/VGABIOS-lgpl-latest
/trunk/tests/i86/05_jump2.s
1,7 → 1,7
# Jump instruction testbench 2
#
# At the end (3535ns in rtl-model, 274.05us in spartan3), %ax=0x1234
#
# (0) = 0x2ff0
# call 1 (direct same seg), 2 (indirect reg, same seg),
# 3 (indirect mem, same seg), 4 (direct diff seg),
# 5 (indirect mem, diff seg)
/trunk/tests/i86/06_interrupt.s
1,7 → 1,8
# Interrupt instruction testbench
#
# At the end (3737ns in rtl-model, 275.9us in spartan3),
# %ax=0x1234, %bx=0x0ed7
# Memory contents at the end should be:
# 0x00: 0x0100 0x0302 0x0504 0xXX06 0x0cd7 0x0ed7 0x4002 0x04ff
# 0x10: 0x1000 0xXXXX 0xXXXX 0xXXXX 0xXXXX 0xXXXX 0xXXXX 0xXXXX
#
# int 1, 2 (int 3)
# into 3
19,12 → 20,13
movw $0x0eff, %ax
push %ax
popf
 
movb $0, (0)
int $13 # (1)
 
movb $2, (2)
jmp *%ax
 
.org 0x0cd7
movb $3, (3)
pushf
pop %bx
movw $0xebe0, (12)
31,7 → 33,7
movw $0xe342, (14)
 
int $3 # (2)
 
movb $4, (4)
movw $0x3001, (16)
movw $0xf000, (18)
 
39,6 → 41,7
hlt
 
.org 0x2000
movb $1, (1)
pushf
pop %ax
clc
45,6 → 48,7
iret # (4)
 
.org 0x3001
movb $5, (5)
pop %cx
movw $0x4002, %cx
push %cx
51,6 → 55,7
iret
 
.org 0x4002
movb $6, (6)
movw $0x4ff, %dx
push %dx
popf
57,7 → 62,11
movw $0x5000, (16)
 
into # (3) branch not taken
movw $0x1234, (0)
movw %ax, (8)
movw %bx, (10)
movw %cx, (12)
movw %dx, (14)
movw %sp, (16)
hlt
 
.org 0x5000
/trunk/tests/i86/11_shifts.s
0,0 → 1,212
# Shift logic instruction test bench
 
# Copyright (c) 2008 Zeus Gomez Marmolejo <zeus@opencores.org>
#
# This file is part of the Zet processor. This processor is free
# hardware; you can redistribute it and/or modify it under the terms of
# the GNU General Public License as published by the Free Software
# Foundation; either version 3, or (at your option) any later version.
#
# Zet is distrubuted in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Zet; see the file COPYING. If not, see
# <http://www.gnu.org/licenses/>.
 
# sal 1 (w:1,r), 2 (w:1,m), 3 (w:cl,r), 4 (w:cl,m)
# 5 (b:1,r), 6 (b:1,m), 7 (b:cl,r), 8 (b:cl,m)
# sar 9 (w:1,r), 10(w:1,m), 11(w:cl,r), 12(w:cl,m)
# 13(b:1,r), 14(b:1,m), 15(b:cl,r), 16(b:cl,m)
# shr 17(w:1,r), 18(w:1,m), 19(w:cl,r), 20(w:cl,m)
# 21(b:1,r), 22(b:1,m), 23(b:cl,r), 24(b:cl,m)
#
# End results, memory contents:
#
# 0x00: 0xa670 0x31e0 0x66c0 0x6480 0x0f5d 0x7402 0xe5d4 0x6eff
# 0x10: 0x5d55 0x3403 0x1d26 0x8d00 0xXXXX 0xXXXX 0xXXXX 0xXXXX
# 0x20: 0xdd8a 0xb1a8 0x0000 0xa800 0x8493 0x9580 0xfdb9 0xdfb9
# 0x30: 0xffff 0xfefd 0x3388 0x93ff 0x3dd0 0x54e8 0x0000 0x054e
# 0x40: 0x0b28 0x0400 0x0046 0x0046 0x0007 0x0002 0x0006 0x0007
# 0x50: 0x0046 0x0806 0x0806 0x0003 0x0087 0x0086 0x0082 0x0006
# 0x60: 0x0003 0x0083 0x0087 0x0003 0x0003 0x0082 0x0083 0x0083
# 0x70: 0x0006 0x0886 0x0083 0x0087 0x0046 0x0882 0x0882 0x0882
 
.code16
start:
 
# sal/shl word operations
movw $0x6ec5, %ax
movw $0xb1a8, %bx
movw $0x5338, (0)
movw $0x31fe, (2)
 
movw $128, %sp
 
sal %ax # (1)
pushf
mov %ax, (32)
 
shlw (0) # (2)
pushf
 
movw $0x100, %cx
shl %cl, %bx # (3), zero bit shift
pushf
movw %bx, (34)
 
movw $0xffff, %cx
movw %bx, %dx
sal %cl, %dx # (3), -1, result 0
pushf
movw %dx, (36)
 
movb $0x8, %cl
sal %cl, %bx # (3) normal
pushf
movw %bx, (38)
 
movb $0x4, %cl
sal %cl, (2) # (4)
pushf
 
# sal/shl byte operations
movw $0x956f, %dx
movw $0x4293, %ax
movw $0x33c0, (4)
movw $0x64ff, (6)
 
shl %ah # (5)
pushf
mov %ax, (40)
 
salb (5) # (6)
pushf
 
movb $0x7, %cl
shl %cl, %dl # (7)
pushf
movw %dx, (42)
 
salb %cl, (6) # (8)
pushf
 
# sar word operations
movw $0xfb72, %ax
movw $0xdfb9, %bx
movw $0x1ebb, (8)
movw $0x742f, (10)
 
sar %ax # (9)
pushf
mov %ax, (44)
 
sarw (8) # (10)
pushf
 
movw $0x100, %cx
sar %cl, %bx # (11), zero bit shift
pushf
movw %bx, (46)
 
movw $0xffff, %cx
movw %bx, %dx
sar %cl, %dx # (11), -1, result 0
pushf
movw %dx, (48)
 
movb $0x5, %cl
sar %cl, %bx # (11) normal
pushf
movw %bx, (50)
 
movb $0x4, %cl
sar %cl, (10) # (12)
pushf
 
# sar byte operations
movw $0x93b8, %dx
movw $0x6688, %ax
movw $0xcad4, (12)
movw $0x6ec9, (14)
 
sar %ah # (13)
pushf
mov %ax, (52)
 
sarb (13) # (14)
pushf
 
movb $0x7, %cl
sar %cl, %dl # (15)
pushf
movw %dx, (54)
 
sarb %cl, (14) # (16)
pushf
 
# shr word operations
movw $0x7ba1, %ax
movw $0x54e8, %bx
movw $0xbaaa, (16)
movw $0x3431, (18)
 
shr %ax # (17)
pushf
mov %ax, (56)
 
shrw (16) # (18)
pushf
 
movw $0x100, %cx
shr %cl, %bx # (19), zero bit shift
pushf
movw %bx, (58)
 
movw $0xffff, %cx
movw %bx, %dx
shr %cl, %dx # (19), -1, result 0
pushf
movw %dx, (60)
 
movb $0x4, %cl
shr %cl, %bx # (19) normal
pushf
movw %bx, (62)
 
movb $0x4, %cl
shr %cl, (18) # (20)
pushf
 
# shr byte operations
movw $0x0410, %dx
movw $0x1628, %ax
movw $0x3b26, (20)
movw $0x8d0d, (22)
 
shr %ah # (21)
pushf
mov %ax, (64)
 
shrb (21) # (22)
pushf
 
movb $0x7, %cl
shr %cl, %dl # (23)
pushf
movw %dx, (66)
 
shrb %cl, (22) # (24)
pushf
 
 
 
 
hlt
 
.org 65520
jmp start
.org 65535
.byte 0xff
/trunk/tests/i86/02_datatrnf.s
22,6 → 22,7
movb $0xed, %ah
sahf # (1)
lahf # (2) Now %ah must have 0xc7
movb %ah, (0)
movb %ah, %al
outb %al, $0xb7 # (19)
movw $0xb7, %ax
28,8 → 29,10
movw %ax, %dx
movb $0xa5, %ah
inb %dx, %al # (24)
movw %ax, (2)
sahf
lahf # Now %ax must have 0x87c7
movw %ax, (32)
 
outw %ax, %dx # (22)
movw $0xf752, %ax
38,6 → 41,12
xchg %bx, %ax # (16)
movw %ax, %ds
lds 781(%bx), %si # (3) %ds=0x5678 and %si=0x1234
movw $0, %ax
movw %ds, %bx
movw %ax, %ds
movw %bx, (4)
movw %si, (6)
movw %bx, %ds
 
movw $-1, %bx
 
56,6 → 65,12
les -46(%bx,%si), %di # (5) %di=0x8cf1, %es=%0xabcd
lea -452(%bp,%di), %si # (4) %si=0x8b2d
pushf # (13)
movw $0, %ax
movw %ax, %ds
movw %di, (8)
movw %es, %ax
movw %ax, (10)
movw %si, (12)
inw $0xb7, %ax # (25)
movw %ax, %ds
pop 1(%si) # (8)
62,10 → 77,26
xchg 2(%bx,%si), %di # (15) %di=0x0cd3
push 2(%bx,%si) # (12)
pop %es # (7) %es=0x8cf1
movw %es, %dx
 
 
movw %ds, %ax
movw $0, %cx
movw %cx, %ds
movw %di, (14)
movw %dx, (16)
movw %ax, %ds
pop %dx # (6)
push %dx
.byte 0x8f,0xc1 # (6) pop %cx (non-standard)
xchg %bx, %cx # (14) %bx=0xabcd, %cx=0xffff
 
movw %ds, %ax
movw $0, %dx
movw %dx, %ds
movw %bx, (18)
movw %cx, (20)
movw %ax, %ds
movw %es, (%bx,%di)
movw $0xb800, %bx
movw $0xa0a1, %ax
72,13 → 103,14
xlat # (18) %al=0x8c
xchg %al, %ah # (17)
xlat # %ax=0x8cf1
movw $0, %dx
movw %dx, %ds
movw %ax, (22)
movw $0xb7, %dx
outb %al, %dx # (20)
movb $0xff, %al
inb $0xb7, %al # (23) %ax=0x8cf1
movw $0x0, %bx
movw %bx, %ds
movw %ax, (0)
movw %ax, (24)
hlt
 
.org 65520
/trunk/tests/i86/10_bitwise.s
26,7 → 26,7
# 43(b:r,r), 44(b:m,r), 45(b:r,m), 46(b:i,a), 47(b:i,r), 48(b:i,m)
# not 49(w:r), 50(w:m), 51(b:r), 52(b:m)
#
# End results:
# End results, memory contents:
#
# 0x00: 0x0000 0x2400 0x30c0 0x57ff 0xff6e 0x3939 0x89ed 0x4a80
# 0x10: 0xa8a8 0x35f6 0x4f00 0xb419 0xe92d 0xXXXX 0xXXXX 0xXXXX
/trunk/tests/i86/Makefile
32,7 → 32,7
out2rom-ml403 < $< > $@
%.bin: %.rom
cat ff.rom $< > $@
cat count.rom $< > $@
 
%.out: %.o
objcopy -O binary -S $< $@
/trunk/tests/i86/08_rep.s
50,7 → 50,6
jmp rep_stos_z
 
.org 0x607
nop ## FIXME: THIS MUST BE INTRODUCED, otherwise the jmp is not taken!!
jmp rep_lods_nz
 
.org 0x809
/trunk/sim/testbench.v
10,6 → 10,7
wire m_io;
wire byte_m;
wire ack_i;
wire stb;
 
reg clk, rst;
reg [15:0] io_reg;
16,7 → 17,7
reg [ 1:0] ack;
 
// Module instantiations
memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m);
memory mem0 (clk, addr, wr_data, mem_data, stb & we & ~m_io, byte_m);
 
cpu cpu0 (
.clk_i (clk),
27,6 → 28,7
.we_o (we),
.mio_o (m_io),
.byte_o (byte_m),
.stb_o (stb),
.ack_i (ack_i)
);
 
/trunk/sim/modelsim/tb.do
1,6 → 1,6
#vdel -all -lib work
vdel -all -lib work
vlib work
vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
vlog -work work +incdir+.. ../memory.v ../testbench.v
vsim -novopt -t ns work.testbench
add wave /testbench/clk

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