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Rev 31 → Rev 32

/trunk/rtl-model/regfile.v
91,6 → 91,6
end
if (wrfl) flags <= iflags;
if (wrhi) r[4'd2] <= d[31:16];
r[14] <= wr_ip0 ? ip : r[14];
if (wr_ip0) r[14] <= ip;
end
endmodule
/trunk/rtl-model/alu.v
70,7 → 70,7
);
 
bitlog log4 (x[15:0], y, log, func, cf_log, of_log);
shifts shi5 (x[15:0], y[4:0], shi, func[1:0], word_op, cf_shi, of_shi);
shifts shi5 (x[15:0], y[4:0], shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
rotate rot6 (x[15:0], y[4:0], func[1:0], cfi, word_op, rot, cf_rot, ofi, of_rot);
othop oth7 (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
 
99,10 → 99,9
assign pfi = iflags[2];
assign cfi = iflags[0];
 
assign flags_unchanged = (t == 3'd6
|| t == 3'd4 && func == 3'd2
assign flags_unchanged = (t == 3'd4 && func == 3'd2
|| t == 3'd5 && y[4:0] == 5'h0
|| t == 3'd6 && y[4:0] == 5'h0);
|| t == 3'd6);
 
assign div_exc = func[1] && (t==3'd3) && dexc;
 
313,7 → 312,7
// This module implements the instructions shl/sal, sar, shr
//
 
module shifts(x, y, out, func, word_op, cfo, ofo);
module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
// IO ports
input [15:0] x;
input [ 4:0] y;
321,6 → 320,7
input word_op;
output [15:0] out;
output cfo, ofo;
input cfi, ofi;
 
// Net declarations
wire [15:0] sal, sar, shr, sal16, sar16, shr16;
328,10 → 328,10
wire ofo_shl, ofo_sar, ofo_shr;
wire cfo_sal8, cfo_sal16, cfo_sar8, cfo_sar16, cfo_shr8, cfo_shr16;
wire cfo16, cfo8;
wire unchanged;
 
// Module instantiations
mux4_16 m0(func, sal, sar, shr, 16'd0, out);
mux4_1 m1(func, ofo_shl, ofo_sar, ofo_shr, 1'b0, ofo);
 
// Assignments
assign { cfo_sal16, sal16 } = x << y;
350,14 → 350,18
assign shr = word_op ? shr16 : { 8'd0, shr8 };
assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
 
assign ofo = unchanged ? ofi
: (func[1] ? ofo_shr : (func[0] ? ofo_sar : ofo_shl));
assign cfo16 = func[1] ? cfo_shr16
: (func[0] ? cfo_sar16 : cfo_sal16);
assign cfo8 = func[1] ? cfo_shr8
: (func[0] ? cfo_sar8 : cfo_sal8);
assign cfo = word_op ? cfo16 : cfo8;
assign cfo = unchanged ? cfi : (word_op ? cfo16 : cfo8);
assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
 
assign unchanged = word_op ? (y==5'b0) : (y[3:0]==4'b0);
endmodule
 
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
/trunk/rtl-model/cpu.v
58,7 → 58,7
wire byte_fetch, byte_exec, fetch_or_exec;
wire of, zf, cx_zero;
wire div_exc;
wire inopco_st;
wire wr_ip0;
 
// Module instantiations
fetch fetch0 (
83,7 → 83,8
.fetch_or_exec (fetch_or_exec),
.mem_rdy (ack_i),
.div_exc (div_exc),
.inopco_st (inopco_st)
 
.wr_ip0 (wr_ip0)
);
 
exec exec0 (
110,7 → 111,7
.byteop (byte_exec),
.mem_rdy (ack_i),
.div_exc (div_exc),
.wrip0 (inopco_st)
.wrip0 (wr_ip0)
);
 
// Assignments
/trunk/rtl-model/fetch.v
41,7 → 41,7
output fetch_or_exec,
input mem_rdy,
input div_exc,
output inopco_st
output wr_ip0
);
 
// Registers, nets and parameters
60,7 → 60,7
wire [7:0] opcode, modrm;
wire exec_st, end_seq;
wire [15:0] imm_d;
wire prefix;
wire prefix, repz_pr, sovr_pr;
wire next_in_opco, next_in_exec;
wire block;
wire need_modrm, need_off, need_imm, off_size, imm_size;
69,11 → 69,12
reg [7:0] opcode_l, modrm_l;
reg [15:0] off_l, imm_l;
reg [1:0] pref_l;
reg [2:0] sop_l;
 
// Module instantiation
decode decode0(opcode, modrm, off_l, imm_l, pref_l[1], clk, rst, block,
exec_st, div_exc, need_modrm, need_off, need_imm, off_size,
imm_size, rom_ir, off, imm_d, end_seq, dive);
imm_size, rom_ir, off, imm_d, end_seq, dive, sop_l);
next_or_not nn0(pref_l, opcode[7:1], cx_zero, zf, next_in_opco,
next_in_exec);
nstate ns0(state, prefix, need_modrm, need_off, need_imm, end_seq,
94,10 → 95,12
: (((state == offse_st) & off_size
| (state == immed_st) & imm_size) ? 16'd2
: 16'd1);
assign prefix = (opcode[7:1]==7'b1111_001);
assign block = ir[`MEM_OP] && !mem_rdy;
assign wr_ip0 = (state == opcod_st) && !pref_l[1] && !sop_l[2];
 
assign inopco_st = (state == opcod_st);
assign sovr_pr = (opcode[7:5]==3'b001 && opcode[2:0]==3'b110);
assign repz_pr = (opcode[7:1]==7'b1111_001);
assign prefix = sovr_pr || repz_pr;
 
// Behaviour
always @(posedge clk)
111,11 → 114,16
default: // opcode or prefix
begin
case (state)
opcod_st: pref_l <= prefix ? { 1'b1, opcode[0] } : 2'b0;
default: pref_l <= 2'b0;
opcod_st:
begin // There has been a prefix
pref_l <= repz_pr ? { 1'b1, opcode[0] } : pref_l;
sop_l <= sovr_pr ? { 1'b1, opcode[4:3] } : sop_l;
end
default: begin pref_l <= 2'b0; sop_l <= 3'b0; end
endcase
state <= opcod_st;
off_l <= 16'd0;
modrm_l <= 8'b0000_0110;
end
 
modrm_st: // modrm
248,7 → 256,9
output [15:0] off_o,
output [15:0] imm_o,
output end_seq,
output reg dive
output reg dive,
 
input [2:0] sop_l
);
 
// Net declarations
259,7 → 269,7
reg [`SEQ_ADDR_WIDTH-1:0] seq;
 
// Module instantiations
opcode_deco opcode_deco0 (opcode, modrm, rep, base_addr, need_modrm,
opcode_deco opcode_deco0 (opcode, modrm, rep, sop_l, base_addr, need_modrm,
need_off, need_imm, off_size, imm_size, src, dst,
base, index, seg);
seq_rom seq_rom0 (seq_addr, {end_seq, micro_addr});
286,6 → 296,7
input [7:0] opcode,
input [7:0] modrm,
input rep,
input [2:0] sovr_pr,
 
output reg [`SEQ_ADDR_WIDTH-1:0] seq_addr,
output reg need_modrm,
311,7 → 322,7
wire [2:0] srcm, dstm;
 
// Module instantiations
memory_regs mr(rm, mod, base, index, seg);
memory_regs mr(rm, mod, sovr_pr, base, index, seg);
 
// Assignments
assign mod = modrm[7:6];
1674,23 → 1685,31
module memory_regs (
input [2:0] rm,
input [1:0] mod,
input [2:0] sovr_pr,
 
output reg [3:0] base,
output reg [3:0] index,
output reg [1:0] seg
output [1:0] seg
);
 
// Register declaration
reg [1:0] s;
 
// Continuous assignments
assign seg = sovr_pr[2] ? sovr_pr[1:0] : s;
 
// Behaviour
always @(rm or mod)
case (rm)
3'b000: begin base <= 4'b0011; index <= 4'b0110; seg <= 2'b11; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; seg <= 2'b11; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; seg <= 2'b10; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; seg <= 2'b10; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; seg <= 2'b11; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; seg <= 2'b11; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
seg <= mod ? 2'b10 : 2'b11; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; seg <= 2'b11; end
3'b000: begin base <= 4'b0011; index <= 4'b0110; s <= 2'b11; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; s <= 2'b11; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; s <= 2'b10; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; s <= 2'b10; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; s <= 2'b11; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; s <= 2'b11; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
s <= mod ? 2'b10 : 2'b11; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; s <= 2'b11; end
endcase
endmodule
 
/trunk/tests/i86/19_segpr.s
0,0 → 1,103
.code16
start:
movw $0xf100, %bx
movw %bx, %es
 
es movw (0), %bx
es movw (2), %ax
movw %ax, (2)
movw $0x2, %sp
es push %bx
 
es les (0), %dx
movw %dx, (4)
movw %es, %dx
movw %dx, (6)
 
movw $5, %di
cs lea 23(%bp,%di), %si
movw %si, (8)
 
movw $0x0005, %bx
movw $0x0005, %ax
movw $0x2345, (10)
movw $0xf100, %dx
movw %dx, %es
es xlat
movw %ax, (12)
 
# inc with segment
movw $0x1, %ax
movw %ax, %ss
movw $0x6, (16)
ss incw (0)
 
# div with interrupt
movw $32, %sp
movw $0x0, (18)
ss
.byte 0xf3
divw (2)
subw $6, %sp
 
movw $0x1200, (20)
movw $5, %bx
movw $3, %si
# repz prefix (do not affect)
.byte 0xf3
ss call *-4(%bx,%si)
 
hlt
 
.org 0x1000
.word 0x1100
.word 0xf000
 
.org 0x100a
.word 0x5678
 
.org 0x1100
movw %sp, %si
ss movw (%si), %si
movw %si, (14)
addw $6, %si
movw %sp, %di
ss movw %si, (%di)
iret
 
.org 0x1200
movw $0xf120, %cx
movw %cx, %es
movw $0x0200, %si
movw $0x0e01, %di
 
es cmpsb
pushf
 
movw $0x1, %ax
movw %ax, %es
movw $6, %di
movw $0x1400, %si
movw $0x6, %cx
# Two prefixes
rep cs movsb
hlt
 
.org 0x1400
.byte 0x01,0xff,0xff,0x80
.word 0x0002
.byte 0xc2
 
.org 0x2001
.byte 0x02,0xff,0x01,0x01
.word 0x8001
 
 
repz cs cmpsb
repz cs lodsb
repz cs scasb
 
.org 65520
jmp start
.org 65535
.byte 0xff
/trunk/tests/i86/.bochsrc
1,4 → 1,4
romimage: file=18_div.out
romimage: file=15_sub.out
cpu: count=1, ips=10000000, reset_on_triple_fault=1
megs: 2
vgaromimage: file=$BXSHARE/VGABIOS-lgpl-latest

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