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URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

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Rev 34 → Rev 35

/trunk/rtl-model/exec.v
44,7 → 44,7
output we,
output m_io,
output byteop,
input mem_rdy,
input block,
output div_exc,
input wrip0
);
56,10 → 56,10
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, memalu, r_byte, c_byte;
wire wr, wr_reg, block;
wire wr, wr_reg;
wire wr_cnd;
wire jmp;
wire mem_op, b_imm;
wire b_imm;
wire [8:0] flags, iflags, oflags;
wire [4:0] logic_flags;
wire alu_word;
91,7 → 91,6
assign func = ir[28:26];
assign byteop = ir[29];
assign memalu = ir[30];
assign mem_op = ir[31];
assign m_io = ir[32];
assign b_imm = ir[33];
assign r_byte = ir[34];
106,7 → 105,6
assign wr_high = high && !block && !div_exc;
assign of = flags[8];
assign zf = flags[3];
assign block = mem_op && !mem_rdy;
 
assign iflags = oflags;
assign alu_iflags = { 4'b0, flags[8:3], 1'b0, flags[2], 1'b0, flags[1],
/trunk/rtl-model/cpu.v
33,17 → 33,18
output [15:0] aluo,
`endif
 
// Wishbone signals
input clk_i,
input rst_i,
input [15:0] dat_i,
output [15:0] dat_o,
output [19:0] adr_o,
output we_o,
output mio_o,
output byte_o,
output stb_o,
input ack_i
// Wishbone master interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o,
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i
);
 
// Net declarations
60,6 → 61,14
wire div_exc;
wire wr_ip0;
 
wire cpu_byte_o;
wire cpu_m_io;
wire [19:0] cpu_adr_o;
wire cpu_block;
wire [15:0] cpu_dat_i;
wire [15:0] cpu_dat_o;
wire cpu_we_o;
 
// Module instantiations
fetch fetch0 (
`ifdef DEBUG
66,13 → 75,13
.state (state),
.next_state (next_state),
`endif
.clk (clk_i),
.rst (rst_i),
.clk (wb_clk_i),
.rst (wb_rst_i),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.data (dat_i),
.data (cpu_dat_i),
.ir (ir),
.off (off),
.imm (imm),
81,7 → 90,7
.cx_zero (cx_zero),
.bytefetch (byte_fetch),
.fetch_or_exec (fetch_or_exec),
.mem_rdy (ack_i),
.block (cpu_block),
.div_exc (div_exc),
 
.wr_ip0 (wr_ip0)
101,25 → 110,165
.of (of),
.zf (zf),
.cx_zero (cx_zero),
.clk (clk_i),
.rst (rst_i),
.memout (dat_i),
.wr_data (dat_o),
.clk (wb_clk_i),
.rst (wb_rst_i),
.memout (cpu_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (we_o),
.m_io (mio_o),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.mem_rdy (ack_i),
.block (cpu_block),
.div_exc (div_exc),
.wrip0 (wr_ip0)
);
 
wb_master wm0 (
.cpu_byte_o (cpu_byte_o),
.cpu_memop (ir[`MEM_OP]),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (cpu_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
 
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
 
// Assignments
assign adr_o = fetch_or_exec ? addr_exec : addr_fetch;
assign byte_o = fetch_or_exec ? byte_exec : byte_fetch;
assign stb_o = rst_i ? 1'b1 : ir[`MEM_OP];
assign cpu_adr_o = fetch_or_exec ? addr_exec : addr_fetch;
assign cpu_byte_o = fetch_or_exec ? byte_exec : byte_fetch;
 
`ifdef DEBUG
assign iralu = ir[28:23];
`endif
endmodule
 
module wb_master (
input cpu_byte_o,
input cpu_memop,
input cpu_m_io,
input [19:0] cpu_adr_o,
output reg cpu_block,
output reg [15:0] cpu_dat_i,
input [15:0] cpu_dat_o,
input cpu_we_o,
 
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output reg [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o,
output reg [ 1:0] wb_sel_o,
output reg wb_stb_o,
output reg wb_cyc_o,
input wb_ack_i
);
 
// Register and nets declarations
reg [ 1:0] cs; // current state
 
wire op; // in an operation
wire odd_word; // unaligned word
wire a0; // address 0 pin
wire [15:0] blw; // low byte (sign extended)
wire [15:0] bhw; // high byte (sign extended)
wire [19:1] adr1; // next address (for unaligned acc)
wire [ 1:0] sel_o; // bus byte select
 
// Declare the symbolic names for states
parameter [1:0]
cyc0_lo = 3'd0,
stb1_hi = 3'd1,
stb1_lo = 3'd2,
stb2_hi = 3'd3;
 
// Assignments
assign op = (cpu_memop | cpu_m_io);
assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
assign a0 = cpu_adr_o[0];
assign blw = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
assign bhw = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
assign adr1 = a0 ? (cpu_adr_o[19:1] + 1'b1)
: cpu_adr_o[19:1];
assign wb_dat_o = a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
: cpu_dat_o;
assign wb_we_o = cpu_we_o;
assign wb_tga_o = cpu_m_io;
assign sel_o = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
 
// Behaviour
// cpu_dat_i
always @(posedge wb_clk_i)
cpu_dat_i <= (cs == cyc0_lo) ?
(wb_ack_i ?
(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
: cpu_dat_i)
: ((cs == stb1_lo && wb_ack_i) ?
{ wb_dat_i[7:0], cpu_dat_i[7:0] }
: cpu_dat_i);
 
// outputs setup
always @(*)
case (cs)
default:
begin
cpu_block <= op;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= op;
wb_cyc_o <= op;
end
stb1_hi:
begin
cpu_block <= odd_word | wb_ack_i;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= 1'b0;
wb_cyc_o <= odd_word;
end
stb1_lo:
begin
cpu_block <= 1'b1;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b1;
wb_cyc_o <= 1'b1;
end
stb2_hi:
begin
cpu_block <= wb_ack_i;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b0;
wb_cyc_o <= 1'b0;
end
endcase
 
// state machine
always @(posedge wb_clk_i)
if (wb_rst_i) cs <= cyc0_lo;
else
case (cs)
default: cs <= wb_ack_i ? (op ? stb1_hi : cyc0_lo)
: cyc0_lo;
stb1_hi: cs <= wb_ack_i ? stb1_hi
: (odd_word ? stb1_lo : cyc0_lo);
stb1_lo: cs <= wb_ack_i ? stb2_hi : stb1_lo;
stb2_hi: cs <= wb_ack_i ? stb2_hi : cyc0_lo;
endcase
 
endmodule
/trunk/rtl-model/fetch.v
39,7 → 39,7
output [19:0] pc,
output bytefetch,
output fetch_or_exec,
input mem_rdy,
input block,
input div_exc,
output wr_ip0
);
62,7 → 62,6
wire [15:0] imm_d;
wire prefix, repz_pr, sovr_pr;
wire next_in_opco, next_in_exec;
wire block;
wire need_modrm, need_off, need_imm, off_size, imm_size;
wire dive;
 
95,7 → 94,6
: (((state == offse_st) & off_size
| (state == immed_st) & imm_size) ? 16'd2
: 16'd1);
assign block = ir[`MEM_OP] && !mem_rdy;
assign wr_ip0 = (state == opcod_st) && !pref_l[1] && !sop_l[2];
 
assign sovr_pr = (opcode[7:5]==3'b001 && opcode[2:0]==3'b110);
/trunk/rtl-model/util/primitives.v
106,6 → 106,7
endcase
endmodule
 
/*
//
// Multiplexor 4:1 de 1 bits d'amplada
//
125,7 → 126,6
endcase
endmodule
 
/*
//
// Multiplexor 2:1 de 8 bits d'amplada
//
/trunk/impl/spartan3an-sk/rtl/vga/char_rom_b16.v File deleted
/trunk/impl/spartan3an-sk/rtl/vga/ram2k_b16.v File deleted \ No newline at end of file
/trunk/impl/spartan3an-sk/rtl/vga/ram2k_b16_attr.v File deleted \ No newline at end of file
/trunk/impl/spartan3an-sk/rtl/vga/vdu.v File deleted
/trunk/impl/virtex4-ml403ep/kotku.v
8,7 → 8,7
output [7:4] db_,
 
`endif
/*
 
output tft_lcd_clk_,
output tft_lcd_r_,
output tft_lcd_g_,
15,7 → 15,7
output tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
*/
 
input sys_clk_in_,
 
output sram_clk_,
72,7 → 72,7
`endif
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
// .vdu_clk (tft_lcd_clk_),
.vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
 
80,9 → 80,17
`ifdef DEBUG
.curr_st (curr_st),
`endif
// VGA pad signals
.vdu_clk (tft_lcd_clk_),
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_),
 
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
.rst_i (rst_lck),
.adr_i (adr),
.dat_i (dat_o),
.dat_o (dat_mem),
101,15 → 109,6
.sram_cen_ (sram_cen_),
.sram_adv_ld_n_ (sram_adv_ld_n_),
.flash_ce2_ (flash_ce2_)
/*
// VGA pad signals
.vdu_clk (tft_lcd_clk_),
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_),
*/
);
 
cpu zet_proc (
/trunk/impl/virtex4-ml403ep/memory/clock.v
27,7 → 27,8
// Continuous assignments
assign rst = (count!=7'h7f);
assign clk_3M = clock[3];
assign clk = clk_3M;
// assign clk = clk_3M;
assign clk = clock[1];
 
// Behavioral description
// count
/trunk/impl/virtex4-ml403ep/memory/mem_map.v
1,6 → 1,6
`timescale 1ns/10ps
 
`include "defines.v"
//`include "defines.v"
 
module mem_map (
`ifdef DEBUG
7,16 → 7,22
output [ 2:0] curr_st,
`endif
/*
output req_write,
output req_read,
output one_more_cycle,
output vga2_we,
output vga2_rw,
output vga4_rw,
*/
// VGA pad signals
input vdu_clk, // 25MHz VDU clock
output vga_red_o,
output vga_green_o,
output vga_blue_o,
output horiz_sync,
output vert_sync,
*/
 
// Wishbone signals
input clk_i,
input clk_i, // 25 Mhz VDU clock
input rst_i,
input [19:0] adr_i,
input [15:0] dat_i,
24,6 → 30,7
input we_i,
output ack_o,
input stb_i,
input cyc_i,
input byte_i,
 
// Pad signals - Flash / SRAM
39,9 → 46,9
);
 
// Net declarations
wire [15:0] dat_mem_o /*, dat_vdu_o */;
wire ack_mem_o /*, ack_vdu_o */;
wire stb_mem_i /*, stb_vdu_i */;
wire [15:0] dat_mem_o, dat_vdu_o;
wire ack_mem_o, ack_vdu_o;
wire stb_mem_i, stb_vdu_i;
 
// Module instantiations
mem_ctrl mem_ctrl0 (
69,12 → 76,21
.sram_adv_ld_n_ (sram_adv_ld_n_),
.flash_ce2_ (flash_ce2_)
);
 
vdu vdu0 (
/*
vdu vdu0 (
.req_write (req_write),
.req_read (req_read),
.one_more_cycle (one_more_cycle),
.vga2_we (vga2_we),
.vga2_rw (vga2_rw),
.vga4_rw (vga4_rw),
*/
// Wishbone signals
.clk_i (clk_i),
.rst_i (rst_i),
.stb_i (stb_vdu_i),
.cyc_i (stb_vdu_i),
.we_i (we_i),
.adr_i (adr_i[11:0]),
.dat_i (dat_i),
83,7 → 99,6
.byte_i (byte_i),
 
// VGA pad signals
.vdu_clk (vdu_clk),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
90,10 → 105,10
.horiz_sync (horiz_sync),
.vert_sync (vert_sync)
);
*/
 
// Continuous assignments
// assign stb_vdu_i = (adr_i[19:13]==7'b1011_100) & stb_i;
assign stb_mem_i = /* (adr_i[19:13]!=7'b1011_100) & */ stb_i;
assign ack_o = /* stb_vdu_i ? ack_vdu_o : */ ack_mem_o;
assign dat_o = /* stb_vdu_i ? dat_vdu_o : */ dat_mem_o;
assign stb_vdu_i = (adr_i[19:13]==7'b1011_100) & stb_i;
assign stb_mem_i = (adr_i[19:13]!=7'b1011_100) & stb_i;
assign ack_o = stb_vdu_i ? ack_vdu_o : ack_mem_o;
assign dat_o = stb_vdu_i ? dat_vdu_o : dat_mem_o;
endmodule
/trunk/impl/virtex4-ml403ep/memory/ml403-with-tft.ucf
99,6 → 99,8
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
NET but_ LOC = B6; # C Button
 
#NET leds_[0] LOC = G5; #GPLED0
#NET leds_[1] LOC = G6; #GPLED1
#NET leds_[2] LOC = A11; #GPLED2
/trunk/impl/virtex4-ml403ep/memory/mem_ctrl.v
1,6 → 1,6
`timescale 1ns/10ps
 
`include "defines.v"
//`include "defines.v"
 
module mem_ctrl (
`ifdef DEBUG
/trunk/impl/virtex4-ml403ep/memory/mem_map_test.v
43,11 → 43,12
output rs_,
output rw_,
output e_,
output [7:4] db_
output [7:4] db_,
 
input but_
);
 
// Net declarations
wire rst;
wire clk;
wire [15:0] dada_ent;
wire ack;
54,7 → 55,16
wire clk_100M;
wire [63:0] f1, f2;
wire [15:0] m1, m2;
wire rst_lck;
 
wire req_write;
wire req_read;
wire one_more_cycle;
wire vga2_we;
wire vga2_rw;
wire vga4_rw;
 
 
// Register declarations
reg [ 7:0] estat;
reg [15:0] dada_sor;
64,17 → 74,46
reg we;
reg stb;
reg byte_o;
reg rst;
 
// DEBUG
wire [35:0] control0;
 
// Module instantiations
icon icon0 (
.CONTROL0 (control0)
);
 
ila ila0 (
.CONTROL (control0),
.CLK (clk_100M),
.TRIG0 ({tft_lcd_clk_,tft_lcd_r_,tft_lcd_g_,tft_lcd_b_,tft_lcd_hsync_,tft_lcd_vsync_}),
.TRIG1 (dada_ent),
.TRIG2 (estat),
.TRIG3 (dada_sor),
.TRIG4 (adr),
.TRIG5 ({rst,clk,ack,we,stb,byte_o}),
.TRIG6 ({req_write,req_read,one_more_cycle,vga2_we,vga2_rw,vga4_rw})
);
 
// Module instantiations
clock c0 (
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
.clk_100M (clk_100M),
.vdu_clk (tft_lcd_clk_),
.rst (rst)
// .vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
assign tft_lcd_clk_ = clk;
 
mem_map mem_map0 (
.req_write (req_write),
.req_read (req_read),
.one_more_cycle (one_more_cycle),
.vga2_we (vga2_we),
.vga2_rw (vga2_rw),
.vga4_rw (vga4_rw),
 
// Wishbone signals
.clk_i (clk),
.rst_i (rst),
126,9 → 165,11
assign m1 = 16'b1101111011111111;
assign m2 = 16'b1111101010101111;
 
 
// Behavioral description
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
 
always @(posedge clk)
if (rst)
begin // ROM word read (dada1 = 1234)
estat <= 8'h00;
/trunk/tests/i86/Makefile
1,6 → 1,7
s3roms := $(patsubst %.s,%.s3rom,$(wildcard *.s))
ml403roms := $(patsubst %.s,%.bin,$(wildcard *.s))
rtlroms := $(patsubst %.s,%.rtlrom,$(wildcard *s))
all: $(s3roms) $(rtlroms)
all: $(ml403roms) $(rtlroms)
 
# altera: ../../altera/zet/simulation/modelsim/bios0.dat ../../altera/zet/simulation/modelsim/bios1.dat
 
26,6 → 27,9
echo :00000001FF >> $@
 
%.rtlrom: %.out
hexdump -v -e '1/2 "%04X"' -e '"\n"' $< > ../../sim/$@
 
%.rtlold: %.out
hexdump -v -e '1/1 "%02X"' -e '"\n"' $< > ../../sim/$@
 
%.rom: %.out
/trunk/soc/vga/ram2k_b16_attr.v
0,0 → 1,92
`timescale 1ns/10ps
 
module ram_2k_attr (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp;
 
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
 
defparam ram.INIT_00 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_01 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_02 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_03 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_04 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_05 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_06 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_07 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_08 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_09 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_10 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_11 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_12 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_13 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_14 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_15 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_16 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_17 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_18 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_19 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_20 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_21 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_22 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_23 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_24 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_25 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_26 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_27 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_28 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_29 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_30 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_31 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_32 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_33 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_34 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_35 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_36 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_37 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_38 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_39 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
 
endmodule
/trunk/soc/vga/vdu.v
0,0 → 1,360
// Video Display terminal
// John Kent
// 3th September 2004
// Assumes a pixel clock input of 50 MHz
// Generates a 12.5MHz CPU Clock output
//
// Display Format is:
// 80 characters across by 25 characters down.
// 8 horizonal pixels / character
// 16 vertical scan lines / character (2 scan lines/row)
`timescale 1ns/10ps
 
module vdu
(
// Wishbone signals
input clk_i, // 25 Mhz VDU clock
input rst_i,
input stb_i,
input cyc_i,
input we_i,
input [11:0] adr_i,
input [15:0] dat_i,
output reg [15:0] dat_o,
output reg ack_o,
input byte_i,
 
// VGA pad signals
output reg vga_red_o,
output reg vga_green_o,
output reg vga_blue_o,
output reg horiz_sync,
output reg vert_sync
);
 
// Net, registers and parameters
 
// Synchronization constants
parameter HOR_DISP_END = 10'd639; // Last horizontal pixel displayed
parameter HOR_SYNC_BEG = 10'd679; // Start of horizontal synch pulse
parameter HOR_SYNC_END = 10'd775; // End of Horizontal Synch pulse
parameter HOR_SCAN_END = 10'd799; // Last pixel in scan line
parameter HOR_DISP_CHR = 80; // Number of characters displayed per row
 
parameter VER_DISP_END = 9'd399; // last row displayed
parameter VER_SYNC_BEG = 9'd413; // start of vertical synch pulse
parameter VER_SYNC_END = 9'd414; // end of vertical synch pulse
parameter VER_SCAN_END = 9'd450; // Last scan row in the frame
parameter VER_DISP_CHR = 6'd25; // Number of character rows displayed
 
reg cursor_on_v;
reg cursor_on_h;
reg video_on_v;
reg video_on_h;
reg [9:0] h_count;
reg [8:0] v_count; // 0 to VER_SCAN_END
reg [22:0] blink_count;
 
// Character generator ROM
wire char_cs;
wire char_we;
wire [11:0] char_addr;
wire [7:0] char_data_in;
wire [7:0] char_data_out;
 
// Control registers
wire [6:0] reg_hcursor; // 80 columns
wire [4:0] reg_vcursor; // 25 rows
wire [4:0] reg_voffset; // 25 rows
 
// Video shift register
reg [7:0] vga_shift;
reg [2:0] vga_fg_colour;
reg [2:0] vga_bg_colour;
reg cursor_on;
wire cursor_on1;
reg video_on;
wire video_on1;
 
// vga character ram access bus
reg [6:0] col_addr; // 0 to 79
reg [4:0] row_addr; // 0 to 49 (25 * 2 -1)
reg [6:0] col1_addr; // 0 to 79
reg [4:0] row1_addr; // 0 to 49 (25 * 2 - 1)
reg [6:0] hor_addr; // 0 to 79
reg [6:0] ver_addr; // 0 to 124
reg vga0_we;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw;
reg vga1_we;
reg vga2_we;
reg buff_we;
reg [7:0] buff_data_in;
reg attr_we;
reg [7:0] attr_data_in;
reg [10:0] buff_addr;
reg [10:0] attr0_addr;
reg attr0_we;
reg [10:0] buff0_addr;
reg buff0_we;
reg [10:0] attr_addr;
wire vga_cs;
wire [7:0] vga_data_out;
wire [7:0] attr_data_out;
wire [10:0] vga_addr; // 2K byte character buffer
wire a0;
wire [10:0] vdu_addr1;
wire byte1;
wire [15:0] out_data;
wire [15:0] ext_attr, ext_buff;
wire fg_or_bg;
wire stb;
 
// Character write handshake signals
reg req_write; // request character write
reg req_read;
reg one_more_cycle;
 
// Module instantiation
char_rom vdu_char_rom (
.clk (clk_i),
.rst (rst_i),
.cs (char_cs),
.we (char_we),
.addr (char_addr),
.wdata (char_data_in),
.rdata (char_data_out)
);
 
ram_2k char_buff_ram (
.clk (clk_i),
.rst (rst_i),
.cs (vga_cs),
.we (buff_we),
.addr (buff_addr),
.wdata (buff_data_in),
.rdata (vga_data_out)
);
 
ram_2k_attr attr_buff_ram (
.clk (clk_i),
.rst (rst_i),
.cs (vga_cs),
.we (attr_we),
.addr (attr_addr),
.wdata (attr_data_in),
.rdata (attr_data_out)
);
 
// Assignments
assign video_on1 = video_on_h && video_on_v;
assign cursor_on1 = cursor_on_h && cursor_on_v;
assign char_cs = 1'b1;
assign char_we = 1'b0;
assign char_data_in = 8'b0;
assign char_addr = { vga_data_out, v_count[3:0] };
assign vga_addr = { 4'b0, hor_addr} + { ver_addr, 4'b0 };
assign a0 = adr_i[0];
assign vdu_addr1 = adr_i[11:1] + 11'd1;
assign byte1 = byte_i || (adr_i == 12'hfff);
assign out_data = a0 ? (byte_i ? ext_attr : {vga_data_out, attr_data_out} )
: (byte_i ? ext_buff : {attr_data_out, vga_data_out} );
assign ext_buff = { {8{vga_data_out[7]}}, vga_data_out };
assign ext_attr = { {8{attr_data_out[7]}}, attr_data_out };
 
assign vga_cs = 1'b1;
assign stb = stb_i && cyc_i;
 
// Old control registers
assign reg_hcursor = 7'b0;
assign reg_vcursor = 5'd0;
assign reg_voffset = 5'd0;
 
assign fg_or_bg = vga_shift[7] ^ cursor_on;
 
// Behaviour
 
// CPU write interface
always @(posedge clk_i)
if (rst_i)
begin
attr0_addr <= 11'b0;
attr0_we <= 1'b0;
attr_data_in <= 8'h0;
buff0_addr <= 11'b0;
buff0_we <= 1'b0;
buff_data_in <= 8'h0;
req_write <= 1'b0;
end
else
begin
if (stb)
begin
attr0_addr <= adr_i[11:1];
attr0_we <= we_i & (!byte1 | a0);
attr_data_in <= a0 ? dat_i[7:0] : dat_i[15:8];
buff0_addr <= (a0 && !byte1) ? vdu_addr1 : adr_i[11:1];
buff0_we <= we_i & (!byte1 | !a0);
buff_data_in <= a0 ? dat_i[15:8] : dat_i[7:0];
req_write <= we_i;
end
end
 
// CPU read interface
always @(posedge clk_i)
if (rst_i)
begin
dat_o <= 16'h0;
ack_o <= 16'h0;
end
else
begin
dat_o <= vga3_rw ? out_data : dat_o;
ack_o <= vga3_rw ? 1'b1 : (ack_o && stb);
end
 
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(posedge clk_i)
if (rst_i)
begin
h_count <= 10'b0;
horiz_sync <= 1'b1;
v_count <= 9'b0;
vert_sync <= 1'b1;
video_on_h <= 1'b1;
video_on_v <= 1'b1;
cursor_on_h <= 1'b0;
cursor_on_v <= 1'b0;
blink_count <= 22'b0;
end
else
begin
h_count <= (h_count==HOR_SCAN_END) ? 10'b0 : h_count + 10'b1;
horiz_sync <= (h_count==HOR_SYNC_BEG) ? 1'b0
: ((h_count==HOR_SYNC_END) ? 1'b1 : horiz_sync);
v_count <= (v_count==VER_SCAN_END && h_count==HOR_SCAN_END) ? 9'b0
: ((h_count==HOR_SYNC_END) ? v_count + 9'b1 : v_count);
vert_sync <= (v_count==VER_SYNC_BEG) ? 1'b0
: ((v_count==VER_SYNC_END) ? 1'b1 : vert_sync);
video_on_h <= (h_count==HOR_SCAN_END) ? 1'b1
: ((h_count==HOR_DISP_END) ? 1'b0 : video_on_h);
video_on_v <= (v_count==VER_SYNC_BEG) ? 1'b1
: ((v_count==VER_DISP_END) ? 1'b0 : video_on_v);
cursor_on_h <= (h_count[9:3] == reg_hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == reg_vcursor[4:0]);
blink_count <= blink_count + 22'd1;
end
 
// Video memory access
always @(posedge clk_i)
if (rst_i)
begin
vga0_we <= 1'b0;
vga0_rw <= 1'b1;
row_addr <= 5'b0;
col_addr <= 7'b0;
 
vga1_we <= 1'b0;
vga1_rw <= 1'b1;
row1_addr <= 5'b0;
col1_addr <= 7'b0;
 
vga2_we <= 1'b0;
vga2_rw <= 1'b0;
vga3_rw <= 1'b0;
ver_addr <= 7'b0;
hor_addr <= 7'b0;
 
buff_addr <= 10'b0;
attr_addr <= 10'b0;
buff_we <= 1'b0;
attr_we <= 1'b0;
end
else
begin
// on h_count = 0 initiate character write
// all other cycles are reads
case (h_count[2:0])
3'b000: // pipeline character write
begin
vga0_we <= we_i;
vga0_rw <= stb_i && cyc_i;
end
default: // other 6 cycles free
begin
vga0_we <= 1'b0;
vga0_rw <= 1'b0;
col_addr <= h_count[9:3];
row_addr <= v_count[8:4] + reg_voffset[4:0];
end
endcase
 
// on vdu_clk + 1 round off row address
// row1_addr = (row_addr % 80)
vga1_we <= vga0_we;
vga1_rw <= vga0_rw;
row1_addr <= (row_addr < VER_DISP_CHR) ? row_addr
: row_addr - VER_DISP_CHR;
col1_addr <= col_addr;
 
// on vdu_clk + 2 calculate vertical address
// ver_addr = (row_addr % 80) x 5
vga2_we <= vga1_we;
vga2_rw <= vga1_rw;
ver_addr <= { 2'b00, row1_addr } + { row1_addr, 2'b00 }; // x5
hor_addr <= col1_addr;
 
// on vdu_clk + 3 calculate memory address
// vga_addr = (row_addr % 80) * 80 + hor_addr
buff_addr <= vga2_rw ? buff0_addr : vga_addr;
attr_addr <= vga2_rw ? attr0_addr : vga_addr;
buff_we <= vga2_rw ? (buff0_we & vga2_we) : 1'b0;
attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0;
vga3_rw <= vga2_rw;
end
 
// Video shift register
always @(posedge clk_i)
if (rst_i)
begin
video_on = 1'b0;
cursor_on = 1'b0;
vga_bg_colour = 3'b000;
vga_fg_colour = 3'b111;
vga_shift = 8'b00000000;
vga_red_o = 1'b0;
vga_green_o = 1'b0;
vga_blue_o = 1'b0;
end
else
begin
if (h_count[2:0] == 3'b000)
begin
video_on = video_on1;
cursor_on = (cursor_on1 | attr_data_out[3]) & blink_count[22];
vga_fg_colour = attr_data_out[2:0];
vga_bg_colour = attr_data_out[6:4];
if (!attr_data_out[7]) vga_shift = char_data_out;
else
case (v_count[3:2])
2'b00: vga_shift = { {4{vga_data_out[0]}}, {4{vga_data_out[1]}} };
2'b01: vga_shift = { {4{vga_data_out[2]}}, {4{vga_data_out[3]}} };
2'b10: vga_shift = { {4{vga_data_out[4]}}, {4{vga_data_out[5]}} };
default: vga_shift = { {4{vga_data_out[6]}}, {4{vga_data_out[7]}} };
endcase
end
else vga_shift = { vga_shift[6:0], 1'b0 };
 
//
// Colour mask is
// 7 6 5 4 3 2 1 0
// X BG BB BR X FG FB FR
//
vga_red_o = fg_or_bg ? video_on & vga_fg_colour[0]
: video_on & vga_bg_colour[0];
vga_green_o = fg_or_bg ? video_on & vga_fg_colour[1]
: video_on & vga_bg_colour[1];
vga_blue_o = fg_or_bg ? video_on & vga_fg_colour[2]
: video_on & vga_bg_colour[2];
end
endmodule
/trunk/soc/vga/char_rom_b16.v
0,0 → 1,181
////////////////////////////////////////////////////////////////
//
// Character generator ROM
//
// 7 pixels x 11 rows x 128 characters.
//
// Last Updated
// 18th Oct 2004
// J. E. Kent.
////////////////////////////////////////////////////////////////
 
`timescale 1ns/10ps
 
module char_rom (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [11:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp0, dp1;
wire [7:0] rdata1, rdata0;
 
// Module instantiations
RAMB16_S9 rom0 (.DO(rdata0),
.DOP (dp0),
.ADDR (addr[10:0]),
.CLK (clk),
.DI (wdata),
.DIP (dp0),
.EN (cs),
.SSR (rst),
.WE (we));
 
RAMB16_S9 rom1 (.DO(rdata1),
.DOP (dp1),
.ADDR (addr[10:0]),
.CLK (clk),
.DI (wdata),
.DIP (dp1),
.EN (cs),
.SSR (rst),
.WE (we));
 
defparam rom0.INIT_00 = 256'h000000007E818199A58181A5817E0000_00000000000000000000000000000000; // 01() 00( )
defparam rom0.INIT_01 = 256'h0000000010387CFEFEFEFE6C00000000_000000007EFFFFE7DBFFFFDBFF7E0000; // 03() 02()
defparam rom0.INIT_02 = 256'h000000003C1818E7E7E73C3C18000000_000000000010387CFE7C381000000000; // 05() 04()
defparam rom0.INIT_03 = 256'h000000000000183C3C18000000000000_000000003C18187EFFFF7E3C18000000; // 07() 06()
defparam rom0.INIT_04 = 256'h00000000003C664242663C0000000000_FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF; // 09( ) 08()
defparam rom0.INIT_05 = 256'h0000000078CCCCCCCC781A0E061E0000_FFFFFFFFFFC399BDBD99C3FFFFFFFFFF; // 0b( ) 0a()
defparam rom0.INIT_06 = 256'h00000000E0F070303030303F333F0000_0000000018187E183C666666663C0000; // 0d() 0c( )
defparam rom0.INIT_07 = 256'h000000001818DB3CE73CDB1818000000_000000C0E6E767636363637F637F0000; // 0f() 0e()
defparam rom0.INIT_08 = 256'h0000000002060E1E3EFE3E1E0E060200_0000000080C0E0F0F8FEF8F0E0C08000; // 11() 10()
defparam rom0.INIT_09 = 256'h00000000666600666666666666660000_0000000000183C7E1818187E3C180000; // 13() 12()
defparam rom0.INIT_0A = 256'h0000007CC60C386CC6C66C3860C67C00_000000001B1B1B1B1B7BDBDBDB7F0000; // 15() 14()
defparam rom0.INIT_0B = 256'h000000007E183C7E1818187E3C180000_00000000FEFEFEFE0000000000000000; // 17() 16()
defparam rom0.INIT_0C = 256'h00000000183C7E181818181818180000_00000000181818181818187E3C180000; // 19() 18()
defparam rom0.INIT_0D = 256'h0000000000003060FE60300000000000_000000000000180CFE0C180000000000; // 1b() 1a()
defparam rom0.INIT_0E = 256'h000000000000286CFE6C280000000000_000000000000FEC0C0C0000000000000; // 1d() 1c()
defparam rom0.INIT_0F = 256'h00000000001038387C7CFEFE00000000_0000000000FEFE7C7C38381000000000; // 1f() 1e()
defparam rom0.INIT_10 = 256'h000000001818001818183C3C3C180000_00000000000000000000000000000000; // 21(!) 20( )
defparam rom0.INIT_11 = 256'h000000006C6CFE6C6C6CFE6C6C000000_00000000000000000000002466666600; // 23(#) 22(")
defparam rom0.INIT_12 = 256'h0000000086C66030180CC6C200000000_000018187CC68606067CC0C2C67C1818; // 25(%) 24($)
defparam rom0.INIT_13 = 256'h00000000000000000000006030303000_0000000076CCCCCCDC76386C6C380000; // 27(') 26(&)
defparam rom0.INIT_14 = 256'h0000000030180C0C0C0C0C0C18300000_000000000C18303030303030180C0000; // 29()) 28(()
defparam rom0.INIT_15 = 256'h00000000000018187E18180000000000_000000000000663CFF3C660000000000; // 2b(+) 2a(*)
defparam rom0.INIT_16 = 256'h0000000000000000FE00000000000000_00000030181818000000000000000000; // 2d(-) 2c(,)
defparam rom0.INIT_17 = 256'h0000000080C06030180C060200000000_00000000181800000000000000000000; // 2f(/) 2e(.)
defparam rom0.INIT_18 = 256'h000000007E1818181818187838180000_00000000386CC6C6D6D6C6C66C380000; // 31(1) 30(0)
defparam rom0.INIT_19 = 256'h000000007CC60606063C0606C67C0000_00000000FEC6C06030180C06C67C0000; // 33(3) 32(2)
defparam rom0.INIT_1A = 256'h000000007CC6060606FCC0C0C0FE0000_000000001E0C0C0CFECC6C3C1C0C0000; // 35(5) 34(4)
defparam rom0.INIT_1B = 256'h0000000030303030180C0606C6FE0000_000000007CC6C6C6C6FCC0C060380000; // 37(7) 36(6)
defparam rom0.INIT_1C = 256'h00000000780C0606067EC6C6C67C0000_000000007CC6C6C6C67CC6C6C67C0000; // 39(9) 38(8)
defparam rom0.INIT_1D = 256'h00000000301818000000181800000000_00000000001818000000181800000000; // 3b(;) 3a(:)
defparam rom0.INIT_1E = 256'h000000000000007E00007E0000000000_00000000060C18306030180C06000000; // 3d(=) 3c(<)
defparam rom0.INIT_1F = 256'h000000001818001818180CC6C67C0000_000000006030180C060C183060000000; // 3f(?) 3e(>)
defparam rom0.INIT_20 = 256'h00000000C6C6C6C6FEC6C66C38100000_000000007CC0DCDEDEDEC6C67C000000; // 41(A) 40(@)
defparam rom0.INIT_21 = 256'h000000003C66C2C0C0C0C0C2663C0000_00000000FC666666667C666666FC0000; // 43(C) 42(B)
defparam rom0.INIT_22 = 256'h00000000FE6662606878686266FE0000_00000000F86C6666666666666CF80000; // 45(E) 44(D)
defparam rom0.INIT_23 = 256'h000000003A66C6C6DEC0C0C2663C0000_00000000F06060606878686266FE0000; // 47(G) 46(F)
defparam rom0.INIT_24 = 256'h000000003C18181818181818183C0000_00000000C6C6C6C6C6FEC6C6C6C60000; // 49(I) 48(H)
defparam rom0.INIT_25 = 256'h00000000E666666C78786C6666E60000_0000000078CCCCCC0C0C0C0C0C1E0000; // 4b(K) 4a(J)
defparam rom0.INIT_26 = 256'h00000000C6C6C6C6C6D6FEFEEEC60000_00000000FE6662606060606060F00000; // 4d(M) 4c(L)
defparam rom0.INIT_27 = 256'h000000007CC6C6C6C6C6C6C6C67C0000_00000000C6C6C6C6CEDEFEF6E6C60000; // 4f(O) 4e(N)
defparam rom0.INIT_28 = 256'h00000E0C7CDED6C6C6C6C6C6C67C0000_00000000F0606060607C666666FC0000; // 51(Q) 50(P)
defparam rom0.INIT_29 = 256'h000000007CC6C6060C3860C6C67C0000_00000000E66666666C7C666666FC0000; // 53(S) 52(R)
defparam rom0.INIT_2A = 256'h000000007CC6C6C6C6C6C6C6C6C60000_000000003C1818181818185A7E7E0000; // 55(U) 54(T)
defparam rom0.INIT_2B = 256'h000000006CEEFED6D6D6C6C6C6C60000_0000000010386CC6C6C6C6C6C6C60000; // 57(W) 56(V)
defparam rom0.INIT_2C = 256'h000000003C181818183C666666660000_00000000C6C66C7C38387C6CC6C60000; // 59(Y) 58(X)
defparam rom0.INIT_2D = 256'h000000003C30303030303030303C0000_00000000FEC6C26030180C86C6FE0000; // 5b([) 5a(Z)
defparam rom0.INIT_2E = 256'h000000003C0C0C0C0C0C0C0C0C3C0000_0000000002060E1C3870E0C080000000; // 5d(]) 5c(\)
defparam rom0.INIT_2F = 256'h0000FF00000000000000000000000000_000000000000000000000000C66C3810; // 5f(_) 5e(^)
defparam rom0.INIT_30 = 256'h0000000076CCCCCC7C0C780000000000_00000000000000000000000000183030; // 61(a) 60(`)
defparam rom0.INIT_31 = 256'h000000007CC6C0C0C0C67C0000000000_000000007C666666666C786060E00000; // 63(c) 62(b)
defparam rom0.INIT_32 = 256'h000000007CC6C0C0FEC67C0000000000_0000000076CCCCCCCC6C3C0C0C1C0000; // 65(e) 64(d)
defparam rom0.INIT_33 = 256'h0078CC0C7CCCCCCCCCCC760000000000_00000000F060606060F060646C380000; // 67(g) 66(f)
defparam rom0.INIT_34 = 256'h000000003C1818181818380018180000_00000000E666666666766C6060E00000; // 69(i) 68(h)
defparam rom0.INIT_35 = 256'h00000000E6666C78786C666060E00000_003C66660606060606060E0006060000; // 6b(k) 6a(j)
defparam rom0.INIT_36 = 256'h00000000C6D6D6D6D6FEEC0000000000_000000003C1818181818181818380000; // 6d(m) 6c(l)
defparam rom0.INIT_37 = 256'h000000007CC6C6C6C6C67C0000000000_00000000666666666666DC0000000000; // 6f(o) 6e(n)
defparam rom0.INIT_38 = 256'h001E0C0C7CCCCCCCCCCC760000000000_00F060607C6666666666DC0000000000; // 71(q) 70(p)
defparam rom0.INIT_39 = 256'h000000007CC60C3860C67C0000000000_00000000F06060606676DC0000000000; // 73(s) 72(r)
defparam rom0.INIT_3A = 256'h0000000076CCCCCCCCCCCC0000000000_000000001C3630303030FC3030100000; // 75(u) 74(t)
defparam rom0.INIT_3B = 256'h000000006CFED6D6D6C6C60000000000_00000000183C66666666660000000000; // 77(w) 76(v)
defparam rom0.INIT_3C = 256'h00F80C067EC6C6C6C6C6C60000000000_00000000C66C3838386CC60000000000; // 79(y) 78(x)
defparam rom0.INIT_3D = 256'h000000000E18181818701818180E0000_00000000FEC6603018CCFE0000000000; // 7b({) 7a(z)
defparam rom0.INIT_3E = 256'h0000000070181818180E181818700000_00000000181818181800181818180000; // 7d(}) 7c(|)
defparam rom0.INIT_3F = 256'h0000000000FEC6C6C66C381000000000_000000000000000000000000DC760000; // 7f() 7e(~)
 
defparam rom1.INIT_00 = 256'h0000000076CCCCCCCCCCCC0000CC0000_00007C060C3C66C2C0C0C0C2663C0000; // 81(�) 80(�)
defparam rom1.INIT_01 = 256'h0000000076CCCCCC7C0C78006C381000_000000007CC6C0C0FEC67C0030180C00; // 83(�) 82(�)
defparam rom1.INIT_02 = 256'h0000000076CCCCCC7C0C780018306000_0000000076CCCCCC7C0C780000CC0000; // 85(�) 84(�)
defparam rom1.INIT_03 = 256'h0000003C060C3C666060663C00000000_0000000076CCCCCC7C0C7800386C3800; // 87(�) 86(�)
defparam rom1.INIT_04 = 256'h000000007CC6C0C0FEC67C0000C60000_000000007CC6C0C0FEC67C006C381000; // 89(�) 88(�)
defparam rom1.INIT_05 = 256'h000000003C1818181818380000660000_000000007CC6C0C0FEC67C0018306000; // 8b(�) 8a(�)
defparam rom1.INIT_06 = 256'h000000003C1818181818380018306000_000000003C18181818183800663C1800; // 8d(�) 8c(�)
defparam rom1.INIT_07 = 256'h00000000C6C6C6FEC6C66C3800386C38_00000000C6C6C6FEC6C66C381000C600; // 8f(�) 8e(�)
defparam rom1.INIT_08 = 256'h000000006ED8D87E3676CC0000000000_00000000FE6660607C6066FE00603018; // 91(�) 90(�)
defparam rom1.INIT_09 = 256'h000000007CC6C6C6C6C67C006C381000_00000000CECCCCCCCCFECCCC6C3E0000; // 93(�) 92(�)
defparam rom1.INIT_0A = 256'h000000007CC6C6C6C6C67C0018306000_000000007CC6C6C6C6C67C0000C60000; // 95(�) 94(�)
defparam rom1.INIT_0B = 256'h0000000076CCCCCCCCCCCC0018306000_0000000076CCCCCCCCCCCC00CC783000; // 97(�) 96(�)
defparam rom1.INIT_0C = 256'h000000007CC6C6C6C6C6C6C67C00C600_00780C067EC6C6C6C6C6C60000C60000; // 99(�) 98(�)
defparam rom1.INIT_0D = 256'h0000000018183C66606060663C181800_000000007CC6C6C6C6C6C6C6C600C600; // 9b(�) 9a(�)
defparam rom1.INIT_0E = 256'h000000001818187E187E183C66660000_00000000FCE660606060F060646C3800; // 9d(�) 9c(�)
defparam rom1.INIT_0F = 256'h000070D818181818187E1818181B0E00_00000000C6CCCCCCDECCC4F8CCCCF800; // 9f(�) 9e(�)
defparam rom1.INIT_10 = 256'h000000003C1818181818380030180C00_0000000076CCCCCC7C0C780060301800; // a1(�) a0(�)
defparam rom1.INIT_11 = 256'h0000000076CCCCCCCCCCCC0060301800_000000007CC6C6C6C6C67C0060301800; // a3(�) a2(�)
defparam rom1.INIT_12 = 256'h00000000C6C6C6CEDEFEF6E6C600DC76_00000000666666666666DC00DC760000; // a5(�) a4(�)
defparam rom1.INIT_13 = 256'h0000000000000000007C00386C6C3800_0000000000000000007E003E6C6C3C00; // a7(�) a6(�)
defparam rom1.INIT_14 = 256'h0000000000C0C0C0C0FE000000000000_000000007CC6C6C06030300030300000; // a9(�) a8(�)
defparam rom1.INIT_15 = 256'h00003E180C86DC603018CCC6C2C0C000_000000000006060606FE000000000000; // ab(�) aa(�)
defparam rom1.INIT_16 = 256'h00000000183C3C3C1818180018180000_000006063E9ECE663018CCC6C2C0C000; // ad(�) ac(�)
defparam rom1.INIT_17 = 256'h000000000000D86C366CD80000000000_000000000000366CD86C360000000000; // af(�) ae(�)
defparam rom1.INIT_18 = 256'hAA55AA55AA55AA55AA55AA55AA55AA55_44114411441144114411441144114411; // b1(�) b0(�)
defparam rom1.INIT_19 = 256'h18181818181818181818181818181818_77DD77DD77DD77DD77DD77DD77DD77DD; // b3(�) b2(�)
defparam rom1.INIT_1A = 256'h1818181818181818F818F81818181818_1818181818181818F818181818181818; // b5(�) b4(�)
defparam rom1.INIT_1B = 256'h3636363636363636FE00000000000000_3636363636363636F636363636363636; // b7(�) b6(�)
defparam rom1.INIT_1C = 256'h3636363636363636F606F63636363636_1818181818181818F818F80000000000; // b9(�) b8(�)
defparam rom1.INIT_1D = 256'h3636363636363636F606FE0000000000_36363636363636363636363636363636; // bb(�) ba(�)
defparam rom1.INIT_1E = 256'h0000000000000000FE36363636363636_0000000000000000FE06F63636363636; // bd(�) bc(�)
defparam rom1.INIT_1F = 256'h1818181818181818F800000000000000_0000000000000000F818F81818181818; // bf(�) be(�)
defparam rom1.INIT_20 = 256'h0000000000000000FF18181818181818_00000000000000001F18181818181818; // c1(�) c0(�)
defparam rom1.INIT_21 = 256'h18181818181818181F18181818181818_1818181818181818FF00000000000000; // c3(�) c2(�)
defparam rom1.INIT_22 = 256'h1818181818181818FF18181818181818_0000000000000000FF00000000000000; // c5(�) c4(�)
defparam rom1.INIT_23 = 256'h36363636363636363736363636363636_18181818181818181F181F1818181818; // c7(�) c6(�)
defparam rom1.INIT_24 = 256'h363636363636363637303F0000000000_00000000000000003F30373636363636; // c9(�) c8(�)
defparam rom1.INIT_25 = 256'h3636363636363636F700FF0000000000_0000000000000000FF00F73636363636; // cb(�) ca(�)
defparam rom1.INIT_26 = 256'h0000000000000000FF00FF0000000000_36363636363636363730373636363636; // cd(�) cc(�)
defparam rom1.INIT_27 = 256'h0000000000000000FF00FF1818181818_3636363636363636F700F73636363636; // cf(�) ce(�)
defparam rom1.INIT_28 = 256'h1818181818181818FF00FF0000000000_0000000000000000FF36363636363636; // d1(�) d0(�)
defparam rom1.INIT_29 = 256'h00000000000000003F36363636363636_3636363636363636FF00000000000000; // d3(�) d2(�)
defparam rom1.INIT_2A = 256'h18181818181818181F181F0000000000_00000000000000001F181F1818181818; // d5(�) d4(�)
defparam rom1.INIT_2B = 256'h3636363636363636FF36363636363636_36363636363636363F00000000000000; // d7(�) d6(�)
defparam rom1.INIT_2C = 256'h0000000000000000F818181818181818_1818181818181818FF18FF1818181818; // d9(�) d8(�)
defparam rom1.INIT_2D = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF_18181818181818181F00000000000000; // db(�) da(�)
defparam rom1.INIT_2E = 256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0_FFFFFFFFFFFFFFFFFF00000000000000; // dd(�) dc(�)
defparam rom1.INIT_2F = 256'h000000000000000000FFFFFFFFFFFFFF_0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F; // df(�) de(�)
defparam rom1.INIT_30 = 256'h00000000CCC6C6C6CCD8CCCCCC780000_0000000076DCD8D8D8DC760000000000; // e1(�) e0(�)
defparam rom1.INIT_31 = 256'h000000006C6C6C6C6C6C6CFE00000000_00000000C0C0C0C0C0C0C0C6C6FE0000; // e3(�) e2(�)
defparam rom1.INIT_32 = 256'h0000000070D8D8D8D8D87E0000000000_00000000FEC66030183060C6FE000000; // e5(�) e4(�)
defparam rom1.INIT_33 = 256'h00000000181818181818DC7600000000_000000C060607C666666666600000000; // e7(�) e6(�)
defparam rom1.INIT_34 = 256'h00000000386CC6C6FEC6C66C38000000_000000007E183C6666663C187E000000; // e9(�) e8(�)
defparam rom1.INIT_35 = 256'h000000003C666666663E0C18301E0000_00000000EE6C6C6C6CC6C6C66C380000; // eb(�) ea(�)
defparam rom1.INIT_36 = 256'h00000000C0607EF3DBDB7E0603000000_0000000000007EDBDBDB7E0000000000; // ed(�) ec(�)
defparam rom1.INIT_37 = 256'h00000000C6C6C6C6C6C6C6C67C000000_000000001C306060607C6060301C0000; // ef(�) ee(�)
defparam rom1.INIT_38 = 256'h00000000FF000018187E181800000000_0000000000FE0000FE0000FE00000000; // f1(�) f0(�)
defparam rom1.INIT_39 = 256'h000000007E000C18306030180C000000_000000007E0030180C060C1830000000; // f3(�) f2(�)
defparam rom1.INIT_3A = 256'h0000000070D8D8D81818181818181818_18181818181818181818181B1B0E0000; // f5(�) f4(�)
defparam rom1.INIT_3B = 256'h000000000000DC7600DC760000000000_00000000001818007E00181800000000; // f7(�) f6(�)
defparam rom1.INIT_3C = 256'h00000000000000181800000000000000_0000000000000000000000386C6C3800; // f9(�) f8(�)
defparam rom1.INIT_3D = 256'h000000001C3C6C6CEC0C0C0C0C0C0F00_00000000000000180000000000000000; // fb(�) fa(�)
defparam rom1.INIT_3E = 256'h000000000000000000F8C86030D87000_0000000000000000006C6C6C6C6CD800; // fd(�) fc(�)
defparam rom1.INIT_3F = 256'h00000000000000000000000000000000_00000000007C7C7C7C7C7C7C00000000; // ff(�) fe(�)
 
// Assignments
assign rdata = addr[11] ? rdata1 : rdata0;
endmodule
/trunk/soc/vga/ram2k_b16.v
0,0 → 1,29
`timescale 1ns/10ps
 
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp;
 
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
 
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
 
endmodule
/trunk/sim/testbench.v
3,54 → 3,71
module testbench;
 
// Net declarations
wire [15:0] rd_data;
wire [15:0] wr_data, mem_data, io_data;
wire [19:0] addr;
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire m_io;
wire byte_m;
wire ack_i;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
 
reg clk, rst;
reg [15:0] io_reg;
reg [ 1:0] ack;
reg clk;
reg rst;
 
reg [15:0] io_reg;
 
// Module instantiations
memory mem0 (clk, addr, wr_data, mem_data, stb & we & ~m_io, byte_m);
memory mem0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (mem_dat_i),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb & !tga),
.wb_cyc_i (cyc & !tga),
.wb_ack_o (mem_ack)
);
 
cpu cpu0 (
.clk_i (clk),
.rst_i (rst),
.dat_i (rd_data),
.dat_o (wr_data),
.adr_o (addr),
.we_o (we),
.mio_o (m_io),
.byte_o (byte_m),
.stb_o (stb),
.ack_i (ack_i)
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack)
);
 
// Assignments
assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
assign rd_data = m_io ? io_data : mem_data;
assign ack_i = (ack==2'b10);
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = tga ? io_dat_i : mem_dat_i;
 
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
 
// Behaviour
// IO Stub
always @(posedge clk)
if (addr==20'hb7 & we & m_io)
io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data;
always @(posedge clk)
if (adr[15:1]==15'h5b && sel[1] && cyc && stb)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15'h5c & sel[0] && cyc && stb)
io_reg[15:8] <= dat_o[7:0];
 
always #1 clk = ~clk;
always #2.13 ack = ack + 2'd1;
 
initial
begin
clk <= 1'b1;
rst <= 1'b0;
ack <= 2'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
end
/trunk/sim/modelsim/tb.do
21,14 → 21,26
add wave -label ir /testbench/cpu0/fetch0/ir
add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
add wave -divider mem
add wave -label cs -radix hexadecimal /testbench/cpu0/wm0/cs
add wave -label op -radix hexadecimal /testbench/cpu0/wm0/op
add wave -label block /testbench/cpu0/wm0/cpu_block
add wave -label dat_o -radix hexadecimal sim:/testbench/dat_o
add wave -label dat_i -radix hexadecimal sim:/testbench/dat_i
add wave -label adr -radix hexadecimal /testbench/adr
add wave -label byte_o -radix hexadecimal /cpu0/wm0/cpu_byte_o
add wave -label sel_o -radix hexadecimal /cpu0/wm0/wb_sel_o
add wave -label stb_o -radix hexadecimal /cpu0/wm0/wb_stb_o
add wave -label cyc_o -radix hexadecimal /cpu0/wm0/wb_cyc_o
add wave -label ack_i -radix hexadecimal /cpu0/wm0/wb_ack_i
add wave -label we_o -radix hexadecimal /cpu0/wm0/wb_we_o
add wave -label tga_o -radix hexadecimal /cpu0/wm0/wb_tga_o
add wave -label cpu_dat_i -radix hexadecimal /cpu0/wm0/cpu_dat_i
add wave -divider alu
add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
add wave -label addr -radix hexadecimal /testbench/addr
add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
35,8 → 47,6
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
add wave -label wr /testbench/cpu0/exec0/reg0/wr
add wave -label we /testbench/we
add wave -label ack_i /testbench/ack_i
add wave -label ack /testbench/ack
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
add wave -divider mul
add wave -radix hexadecimal -r /testbench/cpu0/exec0/alu0/mul3/dut/*
#run 50us
run 15us
/trunk/sim/memory.v
1,28 → 1,39
`timescale 1ns/10ps
 
module memory (
input clk,
input [19:0] addr,
input [15:0] wr_data,
output [15:0] rd_data,
input we,
input byte_m
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o
);
 
// Registers and nets
wire [19:0] addr1;
reg [15:0] ram[2**19-1:0];
 
reg [7:0] ram[2**20-1:0];
wire we;
wire [7:0] bhw, blw;
 
// Assignments
assign rd_data = byte_m ? { {8{ram[addr][7]}}, ram[addr]}
: {ram[addr1], ram[addr]};
assign addr1 = addr + 20'd1;
assign wb_dat_o = ram[wb_adr_i];
assign wb_ack_o = wb_stb_i;
assign we = wb_we_i & wb_stb_i & wb_cyc_i;
 
assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
: ram[wb_adr_i][15:8];
assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
: ram[wb_adr_i][7:0];
 
// Behaviour
always @(posedge clk)
if (we) if (byte_m) ram[addr] <= wr_data[7:0];
else { ram[addr1], ram[addr] } <= wr_data;
always @(posedge wb_clk_i)
if (we) ram[wb_adr_i] <= { bhw, blw };
 
initial $readmemh("/home/zeus/zet/sim/data.rtlrom", ram, 20'hf0000);
initial $readmemh("/home/zeus/zet/sim/data.rtlrom",
ram, 19'h78000);
endmodule

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