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URL https://opencores.org/ocsvn/zet86/zet86/trunk

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  • This comparison shows the changes necessary to convert path 
    /zet86/trunk/soc
    from Rev 52 to Rev 53
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  •

Rev 52 → Rev 53

/aceusb/rtl/aceusb.v
111,13 → 111,12
 
/* Main FSM */
 
reg [1:0] state;
reg [1:0] next_state;
reg state;
reg next_state;
 
localparam
IDLE = 2'd0,
WAIT = 2'd1,
ACK = 2'd2;
IDLE = 1'd0,
WAIT = 1'd1;
 
assign op = wb_cyc_i & wb_stb_i;
 
154,13 → 153,6
access_write = 1'b0;
load_adr_dat = 1'b0;
access_read = 1'b0;
next_state = ACK;
end
end
 
ACK: begin
if(!op) begin
wb_ack_o = 1'b0;
next_state = IDLE;
end
end
/vga/rtl/vdu.v
30,7 → 30,7
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
output wb_ack_o,
 
// VGA pad signals
output reg [ 1:0] vga_red_o,
106,7 → 106,7
reg [6:0] hor_addr; // 0 to 79
reg [6:0] ver_addr; // 0 to 124
reg vga0_we;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw, vga5_rw;
reg vga1_we;
reg vga2_we;
reg buff_we;
193,9 → 193,9
assign v_retrace = !video_on_v;
assign vh_retrace = v_retrace | !video_on_h;
assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace };
assign wb_ack_o = wb_tga_i ? stb : vga5_rw;
 
// Behaviour
 
// CPU write interface
always @(posedge wb_clk_i)
if (wb_rst_i)
221,23 → 221,10
end
 
// CPU read interface
// wb_dat_o
always @(posedge wb_clk_i)
if (wb_rst_i)
begin
wb_dat_o <= 16'h0;
wb_ack_o <= 16'h0;
end
else
if (wb_tga_i)
begin
wb_dat_o <= status_reg1;
wb_ack_o <= stb;
end
else
begin
wb_dat_o <= vga4_rw ? out_data : wb_dat_o;
wb_ack_o <= vga4_rw ? 1'b1 : (wb_ack_o && stb);
end
wb_dat_o <= wb_rst_i ? 16'h0 : (wb_tga_i ? status_reg1
: (vga4_rw ? out_data : wb_dat_o));
 
// Control registers
always @(posedge wb_clk_i)
313,6 → 300,7
vga2_rw <= 1'b0;
vga3_rw <= 1'b0;
vga4_rw <= 1'b0;
vga5_rw <= 1'b0;
ver_addr <= 7'b0;
hor_addr <= 7'b0;
 
363,6 → 351,7
attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0;
vga3_rw <= vga2_rw;
vga4_rw <= vga3_rw;
vga5_rw <= vga4_rw;
end
 
// Video shift register

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