OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

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  • This comparison shows the changes necessary to convert path 
    /zet86/trunk
    from Rev 49 to Rev 52
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  •

Rev 49 → Rev 52

/rtl-model/fetch.v
283,6 → 283,7
wire [1:0] seg;
reg [`SEQ_ADDR_WIDTH-1:0] seq;
reg dive;
reg old_ext_int;
 
// Module instantiations
opcode_deco opcode_deco0 (opcode, modrm, rep, sop_l, base_addr, need_modrm,
316,10 → 317,12
: ((intr & ifl & exec_st & end_seq) ? 1'b1
: (ext_int ? !end_seq : 1'b0));
 
// old_ext_int
always @(posedge clk) old_ext_int <= rst ? 1'b0 : ext_int;
 
// inta
always @(posedge clk)
if (rst) inta <= 1'b0;
else inta <= intr & ext_int;
inta <= rst ? 1'b0 : (!old_ext_int & ext_int);
 
endmodule
 
917,19 → 920,8
dst <= { 1'b0, rm };
end
 
8'b1001_0000: // 90h: nop
8'b1001_0xxx: // nop, xchg acum
begin
seq_addr <= `NOP;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
imm_size <= 1'b0;
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1001_0xxx: // xchg acum
begin
seq_addr <= `XCHRRW;
need_modrm <= 1'b0;
need_off <= 1'b0;
/rtl-model/util/div_uu.v
34,16 → 34,16
 
// CVS Log
//
// $Id: div_uu.v,v 1.7 2009-02-06 03:48:26 zeus Exp $
// $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
//
// $Date: 2009-02-06 03:48:26 $
// $Revision: 1.7 $
// $Author: zeus $
// $Date: 2003/09/17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// $Log: div_uu.v,v $
// Revision 1.3 2003/09/17 13:08:53 rherveille
// Fixed a bug in the remainder output. Changed a hard value into the required parameter.
// Fixed a bug in the testbench.
/rtl-model/util/div_su.v
35,16 → 35,16
 
// CVS Log
//
// $Id: div_su.v,v 1.7 2009-02-06 03:48:26 zeus Exp $
// $Id: div_su.v,v 1.2 2002/10/31 13:54:58 rherveille Exp $
//
// $Date: 2009-02-06 03:48:26 $
// $Revision: 1.7 $
// $Author: zeus $
// $Date: 2002/10/31 13:54:58 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// $Log: div_su.v,v $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
/impl/virtex4-ml403ep/test/base.cpj
1,7 → 1,7
#ChipScope Pro Analyzer Project File, Version 3.0
#Wed Mar 04 02:05:54 GMT+01:00 2009
#Wed Mar 11 23:37:50 GMT+01:00 2009
device.2.configFileDir=/home/zeus/tmp
device.2.configFilename=kotku_ml403-debug.bit
device.2.configFilename=kotku_ml403.bit
deviceChain.deviceName0=System_ACE_CF
deviceChain.deviceName1=XCF32P
deviceChain.deviceName2=XC4VFX12
15,8 → 15,8
deviceChain.name2=MyDevice2
deviceChain.name3=MyDevice3
deviceIds=0a001093f505909321e5809359608093
mdiAreaHeight=0.7659574468085106
mdiAreaHeightLast=0.7659574468085106
mdiAreaHeight=0.828042328042328
mdiAreaHeightLast=0.828042328042328
mdiCount=2
mdiDevice0=2
mdiDevice1=2
24,20 → 24,20
mdiType1=0
mdiUnit0=0
mdiUnit1=0
navigatorHeight=0.4295212765957447
navigatorHeightLast=0.1595744680851064
navigatorWidth=0.09765625
navigatorWidthLast=0.1515625
navigatorHeight=0.42724867724867727
navigatorHeightLast=0.15873015873015872
navigatorWidth=0.17054263565891473
navigatorWidthLast=0.11937984496124031
unit.-1.-1.username=
unit.1.-1.username=
unit.2.-1.username=
unit.2.0.0.HEIGHT0=0.91797554
unit.2.0.0.HEIGHT0=0.7977528
unit.2.0.0.TriggerRow0=1
unit.2.0.0.TriggerRow1=1
unit.2.0.0.TriggerRow2=1
unit.2.0.0.WIDTH0=0.8658429
unit.2.0.0.X0=0.0
unit.2.0.0.Y0=0.0
unit.2.0.0.WIDTH0=0.58587784
unit.2.0.0.X0=0.2509542
unit.2.0.0.Y0=0.072231136
unit.2.0.1.HEIGHT1=1.0
unit.2.0.1.WIDTH1=1.0
unit.2.0.1.X1=0.0
46,15 → 46,15
unit.2.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA10=XXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA11=XXXXXXXXXXXXXXXX
unit.2.0.MFBitsA12=XXXXXXXXX
unit.2.0.MFBitsA12=XXXXXX1XX
unit.2.0.MFBitsA13=XXX
unit.2.0.MFBitsA14=XXXXX
unit.2.0.MFBitsA15=01001011111111111001100110000000
unit.2.0.MFBitsA2=00000000001111100000
unit.2.0.MFBitsA15=00000000001100011111001000000000
unit.2.0.MFBitsA2=11100001100101111111
unit.2.0.MFBitsA3=X1XX1X
unit.2.0.MFBitsA4=XXXXXX
unit.2.0.MFBitsA5=XXX000
unit.2.0.MFBitsA6=XXXXXXXXXXX1XXXX
unit.2.0.MFBitsA6=XXXXXXXXXXXXXX1X
unit.2.0.MFBitsA7=XXXXXXXXXXXXXXXX
unit.2.0.MFBitsA8=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA9=XXXXXXXXXXXXXXXX
144,7 → 144,7
unit.2.0.SequencerOn=0
unit.2.0.TCActive=0
unit.2.0.TCAdvanced0=0
unit.2.0.TCCondition0_0=M2
unit.2.0.TCCondition0_0=M12
unit.2.0.TCCondition0_1=
unit.2.0.TCConditionType0=0
unit.2.0.TCCount=1
198,8 → 198,8
unit.2.0.export.format=2
unit.2.0.export.signals=Waveform Signals/Buses
unit.2.0.export.unitName=DEV\:2 MyDevice2 (XC4VFX12) UNIT\:0 MyILA0 (ILA)
unit.2.0.port.-1.b.0.alias=addr_d
unit.2.0.port.-1.b.0.channellist=90 91 92 93
unit.2.0.port.-1.b.0.alias=aceusb_d_
unit.2.0.port.-1.b.0.channellist=191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
unit.2.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.0.name=DataPort
unit.2.0.port.-1.b.0.orderindex=-1
212,8 → 212,8
unit.2.0.port.-1.b.0.unsignedPrecision=0
unit.2.0.port.-1.b.0.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.0.visible=1
unit.2.0.port.-1.b.1.alias=adr
unit.2.0.port.-1.b.1.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
unit.2.0.port.-1.b.1.alias=ace_dat_o
unit.2.0.port.-1.b.1.channellist=170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
unit.2.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.1.name=DataPort
unit.2.0.port.-1.b.1.orderindex=-1
226,8 → 226,8
unit.2.0.port.-1.b.1.unsignedPrecision=0
unit.2.0.port.-1.b.1.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.1.visible=1
unit.2.0.port.-1.b.10.alias=next_state
unit.2.0.port.-1.b.10.channellist=84 85 86
unit.2.0.port.-1.b.10.alias=flags
unit.2.0.port.-1.b.10.channellist=95 96 97 98 99 100 101 102 103
unit.2.0.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.10.name=DataPort
unit.2.0.port.-1.b.10.orderindex=-1
240,9 → 240,9
unit.2.0.port.-1.b.10.unsignedPrecision=0
unit.2.0.port.-1.b.10.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.10.visible=1
unit.2.0.port.-1.b.11.alias=pc
unit.2.0.port.-1.b.11.channellist=52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
unit.2.0.port.-1.b.11.color=java.awt.Color[r\=204,g\=0,b\=51]
unit.2.0.port.-1.b.11.alias=func
unit.2.0.port.-1.b.11.channellist=81 82 83
unit.2.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.11.name=DataPort
unit.2.0.port.-1.b.11.orderindex=-1
unit.2.0.port.-1.b.11.radix=Hex
254,9 → 254,9
unit.2.0.port.-1.b.11.unsignedPrecision=0
unit.2.0.port.-1.b.11.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.11.visible=1
unit.2.0.port.-1.b.12.alias=state
unit.2.0.port.-1.b.12.channellist=87 88 89
unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=51,b\=204]
unit.2.0.port.-1.b.12.alias=next_state
unit.2.0.port.-1.b.12.channellist=84 85 86
unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.12.name=DataPort
unit.2.0.port.-1.b.12.orderindex=-1
unit.2.0.port.-1.b.12.radix=Hex
268,9 → 268,9
unit.2.0.port.-1.b.12.unsignedPrecision=0
unit.2.0.port.-1.b.12.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.12.visible=1
unit.2.0.port.-1.b.13.alias=s_addr_
unit.2.0.port.-1.b.13.channellist=170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
unit.2.0.port.-1.b.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.13.alias=pc
unit.2.0.port.-1.b.13.channellist=52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
unit.2.0.port.-1.b.13.color=java.awt.Color[r\=204,g\=0,b\=51]
unit.2.0.port.-1.b.13.name=DataPort
unit.2.0.port.-1.b.13.orderindex=-1
unit.2.0.port.-1.b.13.radix=Hex
282,9 → 282,9
unit.2.0.port.-1.b.13.unsignedPrecision=0
unit.2.0.port.-1.b.13.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.13.visible=1
unit.2.0.port.-1.b.14.alias=s_bw_
unit.2.0.port.-1.b.14.channellist=210 211 212 213
unit.2.0.port.-1.b.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.14.alias=state
unit.2.0.port.-1.b.14.channellist=87 88 89
unit.2.0.port.-1.b.14.color=java.awt.Color[r\=0,g\=51,b\=204]
unit.2.0.port.-1.b.14.name=DataPort
unit.2.0.port.-1.b.14.orderindex=-1
unit.2.0.port.-1.b.14.radix=Hex
296,8 → 296,8
unit.2.0.port.-1.b.14.unsignedPrecision=0
unit.2.0.port.-1.b.14.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.14.visible=1
unit.2.0.port.-1.b.15.alias=s_data_
unit.2.0.port.-1.b.15.channellist=191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
unit.2.0.port.-1.b.15.alias=t
unit.2.0.port.-1.b.15.channellist=78 79 80
unit.2.0.port.-1.b.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.15.name=DataPort
unit.2.0.port.-1.b.15.orderindex=-1
310,8 → 310,8
unit.2.0.port.-1.b.15.unsignedPrecision=0
unit.2.0.port.-1.b.15.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.15.visible=1
unit.2.0.port.-1.b.16.alias=t
unit.2.0.port.-1.b.16.channellist=78 79 80
unit.2.0.port.-1.b.16.alias=x
unit.2.0.port.-1.b.16.channellist=138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
unit.2.0.port.-1.b.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.16.name=DataPort
unit.2.0.port.-1.b.16.orderindex=-1
324,8 → 324,8
unit.2.0.port.-1.b.16.unsignedPrecision=0
unit.2.0.port.-1.b.16.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.16.visible=1
unit.2.0.port.-1.b.17.alias=x
unit.2.0.port.-1.b.17.channellist=138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
unit.2.0.port.-1.b.17.alias=y
unit.2.0.port.-1.b.17.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
unit.2.0.port.-1.b.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.17.name=DataPort
unit.2.0.port.-1.b.17.orderindex=-1
366,8 → 366,8
unit.2.0.port.-1.b.19.unsignedPrecision=0
unit.2.0.port.-1.b.19.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.19.visible=1
unit.2.0.port.-1.b.2.alias=aluo
unit.2.0.port.-1.b.2.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
unit.2.0.port.-1.b.2.alias=addr_d
unit.2.0.port.-1.b.2.channellist=90 91 92 93
unit.2.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.2.name=DataPort
unit.2.0.port.-1.b.2.orderindex=-1
380,8 → 380,8
unit.2.0.port.-1.b.2.unsignedPrecision=0
unit.2.0.port.-1.b.2.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.2.visible=1
unit.2.0.port.-1.b.3.alias=cnt
unit.2.0.port.-1.b.3.channellist=216 217 218
unit.2.0.port.-1.b.3.alias=adr
unit.2.0.port.-1.b.3.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
unit.2.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.3.name=DataPort
unit.2.0.port.-1.b.3.orderindex=-1
394,8 → 394,8
unit.2.0.port.-1.b.3.unsignedPrecision=0
unit.2.0.port.-1.b.3.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.3.visible=1
unit.2.0.port.-1.b.4.alias=cnt_time
unit.2.0.port.-1.b.4.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
unit.2.0.port.-1.b.4.alias=aluo
unit.2.0.port.-1.b.4.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
unit.2.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.4.name=DataPort
unit.2.0.port.-1.b.4.orderindex=-1
408,8 → 408,8
unit.2.0.port.-1.b.4.unsignedPrecision=0
unit.2.0.port.-1.b.4.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.4.visible=1
unit.2.0.port.-1.b.5.alias=d
unit.2.0.port.-1.b.5.channellist=106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
unit.2.0.port.-1.b.5.alias=cnt
unit.2.0.port.-1.b.5.channellist=216 217 218
unit.2.0.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.5.name=DataPort
unit.2.0.port.-1.b.5.orderindex=-1
422,8 → 422,8
unit.2.0.port.-1.b.5.unsignedPrecision=0
unit.2.0.port.-1.b.5.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.5.visible=1
unit.2.0.port.-1.b.6.alias=dat_i
unit.2.0.port.-1.b.6.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
unit.2.0.port.-1.b.6.alias=cnt_time
unit.2.0.port.-1.b.6.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
unit.2.0.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.6.name=DataPort
unit.2.0.port.-1.b.6.orderindex=-1
436,8 → 436,8
unit.2.0.port.-1.b.6.unsignedPrecision=0
unit.2.0.port.-1.b.6.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.6.visible=1
unit.2.0.port.-1.b.7.alias=dat_o
unit.2.0.port.-1.b.7.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
unit.2.0.port.-1.b.7.alias=d
unit.2.0.port.-1.b.7.channellist=106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
unit.2.0.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.7.name=DataPort
unit.2.0.port.-1.b.7.orderindex=-1
450,8 → 450,8
unit.2.0.port.-1.b.7.unsignedPrecision=0
unit.2.0.port.-1.b.7.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.7.visible=1
unit.2.0.port.-1.b.8.alias=flags
unit.2.0.port.-1.b.8.channellist=95 96 97 98 99 100 101 102 103
unit.2.0.port.-1.b.8.alias=dat_i
unit.2.0.port.-1.b.8.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
unit.2.0.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.8.name=DataPort
unit.2.0.port.-1.b.8.orderindex=-1
464,8 → 464,8
unit.2.0.port.-1.b.8.unsignedPrecision=0
unit.2.0.port.-1.b.8.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.8.visible=1
unit.2.0.port.-1.b.9.alias=func
unit.2.0.port.-1.b.9.channellist=81 82 83
unit.2.0.port.-1.b.9.alias=dat_o
unit.2.0.port.-1.b.9.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
unit.2.0.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.9.name=DataPort
unit.2.0.port.-1.b.9.orderindex=-1
478,7 → 478,7
unit.2.0.port.-1.b.9.unsignedPrecision=0
unit.2.0.port.-1.b.9.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.9.visible=1
unit.2.0.port.-1.buscount=19
unit.2.0.port.-1.buscount=18
unit.2.0.port.-1.channelcount=256
unit.2.0.port.-1.s.0.alias=
unit.2.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
965,22 → 965,22
unit.2.0.port.-1.s.185.name=DataPort[185]
unit.2.0.port.-1.s.185.orderindex=-1
unit.2.0.port.-1.s.185.visible=1
unit.2.0.port.-1.s.186.alias=
unit.2.0.port.-1.s.186.alias=ace_stb
unit.2.0.port.-1.s.186.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.186.name=DataPort[186]
unit.2.0.port.-1.s.186.orderindex=-1
unit.2.0.port.-1.s.186.visible=1
unit.2.0.port.-1.s.187.alias=
unit.2.0.port.-1.s.187.alias=ace_ack
unit.2.0.port.-1.s.187.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.187.name=DataPort[187]
unit.2.0.port.-1.s.187.orderindex=-1
unit.2.0.port.-1.s.187.visible=1
unit.2.0.port.-1.s.188.alias=
unit.2.0.port.-1.s.188.alias=aceusb_oe_n_
unit.2.0.port.-1.s.188.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.188.name=DataPort[188]
unit.2.0.port.-1.s.188.orderindex=-1
unit.2.0.port.-1.s.188.visible=1
unit.2.0.port.-1.s.189.alias=
unit.2.0.port.-1.s.189.alias=aceusb_we_n
unit.2.0.port.-1.s.189.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.189.name=DataPort[189]
unit.2.0.port.-1.s.189.orderindex=-1
990,7 → 990,7
unit.2.0.port.-1.s.19.name=DataPort[19]
unit.2.0.port.-1.s.19.orderindex=-1
unit.2.0.port.-1.s.19.visible=1
unit.2.0.port.-1.s.190.alias=
unit.2.0.port.-1.s.190.alias=ace_mpce_n_
unit.2.0.port.-1.s.190.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.190.name=DataPort[190]
unit.2.0.port.-1.s.190.orderindex=-1
1085,17 → 1085,17
unit.2.0.port.-1.s.206.name=DataPort[206]
unit.2.0.port.-1.s.206.orderindex=-1
unit.2.0.port.-1.s.206.visible=1
unit.2.0.port.-1.s.207.alias=flash_ce2_
unit.2.0.port.-1.s.207.alias=iid
unit.2.0.port.-1.s.207.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.207.name=DataPort[207]
unit.2.0.port.-1.s.207.orderindex=-1
unit.2.0.port.-1.s.207.visible=1
unit.2.0.port.-1.s.208.alias=sram_adv_
unit.2.0.port.-1.s.208.alias=irr0
unit.2.0.port.-1.s.208.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.208.name=DataPort[208]
unit.2.0.port.-1.s.208.orderindex=-1
unit.2.0.port.-1.s.208.visible=1
unit.2.0.port.-1.s.209.alias=sram_cen_
unit.2.0.port.-1.s.209.alias=irr1
unit.2.0.port.-1.s.209.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.209.name=DataPort[209]
unit.2.0.port.-1.s.209.orderindex=-1
1105,32 → 1105,32
unit.2.0.port.-1.s.21.name=DataPort[21]
unit.2.0.port.-1.s.21.orderindex=-1
unit.2.0.port.-1.s.21.visible=1
unit.2.0.port.-1.s.210.alias=
unit.2.0.port.-1.s.210.alias=int0
unit.2.0.port.-1.s.210.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.210.name=DataPort[210]
unit.2.0.port.-1.s.210.orderindex=-1
unit.2.0.port.-1.s.210.visible=1
unit.2.0.port.-1.s.211.alias=
unit.2.0.port.-1.s.211.alias=int1
unit.2.0.port.-1.s.211.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.211.name=DataPort[211]
unit.2.0.port.-1.s.211.orderindex=-1
unit.2.0.port.-1.s.211.visible=1
unit.2.0.port.-1.s.212.alias=
unit.2.0.port.-1.s.212.alias=released
unit.2.0.port.-1.s.212.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.212.name=DataPort[212]
unit.2.0.port.-1.s.212.orderindex=-1
unit.2.0.port.-1.s.212.visible=1
unit.2.0.port.-1.s.213.alias=
unit.2.0.port.-1.s.213.alias=rx_shift
unit.2.0.port.-1.s.213.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.213.name=DataPort[213]
unit.2.0.port.-1.s.213.orderindex=-1
unit.2.0.port.-1.s.213.visible=1
unit.2.0.port.-1.s.214.alias=sf_we_
unit.2.0.port.-1.s.214.alias=rx_output
unit.2.0.port.-1.s.214.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.214.name=DataPort[214]
unit.2.0.port.-1.s.214.orderindex=-1
unit.2.0.port.-1.s.214.visible=1
unit.2.0.port.-1.s.215.alias=sf_oe_
unit.2.0.port.-1.s.215.alias=nada
unit.2.0.port.-1.s.215.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.215.name=DataPort[215]
unit.2.0.port.-1.s.215.orderindex=-1
2105,22 → 2105,22
unit.2.0.port.10.s.15.name=TriggerPort10[15]
unit.2.0.port.10.s.15.orderindex=-1
unit.2.0.port.10.s.15.visible=1
unit.2.0.port.10.s.16.alias=
unit.2.0.port.10.s.16.alias=ace_stb
unit.2.0.port.10.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.10.s.16.name=TriggerPort10[16]
unit.2.0.port.10.s.16.orderindex=-1
unit.2.0.port.10.s.16.visible=1
unit.2.0.port.10.s.17.alias=
unit.2.0.port.10.s.17.alias=ace_ack
unit.2.0.port.10.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.10.s.17.name=TriggerPort10[17]
unit.2.0.port.10.s.17.orderindex=-1
unit.2.0.port.10.s.17.visible=1
unit.2.0.port.10.s.18.alias=
unit.2.0.port.10.s.18.alias=aceusb_oe_n_
unit.2.0.port.10.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.10.s.18.name=TriggerPort10[18]
unit.2.0.port.10.s.18.orderindex=-1
unit.2.0.port.10.s.18.visible=1
unit.2.0.port.10.s.19.alias=
unit.2.0.port.10.s.19.alias=aceusb_we_n
unit.2.0.port.10.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.10.s.19.name=TriggerPort10[19]
unit.2.0.port.10.s.19.orderindex=-1
2130,7 → 2130,7
unit.2.0.port.10.s.2.name=TriggerPort10[2]
unit.2.0.port.10.s.2.orderindex=-1
unit.2.0.port.10.s.2.visible=1
unit.2.0.port.10.s.20.alias=
unit.2.0.port.10.s.20.alias=ace_mpce_n_
unit.2.0.port.10.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.10.s.20.name=TriggerPort10[20]
unit.2.0.port.10.s.20.orderindex=-1
2185,7 → 2185,7
unit.2.0.port.11.b.0.visible=1
unit.2.0.port.11.buscount=1
unit.2.0.port.11.channelcount=16
unit.2.0.port.11.s.0.alias=
unit.2.0.port.11.s.0.alias=DataPort[191]
unit.2.0.port.11.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.11.s.0.name=TriggerPort11[0]
unit.2.0.port.11.s.0.orderindex=-1
2280,47 → 2280,47
unit.2.0.port.12.b.0.visible=1
unit.2.0.port.12.buscount=1
unit.2.0.port.12.channelcount=9
unit.2.0.port.12.s.0.alias=flash_ce2_
unit.2.0.port.12.s.0.alias=iid
unit.2.0.port.12.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.0.name=TriggerPort12[0]
unit.2.0.port.12.s.0.orderindex=-1
unit.2.0.port.12.s.0.visible=1
unit.2.0.port.12.s.1.alias=sram_adv_
unit.2.0.port.12.s.1.alias=irr0
unit.2.0.port.12.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.1.name=TriggerPort12[1]
unit.2.0.port.12.s.1.orderindex=-1
unit.2.0.port.12.s.1.visible=1
unit.2.0.port.12.s.2.alias=sram_cen_
unit.2.0.port.12.s.2.alias=irr1
unit.2.0.port.12.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.2.name=TriggerPort12[2]
unit.2.0.port.12.s.2.orderindex=-1
unit.2.0.port.12.s.2.visible=1
unit.2.0.port.12.s.3.alias=DataPort[210]
unit.2.0.port.12.s.3.alias=int0
unit.2.0.port.12.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.3.name=TriggerPort12[3]
unit.2.0.port.12.s.3.orderindex=-1
unit.2.0.port.12.s.3.visible=1
unit.2.0.port.12.s.4.alias=
unit.2.0.port.12.s.4.alias=int1
unit.2.0.port.12.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.4.name=TriggerPort12[4]
unit.2.0.port.12.s.4.orderindex=-1
unit.2.0.port.12.s.4.visible=1
unit.2.0.port.12.s.5.alias=
unit.2.0.port.12.s.5.alias=released
unit.2.0.port.12.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.5.name=TriggerPort12[5]
unit.2.0.port.12.s.5.orderindex=-1
unit.2.0.port.12.s.5.visible=1
unit.2.0.port.12.s.6.alias=
unit.2.0.port.12.s.6.alias=rx_shift
unit.2.0.port.12.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.6.name=TriggerPort12[6]
unit.2.0.port.12.s.6.orderindex=-1
unit.2.0.port.12.s.6.visible=1
unit.2.0.port.12.s.7.alias=sf_we_
unit.2.0.port.12.s.7.alias=rx_output
unit.2.0.port.12.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.7.name=TriggerPort12[7]
unit.2.0.port.12.s.7.orderindex=-1
unit.2.0.port.12.s.7.visible=1
unit.2.0.port.12.s.8.alias=sf_oe_
unit.2.0.port.12.s.8.alias=nada
unit.2.0.port.12.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.12.s.8.name=TriggerPort12[8]
unit.2.0.port.12.s.8.orderindex=-1
2340,7 → 2340,7
unit.2.0.port.13.b.0.visible=1
unit.2.0.port.13.buscount=1
unit.2.0.port.13.channelcount=3
unit.2.0.port.13.s.0.alias=
unit.2.0.port.13.s.0.alias=DataPort[216]
unit.2.0.port.13.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.13.s.0.name=TriggerPort13[0]
unit.2.0.port.13.s.0.orderindex=-1
3419,7 → 3419,7
unit.2.0.triggerWindowDepth=1024
unit.2.0.triggerWindowTS=0
unit.2.0.username=MyILA0
unit.2.0.waveform.count=38
unit.2.0.waveform.count=45
unit.2.0.waveform.posn.0.channel=2147483646
unit.2.0.waveform.posn.0.name=aluo
unit.2.0.waveform.posn.0.radix=1
3433,43 → 3433,43
unit.2.0.waveform.posn.10.radix=1
unit.2.0.waveform.posn.10.type=bus
unit.2.0.waveform.posn.100.channel=2147483646
unit.2.0.waveform.posn.100.name=adr
unit.2.0.waveform.posn.100.name=x
unit.2.0.waveform.posn.100.radix=1
unit.2.0.waveform.posn.100.type=bus
unit.2.0.waveform.posn.101.channel=2147483646
unit.2.0.waveform.posn.101.name=adr
unit.2.0.waveform.posn.101.name=x
unit.2.0.waveform.posn.101.radix=1
unit.2.0.waveform.posn.101.type=bus
unit.2.0.waveform.posn.102.channel=2147483646
unit.2.0.waveform.posn.102.name=adr
unit.2.0.waveform.posn.102.name=x
unit.2.0.waveform.posn.102.radix=1
unit.2.0.waveform.posn.102.type=bus
unit.2.0.waveform.posn.103.channel=2147483646
unit.2.0.waveform.posn.103.name=adr
unit.2.0.waveform.posn.103.name=x
unit.2.0.waveform.posn.103.radix=1
unit.2.0.waveform.posn.103.type=bus
unit.2.0.waveform.posn.104.channel=2147483646
unit.2.0.waveform.posn.104.name=adr
unit.2.0.waveform.posn.104.name=x
unit.2.0.waveform.posn.104.radix=1
unit.2.0.waveform.posn.104.type=bus
unit.2.0.waveform.posn.105.channel=2147483646
unit.2.0.waveform.posn.105.name=adr
unit.2.0.waveform.posn.105.name=x
unit.2.0.waveform.posn.105.radix=1
unit.2.0.waveform.posn.105.type=bus
unit.2.0.waveform.posn.106.channel=2147483646
unit.2.0.waveform.posn.106.name=adr
unit.2.0.waveform.posn.106.name=x
unit.2.0.waveform.posn.106.radix=1
unit.2.0.waveform.posn.106.type=bus
unit.2.0.waveform.posn.107.channel=2147483646
unit.2.0.waveform.posn.107.name=adr
unit.2.0.waveform.posn.107.name=x
unit.2.0.waveform.posn.107.radix=1
unit.2.0.waveform.posn.107.type=bus
unit.2.0.waveform.posn.108.channel=2147483646
unit.2.0.waveform.posn.108.name=adr
unit.2.0.waveform.posn.108.name=x
unit.2.0.waveform.posn.108.radix=1
unit.2.0.waveform.posn.108.type=bus
unit.2.0.waveform.posn.109.channel=2147483646
unit.2.0.waveform.posn.109.name=adr
unit.2.0.waveform.posn.109.name=x
unit.2.0.waveform.posn.109.radix=1
unit.2.0.waveform.posn.109.type=bus
unit.2.0.waveform.posn.11.channel=2147483646
3477,43 → 3477,43
unit.2.0.waveform.posn.11.radix=1
unit.2.0.waveform.posn.11.type=bus
unit.2.0.waveform.posn.110.channel=2147483646
unit.2.0.waveform.posn.110.name=adr
unit.2.0.waveform.posn.110.name=x
unit.2.0.waveform.posn.110.radix=1
unit.2.0.waveform.posn.110.type=bus
unit.2.0.waveform.posn.111.channel=2147483646
unit.2.0.waveform.posn.111.name=adr
unit.2.0.waveform.posn.111.name=x
unit.2.0.waveform.posn.111.radix=1
unit.2.0.waveform.posn.111.type=bus
unit.2.0.waveform.posn.112.channel=2147483646
unit.2.0.waveform.posn.112.name=adr
unit.2.0.waveform.posn.112.name=x
unit.2.0.waveform.posn.112.radix=1
unit.2.0.waveform.posn.112.type=bus
unit.2.0.waveform.posn.113.channel=2147483646
unit.2.0.waveform.posn.113.name=adr
unit.2.0.waveform.posn.113.name=x
unit.2.0.waveform.posn.113.radix=1
unit.2.0.waveform.posn.113.type=bus
unit.2.0.waveform.posn.114.channel=2147483646
unit.2.0.waveform.posn.114.name=adr
unit.2.0.waveform.posn.114.name=x
unit.2.0.waveform.posn.114.radix=1
unit.2.0.waveform.posn.114.type=bus
unit.2.0.waveform.posn.115.channel=2147483646
unit.2.0.waveform.posn.115.name=adr
unit.2.0.waveform.posn.115.name=x
unit.2.0.waveform.posn.115.radix=1
unit.2.0.waveform.posn.115.type=bus
unit.2.0.waveform.posn.116.channel=2147483646
unit.2.0.waveform.posn.116.name=adr
unit.2.0.waveform.posn.116.name=x
unit.2.0.waveform.posn.116.radix=1
unit.2.0.waveform.posn.116.type=bus
unit.2.0.waveform.posn.117.channel=2147483646
unit.2.0.waveform.posn.117.name=adr
unit.2.0.waveform.posn.117.name=x
unit.2.0.waveform.posn.117.radix=1
unit.2.0.waveform.posn.117.type=bus
unit.2.0.waveform.posn.118.channel=2147483646
unit.2.0.waveform.posn.118.name=adr
unit.2.0.waveform.posn.118.name=x
unit.2.0.waveform.posn.118.radix=1
unit.2.0.waveform.posn.118.type=bus
unit.2.0.waveform.posn.119.channel=2147483646
unit.2.0.waveform.posn.119.name=adr
unit.2.0.waveform.posn.119.name=x
unit.2.0.waveform.posn.119.radix=1
unit.2.0.waveform.posn.119.type=bus
unit.2.0.waveform.posn.12.channel=72
3521,43 → 3521,43
unit.2.0.waveform.posn.12.radix=1
unit.2.0.waveform.posn.12.type=signal
unit.2.0.waveform.posn.120.channel=2147483646
unit.2.0.waveform.posn.120.name=adr
unit.2.0.waveform.posn.120.name=x
unit.2.0.waveform.posn.120.radix=1
unit.2.0.waveform.posn.120.type=bus
unit.2.0.waveform.posn.121.channel=2147483646
unit.2.0.waveform.posn.121.name=adr
unit.2.0.waveform.posn.121.name=x
unit.2.0.waveform.posn.121.radix=1
unit.2.0.waveform.posn.121.type=bus
unit.2.0.waveform.posn.122.channel=2147483646
unit.2.0.waveform.posn.122.name=adr
unit.2.0.waveform.posn.122.name=x
unit.2.0.waveform.posn.122.radix=1
unit.2.0.waveform.posn.122.type=bus
unit.2.0.waveform.posn.123.channel=2147483646
unit.2.0.waveform.posn.123.name=adr
unit.2.0.waveform.posn.123.name=x
unit.2.0.waveform.posn.123.radix=1
unit.2.0.waveform.posn.123.type=bus
unit.2.0.waveform.posn.124.channel=2147483646
unit.2.0.waveform.posn.124.name=adr
unit.2.0.waveform.posn.124.name=x
unit.2.0.waveform.posn.124.radix=1
unit.2.0.waveform.posn.124.type=bus
unit.2.0.waveform.posn.125.channel=2147483646
unit.2.0.waveform.posn.125.name=adr
unit.2.0.waveform.posn.125.name=x
unit.2.0.waveform.posn.125.radix=1
unit.2.0.waveform.posn.125.type=bus
unit.2.0.waveform.posn.126.channel=2147483646
unit.2.0.waveform.posn.126.name=adr
unit.2.0.waveform.posn.126.name=x
unit.2.0.waveform.posn.126.radix=1
unit.2.0.waveform.posn.126.type=bus
unit.2.0.waveform.posn.127.channel=2147483646
unit.2.0.waveform.posn.127.name=adr
unit.2.0.waveform.posn.127.name=x
unit.2.0.waveform.posn.127.radix=1
unit.2.0.waveform.posn.127.type=bus
unit.2.0.waveform.posn.128.channel=2147483646
unit.2.0.waveform.posn.128.name=adr
unit.2.0.waveform.posn.128.name=x
unit.2.0.waveform.posn.128.radix=1
unit.2.0.waveform.posn.128.type=bus
unit.2.0.waveform.posn.129.channel=2147483646
unit.2.0.waveform.posn.129.name=adr
unit.2.0.waveform.posn.129.name=x
unit.2.0.waveform.posn.129.radix=1
unit.2.0.waveform.posn.129.type=bus
unit.2.0.waveform.posn.13.channel=73
3565,119 → 3565,863
unit.2.0.waveform.posn.13.radix=1
unit.2.0.waveform.posn.13.type=signal
unit.2.0.waveform.posn.130.channel=2147483646
unit.2.0.waveform.posn.130.name=adr
unit.2.0.waveform.posn.130.name=x
unit.2.0.waveform.posn.130.radix=1
unit.2.0.waveform.posn.130.type=bus
unit.2.0.waveform.posn.131.channel=2147483646
unit.2.0.waveform.posn.131.name=x
unit.2.0.waveform.posn.131.radix=1
unit.2.0.waveform.posn.131.type=bus
unit.2.0.waveform.posn.132.channel=2147483646
unit.2.0.waveform.posn.132.name=x
unit.2.0.waveform.posn.132.radix=1
unit.2.0.waveform.posn.132.type=bus
unit.2.0.waveform.posn.133.channel=2147483646
unit.2.0.waveform.posn.133.name=x
unit.2.0.waveform.posn.133.radix=1
unit.2.0.waveform.posn.133.type=bus
unit.2.0.waveform.posn.134.channel=2147483646
unit.2.0.waveform.posn.134.name=x
unit.2.0.waveform.posn.134.radix=1
unit.2.0.waveform.posn.134.type=bus
unit.2.0.waveform.posn.135.channel=2147483646
unit.2.0.waveform.posn.135.name=x
unit.2.0.waveform.posn.135.radix=1
unit.2.0.waveform.posn.135.type=bus
unit.2.0.waveform.posn.136.channel=2147483646
unit.2.0.waveform.posn.136.name=x
unit.2.0.waveform.posn.136.radix=1
unit.2.0.waveform.posn.136.type=bus
unit.2.0.waveform.posn.137.channel=2147483646
unit.2.0.waveform.posn.137.name=x
unit.2.0.waveform.posn.137.radix=1
unit.2.0.waveform.posn.137.type=bus
unit.2.0.waveform.posn.138.channel=2147483646
unit.2.0.waveform.posn.138.name=x
unit.2.0.waveform.posn.138.radix=1
unit.2.0.waveform.posn.138.type=bus
unit.2.0.waveform.posn.139.channel=2147483646
unit.2.0.waveform.posn.139.name=x
unit.2.0.waveform.posn.139.radix=1
unit.2.0.waveform.posn.139.type=bus
unit.2.0.waveform.posn.14.channel=74
unit.2.0.waveform.posn.14.name=cyc
unit.2.0.waveform.posn.14.radix=1
unit.2.0.waveform.posn.14.type=signal
unit.2.0.waveform.posn.140.channel=2147483646
unit.2.0.waveform.posn.140.name=x
unit.2.0.waveform.posn.140.radix=1
unit.2.0.waveform.posn.140.type=bus
unit.2.0.waveform.posn.141.channel=2147483646
unit.2.0.waveform.posn.141.name=x
unit.2.0.waveform.posn.141.radix=1
unit.2.0.waveform.posn.141.type=bus
unit.2.0.waveform.posn.142.channel=2147483646
unit.2.0.waveform.posn.142.name=x
unit.2.0.waveform.posn.142.radix=1
unit.2.0.waveform.posn.142.type=bus
unit.2.0.waveform.posn.143.channel=2147483646
unit.2.0.waveform.posn.143.name=x
unit.2.0.waveform.posn.143.radix=1
unit.2.0.waveform.posn.143.type=bus
unit.2.0.waveform.posn.144.channel=2147483646
unit.2.0.waveform.posn.144.name=x
unit.2.0.waveform.posn.144.radix=1
unit.2.0.waveform.posn.144.type=bus
unit.2.0.waveform.posn.145.channel=2147483646
unit.2.0.waveform.posn.145.name=x
unit.2.0.waveform.posn.145.radix=1
unit.2.0.waveform.posn.145.type=bus
unit.2.0.waveform.posn.146.channel=2147483646
unit.2.0.waveform.posn.146.name=x
unit.2.0.waveform.posn.146.radix=1
unit.2.0.waveform.posn.146.type=bus
unit.2.0.waveform.posn.147.channel=2147483646
unit.2.0.waveform.posn.147.name=x
unit.2.0.waveform.posn.147.radix=1
unit.2.0.waveform.posn.147.type=bus
unit.2.0.waveform.posn.148.channel=2147483646
unit.2.0.waveform.posn.148.name=x
unit.2.0.waveform.posn.148.radix=1
unit.2.0.waveform.posn.148.type=bus
unit.2.0.waveform.posn.149.channel=2147483646
unit.2.0.waveform.posn.149.name=x
unit.2.0.waveform.posn.149.radix=1
unit.2.0.waveform.posn.149.type=bus
unit.2.0.waveform.posn.15.channel=75
unit.2.0.waveform.posn.15.name=tga
unit.2.0.waveform.posn.15.radix=1
unit.2.0.waveform.posn.15.type=signal
unit.2.0.waveform.posn.150.channel=2147483646
unit.2.0.waveform.posn.150.name=x
unit.2.0.waveform.posn.150.radix=1
unit.2.0.waveform.posn.150.type=bus
unit.2.0.waveform.posn.151.channel=2147483646
unit.2.0.waveform.posn.151.name=x
unit.2.0.waveform.posn.151.radix=1
unit.2.0.waveform.posn.151.type=bus
unit.2.0.waveform.posn.152.channel=2147483646
unit.2.0.waveform.posn.152.name=x
unit.2.0.waveform.posn.152.radix=1
unit.2.0.waveform.posn.152.type=bus
unit.2.0.waveform.posn.153.channel=2147483646
unit.2.0.waveform.posn.153.name=x
unit.2.0.waveform.posn.153.radix=1
unit.2.0.waveform.posn.153.type=bus
unit.2.0.waveform.posn.154.channel=2147483646
unit.2.0.waveform.posn.154.name=x
unit.2.0.waveform.posn.154.radix=1
unit.2.0.waveform.posn.154.type=bus
unit.2.0.waveform.posn.155.channel=2147483646
unit.2.0.waveform.posn.155.name=x
unit.2.0.waveform.posn.155.radix=1
unit.2.0.waveform.posn.155.type=bus
unit.2.0.waveform.posn.156.channel=2147483646
unit.2.0.waveform.posn.156.name=x
unit.2.0.waveform.posn.156.radix=1
unit.2.0.waveform.posn.156.type=bus
unit.2.0.waveform.posn.157.channel=2147483646
unit.2.0.waveform.posn.157.name=x
unit.2.0.waveform.posn.157.radix=1
unit.2.0.waveform.posn.157.type=bus
unit.2.0.waveform.posn.158.channel=2147483646
unit.2.0.waveform.posn.158.name=x
unit.2.0.waveform.posn.158.radix=1
unit.2.0.waveform.posn.158.type=bus
unit.2.0.waveform.posn.159.channel=2147483646
unit.2.0.waveform.posn.159.name=x
unit.2.0.waveform.posn.159.radix=1
unit.2.0.waveform.posn.159.type=bus
unit.2.0.waveform.posn.16.channel=76
unit.2.0.waveform.posn.16.name=we
unit.2.0.waveform.posn.16.radix=1
unit.2.0.waveform.posn.16.type=signal
unit.2.0.waveform.posn.160.channel=2147483646
unit.2.0.waveform.posn.160.name=x
unit.2.0.waveform.posn.160.radix=1
unit.2.0.waveform.posn.160.type=bus
unit.2.0.waveform.posn.161.channel=2147483646
unit.2.0.waveform.posn.161.name=x
unit.2.0.waveform.posn.161.radix=1
unit.2.0.waveform.posn.161.type=bus
unit.2.0.waveform.posn.162.channel=2147483646
unit.2.0.waveform.posn.162.name=x
unit.2.0.waveform.posn.162.radix=1
unit.2.0.waveform.posn.162.type=bus
unit.2.0.waveform.posn.163.channel=2147483646
unit.2.0.waveform.posn.163.name=x
unit.2.0.waveform.posn.163.radix=1
unit.2.0.waveform.posn.163.type=bus
unit.2.0.waveform.posn.164.channel=2147483646
unit.2.0.waveform.posn.164.name=x
unit.2.0.waveform.posn.164.radix=1
unit.2.0.waveform.posn.164.type=bus
unit.2.0.waveform.posn.165.channel=2147483646
unit.2.0.waveform.posn.165.name=x
unit.2.0.waveform.posn.165.radix=1
unit.2.0.waveform.posn.165.type=bus
unit.2.0.waveform.posn.166.channel=2147483646
unit.2.0.waveform.posn.166.name=x
unit.2.0.waveform.posn.166.radix=1
unit.2.0.waveform.posn.166.type=bus
unit.2.0.waveform.posn.167.channel=2147483646
unit.2.0.waveform.posn.167.name=x
unit.2.0.waveform.posn.167.radix=1
unit.2.0.waveform.posn.167.type=bus
unit.2.0.waveform.posn.168.channel=2147483646
unit.2.0.waveform.posn.168.name=x
unit.2.0.waveform.posn.168.radix=1
unit.2.0.waveform.posn.168.type=bus
unit.2.0.waveform.posn.169.channel=2147483646
unit.2.0.waveform.posn.169.name=x
unit.2.0.waveform.posn.169.radix=1
unit.2.0.waveform.posn.169.type=bus
unit.2.0.waveform.posn.17.channel=77
unit.2.0.waveform.posn.17.name=clk
unit.2.0.waveform.posn.17.radix=1
unit.2.0.waveform.posn.17.type=signal
unit.2.0.waveform.posn.18.channel=207
unit.2.0.waveform.posn.18.name=flash_ce2_
unit.2.0.waveform.posn.170.channel=2147483646
unit.2.0.waveform.posn.170.name=x
unit.2.0.waveform.posn.170.radix=1
unit.2.0.waveform.posn.170.type=bus
unit.2.0.waveform.posn.171.channel=2147483646
unit.2.0.waveform.posn.171.name=x
unit.2.0.waveform.posn.171.radix=1
unit.2.0.waveform.posn.171.type=bus
unit.2.0.waveform.posn.172.channel=2147483646
unit.2.0.waveform.posn.172.name=x
unit.2.0.waveform.posn.172.radix=1
unit.2.0.waveform.posn.172.type=bus
unit.2.0.waveform.posn.173.channel=2147483646
unit.2.0.waveform.posn.173.name=x
unit.2.0.waveform.posn.173.radix=1
unit.2.0.waveform.posn.173.type=bus
unit.2.0.waveform.posn.174.channel=2147483646
unit.2.0.waveform.posn.174.name=x
unit.2.0.waveform.posn.174.radix=1
unit.2.0.waveform.posn.174.type=bus
unit.2.0.waveform.posn.175.channel=2147483646
unit.2.0.waveform.posn.175.name=x
unit.2.0.waveform.posn.175.radix=1
unit.2.0.waveform.posn.175.type=bus
unit.2.0.waveform.posn.176.channel=2147483646
unit.2.0.waveform.posn.176.name=x
unit.2.0.waveform.posn.176.radix=1
unit.2.0.waveform.posn.176.type=bus
unit.2.0.waveform.posn.177.channel=2147483646
unit.2.0.waveform.posn.177.name=x
unit.2.0.waveform.posn.177.radix=1
unit.2.0.waveform.posn.177.type=bus
unit.2.0.waveform.posn.178.channel=2147483646
unit.2.0.waveform.posn.178.name=x
unit.2.0.waveform.posn.178.radix=1
unit.2.0.waveform.posn.178.type=bus
unit.2.0.waveform.posn.179.channel=2147483646
unit.2.0.waveform.posn.179.name=x
unit.2.0.waveform.posn.179.radix=1
unit.2.0.waveform.posn.179.type=bus
unit.2.0.waveform.posn.18.channel=2147483646
unit.2.0.waveform.posn.18.name=cnt
unit.2.0.waveform.posn.18.radix=1
unit.2.0.waveform.posn.18.type=signal
unit.2.0.waveform.posn.19.channel=208
unit.2.0.waveform.posn.19.name=sram_adv_
unit.2.0.waveform.posn.18.type=bus
unit.2.0.waveform.posn.180.channel=2147483646
unit.2.0.waveform.posn.180.name=x
unit.2.0.waveform.posn.180.radix=1
unit.2.0.waveform.posn.180.type=bus
unit.2.0.waveform.posn.181.channel=2147483646
unit.2.0.waveform.posn.181.name=x
unit.2.0.waveform.posn.181.radix=1
unit.2.0.waveform.posn.181.type=bus
unit.2.0.waveform.posn.182.channel=2147483646
unit.2.0.waveform.posn.182.name=x
unit.2.0.waveform.posn.182.radix=1
unit.2.0.waveform.posn.182.type=bus
unit.2.0.waveform.posn.183.channel=2147483646
unit.2.0.waveform.posn.183.name=x
unit.2.0.waveform.posn.183.radix=1
unit.2.0.waveform.posn.183.type=bus
unit.2.0.waveform.posn.184.channel=2147483646
unit.2.0.waveform.posn.184.name=x
unit.2.0.waveform.posn.184.radix=1
unit.2.0.waveform.posn.184.type=bus
unit.2.0.waveform.posn.185.channel=2147483646
unit.2.0.waveform.posn.185.name=x
unit.2.0.waveform.posn.185.radix=1
unit.2.0.waveform.posn.185.type=bus
unit.2.0.waveform.posn.186.channel=2147483646
unit.2.0.waveform.posn.186.name=x
unit.2.0.waveform.posn.186.radix=1
unit.2.0.waveform.posn.186.type=bus
unit.2.0.waveform.posn.187.channel=2147483646
unit.2.0.waveform.posn.187.name=x
unit.2.0.waveform.posn.187.radix=1
unit.2.0.waveform.posn.187.type=bus
unit.2.0.waveform.posn.188.channel=2147483646
unit.2.0.waveform.posn.188.name=x
unit.2.0.waveform.posn.188.radix=1
unit.2.0.waveform.posn.188.type=bus
unit.2.0.waveform.posn.189.channel=2147483646
unit.2.0.waveform.posn.189.name=x
unit.2.0.waveform.posn.189.radix=1
unit.2.0.waveform.posn.189.type=bus
unit.2.0.waveform.posn.19.channel=219
unit.2.0.waveform.posn.19.name=op
unit.2.0.waveform.posn.19.radix=1
unit.2.0.waveform.posn.19.type=signal
unit.2.0.waveform.posn.190.channel=2147483646
unit.2.0.waveform.posn.190.name=x
unit.2.0.waveform.posn.190.radix=1
unit.2.0.waveform.posn.190.type=bus
unit.2.0.waveform.posn.191.channel=2147483646
unit.2.0.waveform.posn.191.name=x
unit.2.0.waveform.posn.191.radix=1
unit.2.0.waveform.posn.191.type=bus
unit.2.0.waveform.posn.192.channel=2147483646
unit.2.0.waveform.posn.192.name=x
unit.2.0.waveform.posn.192.radix=1
unit.2.0.waveform.posn.192.type=bus
unit.2.0.waveform.posn.193.channel=2147483646
unit.2.0.waveform.posn.193.name=x
unit.2.0.waveform.posn.193.radix=1
unit.2.0.waveform.posn.193.type=bus
unit.2.0.waveform.posn.194.channel=2147483646
unit.2.0.waveform.posn.194.name=x
unit.2.0.waveform.posn.194.radix=1
unit.2.0.waveform.posn.194.type=bus
unit.2.0.waveform.posn.195.channel=2147483646
unit.2.0.waveform.posn.195.name=x
unit.2.0.waveform.posn.195.radix=1
unit.2.0.waveform.posn.195.type=bus
unit.2.0.waveform.posn.196.channel=2147483646
unit.2.0.waveform.posn.196.name=x
unit.2.0.waveform.posn.196.radix=1
unit.2.0.waveform.posn.196.type=bus
unit.2.0.waveform.posn.197.channel=2147483646
unit.2.0.waveform.posn.197.name=x
unit.2.0.waveform.posn.197.radix=1
unit.2.0.waveform.posn.197.type=bus
unit.2.0.waveform.posn.198.channel=2147483646
unit.2.0.waveform.posn.198.name=x
unit.2.0.waveform.posn.198.radix=1
unit.2.0.waveform.posn.198.type=bus
unit.2.0.waveform.posn.199.channel=2147483646
unit.2.0.waveform.posn.199.name=x
unit.2.0.waveform.posn.199.radix=1
unit.2.0.waveform.posn.199.type=bus
unit.2.0.waveform.posn.2.channel=2147483646
unit.2.0.waveform.posn.2.name=y
unit.2.0.waveform.posn.2.radix=1
unit.2.0.waveform.posn.2.type=bus
unit.2.0.waveform.posn.20.channel=209
unit.2.0.waveform.posn.20.name=sram_cen_
unit.2.0.waveform.posn.20.channel=220
unit.2.0.waveform.posn.20.name=zbt_stb
unit.2.0.waveform.posn.20.radix=1
unit.2.0.waveform.posn.20.type=signal
unit.2.0.waveform.posn.21.channel=214
unit.2.0.waveform.posn.21.name=sf_we_
unit.2.0.waveform.posn.200.channel=2147483646
unit.2.0.waveform.posn.200.name=x
unit.2.0.waveform.posn.200.radix=1
unit.2.0.waveform.posn.200.type=bus
unit.2.0.waveform.posn.201.channel=2147483646
unit.2.0.waveform.posn.201.name=x
unit.2.0.waveform.posn.201.radix=1
unit.2.0.waveform.posn.201.type=bus
unit.2.0.waveform.posn.202.channel=2147483646
unit.2.0.waveform.posn.202.name=x
unit.2.0.waveform.posn.202.radix=1
unit.2.0.waveform.posn.202.type=bus
unit.2.0.waveform.posn.203.channel=2147483646
unit.2.0.waveform.posn.203.name=x
unit.2.0.waveform.posn.203.radix=1
unit.2.0.waveform.posn.203.type=bus
unit.2.0.waveform.posn.204.channel=2147483646
unit.2.0.waveform.posn.204.name=x
unit.2.0.waveform.posn.204.radix=1
unit.2.0.waveform.posn.204.type=bus
unit.2.0.waveform.posn.205.channel=2147483646
unit.2.0.waveform.posn.205.name=x
unit.2.0.waveform.posn.205.radix=1
unit.2.0.waveform.posn.205.type=bus
unit.2.0.waveform.posn.206.channel=2147483646
unit.2.0.waveform.posn.206.name=x
unit.2.0.waveform.posn.206.radix=1
unit.2.0.waveform.posn.206.type=bus
unit.2.0.waveform.posn.207.channel=2147483646
unit.2.0.waveform.posn.207.name=x
unit.2.0.waveform.posn.207.radix=1
unit.2.0.waveform.posn.207.type=bus
unit.2.0.waveform.posn.208.channel=2147483646
unit.2.0.waveform.posn.208.name=x
unit.2.0.waveform.posn.208.radix=1
unit.2.0.waveform.posn.208.type=bus
unit.2.0.waveform.posn.209.channel=2147483646
unit.2.0.waveform.posn.209.name=x
unit.2.0.waveform.posn.209.radix=1
unit.2.0.waveform.posn.209.type=bus
unit.2.0.waveform.posn.21.channel=221
unit.2.0.waveform.posn.21.name=flash_stb
unit.2.0.waveform.posn.21.radix=1
unit.2.0.waveform.posn.21.type=signal
unit.2.0.waveform.posn.22.channel=215
unit.2.0.waveform.posn.22.name=sf_oe_
unit.2.0.waveform.posn.210.channel=2147483646
unit.2.0.waveform.posn.210.name=x
unit.2.0.waveform.posn.210.radix=1
unit.2.0.waveform.posn.210.type=bus
unit.2.0.waveform.posn.211.channel=2147483646
unit.2.0.waveform.posn.211.name=x
unit.2.0.waveform.posn.211.radix=1
unit.2.0.waveform.posn.211.type=bus
unit.2.0.waveform.posn.212.channel=2147483646
unit.2.0.waveform.posn.212.name=x
unit.2.0.waveform.posn.212.radix=1
unit.2.0.waveform.posn.212.type=bus
unit.2.0.waveform.posn.213.channel=2147483646
unit.2.0.waveform.posn.213.name=x
unit.2.0.waveform.posn.213.radix=1
unit.2.0.waveform.posn.213.type=bus
unit.2.0.waveform.posn.214.channel=2147483646
unit.2.0.waveform.posn.214.name=x
unit.2.0.waveform.posn.214.radix=1
unit.2.0.waveform.posn.214.type=bus
unit.2.0.waveform.posn.215.channel=2147483646
unit.2.0.waveform.posn.215.name=x
unit.2.0.waveform.posn.215.radix=1
unit.2.0.waveform.posn.215.type=bus
unit.2.0.waveform.posn.216.channel=2147483646
unit.2.0.waveform.posn.216.name=x
unit.2.0.waveform.posn.216.radix=1
unit.2.0.waveform.posn.216.type=bus
unit.2.0.waveform.posn.217.channel=2147483646
unit.2.0.waveform.posn.217.name=x
unit.2.0.waveform.posn.217.radix=1
unit.2.0.waveform.posn.217.type=bus
unit.2.0.waveform.posn.218.channel=2147483646
unit.2.0.waveform.posn.218.name=x
unit.2.0.waveform.posn.218.radix=1
unit.2.0.waveform.posn.218.type=bus
unit.2.0.waveform.posn.219.channel=2147483646
unit.2.0.waveform.posn.219.name=x
unit.2.0.waveform.posn.219.radix=1
unit.2.0.waveform.posn.219.type=bus
unit.2.0.waveform.posn.22.channel=222
unit.2.0.waveform.posn.22.name=flash_arena
unit.2.0.waveform.posn.22.radix=1
unit.2.0.waveform.posn.22.type=signal
unit.2.0.waveform.posn.23.channel=2147483646
unit.2.0.waveform.posn.23.name=s_bw_
unit.2.0.waveform.posn.220.channel=2147483646
unit.2.0.waveform.posn.220.name=x
unit.2.0.waveform.posn.220.radix=1
unit.2.0.waveform.posn.220.type=bus
unit.2.0.waveform.posn.221.channel=2147483646
unit.2.0.waveform.posn.221.name=x
unit.2.0.waveform.posn.221.radix=1
unit.2.0.waveform.posn.221.type=bus
unit.2.0.waveform.posn.222.channel=2147483646
unit.2.0.waveform.posn.222.name=x
unit.2.0.waveform.posn.222.radix=1
unit.2.0.waveform.posn.222.type=bus
unit.2.0.waveform.posn.223.channel=2147483646
unit.2.0.waveform.posn.223.name=x
unit.2.0.waveform.posn.223.radix=1
unit.2.0.waveform.posn.223.type=bus
unit.2.0.waveform.posn.224.channel=2147483646
unit.2.0.waveform.posn.224.name=x
unit.2.0.waveform.posn.224.radix=1
unit.2.0.waveform.posn.224.type=bus
unit.2.0.waveform.posn.225.channel=2147483646
unit.2.0.waveform.posn.225.name=x
unit.2.0.waveform.posn.225.radix=1
unit.2.0.waveform.posn.225.type=bus
unit.2.0.waveform.posn.226.channel=2147483646
unit.2.0.waveform.posn.226.name=x
unit.2.0.waveform.posn.226.radix=1
unit.2.0.waveform.posn.226.type=bus
unit.2.0.waveform.posn.227.channel=2147483646
unit.2.0.waveform.posn.227.name=x
unit.2.0.waveform.posn.227.radix=1
unit.2.0.waveform.posn.227.type=bus
unit.2.0.waveform.posn.228.channel=2147483646
unit.2.0.waveform.posn.228.name=x
unit.2.0.waveform.posn.228.radix=1
unit.2.0.waveform.posn.228.type=bus
unit.2.0.waveform.posn.229.channel=2147483646
unit.2.0.waveform.posn.229.name=x
unit.2.0.waveform.posn.229.radix=1
unit.2.0.waveform.posn.229.type=bus
unit.2.0.waveform.posn.23.channel=223
unit.2.0.waveform.posn.23.name=vdu_arena
unit.2.0.waveform.posn.23.radix=1
unit.2.0.waveform.posn.23.type=bus
unit.2.0.waveform.posn.23.type=signal
unit.2.0.waveform.posn.230.channel=2147483646
unit.2.0.waveform.posn.230.name=x
unit.2.0.waveform.posn.230.radix=1
unit.2.0.waveform.posn.230.type=bus
unit.2.0.waveform.posn.231.channel=2147483646
unit.2.0.waveform.posn.231.name=x
unit.2.0.waveform.posn.231.radix=1
unit.2.0.waveform.posn.231.type=bus
unit.2.0.waveform.posn.232.channel=2147483646
unit.2.0.waveform.posn.232.name=x
unit.2.0.waveform.posn.232.radix=1
unit.2.0.waveform.posn.232.type=bus
unit.2.0.waveform.posn.233.channel=2147483646
unit.2.0.waveform.posn.233.name=x
unit.2.0.waveform.posn.233.radix=1
unit.2.0.waveform.posn.233.type=bus
unit.2.0.waveform.posn.234.channel=2147483646
unit.2.0.waveform.posn.234.name=x
unit.2.0.waveform.posn.234.radix=1
unit.2.0.waveform.posn.234.type=bus
unit.2.0.waveform.posn.235.channel=2147483646
unit.2.0.waveform.posn.235.name=x
unit.2.0.waveform.posn.235.radix=1
unit.2.0.waveform.posn.235.type=bus
unit.2.0.waveform.posn.236.channel=2147483646
unit.2.0.waveform.posn.236.name=x
unit.2.0.waveform.posn.236.radix=1
unit.2.0.waveform.posn.236.type=bus
unit.2.0.waveform.posn.237.channel=2147483646
unit.2.0.waveform.posn.237.name=x
unit.2.0.waveform.posn.237.radix=1
unit.2.0.waveform.posn.237.type=bus
unit.2.0.waveform.posn.238.channel=2147483646
unit.2.0.waveform.posn.238.name=x
unit.2.0.waveform.posn.238.radix=1
unit.2.0.waveform.posn.238.type=bus
unit.2.0.waveform.posn.239.channel=2147483646
unit.2.0.waveform.posn.239.name=x
unit.2.0.waveform.posn.239.radix=1
unit.2.0.waveform.posn.239.type=bus
unit.2.0.waveform.posn.24.channel=2147483646
unit.2.0.waveform.posn.24.name=s_data_
unit.2.0.waveform.posn.24.name=d
unit.2.0.waveform.posn.24.radix=1
unit.2.0.waveform.posn.24.type=bus
unit.2.0.waveform.posn.240.channel=2147483646
unit.2.0.waveform.posn.240.name=x
unit.2.0.waveform.posn.240.radix=1
unit.2.0.waveform.posn.240.type=bus
unit.2.0.waveform.posn.241.channel=2147483646
unit.2.0.waveform.posn.241.name=x
unit.2.0.waveform.posn.241.radix=1
unit.2.0.waveform.posn.241.type=bus
unit.2.0.waveform.posn.242.channel=2147483646
unit.2.0.waveform.posn.242.name=x
unit.2.0.waveform.posn.242.radix=1
unit.2.0.waveform.posn.242.type=bus
unit.2.0.waveform.posn.243.channel=2147483646
unit.2.0.waveform.posn.243.name=x
unit.2.0.waveform.posn.243.radix=1
unit.2.0.waveform.posn.243.type=bus
unit.2.0.waveform.posn.244.channel=2147483646
unit.2.0.waveform.posn.244.name=x
unit.2.0.waveform.posn.244.radix=1
unit.2.0.waveform.posn.244.type=bus
unit.2.0.waveform.posn.245.channel=2147483646
unit.2.0.waveform.posn.245.name=x
unit.2.0.waveform.posn.245.radix=1
unit.2.0.waveform.posn.245.type=bus
unit.2.0.waveform.posn.246.channel=2147483646
unit.2.0.waveform.posn.246.name=x
unit.2.0.waveform.posn.246.radix=1
unit.2.0.waveform.posn.246.type=bus
unit.2.0.waveform.posn.247.channel=2147483646
unit.2.0.waveform.posn.247.name=x
unit.2.0.waveform.posn.247.radix=1
unit.2.0.waveform.posn.247.type=bus
unit.2.0.waveform.posn.248.channel=2147483646
unit.2.0.waveform.posn.248.name=x
unit.2.0.waveform.posn.248.radix=1
unit.2.0.waveform.posn.248.type=bus
unit.2.0.waveform.posn.249.channel=2147483646
unit.2.0.waveform.posn.249.name=x
unit.2.0.waveform.posn.249.radix=1
unit.2.0.waveform.posn.249.type=bus
unit.2.0.waveform.posn.25.channel=2147483646
unit.2.0.waveform.posn.25.name=s_addr_
unit.2.0.waveform.posn.25.name=addr_d
unit.2.0.waveform.posn.25.radix=1
unit.2.0.waveform.posn.25.type=bus
unit.2.0.waveform.posn.26.channel=2147483646
unit.2.0.waveform.posn.26.name=cnt
unit.2.0.waveform.posn.250.channel=2147483646
unit.2.0.waveform.posn.250.name=x
unit.2.0.waveform.posn.250.radix=1
unit.2.0.waveform.posn.250.type=bus
unit.2.0.waveform.posn.251.channel=2147483646
unit.2.0.waveform.posn.251.name=x
unit.2.0.waveform.posn.251.radix=1
unit.2.0.waveform.posn.251.type=bus
unit.2.0.waveform.posn.252.channel=2147483646
unit.2.0.waveform.posn.252.name=x
unit.2.0.waveform.posn.252.radix=1
unit.2.0.waveform.posn.252.type=bus
unit.2.0.waveform.posn.253.channel=2147483646
unit.2.0.waveform.posn.253.name=x
unit.2.0.waveform.posn.253.radix=1
unit.2.0.waveform.posn.253.type=bus
unit.2.0.waveform.posn.254.channel=2147483646
unit.2.0.waveform.posn.254.name=x
unit.2.0.waveform.posn.254.radix=1
unit.2.0.waveform.posn.254.type=bus
unit.2.0.waveform.posn.255.channel=2147483646
unit.2.0.waveform.posn.255.name=x
unit.2.0.waveform.posn.255.radix=1
unit.2.0.waveform.posn.255.type=bus
unit.2.0.waveform.posn.256.channel=2147483646
unit.2.0.waveform.posn.256.name=x
unit.2.0.waveform.posn.256.radix=1
unit.2.0.waveform.posn.256.type=bus
unit.2.0.waveform.posn.257.channel=2147483646
unit.2.0.waveform.posn.257.name=x
unit.2.0.waveform.posn.257.radix=1
unit.2.0.waveform.posn.257.type=bus
unit.2.0.waveform.posn.258.channel=2147483646
unit.2.0.waveform.posn.258.name=x
unit.2.0.waveform.posn.258.radix=1
unit.2.0.waveform.posn.258.type=bus
unit.2.0.waveform.posn.259.channel=2147483646
unit.2.0.waveform.posn.259.name=x
unit.2.0.waveform.posn.259.radix=1
unit.2.0.waveform.posn.259.type=bus
unit.2.0.waveform.posn.26.channel=94
unit.2.0.waveform.posn.26.name=byte_op
unit.2.0.waveform.posn.26.radix=1
unit.2.0.waveform.posn.26.type=bus
unit.2.0.waveform.posn.27.channel=219
unit.2.0.waveform.posn.27.name=op
unit.2.0.waveform.posn.26.type=signal
unit.2.0.waveform.posn.260.channel=2147483646
unit.2.0.waveform.posn.260.name=x
unit.2.0.waveform.posn.260.radix=1
unit.2.0.waveform.posn.260.type=bus
unit.2.0.waveform.posn.261.channel=2147483646
unit.2.0.waveform.posn.261.name=x
unit.2.0.waveform.posn.261.radix=1
unit.2.0.waveform.posn.261.type=bus
unit.2.0.waveform.posn.262.channel=2147483646
unit.2.0.waveform.posn.262.name=x
unit.2.0.waveform.posn.262.radix=1
unit.2.0.waveform.posn.262.type=bus
unit.2.0.waveform.posn.263.channel=2147483646
unit.2.0.waveform.posn.263.name=x
unit.2.0.waveform.posn.263.radix=1
unit.2.0.waveform.posn.263.type=bus
unit.2.0.waveform.posn.264.channel=2147483646
unit.2.0.waveform.posn.264.name=x
unit.2.0.waveform.posn.264.radix=1
unit.2.0.waveform.posn.264.type=bus
unit.2.0.waveform.posn.265.channel=2147483646
unit.2.0.waveform.posn.265.name=x
unit.2.0.waveform.posn.265.radix=1
unit.2.0.waveform.posn.265.type=bus
unit.2.0.waveform.posn.266.channel=2147483646
unit.2.0.waveform.posn.266.name=x
unit.2.0.waveform.posn.266.radix=1
unit.2.0.waveform.posn.266.type=bus
unit.2.0.waveform.posn.267.channel=2147483646
unit.2.0.waveform.posn.267.name=x
unit.2.0.waveform.posn.267.radix=1
unit.2.0.waveform.posn.267.type=bus
unit.2.0.waveform.posn.268.channel=2147483646
unit.2.0.waveform.posn.268.name=x
unit.2.0.waveform.posn.268.radix=1
unit.2.0.waveform.posn.268.type=bus
unit.2.0.waveform.posn.269.channel=2147483646
unit.2.0.waveform.posn.269.name=x
unit.2.0.waveform.posn.269.radix=1
unit.2.0.waveform.posn.269.type=bus
unit.2.0.waveform.posn.27.channel=104
unit.2.0.waveform.posn.27.name=inta
unit.2.0.waveform.posn.27.radix=1
unit.2.0.waveform.posn.27.type=signal
unit.2.0.waveform.posn.28.channel=220
unit.2.0.waveform.posn.28.name=zbt_stb
unit.2.0.waveform.posn.270.channel=2147483646
unit.2.0.waveform.posn.270.name=x
unit.2.0.waveform.posn.270.radix=1
unit.2.0.waveform.posn.270.type=bus
unit.2.0.waveform.posn.271.channel=2147483646
unit.2.0.waveform.posn.271.name=x
unit.2.0.waveform.posn.271.radix=1
unit.2.0.waveform.posn.271.type=bus
unit.2.0.waveform.posn.272.channel=2147483646
unit.2.0.waveform.posn.272.name=x
unit.2.0.waveform.posn.272.radix=1
unit.2.0.waveform.posn.272.type=bus
unit.2.0.waveform.posn.273.channel=2147483646
unit.2.0.waveform.posn.273.name=x
unit.2.0.waveform.posn.273.radix=1
unit.2.0.waveform.posn.273.type=bus
unit.2.0.waveform.posn.274.channel=2147483646
unit.2.0.waveform.posn.274.name=x
unit.2.0.waveform.posn.274.radix=1
unit.2.0.waveform.posn.274.type=bus
unit.2.0.waveform.posn.275.channel=2147483646
unit.2.0.waveform.posn.275.name=x
unit.2.0.waveform.posn.275.radix=1
unit.2.0.waveform.posn.275.type=bus
unit.2.0.waveform.posn.276.channel=2147483646
unit.2.0.waveform.posn.276.name=x
unit.2.0.waveform.posn.276.radix=1
unit.2.0.waveform.posn.276.type=bus
unit.2.0.waveform.posn.277.channel=2147483646
unit.2.0.waveform.posn.277.name=x
unit.2.0.waveform.posn.277.radix=1
unit.2.0.waveform.posn.277.type=bus
unit.2.0.waveform.posn.278.channel=2147483646
unit.2.0.waveform.posn.278.name=x
unit.2.0.waveform.posn.278.radix=1
unit.2.0.waveform.posn.278.type=bus
unit.2.0.waveform.posn.279.channel=2147483646
unit.2.0.waveform.posn.279.name=x
unit.2.0.waveform.posn.279.radix=1
unit.2.0.waveform.posn.279.type=bus
unit.2.0.waveform.posn.28.channel=105
unit.2.0.waveform.posn.28.name=intr
unit.2.0.waveform.posn.28.radix=1
unit.2.0.waveform.posn.28.type=signal
unit.2.0.waveform.posn.29.channel=221
unit.2.0.waveform.posn.29.name=flash_stb
unit.2.0.waveform.posn.280.channel=2147483646
unit.2.0.waveform.posn.280.name=x
unit.2.0.waveform.posn.280.radix=1
unit.2.0.waveform.posn.280.type=bus
unit.2.0.waveform.posn.281.channel=2147483646
unit.2.0.waveform.posn.281.name=x
unit.2.0.waveform.posn.281.radix=1
unit.2.0.waveform.posn.281.type=bus
unit.2.0.waveform.posn.282.channel=2147483646
unit.2.0.waveform.posn.282.name=x
unit.2.0.waveform.posn.282.radix=1
unit.2.0.waveform.posn.282.type=bus
unit.2.0.waveform.posn.283.channel=2147483646
unit.2.0.waveform.posn.283.name=x
unit.2.0.waveform.posn.283.radix=1
unit.2.0.waveform.posn.283.type=bus
unit.2.0.waveform.posn.284.channel=2147483646
unit.2.0.waveform.posn.284.name=x
unit.2.0.waveform.posn.284.radix=1
unit.2.0.waveform.posn.284.type=bus
unit.2.0.waveform.posn.285.channel=2147483646
unit.2.0.waveform.posn.285.name=x
unit.2.0.waveform.posn.285.radix=1
unit.2.0.waveform.posn.285.type=bus
unit.2.0.waveform.posn.286.channel=2147483646
unit.2.0.waveform.posn.286.name=x
unit.2.0.waveform.posn.286.radix=1
unit.2.0.waveform.posn.286.type=bus
unit.2.0.waveform.posn.287.channel=2147483646
unit.2.0.waveform.posn.287.name=x
unit.2.0.waveform.posn.287.radix=1
unit.2.0.waveform.posn.287.type=bus
unit.2.0.waveform.posn.288.channel=2147483646
unit.2.0.waveform.posn.288.name=x
unit.2.0.waveform.posn.288.radix=1
unit.2.0.waveform.posn.288.type=bus
unit.2.0.waveform.posn.289.channel=2147483646
unit.2.0.waveform.posn.289.name=x
unit.2.0.waveform.posn.289.radix=1
unit.2.0.waveform.posn.289.type=bus
unit.2.0.waveform.posn.29.channel=2147483646
unit.2.0.waveform.posn.29.name=cnt_time
unit.2.0.waveform.posn.29.radix=1
unit.2.0.waveform.posn.29.type=signal
unit.2.0.waveform.posn.29.type=bus
unit.2.0.waveform.posn.290.channel=2147483646
unit.2.0.waveform.posn.290.name=x
unit.2.0.waveform.posn.290.radix=1
unit.2.0.waveform.posn.290.type=bus
unit.2.0.waveform.posn.291.channel=2147483646
unit.2.0.waveform.posn.291.name=x
unit.2.0.waveform.posn.291.radix=1
unit.2.0.waveform.posn.291.type=bus
unit.2.0.waveform.posn.292.channel=2147483646
unit.2.0.waveform.posn.292.name=x
unit.2.0.waveform.posn.292.radix=1
unit.2.0.waveform.posn.292.type=bus
unit.2.0.waveform.posn.293.channel=2147483646
unit.2.0.waveform.posn.293.name=x
unit.2.0.waveform.posn.293.radix=1
unit.2.0.waveform.posn.293.type=bus
unit.2.0.waveform.posn.294.channel=2147483646
unit.2.0.waveform.posn.294.name=x
unit.2.0.waveform.posn.294.radix=1
unit.2.0.waveform.posn.294.type=bus
unit.2.0.waveform.posn.295.channel=2147483646
unit.2.0.waveform.posn.295.name=x
unit.2.0.waveform.posn.295.radix=1
unit.2.0.waveform.posn.295.type=bus
unit.2.0.waveform.posn.296.channel=2147483646
unit.2.0.waveform.posn.296.name=x
unit.2.0.waveform.posn.296.radix=1
unit.2.0.waveform.posn.296.type=bus
unit.2.0.waveform.posn.297.channel=2147483646
unit.2.0.waveform.posn.297.name=x
unit.2.0.waveform.posn.297.radix=1
unit.2.0.waveform.posn.297.type=bus
unit.2.0.waveform.posn.298.channel=2147483646
unit.2.0.waveform.posn.298.name=x
unit.2.0.waveform.posn.298.radix=1
unit.2.0.waveform.posn.298.type=bus
unit.2.0.waveform.posn.299.channel=2147483646
unit.2.0.waveform.posn.299.name=x
unit.2.0.waveform.posn.299.radix=1
unit.2.0.waveform.posn.299.type=bus
unit.2.0.waveform.posn.3.channel=2147483646
unit.2.0.waveform.posn.3.name=pc
unit.2.0.waveform.posn.3.radix=1
unit.2.0.waveform.posn.3.type=bus
unit.2.0.waveform.posn.30.channel=222
unit.2.0.waveform.posn.30.name=flash_arena
unit.2.0.waveform.posn.30.channel=2147483646
unit.2.0.waveform.posn.30.name=ace_dat_o
unit.2.0.waveform.posn.30.radix=1
unit.2.0.waveform.posn.30.type=signal
unit.2.0.waveform.posn.31.channel=223
unit.2.0.waveform.posn.31.name=vdu_arena
unit.2.0.waveform.posn.30.type=bus
unit.2.0.waveform.posn.300.channel=2147483646
unit.2.0.waveform.posn.300.name=x
unit.2.0.waveform.posn.300.radix=1
unit.2.0.waveform.posn.300.type=bus
unit.2.0.waveform.posn.301.channel=2147483646
unit.2.0.waveform.posn.301.name=x
unit.2.0.waveform.posn.301.radix=1
unit.2.0.waveform.posn.301.type=bus
unit.2.0.waveform.posn.302.channel=2147483646
unit.2.0.waveform.posn.302.name=x
unit.2.0.waveform.posn.302.radix=1
unit.2.0.waveform.posn.302.type=bus
unit.2.0.waveform.posn.303.channel=2147483646
unit.2.0.waveform.posn.303.name=x
unit.2.0.waveform.posn.303.radix=1
unit.2.0.waveform.posn.303.type=bus
unit.2.0.waveform.posn.304.channel=2147483646
unit.2.0.waveform.posn.304.name=x
unit.2.0.waveform.posn.304.radix=1
unit.2.0.waveform.posn.304.type=bus
unit.2.0.waveform.posn.305.channel=2147483646
unit.2.0.waveform.posn.305.name=x
unit.2.0.waveform.posn.305.radix=1
unit.2.0.waveform.posn.305.type=bus
unit.2.0.waveform.posn.306.channel=2147483646
unit.2.0.waveform.posn.306.name=x
unit.2.0.waveform.posn.306.radix=1
unit.2.0.waveform.posn.306.type=bus
unit.2.0.waveform.posn.307.channel=2147483646
unit.2.0.waveform.posn.307.name=x
unit.2.0.waveform.posn.307.radix=1
unit.2.0.waveform.posn.307.type=bus
unit.2.0.waveform.posn.308.channel=2147483646
unit.2.0.waveform.posn.308.name=x
unit.2.0.waveform.posn.308.radix=1
unit.2.0.waveform.posn.308.type=bus
unit.2.0.waveform.posn.309.channel=2147483646
unit.2.0.waveform.posn.309.name=x
unit.2.0.waveform.posn.309.radix=1
unit.2.0.waveform.posn.309.type=bus
unit.2.0.waveform.posn.31.channel=186
unit.2.0.waveform.posn.31.name=ace_stb
unit.2.0.waveform.posn.31.radix=1
unit.2.0.waveform.posn.31.type=signal
unit.2.0.waveform.posn.32.channel=2147483646
unit.2.0.waveform.posn.32.name=d
unit.2.0.waveform.posn.310.channel=2147483646
unit.2.0.waveform.posn.310.name=x
unit.2.0.waveform.posn.310.radix=1
unit.2.0.waveform.posn.310.type=bus
unit.2.0.waveform.posn.311.channel=2147483646
unit.2.0.waveform.posn.311.name=x
unit.2.0.waveform.posn.311.radix=1
unit.2.0.waveform.posn.311.type=bus
unit.2.0.waveform.posn.312.channel=2147483646
unit.2.0.waveform.posn.312.name=x
unit.2.0.waveform.posn.312.radix=1
unit.2.0.waveform.posn.312.type=bus
unit.2.0.waveform.posn.313.channel=2147483646
unit.2.0.waveform.posn.313.name=x
unit.2.0.waveform.posn.313.radix=1
unit.2.0.waveform.posn.313.type=bus
unit.2.0.waveform.posn.314.channel=2147483646
unit.2.0.waveform.posn.314.name=x
unit.2.0.waveform.posn.314.radix=1
unit.2.0.waveform.posn.314.type=bus
unit.2.0.waveform.posn.315.channel=2147483646
unit.2.0.waveform.posn.315.name=x
unit.2.0.waveform.posn.315.radix=1
unit.2.0.waveform.posn.315.type=bus
unit.2.0.waveform.posn.316.channel=2147483646
unit.2.0.waveform.posn.316.name=y
unit.2.0.waveform.posn.316.radix=1
unit.2.0.waveform.posn.316.type=bus
unit.2.0.waveform.posn.32.channel=187
unit.2.0.waveform.posn.32.name=ace_ack
unit.2.0.waveform.posn.32.radix=1
unit.2.0.waveform.posn.32.type=bus
unit.2.0.waveform.posn.33.channel=2147483646
unit.2.0.waveform.posn.33.name=addr_d
unit.2.0.waveform.posn.32.type=signal
unit.2.0.waveform.posn.33.channel=188
unit.2.0.waveform.posn.33.name=aceusb_oe_n_
unit.2.0.waveform.posn.33.radix=1
unit.2.0.waveform.posn.33.type=bus
unit.2.0.waveform.posn.34.channel=94
unit.2.0.waveform.posn.34.name=byte_op
unit.2.0.waveform.posn.33.type=signal
unit.2.0.waveform.posn.34.channel=189
unit.2.0.waveform.posn.34.name=aceusb_we_n
unit.2.0.waveform.posn.34.radix=1
unit.2.0.waveform.posn.34.type=signal
unit.2.0.waveform.posn.35.channel=104
unit.2.0.waveform.posn.35.name=inta
unit.2.0.waveform.posn.35.channel=190
unit.2.0.waveform.posn.35.name=ace_mpce_n_
unit.2.0.waveform.posn.35.radix=1
unit.2.0.waveform.posn.35.type=signal
unit.2.0.waveform.posn.36.channel=105
unit.2.0.waveform.posn.36.name=intr
unit.2.0.waveform.posn.36.channel=2147483646
unit.2.0.waveform.posn.36.name=aceusb_d_
unit.2.0.waveform.posn.36.radix=1
unit.2.0.waveform.posn.36.type=signal
unit.2.0.waveform.posn.37.channel=2147483646
unit.2.0.waveform.posn.37.name=cnt_time
unit.2.0.waveform.posn.36.type=bus
unit.2.0.waveform.posn.37.channel=214
unit.2.0.waveform.posn.37.name=rx_output
unit.2.0.waveform.posn.37.radix=1
unit.2.0.waveform.posn.37.type=bus
unit.2.0.waveform.posn.38.channel=228
unit.2.0.waveform.posn.38.name=cpu_block
unit.2.0.waveform.posn.37.type=signal
unit.2.0.waveform.posn.38.channel=207
unit.2.0.waveform.posn.38.name=iid
unit.2.0.waveform.posn.38.radix=1
unit.2.0.waveform.posn.38.type=signal
unit.2.0.waveform.posn.39.channel=228
unit.2.0.waveform.posn.39.name=cpu_block
unit.2.0.waveform.posn.39.channel=208
unit.2.0.waveform.posn.39.name=irr0
unit.2.0.waveform.posn.39.radix=1
unit.2.0.waveform.posn.39.type=signal
unit.2.0.waveform.posn.4.channel=2147483646
3684,44 → 4428,44
unit.2.0.waveform.posn.4.name=state
unit.2.0.waveform.posn.4.radix=1
unit.2.0.waveform.posn.4.type=bus
unit.2.0.waveform.posn.40.channel=228
unit.2.0.waveform.posn.40.name=cpu_block
unit.2.0.waveform.posn.40.channel=209
unit.2.0.waveform.posn.40.name=irr1
unit.2.0.waveform.posn.40.radix=1
unit.2.0.waveform.posn.40.type=signal
unit.2.0.waveform.posn.41.channel=2147483646
unit.2.0.waveform.posn.41.name=adr
unit.2.0.waveform.posn.41.channel=210
unit.2.0.waveform.posn.41.name=int0
unit.2.0.waveform.posn.41.radix=1
unit.2.0.waveform.posn.41.type=bus
unit.2.0.waveform.posn.42.channel=2147483646
unit.2.0.waveform.posn.42.name=adr
unit.2.0.waveform.posn.41.type=signal
unit.2.0.waveform.posn.42.channel=211
unit.2.0.waveform.posn.42.name=int1
unit.2.0.waveform.posn.42.radix=1
unit.2.0.waveform.posn.42.type=bus
unit.2.0.waveform.posn.43.channel=2147483646
unit.2.0.waveform.posn.43.name=adr
unit.2.0.waveform.posn.42.type=signal
unit.2.0.waveform.posn.43.channel=212
unit.2.0.waveform.posn.43.name=released
unit.2.0.waveform.posn.43.radix=1
unit.2.0.waveform.posn.43.type=bus
unit.2.0.waveform.posn.44.channel=2147483646
unit.2.0.waveform.posn.44.name=adr
unit.2.0.waveform.posn.43.type=signal
unit.2.0.waveform.posn.44.channel=213
unit.2.0.waveform.posn.44.name=rx_shift
unit.2.0.waveform.posn.44.radix=1
unit.2.0.waveform.posn.44.type=bus
unit.2.0.waveform.posn.44.type=signal
unit.2.0.waveform.posn.45.channel=2147483646
unit.2.0.waveform.posn.45.name=adr
unit.2.0.waveform.posn.45.name=x
unit.2.0.waveform.posn.45.radix=1
unit.2.0.waveform.posn.45.type=bus
unit.2.0.waveform.posn.46.channel=2147483646
unit.2.0.waveform.posn.46.name=adr
unit.2.0.waveform.posn.46.name=x
unit.2.0.waveform.posn.46.radix=1
unit.2.0.waveform.posn.46.type=bus
unit.2.0.waveform.posn.47.channel=2147483646
unit.2.0.waveform.posn.47.name=adr
unit.2.0.waveform.posn.47.name=x
unit.2.0.waveform.posn.47.radix=1
unit.2.0.waveform.posn.47.type=bus
unit.2.0.waveform.posn.48.channel=2147483646
unit.2.0.waveform.posn.48.name=adr
unit.2.0.waveform.posn.48.name=x
unit.2.0.waveform.posn.48.radix=1
unit.2.0.waveform.posn.48.type=bus
unit.2.0.waveform.posn.49.channel=2147483646
unit.2.0.waveform.posn.49.name=adr
unit.2.0.waveform.posn.49.name=x
unit.2.0.waveform.posn.49.radix=1
unit.2.0.waveform.posn.49.type=bus
unit.2.0.waveform.posn.5.channel=2147483646
3729,43 → 4473,43
unit.2.0.waveform.posn.5.radix=1
unit.2.0.waveform.posn.5.type=bus
unit.2.0.waveform.posn.50.channel=2147483646
unit.2.0.waveform.posn.50.name=adr
unit.2.0.waveform.posn.50.name=x
unit.2.0.waveform.posn.50.radix=1
unit.2.0.waveform.posn.50.type=bus
unit.2.0.waveform.posn.51.channel=2147483646
unit.2.0.waveform.posn.51.name=adr
unit.2.0.waveform.posn.51.name=x
unit.2.0.waveform.posn.51.radix=1
unit.2.0.waveform.posn.51.type=bus
unit.2.0.waveform.posn.52.channel=2147483646
unit.2.0.waveform.posn.52.name=adr
unit.2.0.waveform.posn.52.name=x
unit.2.0.waveform.posn.52.radix=1
unit.2.0.waveform.posn.52.type=bus
unit.2.0.waveform.posn.53.channel=2147483646
unit.2.0.waveform.posn.53.name=adr
unit.2.0.waveform.posn.53.name=x
unit.2.0.waveform.posn.53.radix=1
unit.2.0.waveform.posn.53.type=bus
unit.2.0.waveform.posn.54.channel=2147483646
unit.2.0.waveform.posn.54.name=adr
unit.2.0.waveform.posn.54.name=x
unit.2.0.waveform.posn.54.radix=1
unit.2.0.waveform.posn.54.type=bus
unit.2.0.waveform.posn.55.channel=2147483646
unit.2.0.waveform.posn.55.name=adr
unit.2.0.waveform.posn.55.name=x
unit.2.0.waveform.posn.55.radix=1
unit.2.0.waveform.posn.55.type=bus
unit.2.0.waveform.posn.56.channel=2147483646
unit.2.0.waveform.posn.56.name=adr
unit.2.0.waveform.posn.56.name=x
unit.2.0.waveform.posn.56.radix=1
unit.2.0.waveform.posn.56.type=bus
unit.2.0.waveform.posn.57.channel=2147483646
unit.2.0.waveform.posn.57.name=adr
unit.2.0.waveform.posn.57.name=x
unit.2.0.waveform.posn.57.radix=1
unit.2.0.waveform.posn.57.type=bus
unit.2.0.waveform.posn.58.channel=2147483646
unit.2.0.waveform.posn.58.name=adr
unit.2.0.waveform.posn.58.name=x
unit.2.0.waveform.posn.58.radix=1
unit.2.0.waveform.posn.58.type=bus
unit.2.0.waveform.posn.59.channel=2147483646
unit.2.0.waveform.posn.59.name=adr
unit.2.0.waveform.posn.59.name=x
unit.2.0.waveform.posn.59.radix=1
unit.2.0.waveform.posn.59.type=bus
unit.2.0.waveform.posn.6.channel=2147483646
3773,43 → 4517,43
unit.2.0.waveform.posn.6.radix=1
unit.2.0.waveform.posn.6.type=bus
unit.2.0.waveform.posn.60.channel=2147483646
unit.2.0.waveform.posn.60.name=adr
unit.2.0.waveform.posn.60.name=x
unit.2.0.waveform.posn.60.radix=1
unit.2.0.waveform.posn.60.type=bus
unit.2.0.waveform.posn.61.channel=2147483646
unit.2.0.waveform.posn.61.name=adr
unit.2.0.waveform.posn.61.name=x
unit.2.0.waveform.posn.61.radix=1
unit.2.0.waveform.posn.61.type=bus
unit.2.0.waveform.posn.62.channel=2147483646
unit.2.0.waveform.posn.62.name=adr
unit.2.0.waveform.posn.62.name=x
unit.2.0.waveform.posn.62.radix=1
unit.2.0.waveform.posn.62.type=bus
unit.2.0.waveform.posn.63.channel=2147483646
unit.2.0.waveform.posn.63.name=adr
unit.2.0.waveform.posn.63.name=x
unit.2.0.waveform.posn.63.radix=1
unit.2.0.waveform.posn.63.type=bus
unit.2.0.waveform.posn.64.channel=2147483646
unit.2.0.waveform.posn.64.name=adr
unit.2.0.waveform.posn.64.name=x
unit.2.0.waveform.posn.64.radix=1
unit.2.0.waveform.posn.64.type=bus
unit.2.0.waveform.posn.65.channel=2147483646
unit.2.0.waveform.posn.65.name=adr
unit.2.0.waveform.posn.65.name=x
unit.2.0.waveform.posn.65.radix=1
unit.2.0.waveform.posn.65.type=bus
unit.2.0.waveform.posn.66.channel=2147483646
unit.2.0.waveform.posn.66.name=adr
unit.2.0.waveform.posn.66.name=x
unit.2.0.waveform.posn.66.radix=1
unit.2.0.waveform.posn.66.type=bus
unit.2.0.waveform.posn.67.channel=2147483646
unit.2.0.waveform.posn.67.name=adr
unit.2.0.waveform.posn.67.name=x
unit.2.0.waveform.posn.67.radix=1
unit.2.0.waveform.posn.67.type=bus
unit.2.0.waveform.posn.68.channel=2147483646
unit.2.0.waveform.posn.68.name=adr
unit.2.0.waveform.posn.68.name=x
unit.2.0.waveform.posn.68.radix=1
unit.2.0.waveform.posn.68.type=bus
unit.2.0.waveform.posn.69.channel=2147483646
unit.2.0.waveform.posn.69.name=adr
unit.2.0.waveform.posn.69.name=x
unit.2.0.waveform.posn.69.radix=1
unit.2.0.waveform.posn.69.type=bus
unit.2.0.waveform.posn.7.channel=2147483646
3817,43 → 4561,43
unit.2.0.waveform.posn.7.radix=1
unit.2.0.waveform.posn.7.type=bus
unit.2.0.waveform.posn.70.channel=2147483646
unit.2.0.waveform.posn.70.name=adr
unit.2.0.waveform.posn.70.name=x
unit.2.0.waveform.posn.70.radix=1
unit.2.0.waveform.posn.70.type=bus
unit.2.0.waveform.posn.71.channel=2147483646
unit.2.0.waveform.posn.71.name=adr
unit.2.0.waveform.posn.71.name=x
unit.2.0.waveform.posn.71.radix=1
unit.2.0.waveform.posn.71.type=bus
unit.2.0.waveform.posn.72.channel=2147483646
unit.2.0.waveform.posn.72.name=adr
unit.2.0.waveform.posn.72.name=x
unit.2.0.waveform.posn.72.radix=1
unit.2.0.waveform.posn.72.type=bus
unit.2.0.waveform.posn.73.channel=2147483646
unit.2.0.waveform.posn.73.name=adr
unit.2.0.waveform.posn.73.name=x
unit.2.0.waveform.posn.73.radix=1
unit.2.0.waveform.posn.73.type=bus
unit.2.0.waveform.posn.74.channel=2147483646
unit.2.0.waveform.posn.74.name=adr
unit.2.0.waveform.posn.74.name=x
unit.2.0.waveform.posn.74.radix=1
unit.2.0.waveform.posn.74.type=bus
unit.2.0.waveform.posn.75.channel=2147483646
unit.2.0.waveform.posn.75.name=adr
unit.2.0.waveform.posn.75.name=x
unit.2.0.waveform.posn.75.radix=1
unit.2.0.waveform.posn.75.type=bus
unit.2.0.waveform.posn.76.channel=2147483646
unit.2.0.waveform.posn.76.name=adr
unit.2.0.waveform.posn.76.name=x
unit.2.0.waveform.posn.76.radix=1
unit.2.0.waveform.posn.76.type=bus
unit.2.0.waveform.posn.77.channel=2147483646
unit.2.0.waveform.posn.77.name=adr
unit.2.0.waveform.posn.77.name=x
unit.2.0.waveform.posn.77.radix=1
unit.2.0.waveform.posn.77.type=bus
unit.2.0.waveform.posn.78.channel=2147483646
unit.2.0.waveform.posn.78.name=adr
unit.2.0.waveform.posn.78.name=x
unit.2.0.waveform.posn.78.radix=1
unit.2.0.waveform.posn.78.type=bus
unit.2.0.waveform.posn.79.channel=2147483646
unit.2.0.waveform.posn.79.name=adr
unit.2.0.waveform.posn.79.name=x
unit.2.0.waveform.posn.79.radix=1
unit.2.0.waveform.posn.79.type=bus
unit.2.0.waveform.posn.8.channel=2147483646
3861,43 → 4605,43
unit.2.0.waveform.posn.8.radix=1
unit.2.0.waveform.posn.8.type=bus
unit.2.0.waveform.posn.80.channel=2147483646
unit.2.0.waveform.posn.80.name=adr
unit.2.0.waveform.posn.80.name=x
unit.2.0.waveform.posn.80.radix=1
unit.2.0.waveform.posn.80.type=bus
unit.2.0.waveform.posn.81.channel=2147483646
unit.2.0.waveform.posn.81.name=adr
unit.2.0.waveform.posn.81.name=x
unit.2.0.waveform.posn.81.radix=1
unit.2.0.waveform.posn.81.type=bus
unit.2.0.waveform.posn.82.channel=2147483646
unit.2.0.waveform.posn.82.name=adr
unit.2.0.waveform.posn.82.name=x
unit.2.0.waveform.posn.82.radix=1
unit.2.0.waveform.posn.82.type=bus
unit.2.0.waveform.posn.83.channel=2147483646
unit.2.0.waveform.posn.83.name=adr
unit.2.0.waveform.posn.83.name=x
unit.2.0.waveform.posn.83.radix=1
unit.2.0.waveform.posn.83.type=bus
unit.2.0.waveform.posn.84.channel=2147483646
unit.2.0.waveform.posn.84.name=adr
unit.2.0.waveform.posn.84.name=x
unit.2.0.waveform.posn.84.radix=1
unit.2.0.waveform.posn.84.type=bus
unit.2.0.waveform.posn.85.channel=2147483646
unit.2.0.waveform.posn.85.name=adr
unit.2.0.waveform.posn.85.name=x
unit.2.0.waveform.posn.85.radix=1
unit.2.0.waveform.posn.85.type=bus
unit.2.0.waveform.posn.86.channel=2147483646
unit.2.0.waveform.posn.86.name=adr
unit.2.0.waveform.posn.86.name=x
unit.2.0.waveform.posn.86.radix=1
unit.2.0.waveform.posn.86.type=bus
unit.2.0.waveform.posn.87.channel=2147483646
unit.2.0.waveform.posn.87.name=adr
unit.2.0.waveform.posn.87.name=x
unit.2.0.waveform.posn.87.radix=1
unit.2.0.waveform.posn.87.type=bus
unit.2.0.waveform.posn.88.channel=2147483646
unit.2.0.waveform.posn.88.name=adr
unit.2.0.waveform.posn.88.name=x
unit.2.0.waveform.posn.88.radix=1
unit.2.0.waveform.posn.88.type=bus
unit.2.0.waveform.posn.89.channel=2147483646
unit.2.0.waveform.posn.89.name=adr
unit.2.0.waveform.posn.89.name=x
unit.2.0.waveform.posn.89.radix=1
unit.2.0.waveform.posn.89.type=bus
unit.2.0.waveform.posn.9.channel=2147483646
3905,42 → 4649,42
unit.2.0.waveform.posn.9.radix=1
unit.2.0.waveform.posn.9.type=bus
unit.2.0.waveform.posn.90.channel=2147483646
unit.2.0.waveform.posn.90.name=adr
unit.2.0.waveform.posn.90.name=x
unit.2.0.waveform.posn.90.radix=1
unit.2.0.waveform.posn.90.type=bus
unit.2.0.waveform.posn.91.channel=2147483646
unit.2.0.waveform.posn.91.name=adr
unit.2.0.waveform.posn.91.name=x
unit.2.0.waveform.posn.91.radix=1
unit.2.0.waveform.posn.91.type=bus
unit.2.0.waveform.posn.92.channel=2147483646
unit.2.0.waveform.posn.92.name=adr
unit.2.0.waveform.posn.92.name=x
unit.2.0.waveform.posn.92.radix=1
unit.2.0.waveform.posn.92.type=bus
unit.2.0.waveform.posn.93.channel=2147483646
unit.2.0.waveform.posn.93.name=adr
unit.2.0.waveform.posn.93.name=x
unit.2.0.waveform.posn.93.radix=1
unit.2.0.waveform.posn.93.type=bus
unit.2.0.waveform.posn.94.channel=2147483646
unit.2.0.waveform.posn.94.name=adr
unit.2.0.waveform.posn.94.name=x
unit.2.0.waveform.posn.94.radix=1
unit.2.0.waveform.posn.94.type=bus
unit.2.0.waveform.posn.95.channel=2147483646
unit.2.0.waveform.posn.95.name=adr
unit.2.0.waveform.posn.95.name=x
unit.2.0.waveform.posn.95.radix=1
unit.2.0.waveform.posn.95.type=bus
unit.2.0.waveform.posn.96.channel=2147483646
unit.2.0.waveform.posn.96.name=adr
unit.2.0.waveform.posn.96.name=x
unit.2.0.waveform.posn.96.radix=1
unit.2.0.waveform.posn.96.type=bus
unit.2.0.waveform.posn.97.channel=2147483646
unit.2.0.waveform.posn.97.name=adr
unit.2.0.waveform.posn.97.name=x
unit.2.0.waveform.posn.97.radix=1
unit.2.0.waveform.posn.97.type=bus
unit.2.0.waveform.posn.98.channel=2147483646
unit.2.0.waveform.posn.98.name=adr
unit.2.0.waveform.posn.98.name=x
unit.2.0.waveform.posn.98.radix=1
unit.2.0.waveform.posn.98.type=bus
unit.2.0.waveform.posn.99.channel=2147483646
unit.2.0.waveform.posn.99.name=adr
unit.2.0.waveform.posn.99.name=x
unit.2.0.waveform.posn.99.radix=1
unit.2.0.waveform.posn.99.type=bus
/impl/virtex4-ml403ep/sim/test_kotku.v
9,6 → 9,7
wire lcd_vsync;
reg clk;
reg but;
reg ace_clk;
wire s_clk;
wire [20:0] sf_addr;
wire [31:0] sf_data;
19,6 → 20,14
wire s_adv;
wire f_ce;
 
wire [ 6:1] aceusb_a_;
wire [15:0] aceusb_d_;
wire aceusb_oe_n_;
wire aceusb_we_n_;
wire ace_mpce_n_;
wire usb_cs_n_;
wire usb_hpi_reset_n_;
 
// Module instances
kotku_ml403 kotku (
.tft_lcd_clk_ (lcd_clk),
38,13 → 47,18
.sram_bw_ (s_bw),
.sram_cen_ (s_ce),
.sram_adv_ld_n_ (s_adv),
.flash_ce2_ (f_ce) /*,
.flash_ce2_ (f_ce),
 
.butc_ (but),
.bute_ (1'b0),
.butw_ (1'b0),
.butn_ (1'b0),
.buts_ (1'b0) */
.aceusb_a_ (aceusb_a_),
.aceusb_d_ (aceusb_d_),
.aceusb_oe_n_ (aceusb_oe_n_),
.aceusb_we_n_ (aceusb_we_n_),
 
.ace_clkin_ (ace_clk),
.ace_mpce_n_ (ace_mpce_n_),
 
.usb_cs_n_ (usb_cs_n_),
.usb_hpi_reset_n_ (usb_hpi_reset_n_)
);
 
flash_stub fs0 (
72,11 → 86,13
 
// Behaviour
// Clock generation
always #5 clk = ~clk;
always #5 clk = ~clk;
always #15 ace_clk = ~ace_clk;
 
initial
begin
clk <= 1'b1;
clk <= 1'b0;
ace_clk <= 1'b0;
but <= 1'b0;
#100000 but <= 1'b1;
#700000 but <= 1'b0;
/impl/virtex4-ml403ep/sim/t.do
2,7 → 2,7
vdel -all -lib work
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
vlib work
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../../../soc/aceusb/rtl/aceusb_access.v ../../../soc/aceusb/rtl/aceusb_sync.v ../../../soc/aceusb/rtl/aceusb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl
add wave -label clk100 /testbench/clk
65,6 → 65,6
add wave -label we /testbench/kotku/we
add wave -label ack /testbench/kotku/ack
add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec
add wave -divider vdu
add wave -radix hexadecimal -r /testbench/kotku/vdu0/*
run 35us
add wave -divider ace_cf
add wave -radix hexadecimal -r /testbench/kotku/ace_cf/*
run 1ms
/impl/virtex4-ml403ep/sim/flash_stub.v
16,7 → 16,7
assign flash_data_ = flash_ce2_ ? dat_o : 32'hzzzzzzzz;
 
// Behaviour
initial $readmemh("00_test2.ml403", rom, 21'h0);
initial $readmemh("22_sysace.ml403", rom, 21'h0);
initial $readmemh("hd.ml403", rom, 21'h100000);
 
always @(*) dat_o <= #110
/impl/virtex4-ml403ep/syn/clock.v
1,4 → 1,6
module clock (
module clock #(
parameter div = 16 // main clock divider
) (
input sys_clk_in_,
output clk,
output clk_100M,
59,7 → 61,7
.LOCKED (fpga_lock)
);
defparam fpga_dcm.CLKIN_PERIOD = 10.000;
defparam fpga_dcm.CLKDV_DIVIDE = 16;
defparam fpga_dcm.CLKDV_DIVIDE = div;
defparam fpga_dcm.DCM_AUTOCALIBRATION = "FALSE";
 
BUFG b_fpga_fb (
/impl/virtex4-ml403ep/syn/kotku-dbg.prj
15,6 → 15,9
verilog work "../../../../rtl-model/exec.v"
verilog work "../../../../soc/vga/rtl/vdu.v"
verilog work "../../../../soc/keyb/rtl/ps2_keyb.v"
verilog work "../../../../soc/aceusb/rtl/aceusb_access.v"
verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v"
verilog work "../../../../soc/aceusb/rtl/aceusb.v"
verilog work "../../../../soc/timer.v"
verilog work "../../../../rtl-model/cpu.v"
verilog work "../../mem/zbt_cntrl.v"
/impl/virtex4-ml403ep/syn/kotku.v
21,18 → 21,18
 
module kotku_ml403 (
`ifdef DEBUG
(* LOC="B6" *) input butc_,
(* LOC="F10" *) input bute_,
(* LOC="E9" *) input butw_,
(* LOC="E7" *) input butn_,
(* LOC="A6" *) input buts_,
`endif
output rs_,
output rw_,
output e_,
output [7:4] db_,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
output [ 7:4] db_,
 
output trx_,
`endif
 
output tft_lcd_clk_,
output [ 1:0] tft_lcd_r_,
54,7 → 54,18
output flash_ce2_,
 
inout ps2_clk_,
inout ps2_data_
inout ps2_data_,
 
output [ 6:1] aceusb_a_,
inout [15:0] aceusb_d_,
output aceusb_oe_n_,
output aceusb_we_n_,
 
input ace_clkin_,
output ace_mpce_n_,
 
output usb_cs_n_,
output usb_hpi_reset_n_
);
 
// Net declarations
111,6 → 122,15
wire [ 1:0] zbt_sel_i;
wire zbt_stb_i;
 
wire [15:0] ace_dat_o;
wire ace_ack;
wire ace_stb;
wire ace_io_arena;
wire ace_arena;
 
wire [ 1:0] int;
wire iid;
 
`ifdef DEBUG
reg [31:0] cnt_time;
wire [35:0] control0;
161,6 → 181,12
wire end_seq;
wire ext_int;
wire cpu_block2;
 
wire [ 1:0] irr;
 
wire rx_output_strobe;
wire rx_shifting_done;
wire released;
`endif
 
// Register declarations
169,7 → 195,9
reg [ 1:0] vdu_ack_sync;
 
// Module instantiations
clock c0 (
clock #(
.div (8)
) c0 (
.clk_100M (clk_100M),
.sys_clk_in_ (sys_clk_in_),
.clk (sys_clk),
187,8 → 215,8
.wb_we_i (vdu_we_i),
.wb_tga_i (vdu_tga_i),
.wb_sel_i (vdu_sel_i),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_stb_i (vdu_stb_i),
.wb_cyc_i (vdu_stb_i),
.wb_ack_o (vdu_ack_o),
 
// VGA pad signals
199,8 → 227,10
.vert_sync (tft_lcd_vsync_)
);
 
flash_cntrl fc0 (
// Wishbone slave interface
flash_cntrl #(
.timeout (4)
) fc0 (
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
245,29 → 275,69
.sram_adv_ld_n_ (sram_adv_ld_n_)
);
 
ps2_keyb #(5900, // number of clks for 60usec.
13, // number of bits needed for 60usec. timer
126, // number of clks for debounce
7, // number of bits needed for debounce timer
0 // Trap the shift keys, no event generated
ps2_keyb #(1500, // number of clks for 60usec.
11, // number of bits needed for 60usec. timer
120, // number of clks for debounce
7 // number of bits needed for debounce timer
) keyboard0 ( // Instance name
.wb_clk_i (clk_100M),
`ifdef DEBUG
.rx_output_strobe (rx_output_strobe),
.rx_shifting_done (rx_shifting_done),
.released (released),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_o (keyb_dat_o),
.wb_tgc_o (intr),
.wb_tgc_i (inta),
.wb_tgc_o (int[1]),
 
.ps2_clk_ (ps2_clk_),
.ps2_data_ (ps2_data_)
);
/*
timer timer0 (
 
timer #(
.res (34),
.phase (12507)
) timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intr),
.wb_tgc_i (inta)
.wb_tgc_o (int[0])
);
*/
 
simple_pic pic0 (
`ifdef DEBUG
.irr (irr),
`endif
.clk (clk),
.rst (rst),
.int (int),
.inta (inta),
.intr (intr),
.iid (iid)
);
 
aceusb ace_cf (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (adr[6:1]),
.wb_dat_i (dat_o),
.wb_dat_o (ace_dat_o),
.wb_cyc_i (ace_stb),
.wb_stb_i (ace_stb),
.wb_we_i (we),
.wb_ack_o (ace_ack),
 
.aceusb_a_ (aceusb_a_),
.aceusb_d_ (aceusb_d_),
.aceusb_oe_n_ (aceusb_oe_n_),
.aceusb_we_n_ (aceusb_we_n_),
 
.ace_clkin_ (ace_clkin_),
.ace_mpce_n_ (ace_mpce_n_),
 
.usb_cs_n_ (usb_cs_n_),
.usb_hpi_reset_n_ (usb_hpi_reset_n_)
);
 
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
330,19 → 400,16
.TRIG4 (funct),
.TRIG5 ({state,next_state}),
.TRIG6 ({intr,inta,flags,byte_op,addr_d}),
// .TRIG7 (imm),
// .TRIG7 (tr_dat[15:0]),
.TRIG7 (d),
.TRIG8 ({x,y}),
.TRIG9 (aluo),
.TRIG10 (sram_flash_addr_),
.TRIG11 (sram_flash_data_),
.TRIG12 ({sram_flash_oe_n_, sram_flash_we_n_, sram_bw_,
sram_cen_, sram_adv_ld_n_, flash_ce2_}),
.TRIG10 ({ace_mpce_n_,aceusb_we_n_,aceusb_oe_n_,
ace_ack,ace_stb,ace_dat_o}),
.TRIG11 (aceusb_d_),
.TRIG12 ({1'b0,rx_output_strobe,rx_shifting_done,released,int,irr,iid}),
.TRIG13 (cnt),
.TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}),
.TRIG15 (cnt_time)
// .TRIG15 ({block,trx_,rst2,rst,tr_ack,tr_stb,tr_st,tr_new_pc,addr_st,11'h0,pack,old_zet_st,tr_dat[19:16]})
);
 
lcd_display lcd0 (
363,7 → 430,7
 
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst2),
.rst_lck (rst_lck),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
448,19 → 515,28
assign zbt_sel_i = sel;
assign zbt_stb_i = zbt_stb;
assign rst2 = rst_lck;
 
assign rs_ = 1'b1;
assign e_ = 1'b0;
assign rw_ = 1'b1;
assign db_ = 4'h0;
assign trx_ = 1'b1;
`endif
 
`ifdef DEBUG_TRACE
assign clk = clk_921600;
`else
assign clk = sys_clk;
// assign clk = sys_clk;
assign clk = tft_lcd_clk_;
`endif
 
assign io_dat_i = flash_io_arena ? flash_dat_o
: (vdu_io_arena ? vdu_dat_o
: (keyb_io_arena ? keyb_dat_o
: (keyb_io_status ? 16'h10 : 16'h0)));
assign dat_i = inta ? 16'd9 : (tga ? io_dat_i
: (keyb_io_status ? 16'h10
: (ace_io_arena ? ace_dat_o : 16'h0))));
assign dat_i = inta ? { 15'b0000_0000_0000_100, iid }
: (tga ? io_dat_i
: (vdu_mem_arena ? vdu_dat_o
: (flash_mem_arena ? flash_dat_o : zbt_dat_o)));
 
473,6 → 549,7
|| (adr[3:1]==3'h5 && !we));
 
assign keyb_io_arena = (adr[15:1]==15'h0030 && !we);
assign ace_io_arena = (adr[15:7]==9'b1110_0010_0);
 
// MS-DOS is reading IO address 0x64 to check the inhibit bit
assign keyb_io_status = (adr[15:1]==15'h0032 && !we);
482,14 → 559,17
assign vdu_arena = (!tga & vdu_mem_arena)
| (tga & vdu_io_arena);
assign keyb_arena = (tga & keyb_io_arena);
assign ace_arena = (tga & ace_io_arena);
 
assign flash_stb = flash_arena & stb & cyc;
assign zbt_stb = !vdu_mem_arena & !flash_mem_arena
& !tga & stb & cyc;
assign ace_stb = ace_arena & stb & cyc;
 
assign ack = tga ? (flash_io_arena ? flash_ack
: (vdu_io_arena ? vdu_ack_sync[1] : (stb & cyc)))
: (vdu_mem_arena ? vdu_ack_sync[1]
: (vdu_io_arena ? vdu_ack_o
: (ace_io_arena ? ace_ack : (stb & cyc))))
: (vdu_mem_arena ? vdu_ack_o
: (flash_mem_arena ? flash_ack : zbt_ack));
 
assign sram_flash_oe_n_ = 1'b0;
/impl/virtex4-ml403ep/syn/kotku.prj
13,6 → 13,11
verilog work "../../../../rtl-model/exec.v"
verilog work "../../../../soc/vga/rtl/vdu.v"
verilog work "../../../../soc/keyb/rtl/ps2_keyb.v"
verilog work "../../../../soc/aceusb/rtl/aceusb_access.v"
verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v"
verilog work "../../../../soc/aceusb/rtl/aceusb.v"
verilog work "../../../../soc/timer.v"
verilog work "../../../../soc/simple_pic.v"
verilog work "../../../../rtl-model/cpu.v"
verilog work "../../mem/zbt_cntrl.v"
verilog work "../../mem/flash_cntrl.v"
/impl/virtex4-ml403ep/syn/ml403.ucf
5,6 → 5,9
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
 
NET sram_clk_ LOC = AF7 ;
NET "sram_clk_" IOSTANDARD = LVCMOS33;
NET "sram_clk_" DRIVE = 16;
NET "sram_clk_" SLEW = FAST;
 
#NET sram_flash_addr_[24] LOC = T21;
#NET sram_flash_addr_[23] LOC = U20;
32,6 → 35,10
NET sram_flash_addr_[0] LOC = Y1;
#NET sram_flash_addr_[0] LOC = T20;
 
NET "sram_flash_addr_<*>" IOSTANDARD = LVDCI_33;
NET "sram_flash_addr_<*>" SLEW = FAST;
NET "sram_flash_addr_<*>" DRIVE = 8;
 
NET sram_flash_data_[31] LOC = F14;
NET sram_flash_data_[30] LOC = F13;
NET sram_flash_data_[29] LOC = F12;
65,22 → 72,46
NET sram_flash_data_[1] LOC = AC13;
NET sram_flash_data_[0] LOC = AD13;
 
NET "sram_flash_data_<*>" IOSTANDARD = LVCMOS33;
NET "sram_flash_data_<*>" PULLDOWN;
 
NET sram_flash_oe_n_ LOC = AC6;
NET "sram_flash_oe_n_" IOSTANDARD = LVDCI_33;
NET "sram_flash_oe_n_" SLEW = FAST;
NET "sram_flash_oe_n_" DRIVE = 8;
 
NET sram_flash_we_n_ LOC = AB6;
NET "sram_flash_we_n_" IOSTANDARD = LVDCI_33;
NET "sram_flash_we_n_" SLEW = FAST;
NET "sram_flash_we_n_" DRIVE = 8;
 
NET sram_bw_[3] LOC = Y3; #Y4;
NET sram_bw_[2] LOC = Y4; #Y3;
NET sram_bw_[1] LOC = Y5; #Y6;
NET sram_bw_[0] LOC = Y6; #Y5;
NET "sram_bw_<*>" IOSTANDARD = LVDCI_33;
NET "sram_bw_<*>" SLEW = FAST;
NET "sram_bw_<*>" DRIVE = 8;
 
NET sram_cen_ LOC = V7;
NET "sram_cen_" IOSTANDARD = LVDCI_33;
NET "sram_cen_" SLEW = FAST;
NET "sram_cen_" DRIVE = 8;
 
NET sram_adv_ld_n_ LOC = W4;
NET "sram_adv_ld_n_" IOSTANDARD = LVDCI_33;
NET "sram_adv_ld_n_" SLEW = FAST;
NET "sram_adv_ld_n_" DRIVE = 8;
 
NET flash_ce2_ LOC = W7;
NET "flash_ce2_" IOSTANDARD = LVDCI_33;
NET "flash_ce2_" SLEW = FAST;
NET "flash_ce2_" DRIVE = 8;
 
#NET flash_byte_n LOC = N22;
#NET flash_audio_reset_n LOC = AD10;
 
NET tft_lcd_clk_ LOC = AF8;
NET tft_lcd_clk_ LOC = AF8 | IOSTANDARD = LVCMOS33;
NET tft_lcd_r_[0] LOC = E5 | SLEW = FAST | DRIVE = 8; # VGA_R6
NET tft_lcd_r_[1] LOC = E6 | SLEW = FAST | DRIVE = 8; # VGA_R7
NET tft_lcd_g_[0] LOC = H8 | SLEW = FAST | DRIVE = 8; # VGA_G6
99,14 → 130,14
NET tft_lcd_vsync_ SLEW = FAST;
NET tft_lcd_vsync_ DRIVE = 8;
 
#NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
#NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
#NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
 
#NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
#NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
#NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
#NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
#NET butc_ LOC = B6; # C Button
#NET butw_ LOC = E9; # W Button
114,7 → 145,7
#NET butn_ LOC = E7; # N Button
#NET buts_ LOC = A6; # S Button
 
#NET trx_ LOC = W1;
NET trx_ LOC = W1 | IOSTANDARD = LVCMOS33;
 
#NET led_[0] LOC = G5; #GPLED0
#NET led_[1] LOC = G6; #GPLED1
137,3 → 168,43
NET ps2_data_ SLEW = SLOW;
NET ps2_data_ DRIVE = 2;
NET ps2_data_ TIG;
 
# Shared signals
NET "aceusb_a_<1>" LOC = Y10;
NET "aceusb_a_<2>" LOC = AA10;
NET "aceusb_a_<3>" LOC = AC7;
NET "aceusb_a_<4>" LOC = Y7;
NET "aceusb_a_<5>" LOC = AA9;
NET "aceusb_a_<6>" LOC = Y9;
NET "aceusb_a_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "aceusb_d_<0>" LOC = AB7;
NET "aceusb_d_<1>" LOC = AC9;
NET "aceusb_d_<2>" LOC = AB9;
NET "aceusb_d_<3>" LOC = AE6;
NET "aceusb_d_<4>" LOC = AD6;
NET "aceusb_d_<5>" LOC = AF9;
NET "aceusb_d_<6>" LOC = AE9;
NET "aceusb_d_<7>" LOC = AD8;
NET "aceusb_d_<8>" LOC = AC8;
NET "aceusb_d_<9>" LOC = AF4;
NET "aceusb_d_<10>" LOC = AE4;
NET "aceusb_d_<11>" LOC = AD3;
NET "aceusb_d_<12>" LOC = AC3;
NET "aceusb_d_<13>" LOC = AF6;
NET "aceusb_d_<14>" LOC = AF5;
NET "aceusb_d_<15>" LOC = AA7;
NET "aceusb_d_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN;
NET "aceusb_oe_n_" LOC = AA8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "aceusb_we_n_" LOC = Y8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
 
# SystemACE signals
NET "ace_clkin_" LOC = AF11;
NET "ace_clkin_" IOSTANDARD = LVCMOS33;
NET "ace_clkin_" TNM_NET = "ace_clkin_";
TIMESPEC "TSace" = PERIOD "ace_clkin_" 30 ns HIGH 50% INPUT_JITTER 1 ns;
 
NET "ace_mpce_n_" LOC = AD5 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
 
# USB signals
NET "usb_cs_n_" LOC = AF10 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "usb_hpi_reset_n_" LOC = A7 | IOSTANDARD = LVCMOS25 | TIG;
/impl/virtex4-ml403ep/mem/flash_cntrl.v
16,18 → 16,20
* <http://www.gnu.org/licenses/>.
*/
 
module flash_cntrl (
module flash_cntrl #(
parameter timeout = 2 // read timeout (default: 2 cycles)
) (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
 
// Pad signals
output reg [20:0] flash_addr_,
37,7 → 39,9
);
 
// Registers and nets
reg [11:0] base;
reg [ 11:0] base;
reg [timeout-1:0] sft_cnt;
 
wire op;
wire opbase;
 
46,6 → 50,7
assign flash_we_n_ = 1'b1;
assign op = wb_cyc_i & wb_stb_i;
assign opbase = op & wb_tga_i & wb_we_i;
assign wb_ack_o = sft_cnt[timeout-1];
 
// Behaviour
// flash_addr, 21 bits
54,8 → 59,12
: { 5'h0, wb_adr_i[16:1] };
 
always @(posedge wb_clk_i) flash_ce2_ <= op;
always @(posedge wb_clk_i) wb_ack_o <= op;
 
// sft_cnt
always @(posedge wb_clk_i)
sft_cnt <= wb_rst_i ? 0
: (op ? { sft_cnt[timeout-2:0], op } : 0);
 
// base
always @(posedge wb_clk_i)
base <= wb_rst_i ? 12'h0: ((opbase) ? wb_dat_i[11:0] : base);
/tests/22_sysace.s
0,0 → 1,156
.code16
start:
 
# CSR_ACE_BUSMODE = ACE_BUSMODE_16BIT;
movw $0xe200, %dx
movw $0x0001, %ax
outw %ax, %dx
 
# if(!(CSR_ACE_STATUSL & ACE_STATUSL_CFDETECT)) return 0;
movw $0xe204, %dx
inw %dx, %ax
andw $0x0010, %ax
jne cf_detect
movw $0x2, (0)
hlt
cf_detect:
 
# if((CSR_ACE_ERRORL != 0) || (CSR_ACE_ERRORH != 0)) return 0;
movw $0xe208, %dx
inw %dx, %ax
cmpw $0x0, %ax
jne error_l
 
movw $0xe20a, %dx
inw %dx, %ax
cmpw $0x0, %ax
je lock_req
error_l:
movw $0x3, (0)
hlt
lock_req:
 
# CSR_ACE_CTLL |= ACE_CTLL_LOCKREQ;
movw $0xe218, %dx
inw %dx, %ax
orw $0x2, %ax
outw %ax, %dx
 
# timeout = TIMEOUT;
movw $0xffff, %cx
 
# while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_MPULOCK))) timeout--;
movw $0xe204, %dx
ace_statusl:
inw %dx, %ax
andw $0x2, %ax
loopz ace_statusl
 
# if(timeout == 0) return 0;
cmpw $0x0, %cx
jnz success
movw $0x4, (0)
hlt
 
success:
# We are going to read the first block
xor %bx, %bx
 
# timeout = TIMEOUT;
movw $0xffff, %cx
 
# while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_CFCMDRDY))) timeout--;
movw $0xe204, %dx
ace_statusl2:
inw %dx, %ax
andw $0x100, %ax
loopz ace_statusl2
 
# if(timeout == 0) return 0;
cmpw $0x0, %cx
jnz success2
movw $0x5, (0)
hlt
 
success2:
movw $0x4, (2)
# CSR_ACE_MLBAL = blocknr & 0x0000ffff;
# CSR_ACE_MLBAH = (blocknr & 0x0fff0000) >> 16;
xorw %ax, %ax
movw $0xe210, %dx
outw %ax, %dx
movw $0xe212, %dx
outw %ax, %dx
 
movw $0x5, (2)
# CSR_ACE_SECCMD = ACE_SECCMD_READ|0x01;
movw $0x0301, %ax
movw $0xe214, %dx
outw %ax, %dx
 
movw $0x6, (2)
# CSR_ACE_CTLL |= ACE_CTLL_CFGRESET;
movw $0xe218, %dx
inw %dx, %ax
orw $0x0080, %ax
outw %ax, %dx
 
movw $0x7, (2)
# buffer_count = 16;
movw $16, %si
 
movw $0x8, (2)
# while(buffer_count > 0) {
cond_loop:
cmpw $0, %si
jbe exit_loop
 
# timeout = TIMEOUT;
movw $0xffff, %cx
 
# while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_DATARDY))) timeout--;
movw $0xe204, %dx
ace_statusl3:
inw %dx, %ax
andw $0x20, %ax
loopz ace_statusl3
 
# if(timeout == 0) return 0;
cmpw $0x0, %cx
jnz success3
movw $0x6, (0)
hlt
 
success3:
# for(i=0;i<16;i++) {
movw $16, %cx
# *bufw = CSR_ACE_DATA;
movw $0xe240, %dx
ace_data:
inw %dx, %ax
movw %ax, (%bx)
# bufw++;
addw $2, %bx
# }
loop ace_data
 
# buffer_count--;
decw %si
jmp cond_loop
 
# }
exit_loop:
 
# CSR_ACE_CTLL &= ~ACE_CTLL_CFGRESET;
movw $0xe218, %dx
inw %dx, %ax
andw $0xff7f, %ax
outw %ax, %dx
 
hlt
 
.org 65520
jmp start
.org 65535
.byte 0xff
 
/soc/aceusb/rtl/aceusb_sync.v
0,0 → 1,48
/*
* WISHBONE to SystemACE MPU + CY7C67300 bridge
* Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net
* This file is part of Milkymist.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
 
/* Flag synchronizer from clock domain 0 to 1
* See http://www.fpga4fun.com/CrossClockDomain.html
*/
 
module aceusb_sync(
input clk0,
input flagi,
input clk1,
output flago
);
 
/* Turn the flag into a level change */
reg toggle;
initial toggle = 1'b0;
always @(posedge clk0)
if(flagi) toggle <= ~toggle;
 
/* Synchronize the level change to clk1.
* We add a third flip-flop to be able to detect level changes. */
reg [2:0] sync;
initial sync = 3'b000;
always @(posedge clk1)
sync <= {sync[1:0], toggle};
 
/* Recreate the flag from the level change into the clk1 domain */
assign flago = sync[2] ^ sync[1];
 
endmodule
/soc/aceusb/rtl/aceusb.v
0,0 → 1,170
/*
* WISHBONE to SystemACE MPU + CY7C67300 bridge
* Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net
* Modified on Mar 2009 by Zeus Gomez Marmolejo <zeus@opencores.org>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
 
module aceusb (
/* WISHBONE slave interface */
input wb_clk_i,
input wb_rst_i,
input [ 6:1] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
 
/* Signals shared between SystemACE and USB */
output [ 6:1] aceusb_a_,
inout [15:0] aceusb_d_,
output aceusb_oe_n_,
output aceusb_we_n_,
 
/* SystemACE signals */
input ace_clkin_,
output ace_mpce_n_,
 
output usb_cs_n_,
output usb_hpi_reset_n_
);
 
wire access_read1;
wire access_write1;
wire access_ack1;
 
/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
reg load_adr_dat;
reg [5:0] address_reg;
reg [15:0] data_reg;
always @(posedge wb_clk_i) begin
if(load_adr_dat) begin
address_reg <= wb_adr_i;
data_reg <= wb_dat_i;
end
end
 
aceusb_access access(
.ace_clkin(ace_clkin_),
.rst(wb_rst_i),
.a(address_reg),
.di(data_reg),
.do(wb_dat_o),
.read(access_read1),
.write(access_write1),
.ack(access_ack1),
 
.aceusb_a(aceusb_a_),
.aceusb_d(aceusb_d_),
.aceusb_oe_n(aceusb_oe_n_),
.aceusb_we_n(aceusb_we_n_),
.ace_mpce_n(ace_mpce_n_),
.usb_cs_n(usb_cs_n_),
.usb_hpi_reset_n(usb_hpi_reset_n_)
);
 
/* Synchronize read, write and acknowledgement pulses */
reg access_read;
reg access_write;
wire access_ack;
wire op;
 
aceusb_sync sync_read(
.clk0(wb_clk_i),
.flagi(access_read),
.clk1(ace_clkin_),
.flago(access_read1)
);
 
aceusb_sync sync_write(
.clk0(wb_clk_i),
.flagi(access_write),
.clk1(ace_clkin_),
.flago(access_write1)
);
 
aceusb_sync sync_ack(
.clk0(ace_clkin_),
.flagi(access_ack1),
.clk1(wb_clk_i),
.flago(access_ack)
);
 
/* Main FSM */
 
reg [1:0] state;
reg [1:0] next_state;
 
localparam
IDLE = 2'd0,
WAIT = 2'd1,
ACK = 2'd2;
 
assign op = wb_cyc_i & wb_stb_i;
 
always @(posedge wb_clk_i) begin
if(wb_rst_i)
state <= IDLE;
else
state <= next_state;
end
 
always @(state or op or wb_we_i or access_ack) begin
load_adr_dat = 1'b0;
wb_ack_o = 1'b0;
access_read = 1'b0;
access_write = 1'b0;
next_state = state;
case(state)
IDLE: begin
if(op) begin
load_adr_dat = 1'b1;
if(wb_we_i)
access_write = 1'b1;
else
access_read = 1'b1;
next_state = WAIT;
end
end
 
WAIT: begin
if(access_ack) begin
wb_ack_o = 1'b1;
access_write = 1'b0;
load_adr_dat = 1'b0;
access_read = 1'b0;
next_state = ACK;
end
end
 
ACK: begin
if(!op) begin
wb_ack_o = 1'b0;
next_state = IDLE;
end
end
endcase
end
 
endmodule
/soc/aceusb/rtl/aceusb_access.v
0,0 → 1,137
/*
* WISHBONE to SystemACE MPU + CY7C67300 bridge
* Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net
* This file is part of Milkymist.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
 
module aceusb_access(
/* Control */
input ace_clkin,
input rst,
input [5:0] a,
input [15:0] di,
output reg [15:0] do,
input read,
input write,
output reg ack,
 
/* SystemACE/USB interface */
output [6:1] aceusb_a,
inout [15:0] aceusb_d,
output reg aceusb_oe_n,
output reg aceusb_we_n,
 
output reg ace_mpce_n,
 
output usb_cs_n,
output usb_hpi_reset_n
);
 
/* USB is not supported yet. Disable the chip. */
assign usb_cs_n = 1'b1;
assign usb_hpi_reset_n = 1'b1;
 
/* 16-bit mode only */
assign aceusb_a = a;
 
reg d_drive;
assign aceusb_d = d_drive ? di : 16'hzz;
 
reg d_drive_r;
reg aceusb_oe_n_r;
reg aceusb_we_n_r;
reg ace_mpce_n_r;
always @(posedge ace_clkin) begin
d_drive <= d_drive_r;
aceusb_oe_n <= aceusb_oe_n_r;
aceusb_we_n <= aceusb_we_n_r;
ace_mpce_n <= ace_mpce_n_r;
end
 
reg d_in_sample;
always @(posedge ace_clkin)
if(d_in_sample)
do <= aceusb_d;
 
reg [2:0] state;
reg [2:0] next_state;
 
localparam
IDLE = 3'd0,
READ = 3'd1,
READ1 = 3'd2,
READ2 = 3'd3,
WRITE = 3'd4,
ACK = 3'd5;
 
always @(posedge ace_clkin) begin
if(rst)
state <= IDLE;
else
state <= next_state;
end
 
always @(state or read or write) begin
d_drive_r = 1'b0;
aceusb_oe_n_r = 1'b1;
aceusb_we_n_r = 1'b1;
ace_mpce_n_r = 1'b1;
d_in_sample = 1'b0;
ack = 1'b0;
next_state = state;
case(state)
IDLE: begin
if(read) begin
ace_mpce_n_r = 1'b0;
next_state = READ;
end
if(write) begin
ace_mpce_n_r = 1'b0;
next_state = WRITE;
end
end
READ: begin
ace_mpce_n_r = 1'b0;
next_state = READ1;
end
READ1: begin
ace_mpce_n_r = 1'b0;
aceusb_oe_n_r = 1'b0;
next_state = READ2;
end
READ2: begin
d_in_sample = 1'b1;
next_state = ACK;
end
WRITE: begin
d_drive_r = 1'b1;
ace_mpce_n_r = 1'b0;
aceusb_we_n_r = 1'b0;
next_state = ACK;
end
ACK: begin
ack = 1'b1;
next_state = IDLE;
end
endcase
end
 
endmodule
/soc/timer.v
1,36 → 1,40
module timer (
/*
* Phase accumulator clock:
* Fo = Fc * N / 2^bits
* here N: 12507 and bits: 32
* it gives a frequency of 18.200080376 Hz
*/
 
module timer #(
parameter res = 33, // bit resolution (default: 33 bits)
parameter phase = 12507 // phase value for the counter
)
(
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
output reg wb_tgc_o, // intr
input wb_tgc_i // inta
output reg wb_tgc_o // intr
);
 
// Registers and nets
reg [17:0] cnt;
reg old_clk2;
reg pulse;
wire clk2;
reg [res-1:0] cnt;
reg old_clk2;
wire clk2;
 
// Continuous assignments
assign clk2 = cnt[17];
assign clk2 = cnt[res-1];
 
// Behaviour
// cnt
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 18'h00 : (cnt + 18'h1);
cnt <= wb_rst_i ? 0 : (cnt + phase);
 
// old_clk2
always @(posedge wb_clk_i)
old_clk2 <= wb_rst_i ? 1'b0 : clk2;
 
// pulse
// intr
always @(posedge wb_clk_i)
pulse <= wb_rst_i ? 1'b0 : (clk2!=old_clk2);
wb_tgc_o <= wb_rst_i ? 1'b0 : (!old_clk2 & clk2);
 
// intr
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0
: ((pulse & !wb_tgc_i) ? 1'b1
: (wb_tgc_o ? !wb_tgc_i : 1'b0));
endmodule
/soc/simple_pic.v
0,0 → 1,35
`include "defines.v"
 
module simple_pic (
`ifdef DEBUG
output reg [1:0] irr,
`endif
input clk,
input rst,
input [1:0] int,
input inta,
output intr,
output reg iid
);
 
// Registers
`ifndef DEBUG
reg [1:0] irr;
`endif
 
// Continuous assignments
assign intr = |irr;
 
// Behaviour
// irr
always @(posedge clk)
irr[0] <= rst ? 1'b0 : (int[0] | irr[0] & (iid | !inta));
 
always @(posedge clk)
irr[1] <= rst ? 1'b0 : (int[1] | irr[1] & !(iid & inta));
 
// iid
always @(posedge clk)
iid <= rst ? 1'b0 : (!irr[0] | inta);
 
endmodule
/soc/keyb/rtl/ps2_keyb.v
19,6 → 19,8
* <http://www.gnu.org/licenses/>.
*/
 
`include "defines.v"
 
`timescale 1ns/100ps
 
`define TOTAL_BITS 11
27,12 → 29,16
`define RIGHT_SHIFT 16'h59
 
module ps2_keyb (
`ifdef DEBUG
output rx_output_strobe,
output released,
output rx_shifting_done,
`endif
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
output reg [7:0] wb_dat_o, // scancode
output reg wb_tgc_o, // intr
input wb_tgc_i, // inta
 
// PS2 PAD signals
inout ps2_clk_,
77,14 → 83,14
 
// Nets and registers
wire rx_output_event;
wire rx_output_strobe;
wire rx_shifting_done;
wire tx_shifting_done;
wire timer_60usec_done;
wire timer_5usec_done;
 
`ifndef DEBUG
wire rx_output_strobe;
wire rx_shifting_done;
wire released;
 
`endif
wire [6:0] xt_code;
 
reg [3:0] bit_count;
141,11 → 147,9
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
 
// Behaviour
// intr
// wb_tgc_o
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0
: ((rx_output_strobe & !wb_tgc_i) ? 1'b1
: (wb_tgc_o ? !wb_tgc_i : 1'b0));
wb_tgc_o <= wb_rst_i ? 1'b0 : rx_output_strobe;
 
// This is the shift register
always @(posedge wb_clk_i)
/soc/bios/biossums.c
1,5 → 1,5
/*
* $Id: biossums.c,v 1.7 2009-02-06 03:48:27 zeus Exp $
* $Id: biossums.c,v 1.4 2007/05/28 08:09:13 vruppert Exp $
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/soc/bios/makesym.perl
1,6 → 1,6
#!/usr/bin/perl
#
# $Id: makesym.perl,v 1.7 2009-02-06 03:48:27 zeus Exp $
# $Id: makesym.perl,v 1.2 2008/01/26 09:15:27 sshwarts Exp $
#
# Read output file from as86 (e.g. rombios.txt) and write out a symbol
# table suitable for the Bochs debugger.
/soc/bios/rombios.c
421,6 → 421,16
dec bx
ret
 
lincl:
lincul:
inc word ptr [bx]
je LINC_HIGH_WORD
ret
.even
LINC_HIGH_WORD:
inc word ptr 2[bx]
ret
 
ASM_END
 
// for access to RAM area which is used by interrupt vectors
1014,8 → 1024,10
}
}
 
static char bios_svn_version_string[] = "$Revision: 1.13 $ $Date: 2009-03-05 00:26:53 $";
static char bios_svn_version_string[] = "$Version: 0.4.3 $ $Date: Tue, 10 Mar 2009 21:02:08 +0100 $";
 
#define BIOS_COPYRIGHT_STRING "(c) 2009 Zeus Gomez Marmolejo and (c) 2002 MandrakeSoft S.A."
 
//--------------------------------------------------------------------------
// print_bios_banner
// displays a the bios version
1042,7 → 1054,7
// http://www.phoenix.com/en/Customer+Services/White+Papers-Specs/pc+industry+specifications.htm
//--------------------------------------------------------------------------
 
static char drivetypes[][20]={"", "Floppy flash image" };
static char drivetypes[][20]={"", "Floppy flash image", "Compact Flash" };
 
static void
init_boot_vectors()
1062,6 → 1074,11
memcpyb(IPL_SEG, IPL_TABLE_OFFSET + count * sizeof (e), ss, &e, sizeof (e));
count++;
 
/* First HDD */
e.type = IPL_TYPE_HARDDISK; e.flags = 0; e.vector = 0; e.description = 0; e.reserved = 0;
memcpyb(IPL_SEG, IPL_TABLE_OFFSET + count * sizeof (e), ss, &e, sizeof (e));
count++;
 
/* Remember how many devices we have */
write_word(IPL_SEG, IPL_COUNT_OFFSET, count);
/* Not tried booting anything yet */
1501,27 → 1518,495
int13_harddisk(DS, ES, DI, SI, BP, ELDX, BX, DX, CX, AX, IP, CS, FLAGS)
Bit16u DS, ES, DI, SI, BP, ELDX, BX, DX, CX, AX, IP, CS, FLAGS;
{
Bit8u drive, num_sectors, sector, head, status;
Bit8u drive_map;
Bit8u n_drives;
Bit16u max_cylinder, cylinder;
Bit16u hd_cylinders;
Bit8u hd_heads, hd_sectors;
Bit8u sector_count;
Bit16u tempbx;
 
Bit32u log_sector;
 
write_byte(0x0040, 0x008e, 0); // clear completion flag
 
/* at this point, DL is >= 0x80 to be passed from the floppy int13h
handler code */
/* check how many disks first (cmos reg 0x12), return an error if
drive not present */
drive_map = 1;
n_drives = 1;
 
if (!(drive_map & (1<<(GET_ELDL()&0x7f)))) { /* allow 0, 1, or 2 disks */
SET_AH(0x01);
SET_DISK_RET_STATUS(0x01);
SET_CF(); /* error occurred */
return;
}
 
switch (GET_AH()) {
 
case 0x00: /* disk controller reset */
 
SET_AH(0);
SET_DISK_RET_STATUS(0);
set_diskette_ret_status(0);
set_diskette_current_cyl(0, 0); /* current cylinder, diskette 1 */
set_diskette_current_cyl(1, 0); /* current cylinder, diskette 2 */
CLEAR_CF(); /* successful */
return;
break;
 
case 0x01: /* read disk status */
status = read_byte(0x0040, 0x0074);
SET_AH(status);
SET_DISK_RET_STATUS(0);
/* set CF if error status read */
if (status) SET_CF();
else CLEAR_CF();
return;
break;
 
case 0x04: // verify disk sectors
case 0x02: // read disk sectors
drive = GET_ELDL();
 
// get_hd_geometry(drive, &hd_cylinders, &hd_heads, &hd_sectors);
// fixed geometry:
hd_cylinders = 993;
hd_heads = 16;
hd_sectors = 63;
 
num_sectors = GET_AL();
cylinder = (GET_CL() & 0x00c0) << 2 | GET_CH();
sector = (GET_CL() & 0x3f);
head = GET_DH();
 
if ( (cylinder >= hd_cylinders) ||
(sector > hd_sectors) ||
(head >= hd_heads) ) {
SET_AH(1);
SET_DISK_RET_STATUS(1);
SET_CF(); /* error occurred */
return;
}
 
if ( GET_AH() == 0x04 ) {
SET_AH(0);
SET_DISK_RET_STATUS(0);
CLEAR_CF();
return;
}
 
log_sector = ((Bit32u)cylinder) * ((Bit32u)hd_heads) * ((Bit32u)hd_sectors)
+ ((Bit32u)head) * ((Bit32u)hd_sectors)
+ ((Bit32u)sector) - 1;
 
sector_count = 0;
tempbx = BX;
 
ASM_START
sti ;; enable higher priority interrupts
ASM_END
 
while (1) {
ASM_START
;; store temp bx in real DI register
push bp
mov bp, sp
mov di, _int13_harddisk.tempbx + 2 [bp]
pop bp
 
;; adjust if there will be an overrun
cmp di, #0xfe00
jbe i13_f02_no_adjust
i13_f02_adjust:
sub di, #0x0200 ; sub 512 bytes from offset
mov ax, es
add ax, #0x0020 ; add 512 to segment
mov es, ax
 
i13_f02_no_adjust:
; timeout = TIMEOUT;
mov cx, #0xffff
 
; while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_CFCMDRDY))) timeout--;
mov dx, #0xe204
 
i13_f02_ace_statusl2:
in ax, dx
and ax, #0x100
loopz i13_f02_ace_statusl2
 
; if(timeout == 0) return 0;
cmp cx, #0
jnz i13_f02_success2
ASM_END
printf("i13_f02(1): Timeout\n");
ASM_START
jmp _int13_fail
 
i13_f02_success2:
; CSR_ACE_MLBAL = blocknr & 0x0000ffff;
push bp
mov bp, sp
mov ax, _int13_harddisk.log_sector + 2 [bp]
mov dx, #0xe210
out dx, ax
 
; CSR_ACE_MLBAH = (blocknr & 0x0fff0000) >> 16;
mov ax, _int13_harddisk.log_sector + 4 [bp]
mov dx, #0xe212
out dx, ax
pop bp
 
; CSR_ACE_SECCMD = ACE_SECCMD_READ|0x01;
mov ax, #0x0301
mov dx, #0xe214
out dx, ax
 
; CSR_ACE_CTLL |= ACE_CTLL_CFGRESET;
mov dx, #0xe218
in ax, dx
or ax, #0x0080
out dx, ax
 
; buffer_count = 16;
mov si, #16
 
; while(buffer_count > 0) {
i13_f02_cond_loop:
cmp si, #0
jbe i13_f02_exit_loop
 
; timeout = TIMEOUT;
mov cx, #0xffff
mov bx, #0x000f
 
; while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_DATARDY))) timeout--;
mov dx, #0xe204
i13_f02_ace_statusl3:
in ax, dx
and ax, #0x20
loopz i13_f02_ace_statusl3
 
; if(timeout == 0) return 0;
cmp cx, #0
jnz i13_f02_success3
dec bx
mov cx, #0xffff
jne i13_f02_ace_statusl3
ASM_END
printf("i13_f02(2): Timeout\n");
ASM_START
jmp _int13_fail
 
i13_f02_success3:
; for(i=0;i<16;i++) {
mov cx, #16
; *bufw = CSR_ACE_DATA;
mov dx, #0xe240
i13_f02_ace_data:
in ax, dx
eseg
mov [di], ax
; bufw++;
add di, #2
; }
loop i13_f02_ace_data
 
; buffer_count--;
dec si
jmp i13_f02_cond_loop
 
; }
 
i13_f02_exit_loop:
; CSR_ACE_CTLL &= ~ACE_CTLL_CFGRESET;
mov dx, #0xe218
in ax, dx
and ax, #0xff7f
out dx, ax
 
i13_f02_done:
;; store real DI register back to temp bx
push bp
mov bp, sp
mov _int13_harddisk.tempbx + 2 [bp], di
pop bp
ASM_END
 
sector_count++;
log_sector++;
num_sectors--;
if (num_sectors) continue;
else break;
}
 
SET_AH(0);
SET_DISK_RET_STATUS(0);
SET_AL(sector_count);
CLEAR_CF(); /* successful */
return;
break;
 
case 0x03: /* write disk sectors */
drive = GET_ELDL ();
 
// get_hd_geometry(drive, &hd_cylinders, &hd_heads, &hd_sectors);
// fixed geometry:
hd_cylinders = 993;
hd_heads = 16;
hd_sectors = 63;
 
num_sectors = GET_AL();
cylinder = GET_CH();
cylinder |= ( ((Bit16u) GET_CL()) << 2) & 0x300;
sector = (GET_CL() & 0x3f);
head = GET_DH();
 
if ( (cylinder >= hd_cylinders) ||
(sector > hd_sectors) ||
(head >= hd_heads) ) {
SET_AH( 1);
SET_DISK_RET_STATUS(1);
SET_CF(); /* error occurred */
return;
}
 
log_sector = ((Bit32u)cylinder) * ((Bit32u)hd_heads) * ((Bit32u)hd_sectors)
+ ((Bit32u)head) * ((Bit32u)hd_sectors)
+ ((Bit32u)sector) - 1;
 
sector_count = 0;
tempbx = BX;
 
ASM_START
sti ;; enable higher priority interrupts
ASM_END
 
while (1) {
ASM_START
;; store temp bx in real SI register
push bp
mov bp, sp
mov si, _int13_harddisk.tempbx + 2 [bp]
pop bp
 
;; adjust if there will be an overrun
cmp si, #0xfe00
jbe i13_f03_no_adjust
i13_f03_adjust:
sub si, #0x0200 ; sub 512 bytes from offset
mov ax, es
add ax, #0x0020 ; add 512 to segment
mov es, ax
 
i13_f03_no_adjust:
; timeout = TIMEOUT;
mov cx, #0xffff
 
; while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_CFCMDRDY))) timeout--;
mov dx, #0xe204
 
i13_f03_ace_statusl2:
in ax, dx
and ax, #0x100
loopz i13_f03_ace_statusl2
 
; if(timeout == 0) return 0;
cmp cx, #0
jnz i13_f03_success2
ASM_END
printf("i13_f03(1): Timeout\n");
ASM_START
jmp _int13_fail
 
i13_f03_success2:
; CSR_ACE_MLBAL = blocknr & 0x0000ffff;
push bp
mov bp, sp
mov ax, _int13_harddisk.log_sector + 2 [bp]
mov dx, #0xe210
out dx, ax
 
; CSR_ACE_MLBAH = (blocknr & 0x0fff0000) >> 16;
mov ax, _int13_harddisk.log_sector + 4 [bp]
mov dx, #0xe212
out dx, ax
pop bp
 
; CSR_ACE_SECCMD = ACE_SECCMD_WRITE|0x01;
mov ax, #0x0401
mov dx, #0xe214
out dx, ax
 
; CSR_ACE_CTLL |= ACE_CTLL_CFGRESET;
mov dx, #0xe218
in ax, dx
or ax, #0x0080
out dx, ax
 
; buffer_count = 16;
mov di, #16
 
; while(buffer_count > 0) {
i13_f03_cond_loop:
cmp di, #0
jbe i13_f03_exit_loop
 
; timeout = TIMEOUT;
mov cx, #0xffff
mov bx, #0x000f
 
; while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_DATARDY))) timeout--;
mov dx, #0xe204
i13_f03_ace_statusl3:
in ax, dx
and ax, #0x20
loopz i13_f03_ace_statusl3
 
; if(timeout == 0) return 0;
cmp cx, #0
jnz i13_f03_success3
dec bx
mov cx, #0xffff
jne i13_f03_ace_statusl3
ASM_END
printf("i13_f03(2): Timeout\n");
ASM_START
jmp _int13_fail
 
i13_f03_success3:
; for(i=0;i<16;i++) {
mov cx, #16
; *bufw = CSR_ACE_DATA;
mov dx, #0xe240
i13_f03_ace_data:
eseg
mov ax, [si]
out dx, ax
; bufw++;
add si, #2
; }
loop i13_f03_ace_data
 
; buffer_count--;
dec di
jmp i13_f03_cond_loop
 
; }
 
i13_f03_exit_loop:
; CSR_ACE_CTLL &= ~ACE_CTLL_CFGRESET;
mov dx, #0xe218
in ax, dx
and ax, #0xff7f
out dx, ax
 
i13_f03_done:
;; store real SI register back to temp bx
push bp
mov bp, sp
mov _int13_harddisk.tempbx + 2 [bp], si
pop bp
ASM_END
 
sector_count++;
log_sector++;
num_sectors--;
if (num_sectors) continue;
else break;
}
 
SET_AH(0);
SET_DISK_RET_STATUS(0);
SET_AL(sector_count);
CLEAR_CF(); /* successful */
return;
break;
 
case 0x08:
 
drive = GET_ELDL ();
 
// get_hd_geometry(drive, &hd_cylinders, &hd_heads, &hd_sectors);
// fixed geometry:
hd_cylinders = 993;
hd_heads = 16;
hd_sectors = 63;
 
max_cylinder = hd_cylinders - 2; /* 0 based */
SET_AL(0);
SET_CH(0);
SET_CL(0);
SET_DH(0);
SET_DL(0); /* FIXME returns 0, 1, or n hard drives */
SET_CH(max_cylinder & 0xff);
SET_CL(((max_cylinder >> 2) & 0xc0) | (hd_sectors & 0x3f));
SET_DH(hd_heads - 1);
SET_DL(n_drives); /* returns 0, 1, or 2 hard drives */
SET_AH(0);
SET_DISK_RET_STATUS(0);
CLEAR_CF(); /* successful */
 
// FIXME should set ES & DI
return;
break;
 
goto int13_fail;
case 0x09: /* initialize drive parameters */
case 0x0c: /* seek to specified cylinder */
case 0x0d: /* alternate disk reset */
case 0x10: /* check drive ready */
case 0x11: /* recalibrate */
SET_AH(0);
SET_DISK_RET_STATUS(0);
CLEAR_CF(); /* successful */
return;
break;
 
case 0x14: /* controller internal diagnostic */
SET_AH(0);
SET_DISK_RET_STATUS(0);
CLEAR_CF(); /* successful */
SET_AL(0);
return;
break;
 
case 0x15: /* read disk drive size */
drive = GET_ELDL();
// get_hd_geometry(drive, &hd_cylinders, &hd_heads, &hd_sectors);
// fixed geometry:
hd_cylinders = 993;
hd_heads = 16;
hd_sectors = 63;
 
ASM_START
push bp
mov bp, sp
mov al, _int13_harddisk.hd_heads + 2 [bp]
mov ah, _int13_harddisk.hd_sectors + 2 [bp]
mul al, ah ;; ax = heads * sectors
mov bx, _int13_harddisk.hd_cylinders + 2 [bp]
dec bx ;; use (cylinders - 1) ???
mul ax, bx ;; dx:ax = (cylinders -1) * (heads * sectors)
;; now we need to move the 32bit result dx:ax to what the
;; BIOS wants which is cx:dx.
;; and then into CX:DX on the stack
mov _int13_harddisk.CX + 2 [bp], dx
mov _int13_harddisk.DX + 2 [bp], ax
pop bp
ASM_END
SET_AH(3); // hard disk accessible
SET_DISK_RET_STATUS(0); // ??? should this be 0
CLEAR_CF(); // successful
return;
break;
 
default:
BX_INFO("int13_harddisk: function %02xh unsupported, returns fail\n", GET_AH());
goto int13_fail;
break;
}
 
ASM_START
_int13_fail:
ASM_END
int13_fail:
SET_AH(0x01); // defaults to invalid function in AH or invalid parameter
int13_fail_noah:
1681,9 → 2166,9
Bit8u drive;
Bit8u cyl;
{
/* TEMP HACK: FOR MSDOS */
/* TEMP HACK: FOR MSDOS
if (drive > 1)
drive = 1;
drive = 1; */
/* BX_PANIC("set_diskette_current_cyl(): drive > 1\n"); */
write_byte(0x0040, 0x0094+drive, cyl);
}
1725,7 → 2210,7
bootdev >>= 4 * seq_nr;
bootdev &= 0xf;
*/
bootdev = 0x1;
bootdev = 0x2; // 1: flopy disk, 2: hard disk
 
/* Read user selected device */
bootfirst = read_word(IPL_SEG, IPL_BOOTFIRST_OFFSET);
1912,6 → 2397,16
; shl eax, #16
 
int13_out:
;
; ZEUS HACK: put IF flag on.
; Seems that MS-DOS does a 'cli' before calling this
; but after int13 it doesn't set the interrupts back
;
mov bp, sp
mov ax, 24[bp] ; FLAGS location
or ax, #0x0200 ; IF on
mov 24[bp], ax
 
pop ds
pop es
; popa ; we do this instead:
1989,7 → 2484,80
int1c_handler: ;; User Timer Tick
iret
 
;--------------------
;- POST: HARD DRIVE -
;--------------------
; relocated here because the primary POST area isnt big enough.
hard_drive_post:
// IRQ 14 = INT 76h
// INT 76h calls INT 15h function ax=9100
 
xor ax, ax
mov ds, ax
mov 0x0474, al /* hard disk status of last operation */
mov 0x0477, al /* hard disk port offset (XT only ???) */
mov 0x048c, al /* hard disk status register */
mov 0x048d, al /* hard disk error register */
mov 0x048e, al /* hard disk task complete flag */
mov al, #0x01
mov 0x0475, al /* hard disk number attached */
mov al, #0xc0
mov 0x0476, al /* hard disk control byte */
SET_INT_VECTOR(0x13, #0xF000, #int13_handler)
SET_INT_VECTOR(0x76, #0xF000, #int76_handler)
 
;; Initialize the sysace controller
; CSR_ACE_BUSMODE = ACE_BUSMODE_16BIT;
mov dx, #0xe200
mov ax, #0x0001
out dx, ax
 
; if(!(CSR_ACE_STATUSL & ACE_STATUSL_CFDETECT)) return 0;
mov dx, #0xe204
in ax, dx
and ax, #0x0010
jne cf_detect
hlt ;; error
 
cf_detect:
; if((CSR_ACE_ERRORL != 0) || (CSR_ACE_ERRORH != 0)) return 0;
mov dx, #0xe208
in ax, dx
cmp ax, #0x0
jne error_l
mov dx, #0xe20a
in ax, dx
cmp ax, #0x0
je lock_req
error_l:
hlt
 
lock_req:
; CSR_ACE_CTLL |= ACE_CTLL_LOCKREQ;
mov dx, #0xe218
in ax, dx
or ax, #0x2
out dx, ax
 
; timeout = TIMEOUT;
mov cx, #0xffff
 
; while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_MPULOCK))) timeout--;
mov dx, #0xe204
ace_statusl:
in ax, dx
and ax, #0x2
loopz ace_statusl
 
; if(timeout == 0) return 0;
cmp cx, #0x0
jnz success
hlt ;; error obtaining lock
 
success:
ret
 
 
;--------------------
;- POST: EBDA segment
;--------------------
2000,6 → 2568,20
mov word ptr [0x40E], #EBDA_SEG
ret;;
 
;--------------------
int76_handler:
;; record completion in BIOS task complete flag
push ax
push ds
mov ax, #0x0040
mov ds, ax
mov 0x008E, #0xff
; call eoi_both_pics
pop ds
pop ax
iret
 
 
rom_checksum:
push ax
push bx
2225,6 → 2807,10
;; EBDA setup
call ebda_post
 
;; PIT setup
SET_INT_VECTOR(0x08, #0xF000, #int08_handler)
;; int 1C already points at dummy_iret_handler (above)
 
;; Keyboard
SET_INT_VECTOR(0x09, #0xF000, #int09_handler)
SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
2267,8 → 2853,10
 
call _print_bios_banner
 
;; Floppy setup
SET_INT_VECTOR(0x13, #0xF000, #int13_handler)
;;
;; Hard Drive setup
;;
call hard_drive_post
 
call _init_boot_vectors
 
2548,6 → 3136,67
pop ds
iret
 
;---------
;- INT08 -
;---------
.org 0xfea5 ; INT 08h System Timer ISR Entry Point
int08_handler:
sti
push ax
push bx
push ds
xor ax, ax
mov ds, ax
 
mov ax, 0x046c ;; get ticks dword
mov bx, 0x046e
inc ax
jne i08_linc_done
inc bx ;; inc high word
 
i08_linc_done:
push bx
;; compare eax to one days worth of timer ticks at 18.2 hz
sub bx, #0x0018
jne i08_lcmp_done
cmp ax, #0x00B0
jb i08_lcmp_b_and_lt
jge i08_lcmp_done
inc bx
jmp i08_lcmp_done
 
i08_lcmp_b_and_lt:
dec bx
 
i08_lcmp_done:
pop bx
jb int08_store_ticks
;; there has been a midnight rollover at this point
xor ax, ax ;; zero out counter
xor bx, bx
inc BYTE 0x0470 ;; increment rollover flag
 
int08_store_ticks:
mov 0x046c, ax ;; store new ticks dword
mov 0x046e, bx
;; chain to user timer tick INT #0x1c
//pushf
//;; call_ep [ds:loc]
//CALL_EP( 0x1c << 2 )
int #0x1c
cli
;; call eoi_master_pic
pop ds
pop bx
pop ax
iret
 
.org 0xfef3 ; Initial Interrupt Vector Offsets Loaded by POST
 
 
.org 0xff00
.ascii BIOS_COPYRIGHT_STRING
 
;------------------------------------------------
;- IRET Instruction for Dummy Interrupt Handler -
;------------------------------------------------
/soc/bios/vgabios.c
240,7 → 240,7
 
#if defined(USE_BX_INFO) || defined(DEBUG)
msg_vga_init:
.ascii "VGABios $Id: vgabios.c,v 1.9 2009-03-05 19:58:40 zeus Exp $"
.ascii "VGABios $Id: vgabios.c,v 1.66 2006/07/10 07:47:51 vruppert Exp $"
.byte 0x0d,0x0a,0x00
#endif
ASM_END
/src/bochs-diff-2.3.7/disasm/syntax.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: syntax.cc,v 1.5 2009-02-06 03:48:30 zeus Exp $
// $Id: syntax.cc,v 1.14 2008/03/20 18:11:57 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
 
#include <stdio.h>
/src/bochs-diff-2.3.7/bochs.h
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: bochs.h,v 1.5 2009-02-06 03:48:29 zeus Exp $
// $Id: bochs.h,v 1.231 2008/05/23 14:04:42 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/gui/gui.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: gui.cc,v 1.5 2009-02-06 03:48:31 zeus Exp $
// $Id: gui.cc,v 1.105 2008/05/04 09:29:45 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/plugin.h
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: plugin.h,v 1.5 2009-02-06 03:48:29 zeus Exp $
// $Id: plugin.h,v 1.62 2008/02/15 22:05:38 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// This file provides macros and types needed for plugins. It is based on
/src/bochs-diff-2.3.7/iodev/devices.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: devices.cc,v 1.5 2009-02-06 03:48:32 zeus Exp $
// $Id: devices.cc,v 1.121 2008/04/17 14:39:32 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
124,7 → 124,7
unsigned i;
const char def_name[] = "Default";
 
BX_DEBUG(("Init $Id: devices.cc,v 1.5 2009-02-06 03:48:32 zeus Exp $"));
BX_DEBUG(("Init $Id: devices.cc,v 1.121 2008/04/17 14:39:32 sshwarts Exp $"));
mem = newmem;
 
/* set no-default handlers, will be overwritten by the real default handler */
/src/bochs-diff-2.3.7/iodev/hdemu.cc
38,7 → 38,7
{
char name[16];
 
BX_DEBUG(("Init $Id: hdemu.cc,v 1.5 2009-02-06 03:48:32 zeus Exp $"));
BX_DEBUG(("Init $Id: hdemu.cc,v 1.34 2008/01/26 22:24:02 sshwarts Exp $"));
 
sprintf(name, "Hd emu");
/* hdemu i/o ports */
/src/bochs-diff-2.3.7/iodev/iodev.h
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: iodev.h,v 1.5 2009-02-06 03:48:32 zeus Exp $
// $Id: iodev.h,v 1.92 2008/04/17 14:39:32 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/cpu/cpu.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.5 2009-02-06 03:48:30 zeus Exp $
// $Id: cpu.cc,v 1.230 2008/05/10 20:35:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/cpu/crregs.h
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: crregs.h,v 1.5 2009-02-06 03:48:30 zeus Exp $
// $Id: crregs.h,v 1.10 2008/04/16 16:44:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
/src/bochs-diff-2.3.7/cpu/bcd.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: bcd.cc,v 1.5 2009-02-06 03:48:30 zeus Exp $
// $Id: bcd.cc,v 1.24 2008/03/22 21:29:39 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/instrument/zet/instrument.cc
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.5 2009-02-06 03:48:31 zeus Exp $
// $Id: instrument.cc,v 1.23 2008/04/19 10:12:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
/src/bochs-diff-2.3.7/instrument/zet/instrument.h
1,5 → 1,5
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.5 2009-02-06 03:48:31 zeus Exp $
// $Id: instrument.h,v 1.27 2008/04/19 10:12:09 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
/bin/version-date.sh
0,0 → 1,4
#!/bin/bash
sed "s/\$Version:[^\$]\+/\$Version: $1 /g" $2 |
sed "s/\$Date:[^\$]\+/\$Date: $(date -R) /g" > $2.tmp
mv $2.tmp $2
bin/version-date.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sim/signmul17.v =================================================================== --- sim/signmul17.v (nonexistent) +++ sim/signmul17.v (revision 52) @@ -0,0 +1,11 @@ +module signmul17 ( + input clk, + + input signed [16:0] a, + input signed [16:0] b, + output reg signed [33:0] p + ); + + // Behaviour + always @(posedge clk) p <= a * b; +endmodule

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