Subversion Repositories zet86

/trunk/impl/virtex4-ml403ep/lcd/test_lcd_cntrl.v File deleted

/trunk/impl/virtex4-ml403ep/lcd/lcd_display.v File deleted \ No newline at end of file

/trunk/impl/virtex4-ml403ep/lcd/ml403.ucf File deleted

/trunk/impl/virtex4-ml403ep/ace/ml40x_bit2ace File deleted

trunk/impl/virtex4-ml403ep/ace/ml40x_bit2ace Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/impl/virtex4-ml403ep/ace/ml40x_bit2ace.bat =================================================================== --- trunk/impl/virtex4-ml403ep/ace/ml40x_bit2ace.bat (revision 53) +++ trunk/impl/virtex4-ml403ep/ace/ml40x_bit2ace.bat (nonexistent) @@ -1,13 +0,0 @@ -echo off -if exist tmp_ml40x____datafile.bit del tmp_ml40x____datafile.bit -if exist tmp_ml40x____datafile.ace del tmp_ml40x____datafile.ace -copy /Y %XILINX%\xcfp\data\xcf32p_vo48.bsd . -copy /Y %XILINX%\xc9500xl\data\xc95144xl_tq100.bsd . -copy /Y %1 tmp_ml40x____datafile.bit -impact -batch ml40x.scr -impact -batch ml40x_svf2ace.scr -if exist tmp_ml40x____datafile.bit del tmp_ml40x____datafile.bit -if exist tmp_ml40x____datafile.svf del tmp_ml40x____datafile.svf -if exist %2 del %2 -if exist tmp_ml40x____datafile.ace ren tmp_ml40x____datafile.ace %2 -echo on Index: trunk/impl/virtex4-ml403ep/ace/ml40x_svf2ace.scr =================================================================== --- trunk/impl/virtex4-ml403ep/ace/ml40x_svf2ace.scr (revision 53) +++ trunk/impl/virtex4-ml403ep/ace/ml40x_svf2ace.scr (nonexistent) @@ -1,7 +0,0 @@ -setMode -cf -svf2ace -wtck -d -i tmp_ml40x____datafile.svf -o tmp_ml40x____datafile.ace -quit - - - - Index: trunk/impl/virtex4-ml403ep/ace/ml40x.scr =================================================================== --- trunk/impl/virtex4-ml403ep/ace/ml40x.scr (revision 53) +++ trunk/impl/virtex4-ml403ep/ace/ml40x.scr (nonexistent) @@ -1,11 +0,0 @@ -setmode -bs -setCable -p svf -file tmp_ml40x____datafile.svf -addDevice -p 1 -file xcf32p_vo48.bsd -addDevice -p 2 -file tmp_ml40x____datafile.bit -addDevice -p 3 -file xc95144xl_tq100.bsd -program -p 2 -quit - - - - Index: trunk/impl/virtex4-ml403ep/sim/CY7C1354BV25.v =================================================================== --- trunk/impl/virtex4-ml403ep/sim/CY7C1354BV25.v (revision 53) +++ trunk/impl/virtex4-ml403ep/sim/CY7C1354BV25.v (nonexistent) @@ -1,487 +0,0 @@ -//************************************************************************ -//************************************************************************ -//** This model is the property of Cypress Semiconductor Corp and is ** -//** protected by the US copyright laws, any unauthorized copying and ** -//** distribution is prohibited. Cypress reserves the right to change ** -//** any of the functional specifications without any prior notice. ** -//** Cypress is not liable for any damages which may result from the ** -//** use of this functional model. ** -//** ** -//** File Name : CY7C1354BV25 ** -//** ** -//** Revision : 1.1 - 01/30/2004 ** -//** ** -//** The timings are to be selected by the user depending upon the ** -//** frequency of operation from the datasheet. ** -//** ** -//** Model : CY7C1354BV25 - 256K x 36 NoBL Pipelined SRAM ** -//** Queries : MPD Applications ** -//** e-mail: mpd_apps@cypress.com ** -//************************************************************************ -//************************************************************************ - -`timescale 1ns / 10ps - -// NOTE : Any setup/hold errors will force input signal to x state -// or if results indeterminant (write addr) core is reset x - -// define fixed values - -`define wordsize (36 -1) // -`define no_words (262144 -1) // 256K x 36 RAM - -module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -inout [31:0] d; -input clk, // clock input (R) - we_b, // byte write enable(L) - adv_lb, // burst(H)/load(L) address - ce1b, // chip enable(L) - ce2, // chip enable(H) - ce3b, // chip enable(L) - oeb, // async output enable(L)(read) - cenb, // clock enable(L) - mode; // interleave(H)/linear(L) burst -input [3:0] bws; // byte write select(L) -input [18:0] a; // address bus - -// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** -// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** - -//********************************************************************** -// This model is configured for 166 MHz Operation (CY7C1354-166). -//********************************************************************** - `define teohz #3.5 - `define teolz #0 - `define tchz #3.5 - `define tclz #1.5 - - `define tco #3.5 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 - -/********************************************************************** -// Timings for 225MHz -//********************************************************************** - `define teohz #2.8 - `define teolz #0 - `define tchz #2.8 - `define tclz #1.25 - - `define tco #2.8 - `define tdoh #1.25 - - `define tas 1.4 - `define tah 0.4 - -//*********************************************************************** -// Timings for 200MHz -//********************************************************************** - `define teohz #3.2 - `define teolz #0 - `define tchz #3.2 - `define tclz #1.5 - - `define tco #3.2 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -***********************************************************************/ - -reg notifier; // error support reg's -reg noti1_0; -reg noti1_1; -reg noti1_2; -reg noti1_3; -reg noti1_4; -reg noti1_5; -reg noti1_6; -reg noti2; - - -wire chipen; // combined chip enable (high for an active chip) - -reg chipen_d; // _d = delayed -reg chipen_o; // _o = operational = delayed sig or _d sig - -wire writestate; // holds 1 if any of writebus is low -reg writestate_d; -reg writestate_o; - -wire loadcyc; // holds 1 for load cycles (setup and hold checks) -wire writecyc; // holds 1 for write cycles (setup and hold checks) -wire [3:0] bws; // holds the bws values - -wire [3:0] writebusb; // holds the "internal" bws bus based on we_b -reg [3:0] writebusb_d; -reg [3:0] writebusb_o; - -wire [2:0] operation; // holds chipen, adv_ld and writestate -reg [2:0] operation_d; -reg [2:0] operation_o; - -wire [17:0] a; // address input bus -reg [17:0] a_d; -reg [17:0] a_o; - -reg [`wordsize:0] do; // data output reg -reg [`wordsize:0] di; // data input bus -reg [`wordsize:0] dd; // data delayed bus - -wire tristate; // tristate output (on a bytewise basis) when asserted -reg cetri; // register set by chip disable which sets the tristate -reg oetri; // register set by oe which sets the tristate -reg enable; // register to make the ram enabled when equal to 1 -reg [17:0] addreg; // register to hold the input address -reg [`wordsize:0] pipereg; // register for the output data - -reg [`wordsize:0] mem [0:`no_words]; // RAM array - -reg [`wordsize:0] writeword; // temporary holding register for the write data -reg burstinit; // register to hold a[0] for burst type -reg [18:0] i; // temporary register used to write to all mem locs. -reg writetri; // tristate -reg lw, bw; // pipelined write functions -reg we_bl; - - -wire [31:0] d = !tristate ? - {do[34:27],do[25:18],do[16:9],do[7:0]} - : 32'bz ; // data bus - -assign chipen = (adv_lb == 1 ) ? chipen_d : - ~ce1b & ce2 & ~ce3b ; - -assign writestate = ~& writebusb; - -assign operation = {chipen, adv_lb, writestate}; - -assign writebusb[3:0] = ( we_b ==0 & adv_lb ==0) ? bws[3:0]: - ( we_b ==1 & adv_lb ==0) ? 4'b1111 : - ( we_bl ==0 & adv_lb ==1) ? bws[3:0]: - ( we_bl ==1 & adv_lb ==1) ? 4'b1111 : - 4'bxxxx ; - -assign loadcyc = chipen & !cenb; - -assign writecyc = writestate_d & enable & ~cenb & chipen; // check - -assign tristate = cetri | writetri | oetri; - -pullup (mode); - -// formers for notices/errors etc -// -//$display("NOTICE : xxx :"); -//$display("WARNING : xxx :"); -//$display("ERROR *** : xxx :"); - - -// initialize the output to be tri-state, ram to be disabled - -initial - begin -// signals - - writetri = 0; - cetri = 1; - enable = 0; - lw = 0; - bw = 0; - -// error signals - - notifier = 0; - noti1_0 = 0; - noti1_1 = 0; - noti1_2 = 0; - noti1_3 = 0; - noti1_4 = 0; - noti1_5 = 0; - noti1_6 = 0; - noti2 = 0; - -end - - - -// asynchronous OE - -always @(oeb) -begin - if (oeb == 1) - oetri <= `teohz 1; - else - oetri <= `teolz 0; -end - -// *** SETUP / HOLD VIOLATIONS *** - -always @(noti2) -begin -$display("NOTICE : 020 : Data bus corruption"); - force d =36'bx; - #1; - release d; -end - -always @(noti1_0) -begin -$display("NOTICE : 010 : Byte write corruption"); - force bws = 4'bx; - #1; - release bws; -end - -always @(noti1_1) -begin -$display("NOTICE : 011 : Byte enable corruption"); - force we_b = 1'bx; - #1; - release we_b; -end - -always @(noti1_2) -begin -$display("NOTICE : 012 : CE1B corruption"); - force ce1b =1'bx; - #1; - release ce1b; -end - -always @(noti1_3) -begin -$display("NOTICE : 013 : CE2 corruption"); - force ce2 =1'bx; - #1; - release ce2; -end - -always @(noti1_4) -begin -$display("NOTICE : 014 : CE3B corruption"); - force ce3b =1'bx; - #1; - release ce3b; -end - -always @(noti1_5) -begin -$display("NOTICE : 015 : CENB corruption"); - force cenb =1'bx; - #1; - release cenb; -end - -always @(noti1_6) -begin -$display("NOTICE : 016 : ADV_LB corruption"); - force adv_lb = 1'bx; - #1; - release adv_lb; -end - -// synchronous functions from clk edge - -always @(posedge clk) -if (!cenb) -begin -#0.01; - // latch conditions on adv_lb - - if (adv_lb) - we_bl <= we_bl; - else - we_bl <= we_b; - - chipen_d <= chipen; - - - chipen_o <= chipen; - writestate_o <= writestate; - writestate_d <= writestate_o; - writebusb_o <= writebusb; - writebusb_d <= writebusb_o; - operation_o <= operation; - a_o <= a; - a_d <= a_o; - di = {1'b0,d[31:24], - 1'b0,d[23:16], - 1'b0,d[15:8], - 1'b0,d[7:0]}; - - // execute previously pipelined fns - - if (lw) begin - loadwrite; - lw =0; - end - - if (bw) begin - burstwrite; - bw =0; - end - - // decode input/piplined state - - casex (operation_o) - 3'b0?? : turnoff; - 3'b101 : setlw; - 3'b111 : setbw; - 3'b100 : loadread; - 3'b110 : burstread; - default : unknown; // output unknown values and display an error message - endcase - - do <= `tco pipereg; - -end - -// *** task section *** - -task read; -begin - if (enable) cetri <= `tclz 0; - do <= `tdoh 36'hx; - writetri <= `tchz 0; - pipereg = mem[addreg]; -end -endtask - -task write; -begin - if (enable) cetri <= `tclz 0; - writeword = mem[addreg]; // set up a word to hold the data for the current location - /* overwrite the current word for the bytes being written to */ - if (!writebusb_d[3]) writeword[35:27] = di[35:27]; - if (!writebusb_d[2]) writeword[26:18] = di[26:18]; - if (!writebusb_d[1]) writeword[17:9] = di[17:9]; - if (!writebusb_d[0]) writeword[8:0] = di[8:0]; - writeword = writeword & writeword; //convert z to x states - mem[addreg] = writeword; // store the new word into the memory location - //writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setlw; -begin - lw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setbw; -begin - bw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task loadread; -begin - burstinit = a_o[0]; - addreg = a_o; - enable = 1; - read; -end -endtask - -task loadwrite; -begin - burstinit = a_d[0]; - addreg = a_d; - enable = 1; - write; -end -endtask - -task burstread; -begin - burst; - read; -end -endtask - -task burstwrite; -begin - burst; - write; -end -endtask - -task unknown; -begin - do = 36'bx; - // $display ("Unknown function: Operation = %b\n", operation); -end -endtask - -task turnoff; -begin - enable = 0; - cetri <= `tchz 1; - pipereg = 36'h0; -end -endtask - -task burst; -begin - if (burstinit == 0 || mode == 0) - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b01; - 2'b01: addreg[1:0] = 2'b10; - 2'b10: addreg[1:0] = 2'b11; - 2'b11: addreg[1:0] = 2'b00; - default: addreg[1:0] = 2'bxx; - endcase - end - else - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b11; - 2'b01: addreg[1:0] = 2'b00; - 2'b10: addreg[1:0] = 2'b01; - 2'b11: addreg[1:0] = 2'b10; - default: addreg[1:0] = 2'bxx; - endcase - end -end -endtask - -// IO checks -/* -specify -// specify the setup and hold checks - -// notifier will wipe memory as result is indeterminent - -$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); - -// noti1 should make ip = 'bx; - -$setuphold(posedge clk, bws, `tas, `tah, noti1_0); - -$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); -$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); -$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); -$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); - -// noti2 should make d = 36'hxxxxxxxxx; - -$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); -//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2); - -// add extra tests here. - -$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); -$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); - -endspecify -*/ -endmodule - - Index: trunk/impl/virtex4-ml403ep/sim/flash_stub.v =================================================================== --- trunk/impl/virtex4-ml403ep/sim/flash_stub.v (revision 53) +++ trunk/impl/virtex4-ml403ep/sim/flash_stub.v (nonexistent) @@ -1,26 +0,0 @@ -`timescale 1ns/10ps - -module flash_stub ( - input [20:0] flash_addr_, - output [31:0] flash_data_, - input flash_oe_n_, - input flash_we_n_, - input flash_ce2_ - ); - - // Registers and nets - reg [31:0] rom[2**21-1:0]; - reg [31:0] dat_o; - - // Continous assignments - assign flash_data_ = flash_ce2_ ? dat_o : 32'hzzzzzzzz; - - // Behaviour - initial $readmemh("00_mov.ml403", rom, 21'h0); - initial $readmemh("hd.ml403", rom, 21'h100000); - - always @(*) dat_o <= #110 - (!flash_oe_n_ & flash_we_n_ & flash_ce2_) ? - rom[flash_addr_] : 32'hzzzzzzzz; - -endmodule Index: trunk/impl/virtex4-ml403ep/sim/test_kotku.v =================================================================== --- trunk/impl/virtex4-ml403ep/sim/test_kotku.v (revision 53) +++ trunk/impl/virtex4-ml403ep/sim/test_kotku.v (nonexistent) @@ -1,102 +0,0 @@ -`timescale 1ns/10ps - -module testbench; - - // Net and register declarations - wire lcd_clk; - wire [ 1:0] lcd_r, lcd_g, lcd_b; - wire lcd_hsync; - wire lcd_vsync; - reg clk; - reg but; - reg ace_clk; - wire s_clk; - wire [20:0] sf_addr; - wire [31:0] sf_data; - wire sf_oe; - wire sf_we; - wire [ 3:0] s_bw; - wire s_ce; - wire s_adv; - wire f_ce; - - wire [ 6:1] aceusb_a_; - wire [15:0] aceusb_d_; - wire aceusb_oe_n_; - wire aceusb_we_n_; - wire ace_mpce_n_; - wire usb_cs_n_; - wire usb_hpi_reset_n_; - - // Module instances - kotku_ml403 kotku ( - .tft_lcd_clk_ (lcd_clk), - .tft_lcd_r_ (lcd_r), - .tft_lcd_g_ (lcd_g), - .tft_lcd_b_ (lcd_b), - .tft_lcd_hsync_ (lcd_hsync), - .tft_lcd_vsync_ (lcd_vsync), - - .sys_clk_in_ (clk), - - .sram_clk_ (s_clk), - .sram_flash_addr_ (sf_addr), - .sram_flash_data_ (sf_data), - .sram_flash_oe_n_ (sf_oe), - .sram_flash_we_n_ (sf_we), - .sram_bw_ (s_bw), - .sram_cen_ (s_ce), - .sram_adv_ld_n_ (s_adv), - .flash_ce2_ (f_ce), - - .aceusb_a_ (aceusb_a_), - .aceusb_d_ (aceusb_d_), - .aceusb_oe_n_ (aceusb_oe_n_), - .aceusb_we_n_ (aceusb_we_n_), - - .ace_clkin_ (ace_clk), - .ace_mpce_n_ (ace_mpce_n_), - - .usb_cs_n_ (usb_cs_n_), - .usb_hpi_reset_n_ (usb_hpi_reset_n_) - ); - - flash_stub fs0 ( - .flash_addr_ (sf_addr), - .flash_data_ (sf_data), - .flash_oe_n_ (sf_oe), - .flash_we_n_ (sf_we), - .flash_ce2_ (f_ce) - ); - - cy7c1354 zbt ( - .d (sf_data), - .clk (s_clk), - .a (sf_addr[17:0]), - .bws (s_bw), - .we_b (sf_we), - .adv_lb (s_adv), - .ce1b (s_ce), - .ce2 (1'b1), - .ce3b (1'b0), - .oeb (sf_oe), - .cenb (1'b0), - .mode (1'b0) - ); - - // Behaviour - // Clock generation - always #5 clk = ~clk; - always #15 ace_clk = ~ace_clk; - - initial - begin - clk <= 1'b0; - ace_clk <= 1'b0; - but <= 1'b0; - #100000 but <= 1'b1; - #700000 but <= 1'b0; - #700000 but <= 1'b1; - end - -endmodule Index: trunk/impl/virtex4-ml403ep/sim/s.do =================================================================== --- trunk/impl/virtex4-ml403ep/sim/s.do (revision 53) +++ trunk/impl/virtex4-ml403ep/sim/s.do (nonexistent) @@ -1,48 +0,0 @@ -vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl -add wave -label clk100 /testbench/clk -add wave -label clk /testbench/kotku/clk -add wave -label rst /testbench/kotku/rst -add wave -label pc -radix hexadecimal /testbench/kotku/zet_proc/fetch0/pc -add wave -divider fetch -add wave -label state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/state -add wave -label next_state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/next_state -add wave -label opcode -radix hexadecimal /testbench/kotku/zet_proc/fetch0/opcode -add wave -label modrm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/modrm -add wave -label seq_addr /testbench/kotku/zet_proc/fetch0/decode0/seq_addr -add wave -label end_seq /testbench/kotku/zet_proc/fetch0/end_seq -add wave -label need_modrm /testbench/kotku/zet_proc/fetch0/need_modrm -add wave -label need_off /testbench/kotku/zet_proc/fetch0/need_off -add wave -label need_imm /testbench/kotku/zet_proc/fetch0/need_imm -add wave -label ir /testbench/kotku/zet_proc/fetch0/ir -add wave -label imm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/imm -add wave -label off -radix hexadecimal /testbench/kotku/zet_proc/fetch0/off -add wave -divider mem -add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs -add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op -add wave -label block /testbench/kotku/zet_proc/wm0/cpu_block -add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o -add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i -add wave -label adr -radix hexadecimal /testbench/kotku/adr -add wave -label byte_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_byte_o -add wave -label sel_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_sel_o -add wave -label stb_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_stb_o -add wave -label cyc_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_cyc_o -add wave -label ack_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_ack_i -add wave -label we_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_we_o -add wave -label tga_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_tga_o -add wave -label cpu_dat_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_dat_i -add wave -divider alu -add wave -label x -radix hexadecimal /testbench/kotku/zet_proc/exec0/a -add wave -label y -radix hexadecimal /testbench/kotku/zet_proc/exec0/bus_b -add wave -label t -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/t -add wave -label func -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/func -add wave -label r\[1\] -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\] -add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d -add wave -label addr_a /testbench/kotku/zet_proc/exec0/reg0/addr_a -add wave -label addr_d /testbench/kotku/zet_proc/exec0/reg0/addr_d -add wave -label wr /testbench/kotku/zet_proc/exec0/reg0/wr -add wave -label we /testbench/kotku/we -add wave -label ack /testbench/kotku/ack -add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec -add memory /testbench/zbt/mem -run 3ms Index: trunk/impl/virtex4-ml403ep/sim/t.do =================================================================== --- trunk/impl/virtex4-ml403ep/sim/t.do (revision 53) +++ trunk/impl/virtex4-ml403ep/sim/t.do (nonexistent) @@ -1,72 +0,0 @@ -quit -sim -vdel -all -lib work -vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims -vlib work -vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../../../soc/aceusb/rtl/aceusb_access.v ../../../soc/timer.v ../../../soc/simple_pic.v ../../../soc/aceusb/rtl/aceusb_sync.v ../../../soc/aceusb/rtl/aceusb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v -vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v -vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl -add wave -label clk100 /testbench/clk -add wave -label clk /testbench/kotku/zet_proc/wb_clk_i -add wave -label rst /testbench/kotku/rst -add wave -label pc -radix hexadecimal /testbench/kotku/zet_proc/fetch0/pc -add wave -divider fetch -add wave -label state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/state -add wave -label next_state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/next_state -add wave -label opcode -radix hexadecimal /testbench/kotku/zet_proc/fetch0/opcode -add wave -label modrm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/modrm -add wave -label seq_addr /testbench/kotku/zet_proc/fetch0/decode0/seq_addr -add wave -label end_seq /testbench/kotku/zet_proc/fetch0/end_seq -add wave -label need_modrm /testbench/kotku/zet_proc/fetch0/need_modrm -add wave -label need_off /testbench/kotku/zet_proc/fetch0/need_off -add wave -label off_size /testbench/kotku/zet_proc/fetch0/off_size -add wave -label need_imm /testbench/kotku/zet_proc/fetch0/need_imm -add wave -label imm_size /testbench/kotku/zet_proc/fetch0/imm_size -add wave -label ir /testbench/kotku/zet_proc/fetch0/ir -add wave -label imm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/imm -add wave -label off -radix hexadecimal /testbench/kotku/zet_proc/fetch0/off -add wave -divider regfile -add wave -label ax -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[0\] -add wave -label cx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\] -add wave -label dx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[2\] -add wave -label si -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[6\] -add wave -label tmp -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[13\] -add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d\[15:0\] -add wave -label wr -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/wr -add wave -divider wb_master -add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs -add wave -label ns -radix hexadecimal /testbench/kotku/zet_proc/wm0/ns -add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op -add wave -label wb_block /testbench/kotku/zet_proc/wb_block -add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o -add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i -add wave -label adr -radix hexadecimal /testbench/kotku/adr -add wave -label odd_word -radix hexadecimal /testbench/kotku/zet_proc/wm0/odd_word -add wave -label byte_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_byte_o -add wave -label sel_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_sel_o -add wave -label stb_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_stb_o -add wave -label cyc_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_cyc_o -add wave -label ack_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_ack_i -add wave -label we_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_we_o -add wave -label tga_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_tga_o -add wave -label cpu_dat_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_dat_i -add wave -divider flash -add wave -radix hexadecimal /sf_addr -add wave -radix hexadecimal /sf_data -add wave -radix hexadecimal /sf_oe -add wave -radix hexadecimal /sf_we -add wave -radix hexadecimal /f_ce -add wave -divider alu -add wave -label x -radix hexadecimal /testbench/kotku/zet_proc/exec0/a -add wave -label y -radix hexadecimal /testbench/kotku/zet_proc/exec0/bus_b -add wave -label t -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/t -add wave -label func -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/func -add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d -add wave -label addr_a /testbench/kotku/zet_proc/exec0/reg0/addr_a -add wave -label addr_d /testbench/kotku/zet_proc/exec0/reg0/addr_d -add wave -label wr /testbench/kotku/zet_proc/exec0/reg0/wr -add wave -label we /testbench/kotku/we -add wave -label ack /testbench/kotku/ack -add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec -add wave -divider zbt -add wave -radix hexadecimal -r /testbench/kotku/zbt0/* -run 50us Index: trunk/impl/virtex4-ml403ep/syn/ila.xco =================================================================== --- trunk/impl/virtex4-ml403ep/syn/ila.xco (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/ila.xco (nonexistent) @@ -1,131 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Sat Feb 28 12:16:13 2009 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc4vfx12 -SET devicefamily = virtex4 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ff668 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -10 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a -# END Select -# BEGIN Parameters -CSET component_name=ila -CSET counter_width_1=32 -CSET counter_width_10=Disabled -CSET counter_width_11=16 -CSET counter_width_12=Disabled -CSET counter_width_13=Disabled -CSET counter_width_14=Disabled -CSET counter_width_15=Disabled -CSET counter_width_16=Disabled -CSET counter_width_2=Disabled -CSET counter_width_3=32 -CSET counter_width_4=Disabled -CSET counter_width_5=Disabled -CSET counter_width_6=Disabled -CSET counter_width_7=Disabled -CSET counter_width_8=Disabled -CSET counter_width_9=Disabled -CSET data_port_width=0 -CSET data_same_as_trigger=true -CSET enable_storage_qualification=true -CSET enable_trigger_output_port=false -CSET exclude_from_data_storage_1=false -CSET exclude_from_data_storage_10=false -CSET exclude_from_data_storage_11=false -CSET exclude_from_data_storage_12=false -CSET exclude_from_data_storage_13=false -CSET exclude_from_data_storage_14=false -CSET exclude_from_data_storage_15=false -CSET exclude_from_data_storage_16=false -CSET exclude_from_data_storage_2=false -CSET exclude_from_data_storage_3=false -CSET exclude_from_data_storage_4=false -CSET exclude_from_data_storage_5=false -CSET exclude_from_data_storage_6=false -CSET exclude_from_data_storage_7=false -CSET exclude_from_data_storage_8=false -CSET exclude_from_data_storage_9=false -CSET match_type_1=basic -CSET match_type_10=basic -CSET match_type_11=basic -CSET match_type_12=basic -CSET match_type_13=basic -CSET match_type_14=basic -CSET match_type_15=basic -CSET match_type_16=range -CSET match_type_2=basic -CSET match_type_3=basic -CSET match_type_4=basic -CSET match_type_5=basic -CSET match_type_6=basic -CSET match_type_7=basic -CSET match_type_8=basic -CSET match_type_9=basic -CSET match_units_1=1 -CSET match_units_10=1 -CSET match_units_11=1 -CSET match_units_12=1 -CSET match_units_13=1 -CSET match_units_14=1 -CSET match_units_15=1 -CSET match_units_16=1 -CSET match_units_2=1 -CSET match_units_3=1 -CSET match_units_4=1 -CSET match_units_5=1 -CSET match_units_6=1 -CSET match_units_7=1 -CSET match_units_8=1 -CSET match_units_9=1 -CSET max_sequence_levels=16 -CSET number_of_trigger_ports=16 -CSET sample_data_depth=1024 -CSET sample_on=Rising -CSET trigger_port_width_1=20 -CSET trigger_port_width_10=16 -CSET trigger_port_width_11=21 -CSET trigger_port_width_12=16 -CSET trigger_port_width_13=9 -CSET trigger_port_width_14=3 -CSET trigger_port_width_15=5 -CSET trigger_port_width_16=32 -CSET trigger_port_width_2=32 -CSET trigger_port_width_3=20 -CSET trigger_port_width_4=6 -CSET trigger_port_width_5=6 -CSET trigger_port_width_6=6 -CSET trigger_port_width_7=16 -CSET trigger_port_width_8=16 -CSET trigger_port_width_9=32 -CSET use_rpms=true -# END Parameters -GENERATE -# CRC: c1a9a9f1 - Index: trunk/impl/virtex4-ml403ep/syn/Makefile =================================================================== --- trunk/impl/virtex4-ml403ep/syn/Makefile (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/Makefile (nonexistent) @@ -1,43 +0,0 @@ -all: kotku_ml403.bit - -run: tmp/kotku_ml403.bit - (cd tmp/ && ../../../../bin/ml403 kotku_ml403.bit) - -debug: tmp/mult.v tmp/icon.v tmp/ila.v kotku-dbg.prj kotku-dbg.xst - (cd tmp/ && xst -ifn ../kotku-dbg.xst) - -tmp/icon.v: icon.xco - mkdir -p tmp - (cd tmp/ && coregen -b ../icon.xco) - -tmp/ila.v: ila.xco - mkdir -p tmp - (cd tmp/ && coregen -b ../ila.xco) - -Zet.ace: tmp/kotku_ml403.bit - (cd tmp/ && ../../ace/ml40x_bit2ace kotku_ml403.bit ../Zet.ace ../../ace/) - -tmp/mult.v: mult.xco - mkdir -p tmp - (cd tmp/ && coregen -b ../mult.xco) - -tmp/kotku_ml403.ngc: tmp/mult.v kotku.prj kotku.xst - (cd tmp/ && xst -ifn ../kotku.xst) - -tmp/kotku_ml403.ngd: tmp/kotku_ml403.ngc ml403.ucf tmp/mult.ngc - (cd tmp/ && ngdbuild -uc ../ml403.ucf kotku_ml403.ngc) - -tmp/kotku_ml403.ncd: tmp/kotku_ml403.ngd - (cd tmp/ && map kotku_ml403.ngd) - -tmp/kotku_ml403-par.ncd: tmp/kotku_ml403.ncd - (cd tmp/ && par -w kotku_ml403.ncd kotku_ml403-par.ncd) - -tmp/kotku_ml403.bit: tmp/kotku_ml403-par.ncd - (cd tmp/ && bitgen -w kotku_ml403-par.ncd kotku_ml403.bit) - -kotku_ml403.bit: tmp/kotku_ml403.bit - cp tmp/kotku_ml403.bit /home/zeus/tmp - -clean: - rm -fR Zet.ace tmp/ Index: trunk/impl/virtex4-ml403ep/syn/clock.v =================================================================== --- trunk/impl/virtex4-ml403ep/syn/clock.v (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/clock.v (nonexistent) @@ -1,87 +0,0 @@ -module clock #( - parameter div = 16 // main clock divider - ) ( - input sys_clk_in_, - output clk, - output clk_100M, - output vdu_clk, - output rst - ); - - // Register declarations - reg [6:0] count; - - // Net declarations - wire ref_clk; - wire ref_clk0; - wire lock; - wire vdu_lock; - wire fpga_lock; - wire vdu_clk0; - wire fpga_fb; - wire fpga_fb0; - wire fpga_clk0; - - // Module instantiations - IBUFG ref_buf ( - .O (ref_clk), - .I (sys_clk_in_) - ); - - // DCM for the VGA - 25 Mhz - DCM_ADV vdu_dcm ( - .CLKIN (ref_clk), - .CLKFB (clk_100M), - .CLK0 (ref_clk0), - .CLKDV (vdu_clk0), - .RST (1'b0), - .LOCKED (vdu_lock) - ); - defparam vdu_dcm.CLKIN_PERIOD = 10.000; - defparam vdu_dcm.CLKDV_DIVIDE = 4; - defparam vdu_dcm.DCM_AUTOCALIBRATION = "FALSE"; - - BUFG b_clk_100M ( - .O (clk_100M), - .I (ref_clk0) - ); - - BUFG b_vdu_clk ( - .O (vdu_clk), - .I (vdu_clk0) - ); - - // fpga DCM - DCM_ADV fpga_dcm ( - .CLKIN (ref_clk), - .CLKFB (fpga_fb), - .CLK0 (fpga_fb0), - .CLKDV (fpga_clk0), - .RST (1'b0), - .LOCKED (fpga_lock) - ); - defparam fpga_dcm.CLKIN_PERIOD = 10.000; - defparam fpga_dcm.CLKDV_DIVIDE = div; - defparam fpga_dcm.DCM_AUTOCALIBRATION = "FALSE"; - - BUFG b_fpga_fb ( - .O (fpga_fb), - .I (fpga_fb0) - ); - - BUFG b_fpga_clk ( - .O (clk), - .I (fpga_clk0) - ); - - // Continuous assignments - assign rst = (count!=7'h7f); - assign lock = vdu_lock & fpga_lock; - - // Behavioral description - // count - always @(posedge clk) - if (!lock) count <= 7'b0; - else count <= (count==7'h7f) ? count : (count + 7'h1); - -endmodule Index: trunk/impl/virtex4-ml403ep/syn/icon.xco =================================================================== --- trunk/impl/virtex4-ml403ep/syn/icon.xco (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/icon.xco (nonexistent) @@ -1,47 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Tue Nov 11 20:50:43 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc4vfx12 -SET devicefamily = virtex4 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ff668 -SET removerpms = False -SET simulationfiles = Structural -SET speedgrade = -10 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.03.a -# END Select -# BEGIN Parameters -CSET component_name=icon -CSET enable_jtag_bufg=true -CSET number_control_ports=1 -CSET use_ext_bscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -GENERATE -# CRC: 7feea034 - Index: trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj =================================================================== --- trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj (nonexistent) @@ -1,32 +0,0 @@ -verilog work "../../../../rtl-model/util/div_uu.v" -verilog work "../../../../rtl-model/util/primitives.v" -verilog work "../../../../rtl-model/util/div_su.v" -verilog work "../../../../rtl-model/rotate.v" -verilog work "mult.v" -verilog work "icon.v" -verilog work "ila.v" -verilog work "../../../../rtl-model/regfile.v" -verilog work "../../../../rtl-model/jmp_cond.v" -verilog work "../../../../rtl-model/alu.v" -verilog work "../../../../soc/vga/rtl/ram2k_b16_attr.v" -verilog work "../../../../soc/vga/rtl/ram2k_b16.v" -verilog work "../../../../soc/vga/rtl/char_rom_b16.v" -verilog work "../../../../rtl-model/fetch.v" -verilog work "../../../../rtl-model/exec.v" -verilog work "../../../../soc/vga/rtl/vdu.v" -verilog work "../../../../soc/keyb/rtl/ps2_keyb.v" -verilog work "../../../../soc/aceusb/rtl/aceusb_access.v" -verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v" -verilog work "../../../../soc/aceusb/rtl/aceusb.v" -verilog work "../../../../soc/timer.v" -verilog work "../../../../rtl-model/cpu.v" -verilog work "../../mem/zbt_cntrl.v" -verilog work "../../mem/flash_cntrl.v" -verilog work "../../dbg/hw_dbg.v" -verilog work "../../dbg/send_serial.v" -verilog work "../../dbg/send_addr.v" -verilog work "../../dbg/pc_trace.v" -verilog work "../../dbg/clk_uart.v" -verilog work "../clock.v" -verilog work "../kotku.v" -verilog work "../../lcd/lcd_display.v" \ No newline at end of file Index: trunk/impl/virtex4-ml403ep/syn/kotku.v =================================================================== --- trunk/impl/virtex4-ml403ep/syn/kotku.v (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/kotku.v (nonexistent) @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2008 Zeus Gomez Marmolejo - * - * This file is part of the Zet processor. This processor is free - * hardware; you can redistribute it and/or modify it under the terms of - * the GNU General Public License as published by the Free Software - * Foundation; either version 3, or (at your option) any later version. - * - * Zet is distrubuted in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Zet; see the file COPYING. If not, see - * . - */ - -`timescale 1ns/10ps -`include "defines.v" - -module kotku_ml403 ( -`ifdef DEBUG - (* LOC="B6" *) input butc_, - (* LOC="F10" *) input bute_, - (* LOC="E9" *) input butw_, - (* LOC="E7" *) input butn_, - (* LOC="A6" *) input buts_, -`endif - output rs_, - output rw_, - output e_, - output [ 7:4] db_, - - output trx_, - - output tft_lcd_clk_, - output [ 1:0] tft_lcd_r_, - output [ 1:0] tft_lcd_g_, - output [ 1:0] tft_lcd_b_, - output tft_lcd_hsync_, - output tft_lcd_vsync_, - - input sys_clk_in_, - - output sram_clk_, - output [20:0] sram_flash_addr_, - inout [31:0] sram_flash_data_, - output sram_flash_oe_n_, - output sram_flash_we_n_, - output [ 3:0] sram_bw_, - output sram_cen_, - output sram_adv_ld_n_, - output flash_ce2_, - - inout ps2_clk_, - inout ps2_data_, - - output [ 6:1] aceusb_a_, - inout [15:0] aceusb_d_, - output aceusb_oe_n_, - output aceusb_we_n_, - - input ace_clkin_, - output ace_mpce_n_, - - output usb_cs_n_, - output usb_hpi_reset_n_ - ); - - // Net declarations - wire clk; - wire sys_clk; - wire rst2; - wire rst_lck; - wire [15:0] dat_i; - wire [15:0] dat_o; - wire [19:1] adr; - wire we; - wire tga; - wire stb; - wire ack; - wire [15:0] io_dat_i; - wire [ 1:0] sel; - wire cyc; - wire [ 7:0] keyb_dat_o; - wire keyb_io_arena; - wire keyb_io_status; - wire keyb_arena; - - wire [15:0] vdu_dat_o; - wire vdu_ack_o; - wire vdu_mem_arena; - wire vdu_io_arena; - wire vdu_arena; - wire [15:0] flash_dat_o; - wire flash_stb; - wire flash_ack; - wire flash_mem_arena; - wire flash_io_arena; - wire flash_arena; - wire [15:0] zbt_dat_o; - wire zbt_stb; - wire zbt_ack; - wire [20:0] flash_addr_; - wire [20:0] sram_addr_; - wire flash_we_n_; - wire sram_we_n_; - wire intr; - wire inta; - wire clk_100M; - wire rst; - wire [15:0] vdu_dat_i; - wire [11:1] vdu_adr_i; - wire vdu_we_i; - wire [ 1:0] vdu_sel_i; - wire vdu_stb_i; - wire vdu_tga_i; - - wire [19:1] zbt_adr_i; - wire zbt_we_i; - wire [ 1:0] zbt_sel_i; - wire zbt_stb_i; - - wire [15:0] ace_dat_o; - wire ace_ack; - wire ace_stb; - wire ace_io_arena; - wire ace_arena; - - wire [ 1:0] int; - wire iid; - -`ifdef DEBUG - reg [31:0] cnt_time; - wire [35:0] control0; - wire [ 5:0] funct; - wire [ 2:0] state, next_state; - wire [15:0] x, y; - wire [15:0] imm; - wire [63:0] f1, f2; - wire [15:0] m1, m2; - wire [19:0] pc; - wire [15:0] cs, ip; - wire [15:0] aluo; - wire [ 2:0] cnt; - wire op; - wire block; - wire cpu_block; - wire clk_921600; - wire [15:0] ax, dx, bp, si, es; - wire [15:0] c; - wire [ 3:0] addr_c; - wire [15:0] cpu_dat_o; - wire [15:0] d; - wire [ 3:0] addr_d; - wire byte_op; - wire [ 8:0] flags; - - wire [15:0] dbg_vdu_dat_o; - wire [11:1] dbg_vdu_adr_o; - wire dbg_vdu_we_o; - wire dbg_vdu_stb_o; - wire [ 1:0] dbg_vdu_sel_o; - wire dbg_vdu_tga_o; - - wire [19:1] dbg_zbt_adr_o; - wire dbg_zbt_we_o; - wire [ 1:0] dbg_zbt_sel_o; - wire dbg_zbt_stb_o; - - wire [ 2:0] old_zet_st; - wire [ 4:0] pack; - wire [19:0] tr_dat; - wire tr_new_pc; - wire tr_st; - wire tr_stb; - wire tr_ack; - wire addr_st; - - wire end_seq; - wire ext_int; - wire cpu_block2; - - wire [ 1:0] irr; - - wire rx_output_strobe; - wire rx_shifting_done; - wire released; -`endif - - // Register declarations - reg [15:0] io_reg; - reg [ 1:0] vdu_stb_sync; - reg [ 1:0] vdu_ack_sync; - - // Module instantiations - clock #( - .div (8) - ) c0 ( - .clk_100M (clk_100M), - .sys_clk_in_ (sys_clk_in_), - .clk (sys_clk), - .vdu_clk (tft_lcd_clk_), - .rst (rst_lck) - ); - - vdu vdu0 ( - // Wishbone signals - .wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock - .wb_rst_i (rst2), - .wb_dat_i (vdu_dat_i), - .wb_dat_o (vdu_dat_o), - .wb_adr_i (vdu_adr_i), - .wb_we_i (vdu_we_i), - .wb_tga_i (vdu_tga_i), - .wb_sel_i (vdu_sel_i), - .wb_stb_i (vdu_stb_i), - .wb_cyc_i (vdu_stb_i), - .wb_ack_o (vdu_ack_o), - - // VGA pad signals - .vga_red_o (tft_lcd_r_), - .vga_green_o (tft_lcd_g_), - .vga_blue_o (tft_lcd_b_), - .horiz_sync (tft_lcd_hsync_), - .vert_sync (tft_lcd_vsync_) - ); - - flash_cntrl #( - .timeout (4) - ) fc0 ( - // Wishbone slave interface - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_dat_i (dat_o), - .wb_dat_o (flash_dat_o), - .wb_adr_i (adr[16:1]), - .wb_we_i (we), - .wb_tga_i (tga), - .wb_stb_i (flash_stb), - .wb_cyc_i (flash_stb), - .wb_ack_o (flash_ack), - - // Pad signals - .flash_addr_ (flash_addr_), - .flash_data_ (sram_flash_data_[15:0]), - .flash_we_n_ (flash_we_n_), - .flash_ce2_ (flash_ce2_) - ); - - zbt_cntrl zbt0 ( -`ifdef DEBUG - .cnt (cnt), - .op (op), -`endif - .wb_clk_i (clk), - .wb_rst_i (rst2), - .wb_dat_i (dat_o), - .wb_dat_o (zbt_dat_o), - .wb_adr_i (zbt_adr_i), - .wb_we_i (zbt_we_i), - .wb_sel_i (zbt_sel_i), - .wb_stb_i (zbt_stb_i), - .wb_cyc_i (zbt_stb_i), - .wb_ack_o (zbt_ack), - - // Pad signals - .sram_clk_ (sram_clk_), - .sram_addr_ (sram_addr_), - .sram_data_ (sram_flash_data_), - .sram_we_n_ (sram_we_n_), - .sram_bw_ (sram_bw_), - .sram_cen_ (sram_cen_), - .sram_adv_ld_n_ (sram_adv_ld_n_) - ); - - ps2_keyb #(1500, // number of clks for 60usec. - 11, // number of bits needed for 60usec. timer - 120, // number of clks for debounce - 7 // number of bits needed for debounce timer - ) keyboard0 ( // Instance name -`ifdef DEBUG - .rx_output_strobe (rx_output_strobe), - .rx_shifting_done (rx_shifting_done), - .released (released), -`endif - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_dat_o (keyb_dat_o), - .wb_tgc_o (int[1]), - - .ps2_clk_ (ps2_clk_), - .ps2_data_ (ps2_data_) - ); - - timer #( - .res (34), - .phase (12507) - ) timer0 ( - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_tgc_o (int[0]) - ); - - simple_pic pic0 ( -`ifdef DEBUG - .irr (irr), -`endif - .clk (clk), - .rst (rst), - .int (int), - .inta (inta), - .intr (intr), - .iid (iid) - ); - - aceusb ace_cf ( - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_adr_i (adr[6:1]), - .wb_dat_i (dat_o), - .wb_dat_o (ace_dat_o), - .wb_cyc_i (ace_stb), - .wb_stb_i (ace_stb), - .wb_we_i (we), - .wb_ack_o (ace_ack), - - .aceusb_a_ (aceusb_a_), - .aceusb_d_ (aceusb_d_), - .aceusb_oe_n_ (aceusb_oe_n_), - .aceusb_we_n_ (aceusb_we_n_), - - .ace_clkin_ (ace_clkin_), - .ace_mpce_n_ (ace_mpce_n_), - - .usb_cs_n_ (usb_cs_n_), - .usb_hpi_reset_n_ (usb_hpi_reset_n_) - ); - - cpu zet_proc ( -`ifdef DEBUG - .cs (cs), - .ip (ip), - .state (state), - .next_state (next_state), - .iralu (funct), - .x (x), - .y (y), - .imm (imm), - .aluo (aluo), - .ax (ax), - .dx (dx), - .bp (bp), - .si (si), - .es (es), - .dbg_block (cpu_block), - .c (c), - .addr_c (addr_c), - .cpu_dat_o (cpu_dat_o), - .d (d), - .byte_exec (byte_op), - .addr_d (addr_d), - .flags (flags), - .end_seq (end_seq), - .ext_int (ext_int), - .cpu_block (cpu_block2), -`endif - - // Wishbone master interface - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_dat_i (dat_i), - .wb_dat_o (dat_o), - .wb_adr_o (adr), - .wb_we_o (we), - .wb_tga_o (tga), - .wb_sel_o (sel), - .wb_stb_o (stb), - .wb_cyc_o (cyc), - .wb_ack_i (ack), - .wb_tgc_i (intr), - .wb_tgc_o (inta) - ); - -`ifdef DEBUG - // Module instantiations - - icon icon0 ( - .CONTROL0 (control0) - ); - - ila ila0 ( - .CONTROL (control0), - .CLK (clk), - .TRIG0 (adr), - .TRIG1 ({dat_o,dat_i}), - .TRIG2 (pc), - .TRIG3 ({clk,we,tga,cyc,stb,ack}), - .TRIG4 (funct), - .TRIG5 ({state,next_state}), - .TRIG6 ({intr,inta,flags,byte_op,addr_d}), - .TRIG7 (d), - .TRIG8 ({x,y}), - .TRIG9 (aluo), - .TRIG10 ({ace_mpce_n_,aceusb_we_n_,aceusb_oe_n_, - ace_ack,ace_stb,ace_dat_o}), - .TRIG11 (aceusb_d_), - .TRIG12 ({1'b0,rx_output_strobe,rx_shifting_done,released,int,irr,iid}), - .TRIG13 (cnt), - .TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}), - .TRIG15 (cnt_time) - ); - - lcd_display lcd0 ( - .f1 (f1), // 1st row - .f2 (f2), // 2nd row - .m1 (m1), // 1st row mask - .m2 (m2), // 2nd row mask - - .clk (clk_100M), // 100 Mhz clock - .rst (rst_lck), - - // Pad signals - .lcd_rs_ (rs_), - .lcd_rw_ (rw_), - .lcd_e_ (e_), - .lcd_dat_ (db_) - ); - - hw_dbg dbg0 ( - .clk (clk), - .rst_lck (rst_lck), - .rst (rst), - .butc_ (butc_), - .bute_ (bute_), - .butw_ (butw_), - .butn_ (butn_), - .buts_ (buts_), - - .vdu_dat_o (dbg_vdu_dat_o), - .vdu_adr_o (dbg_vdu_adr_o), - .vdu_we_o (dbg_vdu_we_o), - .vdu_stb_o (dbg_vdu_stb_o), - .vdu_sel_o (dbg_vdu_sel_o), - .vdu_tga_o (dbg_vdu_tga_o), - .vdu_ack_i (vdu_ack_sync[1]), - - .zbt_dat_i (zbt_dat_o), - .zbt_adr_o (dbg_zbt_adr_o), - .zbt_we_o (dbg_zbt_we_o), - .zbt_sel_o (dbg_zbt_sel_o), - .zbt_stb_o (dbg_zbt_stb_o), - .zbt_ack_i (zbt_ack) - ); - - clk_uart clk0 ( - .clk_100M (clk_100M), - .rst (rst_lck), - .clk_921600 (clk_921600), - .rst2 (rst2) - ); - - pc_trace pc0 ( - .old_zet_st (old_zet_st), - - .dat (tr_dat), - .new_pc (tr_new_pc), - .st (tr_st), - .stb (tr_stb), - .ack (tr_ack), - .pack (pack), - .addr_st (addr_st), - .trx_ (trx_), - - .clk (clk), - .rst (rst2), - .pc (pc), - .zet_st (state), - .block (block) - ); - - // Continuous assignments - assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 }; - assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc }; - assign m1 = 16'b1011110111101010; - assign m2 = 16'b1111101110011111; - - assign pc = (cs << 4) + ip; - - assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o; - assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1]; - assign vdu_we_i = rst ? dbg_vdu_we_o : we; - assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel; - assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena; - assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga; - assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr; - assign zbt_we_i = rst ? dbg_zbt_we_o : we; - assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel; - assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb; -`ifdef DEBUG_TRACE - assign cpu_block = block; -`else - assign cpu_block = 1'b0; -`endif -`else - assign vdu_dat_i = dat_o; - assign vdu_adr_i = adr[11:1]; - assign vdu_we_i = we; - assign vdu_sel_i = sel; - assign vdu_stb_i = stb & cyc & vdu_arena; - assign vdu_tga_i = tga; - assign zbt_adr_i = adr; - assign zbt_we_i = we; - assign zbt_sel_i = sel; - assign zbt_stb_i = zbt_stb; - assign rst2 = rst_lck; - - assign rs_ = 1'b1; - assign e_ = 1'b0; - assign rw_ = 1'b1; - assign db_ = 4'h0; - assign trx_ = 1'b1; -`endif - -`ifdef DEBUG_TRACE - assign clk = clk_921600; -`else -// assign clk = sys_clk; - assign clk = tft_lcd_clk_; -`endif - - assign io_dat_i = flash_io_arena ? flash_dat_o - : (vdu_io_arena ? vdu_dat_o - : (keyb_io_arena ? keyb_dat_o - : (keyb_io_status ? 16'h10 - : (ace_io_arena ? ace_dat_o : 16'h0)))); - assign dat_i = inta ? { 15'b0000_0000_0000_100, iid } - : (tga ? io_dat_i - : (vdu_mem_arena ? vdu_dat_o - : (flash_mem_arena ? flash_dat_o : zbt_dat_o))); - - assign flash_mem_arena = (adr[19:16]==4'hc || adr[19:16]==4'hf); - assign vdu_mem_arena = (adr[19:12]==8'hb8); - - assign flash_io_arena = (adr[15:9]==7'b1110_000); - assign vdu_io_arena = (adr[15:4]==12'h03d) && - ((adr[3:1]==3'h2 && we) - || (adr[3:1]==3'h5 && !we)); - - assign keyb_io_arena = (adr[15:1]==15'h0030 && !we); - assign ace_io_arena = (adr[15:7]==9'b1110_0010_0); - - // MS-DOS is reading IO address 0x64 to check the inhibit bit - assign keyb_io_status = (adr[15:1]==15'h0032 && !we); - - assign flash_arena = (!tga & flash_mem_arena) - | (tga & flash_io_arena); - assign vdu_arena = (!tga & vdu_mem_arena) - | (tga & vdu_io_arena); - assign keyb_arena = (tga & keyb_io_arena); - assign ace_arena = (tga & ace_io_arena); - - assign flash_stb = flash_arena & stb & cyc; - assign zbt_stb = !vdu_mem_arena & !flash_mem_arena - & !tga & stb & cyc; - assign ace_stb = ace_arena & stb & cyc; - - assign ack = tga ? (flash_io_arena ? flash_ack - : (vdu_io_arena ? vdu_ack_o - : (ace_io_arena ? ace_ack : (stb & cyc)))) - : (vdu_mem_arena ? vdu_ack_o - : (flash_mem_arena ? flash_ack : zbt_ack)); - - assign sram_flash_oe_n_ = 1'b0; - assign sram_flash_addr_ = flash_arena ? flash_addr_ - : sram_addr_; - assign sram_flash_we_n_ = flash_arena ? flash_we_n_ - : sram_we_n_; - - // Behaviour - // vdu_stb_sync[0] - always @(posedge tft_lcd_clk_) - vdu_stb_sync[0] <= vdu_stb_i; - - // vdu_stb_sync[1] - always @(posedge clk) - vdu_stb_sync[1] <= vdu_stb_sync[0]; - - // vdu_ack_sync[0] - always @(posedge clk) vdu_ack_sync[0] <= vdu_ack_o; - - // vdu_ack_sync[1] - always @(posedge clk) vdu_ack_sync[1] <= vdu_ack_sync[0]; - - // io_reg - always @(posedge clk) - io_reg <= rst ? 16'h0 - : ((tga && stb && cyc && we && adr[15:8]==8'hf1) ? - dat_o : io_reg ); - -`ifdef DEBUG - // cnt_time - always @(posedge clk) - cnt_time <= rst ? 32'h0 : (cnt_time + 32'h1); -`else - assign rst = rst_lck; -`endif -endmodule Index: trunk/impl/virtex4-ml403ep/syn/kotku-dbg.xst =================================================================== --- trunk/impl/virtex4-ml403ep/syn/kotku-dbg.xst (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/kotku-dbg.xst (nonexistent) @@ -1,57 +0,0 @@ -run --ifn ../kotku-dbg.prj --ifmt mixed --ofn kotku_ml403 --ofmt NGC --p xc4vfx12-10-ff668 --top kotku_ml403 --opt_mode Speed --opt_level 1 --power NO --iuc NO --keep_hierarchy NO --netlist_hierarchy as_optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --use_dsp48 auto --iobuf YES --max_fanout 500 --bufg 32 --bufr 16 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: trunk/impl/virtex4-ml403ep/syn/kotku.prj =================================================================== --- trunk/impl/virtex4-ml403ep/syn/kotku.prj (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/kotku.prj (nonexistent) @@ -1,25 +0,0 @@ -verilog work "../../../../rtl-model/util/div_uu.v" -verilog work "../../../../rtl-model/util/primitives.v" -verilog work "../../../../rtl-model/util/div_su.v" -verilog work "../../../../rtl-model/rotate.v" -verilog work "mult.v" -verilog work "../../../../rtl-model/regfile.v" -verilog work "../../../../rtl-model/jmp_cond.v" -verilog work "../../../../rtl-model/alu.v" -verilog work "../../../../soc/vga/rtl/ram2k_b16_attr.v" -verilog work "../../../../soc/vga/rtl/ram2k_b16.v" -verilog work "../../../../soc/vga/rtl/char_rom_b16.v" -verilog work "../../../../rtl-model/fetch.v" -verilog work "../../../../rtl-model/exec.v" -verilog work "../../../../soc/vga/rtl/vdu.v" -verilog work "../../../../soc/keyb/rtl/ps2_keyb.v" -verilog work "../../../../soc/aceusb/rtl/aceusb_access.v" -verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v" -verilog work "../../../../soc/aceusb/rtl/aceusb.v" -verilog work "../../../../soc/timer.v" -verilog work "../../../../soc/simple_pic.v" -verilog work "../../../../rtl-model/cpu.v" -verilog work "../../mem/zbt_cntrl.v" -verilog work "../../mem/flash_cntrl.v" -verilog work "../clock.v" -verilog work "../kotku.v" Index: trunk/impl/virtex4-ml403ep/syn/mult.xco =================================================================== --- trunk/impl/virtex4-ml403ep/syn/mult.xco (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/mult.xco (nonexistent) @@ -1,62 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version K.39 -# Date: Wed Nov 12 21:43:31 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc4vfx12 -SET devicefamily = virtex4 -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = ff668 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -12 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Multiplier family Xilinx,_Inc. 10.1 -# END Select -# BEGIN Parameters -CSET ccmimp=Distributed_Memory -CSET clockenable=false -CSET component_name=mult -CSET constvalue=129 -CSET internaluser=0 -CSET multiplier_construction=Use_Mults -CSET multtype=Parallel_Multiplier -CSET optgoal=Speed -CSET outputwidthhigh=33 -CSET outputwidthlow=0 -CSET pipestages=1 -CSET portatype=Signed -CSET portawidth=17 -CSET portbtype=Signed -CSET portbwidth=17 -CSET roundpoint=0 -CSET sclrcepriority=SCLR_Overrides_CE -CSET syncclear=false -CSET use_custom_output_width=false -CSET userounding=false -CSET zerodetect=false -# END Parameters -GENERATE -# CRC: 39b5f86a - Index: trunk/impl/virtex4-ml403ep/syn/kotku.xst =================================================================== --- trunk/impl/virtex4-ml403ep/syn/kotku.xst (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/kotku.xst (nonexistent) @@ -1,57 +0,0 @@ -run --ifn ../kotku.prj --ifmt mixed --ofn kotku_ml403 --ofmt NGC --p xc4vfx12-10-ff668 --top kotku_ml403 --opt_mode Speed --opt_level 1 --power NO --iuc NO --keep_hierarchy NO --netlist_hierarchy as_optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --use_dsp48 auto --iobuf YES --max_fanout 500 --bufg 32 --bufr 16 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: trunk/impl/virtex4-ml403ep/syn/ml403.ucf =================================================================== --- trunk/impl/virtex4-ml403ep/syn/ml403.ucf (revision 53) +++ trunk/impl/virtex4-ml403ep/syn/ml403.ucf (nonexistent) @@ -1,210 +0,0 @@ -#NET sys_clk_in_ TNM_NET = "sys_clk_in_"; -#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %; - -NET sys_clk_in_ LOC = AE14; -NET sys_clk_in_ IOSTANDARD = LVCMOS33; - -NET sram_clk_ LOC = AF7 ; -NET "sram_clk_" IOSTANDARD = LVCMOS33; -NET "sram_clk_" DRIVE = 16; -NET "sram_clk_" SLEW = FAST; - -#NET sram_flash_addr_[24] LOC = T21; -#NET sram_flash_addr_[23] LOC = U20; -#NET sram_flash_addr_[22] LOC = T19; -NET sram_flash_addr_[20] LOC = AC5; -NET sram_flash_addr_[19] LOC = AB5; -NET sram_flash_addr_[18] LOC = AC4; -NET sram_flash_addr_[17] LOC = AB4; -NET sram_flash_addr_[16] LOC = AB3; -NET sram_flash_addr_[15] LOC = AA4; -NET sram_flash_addr_[14] LOC = AA3; -NET sram_flash_addr_[13] LOC = W5; -NET sram_flash_addr_[12] LOC = W6; -NET sram_flash_addr_[11] LOC = W3; -NET sram_flash_addr_[10] LOC = AF3; -NET sram_flash_addr_[9] LOC = AE3; -NET sram_flash_addr_[8] LOC = AD2; -NET sram_flash_addr_[7] LOC = AD1; -NET sram_flash_addr_[6] LOC = AC2; -NET sram_flash_addr_[5] LOC = AC1; -NET sram_flash_addr_[4] LOC = AB2; -NET sram_flash_addr_[3] LOC = AB1; -NET sram_flash_addr_[2] LOC = AA1; -NET sram_flash_addr_[1] LOC = Y2; -NET sram_flash_addr_[0] LOC = Y1; -#NET sram_flash_addr_[0] LOC = T20; - -NET "sram_flash_addr_<*>" IOSTANDARD = LVDCI_33; -NET "sram_flash_addr_<*>" SLEW = FAST; -NET "sram_flash_addr_<*>" DRIVE = 8; - -NET sram_flash_data_[31] LOC = F14; -NET sram_flash_data_[30] LOC = F13; -NET sram_flash_data_[29] LOC = F12; -NET sram_flash_data_[28] LOC = F11; -NET sram_flash_data_[27] LOC = F16; -NET sram_flash_data_[26] LOC = F15; -NET sram_flash_data_[25] LOC = D14; -NET sram_flash_data_[24] LOC = D13; -NET sram_flash_data_[23] LOC = D15; -NET sram_flash_data_[22] LOC = E14; -NET sram_flash_data_[21] LOC = C11; -NET sram_flash_data_[20] LOC = D11; -NET sram_flash_data_[19] LOC = D16; -NET sram_flash_data_[18] LOC = C16; -NET sram_flash_data_[17] LOC = E13; -NET sram_flash_data_[16] LOC = D12; -NET sram_flash_data_[15] LOC = AA14; -NET sram_flash_data_[14] LOC = AB14; -NET sram_flash_data_[13] LOC = AC12; -NET sram_flash_data_[12] LOC = AC11; -NET sram_flash_data_[11] LOC = AA16; -NET sram_flash_data_[10] LOC = AA15; -NET sram_flash_data_[9] LOC = AB13; -NET sram_flash_data_[8] LOC = AA13; -NET sram_flash_data_[7] LOC = AC14; -NET sram_flash_data_[6] LOC = AD14; -NET sram_flash_data_[5] LOC = AA12; -NET sram_flash_data_[4] LOC = AA11; -NET sram_flash_data_[3] LOC = AC16; -NET sram_flash_data_[2] LOC = AC15; -NET sram_flash_data_[1] LOC = AC13; -NET sram_flash_data_[0] LOC = AD13; - -NET "sram_flash_data_<*>" IOSTANDARD = LVCMOS33; -NET "sram_flash_data_<*>" PULLDOWN; - -NET sram_flash_oe_n_ LOC = AC6; -NET "sram_flash_oe_n_" IOSTANDARD = LVDCI_33; -NET "sram_flash_oe_n_" SLEW = FAST; -NET "sram_flash_oe_n_" DRIVE = 8; - -NET sram_flash_we_n_ LOC = AB6; -NET "sram_flash_we_n_" IOSTANDARD = LVDCI_33; -NET "sram_flash_we_n_" SLEW = FAST; -NET "sram_flash_we_n_" DRIVE = 8; - -NET sram_bw_[3] LOC = Y3; #Y4; -NET sram_bw_[2] LOC = Y4; #Y3; -NET sram_bw_[1] LOC = Y5; #Y6; -NET sram_bw_[0] LOC = Y6; #Y5; -NET "sram_bw_<*>" IOSTANDARD = LVDCI_33; -NET "sram_bw_<*>" SLEW = FAST; -NET "sram_bw_<*>" DRIVE = 8; - -NET sram_cen_ LOC = V7; -NET "sram_cen_" IOSTANDARD = LVDCI_33; -NET "sram_cen_" SLEW = FAST; -NET "sram_cen_" DRIVE = 8; - -NET sram_adv_ld_n_ LOC = W4; -NET "sram_adv_ld_n_" IOSTANDARD = LVDCI_33; -NET "sram_adv_ld_n_" SLEW = FAST; -NET "sram_adv_ld_n_" DRIVE = 8; - -NET flash_ce2_ LOC = W7; -NET "flash_ce2_" IOSTANDARD = LVDCI_33; -NET "flash_ce2_" SLEW = FAST; -NET "flash_ce2_" DRIVE = 8; - -#NET flash_byte_n LOC = N22; -#NET flash_audio_reset_n LOC = AD10; - -NET tft_lcd_clk_ LOC = AF8 | IOSTANDARD = LVCMOS33; -NET tft_lcd_r_[0] LOC = E5 | SLEW = FAST | DRIVE = 8; # VGA_R6 -NET tft_lcd_r_[1] LOC = E6 | SLEW = FAST | DRIVE = 8; # VGA_R7 -NET tft_lcd_g_[0] LOC = H8 | SLEW = FAST | DRIVE = 8; # VGA_G6 -NET tft_lcd_g_[1] LOC = C1 | SLEW = FAST | DRIVE = 8; # VGA_G7 -NET tft_lcd_b_[0] LOC = G8 | SLEW = FAST | DRIVE = 8; # VGA_B6 -NET tft_lcd_b_[1] LOC = F8 | SLEW = FAST | DRIVE = 8; # VGA_B7 -NET tft_lcd_hsync_ LOC = C10; -NET tft_lcd_vsync_ LOC = A8; - -NET tft_lcd_clk_ SLEW = FAST; -NET tft_lcd_clk_ DRIVE = 8; - -NET tft_lcd_hsync_ SLEW = FAST; -NET tft_lcd_hsync_ DRIVE = 8; - -NET tft_lcd_vsync_ SLEW = FAST; -NET tft_lcd_vsync_ DRIVE = 8; - -NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E -NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS -NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW - -NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7 -NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6 -NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5 -NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4 - -#NET butc_ LOC = B6; # C Button -#NET butw_ LOC = E9; # W Button -#NET bute_ LOC = F10; # E Button -#NET butn_ LOC = E7; # N Button -#NET buts_ LOC = A6; # S Button - -NET trx_ LOC = W1 | IOSTANDARD = LVCMOS33; - -#NET led_[0] LOC = G5; #GPLED0 -#NET led_[1] LOC = G6; #GPLED1 -#NET led_[2] LOC = A11; #GPLED2 -#NET led_[3] LOC = A12; #GPLED3 - -# North-East-South-West-Center LEDs -#NET led_[4] LOC = C6; # C LED -#NET led_[5] LOC = F9; # W LED -#NET led_[6] LOC = A5; # S LED -#NET led_[7] LOC = E10; # E LED -#NET led_[8] LOC = E2; # N LED - -#Keyboard -NET ps2_clk_ LOC = D2; -NET ps2_clk_ SLEW = SLOW; -NET ps2_clk_ DRIVE = 2; -NET ps2_clk_ TIG; -NET ps2_data_ LOC = G9; -NET ps2_data_ SLEW = SLOW; -NET ps2_data_ DRIVE = 2; -NET ps2_data_ TIG; - -# Shared signals -NET "aceusb_a_<1>" LOC = Y10; -NET "aceusb_a_<2>" LOC = AA10; -NET "aceusb_a_<3>" LOC = AC7; -NET "aceusb_a_<4>" LOC = Y7; -NET "aceusb_a_<5>" LOC = AA9; -NET "aceusb_a_<6>" LOC = Y9; -NET "aceusb_a_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; -NET "aceusb_d_<0>" LOC = AB7; -NET "aceusb_d_<1>" LOC = AC9; -NET "aceusb_d_<2>" LOC = AB9; -NET "aceusb_d_<3>" LOC = AE6; -NET "aceusb_d_<4>" LOC = AD6; -NET "aceusb_d_<5>" LOC = AF9; -NET "aceusb_d_<6>" LOC = AE9; -NET "aceusb_d_<7>" LOC = AD8; -NET "aceusb_d_<8>" LOC = AC8; -NET "aceusb_d_<9>" LOC = AF4; -NET "aceusb_d_<10>" LOC = AE4; -NET "aceusb_d_<11>" LOC = AD3; -NET "aceusb_d_<12>" LOC = AC3; -NET "aceusb_d_<13>" LOC = AF6; -NET "aceusb_d_<14>" LOC = AF5; -NET "aceusb_d_<15>" LOC = AA7; -NET "aceusb_d_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN; -NET "aceusb_oe_n_" LOC = AA8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; -NET "aceusb_we_n_" LOC = Y8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; - -# SystemACE signals -NET "ace_clkin_" LOC = AF11; -NET "ace_clkin_" IOSTANDARD = LVCMOS33; -NET "ace_clkin_" TNM_NET = "ace_clkin_"; -TIMESPEC "TSace" = PERIOD "ace_clkin_" 30 ns HIGH 50% INPUT_JITTER 1 ns; - -NET "ace_mpce_n_" LOC = AD5 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; - -# USB signals -NET "usb_cs_n_" LOC = AF10 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; -NET "usb_hpi_reset_n_" LOC = A7 | IOSTANDARD = LVCMOS25 | TIG; Index: trunk/impl/virtex4-ml403ep/dbg/pc_trace.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/pc_trace.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/pc_trace.v (nonexistent) @@ -1,85 +0,0 @@ -`timescale 1ns/10ps -`include "defines.v" - -module pc_trace ( -`ifdef DEBUG - output reg [ 2:0] old_zet_st, - output reg [19:0] dat, - output reg new_pc, - output reg st, - output reg stb, - output ack, - output [ 4:0] pack, - output addr_st, -`endif - // PAD signals - output trx_, - - input clk, - input rst, - input [19:0] pc, - input [ 2:0] zet_st, - output reg block - ); - -`ifndef DEBUG - // Registers and nets - reg [19:0] dat; - reg [ 2:0] old_zet_st; - reg new_pc; - reg st; - reg stb; - wire ack; -`endif - wire op_st; - wire rom; - - // Module instantiations - send_addr ser0 ( -`ifdef DEBUG - .pack (pack), - .st (addr_st), -`endif - .trx_ (trx_), - .wb_clk_i (clk), - .wb_rst_i (rst), - .wb_dat_i (dat), - .wb_we_i (stb), - .wb_stb_i (stb), - .wb_cyc_i (stb), - .wb_ack_o (ack) - ); - - // Continous assignments - assign op_st = (zet_st == 3'b0); - assign rom = pc[19:16]==4'hf || pc[19:16]==4'hc; - - // Behaviour - // old_zet_st - always @(posedge clk) - old_zet_st <= rst ? 3'b0 : zet_st; - - // new_pc - always @(posedge clk) - new_pc <= rst ? 1'b0 - : (op_st ? (zet_st!=old_zet_st && !rom) : 1'b0); - - // block - always @(posedge clk) - block <= rst ? 1'b0 - : (new_pc ? (st & !ack) : (ack ? 1'b0 : block)); - - // dat - always @(posedge clk) - dat <= rst ? 20'h0 - : ((new_pc & !st) ? pc : (ack ? pc : dat)); - - // stb - always @(posedge clk) - stb <= rst ? 1'b0 : (ack ? 1'b0 : (st | new_pc)); - - // st - always @(posedge clk) - st <= rst ? 1'b0 - : (st ? (ack ? (new_pc | block) : 1'b1) : new_pc); -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/sim_addr.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/sim_addr.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/sim_addr.v (nonexistent) @@ -1,46 +0,0 @@ -`timescale 1ns/10ps - -module sim_addr; - - // Registers and nets - reg clk_100M; - reg rst; - reg stb; - wire clk_921600; - wire trx_; - wire rst2; - wire ack; - - // Module instantiation - clk_uart clk0 ( - .clk_100M (clk_100M), - .rst (rst), - .clk_921600 (clk_921600), - .rst2 (rst2) - ); - - send_addr ser0 ( - .trx_ (trx_), - .wb_clk_i (clk_921600), - .wb_rst_i (rst2), - .wb_dat_i (20'h4fb31), - .wb_we_i (1'b1), - .wb_stb_i (stb), - .wb_cyc_i (1'b1), - .wb_ack_o (ack) - ); - - // Behaviour - initial - begin - stb <= 1'b1; - clk_100M <= 1'b0; - rst <= 1'b1; - #400 rst <= 1'b0; - #33635 stb <= 1'b0; - #10000 stb <= 1'b1; - end - - // clk_50M - always #5 clk_100M <= !clk_100M; -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/send_addr.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/send_addr.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/send_addr.v (nonexistent) @@ -1,75 +0,0 @@ -`timescale 1ns/10ps -`include "defines.v" - -module send_addr ( -`ifdef DEBUG - output reg [ 4:0] pack, - output reg st, -`endif - // Serial pad signal - output trx_, - - // Wishbone slave interface - input wb_clk_i, - input wb_rst_i, - input [19:0] wb_dat_i, - input wb_we_i, - input wb_stb_i, - input wb_cyc_i, - output wb_ack_o - ); - - // Registers and nets -`ifndef DEBUG - reg [4:0] pack; - reg st; -`endif - wire op; - wire start; - wire sack; - wire [7:0] dat; - wire [7:0] b0, b1, b2, b3, b4; - - // Module instantiation - send_serial ss0 ( - .trx_ (trx_), - - .wb_clk_i (wb_clk_i), - .wb_rst_i (wb_rst_i), - .wb_dat_i (dat), - .wb_we_i (wb_we_i), - .wb_stb_i (wb_stb_i), - .wb_cyc_i (wb_cyc_i), - .wb_ack_o (sack) - ); - - // Continuous assignments - assign op = wb_we_i & wb_stb_i & wb_cyc_i; - assign start = !st & op; - assign wb_ack_o = st & sack & pack[4]; - - assign dat = st & pack[0] ? - (pack[1] ? (pack[2] ? (pack[3] ? (pack[4] ? 8'h0a : b0) - : b1) : b2) : b3) : b4; - - assign b0 = { 1'b0, ascii(wb_dat_i[ 3: 0]) }; - assign b1 = { 1'b0, ascii(wb_dat_i[ 7: 4]) }; - assign b2 = { 1'b0, ascii(wb_dat_i[11: 8]) }; - assign b3 = { 1'b0, ascii(wb_dat_i[15:12]) }; - assign b4 = { 1'b0, ascii(wb_dat_i[19:16]) }; - - // Behaviour - // pack - always @(posedge wb_clk_i) - pack <= wb_rst_i ? 5'b0 : (start ? 5'b0 - : (st ? (sack ? { pack[3:0], 1'b1 } : pack) : 5'b0)); - - // st - always @(posedge wb_clk_i) - st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op); - - function [6:0] ascii(input [3:0] num); - if (num <= 4'd9) ascii = 7'h30 + num; - else ascii = 7'd87 + num; - endfunction -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/clk_uart.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/clk_uart.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/clk_uart.v (nonexistent) @@ -1,34 +0,0 @@ - /* - * Phase accumulator clock: - * Fo = Fc * N / 2^bits - * here N: 154619 and bits: 24 - */ - -module clk_uart ( - input clk_100M, - input rst, - output clk_921600, - output rst2 - ); - - // Registers - reg [25:0] cnt; - reg [ 2:0] init; - - // Continuous assignments - assign clk_921600 = cnt[25]; - assign rst2 = init[2]; - - // Behaviour - // cnt - always @(posedge clk_100M) - cnt <= rst ? 26'd0 : cnt + 26'd154619; - - // init[0] - always @(posedge clk_100M) - init[0] <= rst ? 1'b1 : (clk_921600 ? 1'b0 : init[0]); - - // init[2:1] - always @(posedge clk_921600) - init[2:1] <= init[0] ? 2'b11 : init[1:0]; -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/sim_serial.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/sim_serial.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/sim_serial.v (nonexistent) @@ -1,46 +0,0 @@ -`timescale 1ns/10ps - -module sim_serial; - - // Registers and nets - reg clk_100M; - reg rst; - reg stb; - wire clk_921600; - wire trx_; - wire rst2; - wire ack; - - // Module instantiation - clk_uart clk0 ( - .clk_100M (clk_100M), - .rst (rst), - .clk_921600 (clk_921600), - .rst2 (rst2) - ); - - send_serial ser0 ( - .trx_ (trx_), - .wb_clk_i (clk_921600), - .wb_rst_i (rst2), - .wb_dat_i (8'h4b), - .wb_we_i (1'b1), - .wb_stb_i (stb), - .wb_cyc_i (1'b1), - .wb_ack_o (ack) - ); - - // Behaviour - initial - begin - stb <= 1'b1; - clk_100M <= 1'b0; - rst <= 1'b1; - #400 rst <= 1'b0; - #95490 stb <= 1'b0; - #40000 stb <= 1'b1; - end - - // clk_50M - always #5 clk_100M <= !clk_100M; -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/send_serial.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/send_serial.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/send_serial.v (nonexistent) @@ -1,44 +0,0 @@ - -module send_serial ( - // Serial pad signal - output reg trx_, - - // Wishbone slave interface - input wb_clk_i, - input wb_rst_i, - input [7:0] wb_dat_i, - input wb_we_i, - input wb_stb_i, - input wb_cyc_i, - output reg wb_ack_o - ); - - // Registers and nets - wire op; - wire start; - reg [8:0] tr; - reg st; - reg [7:0] sft; - - // Continuous assignments - assign op = wb_we_i & wb_stb_i & wb_cyc_i; - assign start = !st & op; - - // Behaviour - // trx_ - always @(posedge wb_clk_i) - trx_ <= wb_rst_i ? 1'b1 : (start ? 1'b0 : tr[0]); - - // tr - always @(posedge wb_clk_i) - tr <= wb_rst_i ? 9'h1ff - : { 1'b1, (start ? wb_dat_i : tr[8:1]) }; - - // sft, wb_ack_o - always @(posedge wb_clk_i) - { sft, wb_ack_o } <= wb_rst_i ? 9'h0 : { start, sft }; - - // st - always @(posedge wb_clk_i) - st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op); -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/hw_dbg.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/hw_dbg.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/hw_dbg.v (nonexistent) @@ -1,411 +0,0 @@ -/* - * Copyright (c) 2009 Zeus Gomez Marmolejo - * - * Nobody can figure out what this file is for... hehe - * - * This file is part of the Zet processor. This processor is free - * hardware; you can redistribute it and/or modify it under the terms of - * the GNU General Public License as published by the Free Software - * Foundation; either version 3, or (at your option) any later version. - * - * Zet is distrubuted in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Zet; see the file COPYING. If not, see - * . - */ - -`timescale 1ns/10ps - -module hw_dbg ( - input clk, - input rst_lck, - output reg rst, - input butc_, - input bute_, - input butw_, - input butn_, - input buts_, - - // Wishbone master interface for the VDU - output reg [15:0] vdu_dat_o, - output reg [11:1] vdu_adr_o, - output vdu_we_o, - output vdu_stb_o, - output [ 1:0] vdu_sel_o, - output reg vdu_tga_o, - input vdu_ack_i, - - // Wishbone master interface for the ZBT SRAM - input [15:0] zbt_dat_i, - output [19:1] zbt_adr_o, - output zbt_we_o, - output [ 1:0] zbt_sel_o, - output reg zbt_stb_o, - input zbt_ack_i - ); - - // Registers and nets - reg [ 5:0] st; - reg op; - reg [ 6:0] cur; - reg mr, ml, md, mu, dm; - reg br, bl, bd, bu, bc; - reg [15:0] cnt; - reg [ 4:0] i; - reg [19:0] adr; - reg [ 2:0] sp; - reg [15:0] col; - reg [ 3:0] nibb; - reg [ 7:0] low_adr; - - wire [7:0] o; - wire cur_dump; - wire action; - wire [2:0] off; - wire [3:0] nib, inc_nib, dec_nib; - wire up_down; - wire left_right; - wire spg; - - // Module instantiations - init_msg msg0 ( - .i (i), - .o (o) - ); - - inc i0 ( - .i (nib), - .o (inc_nib) - ); - - dec d0 ( - .i (nib), - .o (dec_nib) - ); - - // Continuous assignments - assign vdu_we_o = op; - assign vdu_stb_o = op; - assign vdu_sel_o = 2'b11; - assign zbt_we_o = 1'b0; - assign zbt_sel_o = 2'b11; - assign cur_dump = (cur < 7'd25 && cur > 7'd19); - assign off = cur - 7'd20; - assign nib = off==3'd0 ? adr[19:16] - : (off==3'd1 ? adr[15:12] - : (off==3'd2 ? adr[11:8] - : (off==3'd3 ? adr[7:4] : adr[3:0]))); - - assign left_right = mr | ml; - assign up_down = mu | md; - assign action = left_right | up_down | dm; - assign spg = sp>3'b0; - assign zbt_adr_o = { adr[19:5] + low_adr[7:4], low_adr[3:0] }; - - // Behaviour - always @(posedge clk) - if (rst_lck) - begin - vdu_dat_o <= 16'd12; - vdu_adr_o <= 11'h4; - vdu_tga_o <= 1'b1; - st <= 6'd0; - op <= 1'b1; - i <= 4'h0; - zbt_stb_o <= 1'b0; - end - else - case (st) - 6'd0: if (vdu_ack_i) begin - vdu_dat_o <= { 8'h06, o }; - vdu_adr_o <= i + 5'h4; - vdu_tga_o <= 1'b0; - st <= (i==5'd21) ? 6'h2 : 6'h1; - op <= 1'b0; - i <= i + 5'h1; - end - 6'd1: if (!vdu_ack_i) begin - st <= 6'h0; - op <= 1'b1; - i <= i; - end - 6'd2: // main wait state - if (!vdu_ack_i && action) begin - vdu_dat_o <= mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1) - : ((ml && cur==7'd20) ? 7'd15 : cur - 7'b1); - vdu_adr_o <= 11'h0; - vdu_tga_o <= 1'b1; - st <= left_right ? 6'h3 : (dm ? 6'h5 : 6'h4); - op <= left_right; - col <= 16'd80; - sp <= 2'h3; - nibb <= 4'h0; - end - 6'd3: if (vdu_ack_i) begin - vdu_dat_o <= 16'h0; - vdu_adr_o <= 11'h0; - vdu_tga_o <= 1'b1; - st <= 6'h2; - op <= 1'b0; - end - 6'd4: // redraw the mem_dump counter - if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h03, itoa(nib) }; - vdu_adr_o <= cur; - vdu_tga_o <= 1'b0; - st <= 6'h3; - op <= 1'b1; - end - 6'd5: // memory dump - if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h05, spg ? 8'h20 : itoa(nibb) }; - vdu_adr_o <= col; - vdu_tga_o <= 1'b0; - st <= 6'h6; - op <= 1'b1; - sp <= spg ? (sp - 3'b1) : 3'd4; - col <= col + 16'd1; - nibb <= spg ? nibb : (nibb + 4'h2); - end - 6'd6: if (vdu_ack_i) begin - st <= (col==16'd160) ? 6'h7 : 6'h5; - op <= 1'b0; - end - 6'd7: begin - low_adr <= 8'h0; - st <= 6'h8; - end - 6'd8: if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h5, itoa(zbt_adr_o[7:4]) }; - vdu_adr_o <= col; - st <= 6'd9; - op <= 1'b1; - end - 6'd9: if (vdu_ack_i) begin - st <= 6'd10; - op <= 1'b0; - col <= col + 16'd1; - end - 6'd10: if (!zbt_ack_i) begin - st <= 6'd11; - zbt_stb_o <= 1'b1; - end - 6'd11: if (zbt_ack_i) begin - st <= 6'd12; - zbt_stb_o <= 1'b0; - end - 6'd12: if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[15:12]) }; - vdu_adr_o <= col; - st <= 6'd13; - op <= 1'b1; - end - 6'd13: if (vdu_ack_i) begin - st <= 6'd14; - op <= 1'b0; - col <= col + 16'd1; - end - 6'd14: if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[11:8]) }; - vdu_adr_o <= col; - st <= 6'd15; - op <= 1'b1; - end - 6'd15: if (vdu_ack_i) begin - st <= 6'd16; - op <= 1'b0; - col <= col + 16'd1; - end - 6'd16: if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[7:4]) }; - vdu_adr_o <= col; - st <= 6'd17; - op <= 1'b1; - end - 6'd17: if (vdu_ack_i) begin - st <= 6'd18; - op <= 1'b0; - col <= col + 16'd1; - end - 6'd18: if (!vdu_ack_i) begin - vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[3:0]) }; - vdu_adr_o <= col; - st <= 6'd19; - op <= 1'b1; - end - 6'd19: if (vdu_ack_i) begin - st <= (zbt_adr_o[4:1]==4'hf) ? 6'd22 : 6'd20; - op <= 1'b0; - col <= col + 16'd1; - low_adr <= low_adr + 8'h1; - end - 6'd20: if (!vdu_ack_i) begin - vdu_dat_o <= 16'h0720; - vdu_adr_o <= col; - st <= 6'd21; - op <= 1'b1; - end - 6'd21: if (vdu_ack_i) begin - st <= 6'd10; - op <= 1'b0; - col <= col + 16'd1; - end - 6'd22: st <= (low_adr==8'h0) ? 6'd2 : 6'd8; - endcase - - // rst - always @(posedge clk) - rst <= rst_lck ? 1'b1 : ((butc_ && cur==7'd12) ? 1'b0 : rst); - - // cur - always @(posedge clk) - cur <= rst_lck ? 7'd12 : (mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1) - : (ml ? (cur==7'd20 ? 7'd15 : cur - 7'b1) : cur)); - - // adr - always @(posedge clk) - adr <= rst_lck ? 16'h0 - : (mu ? (off==3'd0 ? { inc_nib, adr[15:0] } - : (off==3'd1 ? { adr[19:16], inc_nib, adr[11:0] } - : (off==3'd2 ? { adr[19:12], inc_nib, adr[7:0] } - : (off==3'd3 ? { adr[19:8], inc_nib, adr[3:0] } - : { adr[19:4], inc_nib })))) - : (md ? (off==3'd0 ? { dec_nib, adr[15:0] } - : (off==3'd1 ? { adr[19:16], dec_nib, adr[11:0] } - : (off==3'd2 ? { adr[19:12], dec_nib, adr[7:0] } - : (off==3'd3 ? { adr[19:8], dec_nib, adr[3:0] } - : { adr[19:4], dec_nib })))) : adr)); - - // mr - move right - always @(posedge clk) - mr <= rst_lck ? 1'b0 : (bute_ && !br - && cnt==16'h0 && cur != 7'd24); - - // br - button right - always @(posedge clk) br <= (cnt==16'h0 ? bute_ : br); - - // ml - move right - always @(posedge clk) - ml <= rst_lck ? 1'b0 : (butw_ && !bl - && cnt==16'h0 && cur != 7'd12); - - // bl - button right - always @(posedge clk) bl <= (cnt==16'h0 ? butw_ : bl); - - // md - move down - always @(posedge clk) - md <= rst_lck ? 1'b0 : (buts_ && !bd && cnt==16'h0 && cur_dump); - - // bd - button down - always @(posedge clk) bd <= (cnt==16'h0 ? buts_ : bd); - - // mu - move up - always @(posedge clk) - mu <= rst_lck ? 1'b0 : (butn_ && !bu && cnt==16'h0 && cur_dump); - - // bu - button up - always @(posedge clk) bu <= (cnt==16'h0 ? butn_ : bu); - - // dm - dump - always @(posedge clk) - dm <= rst_lck ? 1'b0 : (butc_ && !bc && cur==7'd13); - - // bc - center button - always @(posedge clk) bc <= (cnt==16'h0 ? butc_ : bc); - - // cnt - button counter - always @(posedge clk) cnt <= cnt + 1'b1; - - function [7:0] itoa; - input [3:0] i; - begin - if (i < 8'd10) itoa = i + 8'h30; - else itoa = i + 8'h57; - end - endfunction -endmodule - -module init_msg ( - input [4:0] i, - output reg [7:0] o - ); - - // Behaviour - always @(i) - case (i) - 5'h00: o <= 8'h68; // h - 5'h01: o <= 8'h77; // w - 5'h02: o <= 8'h5f; // _ - 5'h03: o <= 8'h64; // d - 5'h04: o <= 8'h62; // b - 5'h05: o <= 8'h67; // g - 5'h06: o <= 8'h20; // - 5'h07: o <= 8'h5b; // [ - 5'h08: o <= 8'h43; // C - 5'h09: o <= 8'h44; // D - 5'h0a: o <= 8'h57; // W - 5'h0b: o <= 8'h42; // B - 5'h0c: o <= 8'h5d; // ] - 5'h0d: o <= 8'h20; // - 5'h0f: o <= 8'h78; // x - default: o <= 8'h30; // 0 - endcase -endmodule - -module inc ( - input [3:0] i, - output reg [3:0] o - ); - - // Behaviour - always @(i) - case (i) - 4'h0: o <= 4'h1; - 4'h1: o <= 4'h2; - 4'h2: o <= 4'h3; - 4'h3: o <= 4'h4; - 4'h4: o <= 4'h5; - 4'h5: o <= 4'h6; - 4'h6: o <= 4'h7; - 4'h7: o <= 4'h8; - 4'h8: o <= 4'h9; - 4'h9: o <= 4'ha; - 4'ha: o <= 4'hb; - 4'hb: o <= 4'hc; - 4'hc: o <= 4'hd; - 4'hd: o <= 4'he; - 4'he: o <= 4'hf; - default: o <= 4'h0; - endcase -endmodule - -module dec ( - input [3:0] i, - output reg [3:0] o - ); - - // Behaviour - always @(i) - case (i) - 4'h0: o <= 4'hf; - 4'h1: o <= 4'h0; - 4'h2: o <= 4'h1; - 4'h3: o <= 4'h2; - 4'h4: o <= 4'h3; - 4'h5: o <= 4'h4; - 4'h6: o <= 4'h5; - 4'h7: o <= 4'h6; - 4'h8: o <= 4'h7; - 4'h9: o <= 4'h8; - 4'ha: o <= 4'h9; - 4'hb: o <= 4'ha; - 4'hc: o <= 4'hb; - 4'hd: o <= 4'hc; - 4'he: o <= 4'hd; - default: o <= 4'he; - endcase -endmodule Index: trunk/impl/virtex4-ml403ep/dbg/test_serial.v =================================================================== --- trunk/impl/virtex4-ml403ep/dbg/test_serial.v (revision 53) +++ trunk/impl/virtex4-ml403ep/dbg/test_serial.v (nonexistent) @@ -1,48 +0,0 @@ - - -module test_serial ( - input clk_, - output trx_ - ); - - // Registers and nets - wire clk_100M; - wire rst; - wire clk_921600; - wire rst2; - wire ack; - wire lock; - wire [19:0] inc_dat; - reg [19:0] dat; - - // Module instantiation - clocks c0 ( - .CLKIN_IN (clk_), - .CLK0_OUT (clk_100M), - .LOCKED_OUT (lock) - ); - - clk_uart clk0 ( - .clk_100M (clk_100M), - .rst (rst), - .clk_921600 (clk_921600), - .rst2 (rst2) - ); - - send_addr ser0 ( - .trx_ (trx_), - .wb_clk_i (clk_921600), - .wb_rst_i (rst2), - .wb_dat_i (dat), - .wb_we_i (1'b1), - .wb_stb_i (1'b1), - .wb_cyc_i (1'b1), - .wb_ack_o (ack) - ); - - assign rst = !lock; - assign inc_dat = dat + 20'h1; - - always @(posedge clk_921600) - dat <= rst2 ? 20'h12345 : (ack ? inc_dat : dat); -endmodule Index: trunk/impl/virtex4-ml403ep/mem/zbt_cntrl.v =================================================================== --- trunk/impl/virtex4-ml403ep/mem/zbt_cntrl.v (revision 53) +++ trunk/impl/virtex4-ml403ep/mem/zbt_cntrl.v (nonexistent) @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2008 Zeus Gomez Marmolejo - * - * This file is part of the Zet processor. This processor is free - * hardware; you can redistribute it and/or modify it under the terms of - * the GNU General Public License as published by the Free Software - * Foundation; either version 3, or (at your option) any later version. - * - * Zet is distrubuted in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Zet; see the file COPYING. If not, see - * . - */ - -`include "defines.v" - -module zbt_cntrl ( -`ifdef DEBUG - output reg [2:0] cnt, - output op, -`endif - - // Wishbone slave interface - input wb_clk_i, - input wb_rst_i, - input [15:0] wb_dat_i, - output reg [15:0] wb_dat_o, - input [19:1] wb_adr_i, - input wb_we_i, - input [ 1:0] wb_sel_i, - input wb_stb_i, - input wb_cyc_i, - output wb_ack_o, - - // Pad signals - output sram_clk_, - output reg [20:0] sram_addr_, - inout [31:0] sram_data_, - output reg sram_we_n_, - output reg [ 3:0] sram_bw_, - output reg sram_cen_, - output sram_adv_ld_n_ - ); - - // Registers and nets - reg [31:0] wr; - wire nload; - -`ifndef DEBUG - reg [ 3:0] cnt; - wire op; -`endif - - // Continuous assignments - assign op = wb_stb_i & wb_cyc_i; - assign nload = |cnt; - - assign sram_clk_ = wb_clk_i; - assign sram_adv_ld_n_ = 1'b0; - assign sram_data_ = (op && wb_we_i) ? wr : 32'hzzzzzzzz; - assign wb_ack_o = cnt[3]; - - // Behaviour - // cnt - always @(posedge wb_clk_i) - cnt <= wb_rst_i ? 4'b0 - : { cnt[2:0], nload ? 1'b0 : op }; - - // wb_dat_o - always @(posedge wb_clk_i) - wb_dat_o <= cnt[2] ? (wb_adr_i[1] ? sram_data_[31:16] - : sram_data_[15:0]) : wb_dat_o; - - // sram_addr_ - always @(posedge wb_clk_i) - sram_addr_ <= op ? { 3'b0, wb_adr_i[19:2] } : sram_addr_; - - // sram_we_n_ - always @(posedge wb_clk_i) - sram_we_n_ <= wb_we_i ? (nload ? 1'b1 : !op) : 1'b1; - - // sram_bw_ - always @(posedge wb_clk_i) - sram_bw_ <= wb_adr_i[1] ? { ~wb_sel_i, 2'b11 } - : { 2'b11, ~wb_sel_i }; - - // sram_cen_ - always @(posedge wb_clk_i) - sram_cen_ <= wb_rst_i ? 1'b1 : !op; - - // wr - always @(posedge wb_clk_i) - wr <= op ? (wb_adr_i[1] ? { wb_dat_i, 16'h0 } - : { 16'h0, wb_dat_i }) : wr; -endmodule Index: trunk/impl/virtex4-ml403ep/mem/flash_cntrl.v =================================================================== --- trunk/impl/virtex4-ml403ep/mem/flash_cntrl.v (revision 53) +++ trunk/impl/virtex4-ml403ep/mem/flash_cntrl.v (nonexistent) @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2008 Zeus Gomez Marmolejo - * - * This file is part of the Zet processor. This processor is free - * hardware; you can redistribute it and/or modify it under the terms of - * the GNU General Public License as published by the Free Software - * Foundation; either version 3, or (at your option) any later version. - * - * Zet is distrubuted in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - * License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Zet; see the file COPYING. If not, see - * . - */ - -module flash_cntrl #( - parameter timeout = 2 // read timeout (default: 2 cycles) - ) ( - // Wishbone slave interface - input wb_clk_i, - input wb_rst_i, - input [15:0] wb_dat_i, - output [15:0] wb_dat_o, - input [16:1] wb_adr_i, - input wb_we_i, - input wb_tga_i, - input wb_stb_i, - input wb_cyc_i, - output wb_ack_o, - - // Pad signals - output reg [20:0] flash_addr_, - input [15:0] flash_data_, - output flash_we_n_, - output reg flash_ce2_ - ); - - // Registers and nets - reg [ 11:0] base; - reg [timeout-1:0] sft_cnt; - - wire op; - wire opbase; - - // Continuous assignments - assign wb_dat_o = flash_data_; - assign flash_we_n_ = 1'b1; - assign op = wb_cyc_i & wb_stb_i; - assign opbase = op & wb_tga_i & wb_we_i; - assign wb_ack_o = sft_cnt[timeout-1]; - - // Behaviour - // flash_addr, 21 bits - always @(posedge wb_clk_i) - flash_addr_ <= wb_tga_i ? { 1'b1, base, wb_adr_i[8:1] } - : { 5'h0, wb_adr_i[16:1] }; - - always @(posedge wb_clk_i) flash_ce2_ <= op; - - // sft_cnt - always @(posedge wb_clk_i) - sft_cnt <= wb_rst_i ? 0 - : (op ? ((|sft_cnt) ? { sft_cnt[timeout-2:0], 1'b0 } - : { sft_cnt[timeout-2:0], 1'b1 }) : 0); - - // base - always @(posedge wb_clk_i) - base <= wb_rst_i ? 12'h0: ((opbase) ? wb_dat_i[11:0] : base); -endmodule Index: trunk/impl/virtex4-ml403ep/test/sram_dump.v =================================================================== --- trunk/impl/virtex4-ml403ep/test/sram_dump.v (revision 53) +++ trunk/impl/virtex4-ml403ep/test/sram_dump.v (nonexistent) @@ -1,157 +0,0 @@ -`define HIGH_RAM 13'h00fd - -module sram_dump ( - input sys_clk_in, - output trx, - - output sram_clk, - output [20:0] sram_flash_addr, - inout [15:0] sram_flash_data, - output [ 3:0] sram_bw, - - output sram_cen, - output sram_flash_oe_n, - output sram_flash_we_n, - output flash_ce - ); - - reg clk_9600; - reg [11:0] count_uart; - reg [ 6:0] dada_wr; - reg [ 7:0] estat; - reg [ 7:0] addr; - reg [ 2:0] espacios; - reg [ 6:0] char; - reg [ 3:0] nibble; - reg [ 7:0] col; - reg trx_req; - reg [ 8:0] adr0; - - wire clk_60M; - wire rst, lock; - wire trx_ack; - wire [15:0] rd_data; - - reg [15:0] ram[0:255]; - reg [15:0] dades; - - reg [ 3:0] count; - - // Instanciacions de mòduls - clocks c0 ( - .CLKIN_IN (sys_clk_in), - .CLKFX_OUT (clk_60M), - .LOCKED_OUT (lock) - ); - - uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx, - rst, clk_9600); - - // Assignacions contínues - assign rst = ~lock; - - assign sram_clk = clk_60M; - assign sram_flash_addr = { `HIGH_RAM, adr0[7:0] }; - assign rd_data = sram_flash_data; - assign sram_bw = 4'b00; - //assign SRAM_ADV_LB = 1'b0; - assign sram_cen = 1'b0; - assign sram_flash_oe_n = 1'b0; - assign sram_flash_we_n = 1'b1; - assign flash_ce = 1'b0; - - // Descripció del comportament - // count_uart - always @(posedge clk_60M) - if (rst) count_uart <= 12'h0; - else count_uart <= (count_uart==12'd3124) ? - 12'd0 : count_uart + 12'd1; - - // clk_9600 - always @(posedge clk_60M) - if (rst) clk_9600 <= 1'b0; - else clk_9600 <= (count_uart==12'd0) ? - !clk_9600 : clk_9600; - - // adr0 - always @(posedge clk_60M) - if (rst) adr0 <= 9'h000; - else adr0 <= (adr0==9'h1ff || count!=4'hf) ? adr0 - : (adr0 + 8'h01); - // count - always @(posedge clk_60M) - if (rst) count <= 4'h0; - else count <= count + 4'h1; - - // ram - always @(posedge clk_60M) ram[adr0] <= rd_data; - - // dades - always @(posedge clk_60M) - if (rst) dades <= 16'h0; - else dades <= ram[addr]; - - always @(posedge clk_60M) - if (adr0!=9'h1ff) - begin - dada_wr <= 7'h30; - trx_req <= 0; - estat <= 8'd0; - addr <= 8'h00; - espacios <= 3'd2; - char <= 7'd00; - nibble <= 4'd0; - col <= 8'd79; - end - else - case (estat) - 8'd00: if (~trx_ack) - begin estat <= 8'd01; - if (espacios > 3'd0) - begin char <= 7'h20; espacios <= espacios - 3'd1; end - else - begin - char <= ascii(nibble); espacios <= 3'd4; - nibble <= nibble + 4'd1; - end - end - 8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end - 8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end - 8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end - else estat <= 8'd04; - - 8'd04: if (~trx_ack) estat <= 8'd05; - 8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end - 8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end - - 8'd15: if (~trx_ack) estat <= 8'd20; - 8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end - 8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end - - 8'd30: if (~trx_ack) estat <= 8'd35; - 8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end - 8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end - - 8'd45: if (~trx_ack) estat <= 8'd50; - 8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end - 8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end - - 8'd60: if (~trx_ack) estat <= 8'd65; - 8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end - 8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end - - 8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90; - else if (~trx_ack) estat <= 8'd80; - 8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end - 8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end - - 8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end - else estat <= 8'd95; - 8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15; - endcase - - function [6:0] ascii(input [3:0] num); - if (num <= 4'd9) ascii = 7'h30 + num; - else ascii = 7'd87 + num; - endfunction -endmodule Index: trunk/impl/virtex4-ml403ep/test/ml403-sram.ucf =================================================================== --- trunk/impl/virtex4-ml403ep/test/ml403-sram.ucf (revision 53) +++ trunk/impl/virtex4-ml403ep/test/ml403-sram.ucf (nonexistent) @@ -1,146 +0,0 @@ -NET sys_clk_in TNM_NET = "sys_clk_in"; -TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; - -NET sys_clk_in LOC = AE14; -NET sys_clk_in IOSTANDARD = LVCMOS33; -#NET sys_rst_in LOC = D6; -#NET sys_rst_in PULLUP; -#NET sys_rst_in TIG; - -NET trx LOC = W1; -#NET trx IOSTANDARD = LVCMOS33; -#NET trx TIG; - -# GPLED 0-3 -#NET gpio[0] LOC = G5; #GPLED0 -#NET gpio[1] LOC = G6; #GPLED1 -#NET gpio[2] LOC = A11; #GPLED2 -#NET gpio[3] LOC = A12; #GPLED3 -# North-East-South-West-Center LEDs -#NET gpio[4] LOC = C6; # C LED -#NET gpio[5] LOC = F9; # W LED -#NET gpio[6] LOC = A5; # S LED -#NET gpio[7] LOC = E10; # E LED -#NET gpio[8] LOC = E2; # N LED - -#NET "gpio[*]" PULLDOWN; -#NET "gpio[*]" TIG; -#NET "gpio[*]" SLEW = SLOW; -#NET "gpio[*]" DRIVE = 2; - -NET "sram_clk" LOC = "AF7" ; #| IOSTANDARD = LVCMOS33 | DRIVE = 16 | SLEW = FAST; -NET "flash_ce" LOC = "W7" ; #| IOSTANDARD = LVDCI_33; - -#NET sram_clk_fb LOC = AD17; -#NET flash_a23 LOC = T21; -#NET sram_flash_addr[22] LOC = U20; -#NET sram_flash_addr[21] LOC = T19; -NET sram_flash_addr[20] LOC = AC5; -NET sram_flash_addr[19] LOC = AB5; -NET sram_flash_addr[18] LOC = AC4; -NET sram_flash_addr[17] LOC = AB4; - -NET sram_flash_addr[16] LOC = AB3; -NET sram_flash_addr[15] LOC = AA4; -NET sram_flash_addr[14] LOC = AA3; -NET sram_flash_addr[13] LOC = W5; -NET sram_flash_addr[12] LOC = W6; -NET sram_flash_addr[11] LOC = W3; -NET sram_flash_addr[10] LOC = AF3; -NET sram_flash_addr[9] LOC = AE3; -NET sram_flash_addr[8] LOC = AD2; -NET sram_flash_addr[7] LOC = AD1; -NET sram_flash_addr[6] LOC = AC2; -NET sram_flash_addr[5] LOC = AC1; -NET sram_flash_addr[4] LOC = AB2; -NET sram_flash_addr[3] LOC = AB1; -NET sram_flash_addr[2] LOC = AA1; -NET sram_flash_addr[1] LOC = Y2; -NET sram_flash_addr[0] LOC = Y1; -#NET sram_flash_data[31] LOC = F14; -#NET sram_flash_data[30] LOC = F13; -#NET sram_flash_data[29] LOC = F12; -#NET sram_flash_data[28] LOC = F11; -#NET sram_flash_data[27] LOC = F16; -#NET sram_flash_data[26] LOC = F15; -#NET sram_flash_data[25] LOC = D14; -#NET sram_flash_data[24] LOC = D13; -#NET sram_flash_data[23] LOC = D15; -#NET sram_flash_data[22] LOC = E14; -#NET sram_flash_data[21] LOC = C11; -#NET sram_flash_data[20] LOC = D11; -#NET sram_flash_data[19] LOC = D16; -#NET sram_flash_data[18] LOC = C16; -#NET sram_flash_data[17] LOC = E13; - -#NET sram_flash_data[16] LOC = D12; -#NET sram_flash_data[15] LOC = AA14; -#NET sram_flash_data[14] LOC = AB14; -#NET sram_flash_data[13] LOC = AC12; -#NET sram_flash_data[12] LOC = AC11; -#NET sram_flash_data[11] LOC = AA16; -#NET sram_flash_data[10] LOC = AA15; -#NET sram_flash_data[9] LOC = AB13; - -NET sram_flash_data[15] LOC = AA14; -NET sram_flash_data[14] LOC = AB14; -NET sram_flash_data[13] LOC = AC12; -NET sram_flash_data[12] LOC = AC11; -NET sram_flash_data[11] LOC = AA16; -NET sram_flash_data[10] LOC = AA15; -NET sram_flash_data[9] LOC = AB13; - -NET sram_flash_data[8] LOC = AA13; -NET sram_flash_data[7] LOC = AC14; -NET sram_flash_data[6] LOC = AD14; -NET sram_flash_data[5] LOC = AA12; -NET sram_flash_data[4] LOC = AA11; -NET sram_flash_data[3] LOC = AC16; -NET sram_flash_data[2] LOC = AC15; -NET sram_flash_data[1] LOC = AC13; -NET sram_flash_data[0] LOC = AD13; -NET sram_cen LOC = V7; -NET sram_flash_oe_n LOC = AC6; -NET sram_flash_we_n LOC = AB6; -NET sram_bw[3] LOC = Y3; #Y4; -NET sram_bw[2] LOC = Y4; #Y3; -NET sram_bw[1] LOC = Y5; #Y6; -NET sram_bw[0] LOC = Y6; #Y5; -#NET sram_adv_ld_n LOC = W4; -#NET sram_mode LOC = V26; - -#NET sram_clk_fb IOSTANDARD = LVCMOS33; - -#NET flash_a23 IOSTANDARD = LVDCI_33; -#NET sram_mode IOSTANDARD = LVDCI_33; - -#NET sram_flash_addr[*] IOSTANDARD = LVDCI_33; -#NET sram_flash_addr[*] SLEW = FAST; -#NET sram_flash_addr[*] DRIVE = 8; - -#NET sram_flash_data[*] IOSTANDARD = LVCMOS33; -#NET sram_flash_data[*] DRIVE = 12; -#NET sram_flash_data[*] SLEW = FAST; -#NET sram_flash_data[*] PULLDOWN; - -#NET sram_flash_oe_n IOSTANDARD = LVDCI_33; -#NET sram_flash_oe_n SLEW = FAST; -#NET sram_flash_oe_n DRIVE = 8; - -#NET sram_flash_we_n IOSTANDARD = LVDCI_33; -#NET sram_flash_we_n SLEW = FAST; -#NET sram_flash_we_n DRIVE = 8; - -#NET sram_bw[*] IOSTANDARD = LVDCI_33; -#NET sram_bw[*] SLEW = FAST; -#NET sram_bw[*] DRIVE = 8; - -#NET flash_ce SLEW = FAST; -#NET flash_ce DRIVE = 8; - -#NET sram_cen SLEW = FAST; -#NET sram_cen DRIVE = 8; - -#NET sram_adv_ld_n IOSTANDARD = LVDCI_33; -#NET sram_adv_ld_n SLEW = FAST; -#NET sram_adv_ld_n DRIVE = 8; Index: trunk/impl/virtex4-ml403ep/test/clocks.xaw =================================================================== --- trunk/impl/virtex4-ml403ep/test/clocks.xaw (revision 53) +++ trunk/impl/virtex4-ml403ep/test/clocks.xaw (nonexistent) @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e -$8;x77=(`fgn#wkzs.reg*vugox#ugcioz,p`usW|kyx"!llnahw+~f81;96>!0026?5(6?=;0=;5>0/2346=68980=;6417%kB5@7:2;S=6=<;5,;5>3030$9"=GU_SUDBAWPCMIJJZC_\LXEMA?:;@PT^ZIIDPUH@FGA_WCOQ@7e3HX\VRAALX]GGHYT_@^HDD@H_BNH55=FZ^PTCCBV_EFQ[F6682KY[WQ@NM[\@ATXK8;:7L\XZ^MMH\YCL[UH@F?9;@PT^ZIIDPUOH_QJDFGNKAC6>2KY[WQ@NM[\@ATXNEC[JAA_139BVR\XGGFRSIJ]_HLJP415:CQS_YHFESTJOQJXUGQJDJ6:2KY[WQ@NM[\MKUSWG_F=h5NRVX\KKJ^WCC_XH\PPJ0SOZHHFFCXIGPRVIGGRAZTQWW[Q_WMj1J[WQILNUW]UC?3H]QS]O]Te9BS_YTQG^CXBAC4:@LPM2EKCOR37NBDFY3;4<=DDBLSSO[If:AOOC^XJ\LLSD@\Tb9@HN@_WMC]EIKj;BNHB]YJ]E^B\AW6;BNHB]YH]]?0OAEFN038GIMNFVNBZDJJ_C[\6g=DDBCESDLZFF33?FJLAGUBNXHH_HLPPc=DDBCESDLZFF]LQQ>4:F@IZVBZOEYAL@LE^OL@@52:FOHZ@UMX_NBNWPMNFF6>BH<2NYHT?:;EWW]ZE^KEOTOB\]EBVJKK5C_\LXEMAo4F@AWKW_XBO?0JLB\E89EFZUH][INo6HJEE@BGNYE]O30JD@PUOKWWd=AG\^TYCG[S`9EKPRX^HF^I<5F5:KAQCA?3@D_I_@NL038NLRSM[UBB][[_U[SA3=KGHNNH;5COBIF@d=KGJANHRAZT29OKR?;N68KABU02E[\B]FTD`8TMGTMVYCEKZ6;QKMLDUE]Zk0\D@FSFLGAA>VTLFDN86^\EO:8TVOIKMOH?6\\Tc9PMBC_\LXEMA84SHLDH@e<[]KYXX^PW@KWf>U^FJBYCCAZS008W\USMDUXUCMGRNLLQV5<\FZ?7Y\ZE99VW@YE]OM27X]J_CWECV3<^@O\=o5WAV]UAWUNGG;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@90T^Z9;Yfa[Lb682RoaRCnjnpUawungg;;7Ujb_LkmkwPbzzcdb85T0;2^2>]728?V96U?:7_7?dtpr:1oo`l4vdppmjh'9':?7{fkl028|f2qnq;9!<5F;695~U3i33?648512051`0=:h93;v`7f;38j<6=<2.3i76l;|Q7=??320<1=><95d496d5cn2Y=477;:8495641=l<1>ll:f:Q7=??320<1=><95d496a36:2n287>51;3xW1g=1=02:7?<277f2?4f;1=0zY6n:182>4<>sZ>j64:597827702m?09m>68;c:5>5<72=02w)k5949'63<>?2.9;777;%0;>=b<,1h1h6l;e;295=<729q/;l4;d:&e>62<,8:14?5+1381f>"6i3297)?m:59'52<0<2.:?77`<,8?1>o5+17841>"603;0(<75859'5`<2m2.:j7;j;%03>0c<,=2156*<5;58 6e=k2.8h7o4$5291`=#<<0>7):9:4a8 11=?81/8k477:&64?0d3-?965;4$4192g=#=?0=n6*:9;:4?!3e2j1/9i47;%7e>30<,?;1:i5+63846>"1;3h0(;956d9'2c"?03227)?>:79'60<2=2.9=7<6;%3g>7=#9j087d=i:18'3<<>92.315<5+7c8;3>=n=0>1/;:477:9j11<72-=264<4$6:9<2=#?>03;65f5`83>!1>20;0(:658698m07=83.<577>;%5;>=1<3`>h6=4+788:5>"0032<76g70;29 2?=181/;5477:9j3`<72-=264?4$6:9<2=l1<7*89;;2?!1?21=07d9l:18'3<<>92.<4768;:m1f?6=,>315<5+7c8;3>"5;38j7)<;:728?j54290/;4461:9l6c<72-=264?4;n13>5<#?002=65`3583>!1>20;0(?=52`98k67=83.<577>;:m06?6=,>315<54o2:94?"0133:7)9m:958 75=:h10c>750;&4=??632e>47>5$6;9=4=92.315<54}c61>5<5290;w)9n:778m32=83.<577>;%5a>=1<3f=86=4+788:5>"0j32<76sm2e83>7<729q/;l4=a:k50?6=,>315<5+7c8;3>=h?:0;6)96:838 2d=0>10qo=m:181>5<7s-=j6?o4i7694?"0133:7)9m:958?j14290/;4461:&4f?>032wx8<4?:3y>0`<4n27?>79<;%01>1560<5;n1;>5+2381a>{t:j0;6?u24d81f>;5l3=1/4<494:p7`<728q6?o483:&;5?143ty??7>50z&;5?143ty9i7>50z&;5?143twe>n4?:0y~j7b=83;pqc4}zf:;1<7?t}o11>5<6std8?7>51zm71<728qvqpsO@By0a?`e<>>i=osO@Cy3yEFWstJK \ No newline at end of file Index: trunk/impl/virtex4-ml403ep/test/uart.v =================================================================== --- trunk/impl/virtex4-ml403ep/test/uart.v (revision 53) +++ trunk/impl/virtex4-ml403ep/test/uart.v (nonexistent) @@ -1,47 +0,0 @@ -module uart_ctrl(wr, trx_req, trx_ack, trx, - clr, clk); - // Entrades - input [6:0] wr; - input trx_req; - input clr, clk; - - // Sortides - output reg trx_ack, trx; - - // Registres - reg [7:0] et, etrx; - reg [6:0] data_wr; - - // Algorisme de transmissi� - always @(negedge clk) - if (clr) - begin - et <= 8'd00; - etrx <= 8'd00; - trx <= 1'b1; - trx_ack <= 1'b0; - end - else - case (et) - 8'd00: if (trx_req) et <= 8'd05; - 8'd05: - if (~trx_req) - begin et <= 8'd00; etrx <= 8'd00; end - else - case (etrx) - 8'd00: begin data_wr <= wr; trx <= 1'b1; etrx <= 8'd05; end - 8'd05: begin trx <= 1'b0; etrx <= 8'd10; end // Start bit - 8'd10: begin trx <= data_wr[0]; etrx <= 8'd15; end - 8'd15: begin trx <= data_wr[1]; etrx <= 8'd20; end - 8'd20: begin trx <= data_wr[2]; etrx <= 8'd25; end - 8'd25: begin trx <= data_wr[3]; etrx <= 8'd30; end - 8'd30: begin trx <= data_wr[4]; etrx <= 8'd35; end - 8'd35: begin trx <= data_wr[5]; etrx <= 8'd40; end - 8'd40: begin trx <= data_wr[6]; etrx <= 8'd45; end - 8'd45: begin trx <= 1'b0; etrx <= 8'd50; end - 8'd50: begin trx_ack <= 1'b1; trx <= 1'b1; etrx <= 8'd00; et <= 8'd10; end - endcase - 8'd10: if (~trx_req) begin trx_ack <= 1'b0; et <= 8'd00; end - endcase - -endmodule \ No newline at end of file Index: trunk/impl/virtex4-ml403ep/test/base.cpj =================================================================== --- trunk/impl/virtex4-ml403ep/test/base.cpj (revision 53) +++ trunk/impl/virtex4-ml403ep/test/base.cpj (nonexistent) @@ -1,4690 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Wed Mar 11 23:37:50 GMT+01:00 2009 -device.2.configFileDir=/home/zeus/tmp -device.2.configFilename=kotku_ml403.bit -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XCF32P -deviceChain.deviceName2=XC4VFX12 -deviceChain.deviceName3=XC9500XL -deviceChain.iRLength0=8 -deviceChain.iRLength1=16 -deviceChain.iRLength2=10 -deviceChain.iRLength3=8 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceChain.name2=MyDevice2 -deviceChain.name3=MyDevice3 -deviceIds=0a001093f505909321e5809359608093 -mdiAreaHeight=0.828042328042328 -mdiAreaHeightLast=0.828042328042328 -mdiCount=2 -mdiDevice0=2 -mdiDevice1=2 -mdiType0=1 -mdiType1=0 -mdiUnit0=0 -mdiUnit1=0 -navigatorHeight=0.42724867724867727 -navigatorHeightLast=0.15873015873015872 -navigatorWidth=0.17054263565891473 -navigatorWidthLast=0.11937984496124031 -unit.-1.-1.username= -unit.1.-1.username= -unit.2.-1.username= -unit.2.0.0.HEIGHT0=0.7977528 -unit.2.0.0.TriggerRow0=1 -unit.2.0.0.TriggerRow1=1 -unit.2.0.0.TriggerRow2=1 -unit.2.0.0.WIDTH0=0.58587784 -unit.2.0.0.X0=0.2509542 -unit.2.0.0.Y0=0.072231136 -unit.2.0.1.HEIGHT1=1.0 -unit.2.0.1.WIDTH1=1.0 -unit.2.0.1.X1=0.0 -unit.2.0.1.Y1=0.0 -unit.2.0.MFBitsA0=00110101110111001000 -unit.2.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.2.0.MFBitsA10=XXXXXXXXXXXXXXXXXXXXX -unit.2.0.MFBitsA11=XXXXXXXXXXXXXXXX -unit.2.0.MFBitsA12=XXXXXX1XX -unit.2.0.MFBitsA13=XXX -unit.2.0.MFBitsA14=XXXXX -unit.2.0.MFBitsA15=00000000001100011111001000000000 -unit.2.0.MFBitsA2=11100001100101111111 -unit.2.0.MFBitsA3=X1XX1X -unit.2.0.MFBitsA4=XXXXXX -unit.2.0.MFBitsA5=XXX000 -unit.2.0.MFBitsA6=XXXXXXXXXXXXXX1X -unit.2.0.MFBitsA7=XXXXXXXXXXXXXXXX -unit.2.0.MFBitsA8=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.2.0.MFBitsA9=XXXXXXXXXXXXXXXX -unit.2.0.MFBitsB0=00000000000000000000 -unit.2.0.MFBitsB1=00000000000000000000000000000000 -unit.2.0.MFBitsB10=000000000000000000000 -unit.2.0.MFBitsB11=0000000000000000 -unit.2.0.MFBitsB12=000000000 -unit.2.0.MFBitsB13=000 -unit.2.0.MFBitsB14=00000 -unit.2.0.MFBitsB15=00000000000000000000000000000000 -unit.2.0.MFBitsB2=00000000000000000000 -unit.2.0.MFBitsB3=000000 -unit.2.0.MFBitsB4=000000 -unit.2.0.MFBitsB5=000000 -unit.2.0.MFBitsB6=0000000000000000 -unit.2.0.MFBitsB7=0000000000000000 -unit.2.0.MFBitsB8=00000000000000000000000000000000 -unit.2.0.MFBitsB9=0000000000000000 -unit.2.0.MFCompareA0=0 -unit.2.0.MFCompareA1=0 -unit.2.0.MFCompareA10=0 -unit.2.0.MFCompareA11=0 -unit.2.0.MFCompareA12=0 -unit.2.0.MFCompareA13=0 -unit.2.0.MFCompareA14=0 -unit.2.0.MFCompareA15=2 -unit.2.0.MFCompareA2=0 -unit.2.0.MFCompareA3=0 -unit.2.0.MFCompareA4=0 -unit.2.0.MFCompareA5=0 -unit.2.0.MFCompareA6=0 -unit.2.0.MFCompareA7=0 -unit.2.0.MFCompareA8=0 -unit.2.0.MFCompareA9=0 -unit.2.0.MFCompareB0=999 -unit.2.0.MFCompareB1=999 -unit.2.0.MFCompareB10=999 -unit.2.0.MFCompareB11=999 -unit.2.0.MFCompareB12=999 -unit.2.0.MFCompareB13=999 -unit.2.0.MFCompareB14=999 -unit.2.0.MFCompareB15=999 -unit.2.0.MFCompareB2=999 -unit.2.0.MFCompareB3=999 -unit.2.0.MFCompareB4=999 -unit.2.0.MFCompareB5=999 -unit.2.0.MFCompareB6=999 -unit.2.0.MFCompareB7=999 -unit.2.0.MFCompareB8=999 -unit.2.0.MFCompareB9=999 -unit.2.0.MFCount=16 -unit.2.0.MFDisplay0=1 -unit.2.0.MFDisplay1=1 -unit.2.0.MFDisplay10=1 -unit.2.0.MFDisplay11=0 -unit.2.0.MFDisplay12=0 -unit.2.0.MFDisplay13=0 -unit.2.0.MFDisplay14=0 -unit.2.0.MFDisplay15=1 -unit.2.0.MFDisplay2=1 -unit.2.0.MFDisplay3=0 -unit.2.0.MFDisplay4=0 -unit.2.0.MFDisplay5=0 -unit.2.0.MFDisplay6=0 -unit.2.0.MFDisplay7=1 -unit.2.0.MFDisplay8=0 -unit.2.0.MFDisplay9=0 -unit.2.0.MFEventType0=3 -unit.2.0.MFEventType1=3 -unit.2.0.MFEventType10=3 -unit.2.0.MFEventType11=3 -unit.2.0.MFEventType12=3 -unit.2.0.MFEventType13=3 -unit.2.0.MFEventType14=3 -unit.2.0.MFEventType15=3 -unit.2.0.MFEventType2=3 -unit.2.0.MFEventType3=3 -unit.2.0.MFEventType4=3 -unit.2.0.MFEventType5=3 -unit.2.0.MFEventType6=3 -unit.2.0.MFEventType7=3 -unit.2.0.MFEventType8=3 -unit.2.0.MFEventType9=3 -unit.2.0.SQCondition=All Data -unit.2.0.SQContiguous0=0 -unit.2.0.SequencerOn=0 -unit.2.0.TCActive=0 -unit.2.0.TCAdvanced0=0 -unit.2.0.TCCondition0_0=M12 -unit.2.0.TCCondition0_1= -unit.2.0.TCConditionType0=0 -unit.2.0.TCCount=1 -unit.2.0.TCEventCount0=1 -unit.2.0.TCEventType0=3 -unit.2.0.TCName0=TriggerCondition0 -unit.2.0.TCOutputEnable0=0 -unit.2.0.TCOutputHigh0=1 -unit.2.0.TCOutputMode0=0 -unit.2.0.browser_tree_state=1 -unit.2.0.browser_tree_state=1 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=1 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=1 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.browser_tree_state=0 -unit.2.0.coretype=ILA -unit.2.0.eventCount0=1 -unit.2.0.eventCount1=1 -unit.2.0.eventCount10=1 -unit.2.0.eventCount11=1 -unit.2.0.eventCount12=1 -unit.2.0.eventCount13=1 -unit.2.0.eventCount14=1 -unit.2.0.eventCount15=1 -unit.2.0.eventCount2=1 -unit.2.0.eventCount3=1 -unit.2.0.eventCount4=1 -unit.2.0.eventCount5=1 -unit.2.0.eventCount6=1 -unit.2.0.eventCount7=1 -unit.2.0.eventCount8=1 -unit.2.0.eventCount9=1 -unit.2.0.export.format=2 -unit.2.0.export.signals=Waveform Signals/Buses -unit.2.0.export.unitName=DEV\:2 MyDevice2 (XC4VFX12) UNIT\:0 MyILA0 (ILA) -unit.2.0.port.-1.b.0.alias=aceusb_d_ -unit.2.0.port.-1.b.0.channellist=191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 -unit.2.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.0.name=DataPort -unit.2.0.port.-1.b.0.orderindex=-1 -unit.2.0.port.-1.b.0.radix=Hex -unit.2.0.port.-1.b.0.signedOffset=0.0 -unit.2.0.port.-1.b.0.signedPrecision=0 -unit.2.0.port.-1.b.0.signedScaleFactor=1.0 -unit.2.0.port.-1.b.0.tokencount=0 -unit.2.0.port.-1.b.0.unsignedOffset=0.0 -unit.2.0.port.-1.b.0.unsignedPrecision=0 -unit.2.0.port.-1.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.0.visible=1 -unit.2.0.port.-1.b.1.alias=ace_dat_o -unit.2.0.port.-1.b.1.channellist=170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 -unit.2.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.1.name=DataPort -unit.2.0.port.-1.b.1.orderindex=-1 -unit.2.0.port.-1.b.1.radix=Hex -unit.2.0.port.-1.b.1.signedOffset=0.0 -unit.2.0.port.-1.b.1.signedPrecision=0 -unit.2.0.port.-1.b.1.signedScaleFactor=1.0 -unit.2.0.port.-1.b.1.tokencount=0 -unit.2.0.port.-1.b.1.unsignedOffset=0.0 -unit.2.0.port.-1.b.1.unsignedPrecision=0 -unit.2.0.port.-1.b.1.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.1.visible=1 -unit.2.0.port.-1.b.10.alias=flags -unit.2.0.port.-1.b.10.channellist=95 96 97 98 99 100 101 102 103 -unit.2.0.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.10.name=DataPort -unit.2.0.port.-1.b.10.orderindex=-1 -unit.2.0.port.-1.b.10.radix=Hex -unit.2.0.port.-1.b.10.signedOffset=0.0 -unit.2.0.port.-1.b.10.signedPrecision=0 -unit.2.0.port.-1.b.10.signedScaleFactor=1.0 -unit.2.0.port.-1.b.10.tokencount=0 -unit.2.0.port.-1.b.10.unsignedOffset=0.0 -unit.2.0.port.-1.b.10.unsignedPrecision=0 -unit.2.0.port.-1.b.10.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.10.visible=1 -unit.2.0.port.-1.b.11.alias=func -unit.2.0.port.-1.b.11.channellist=81 82 83 -unit.2.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.11.name=DataPort -unit.2.0.port.-1.b.11.orderindex=-1 -unit.2.0.port.-1.b.11.radix=Hex -unit.2.0.port.-1.b.11.signedOffset=0.0 -unit.2.0.port.-1.b.11.signedPrecision=0 -unit.2.0.port.-1.b.11.signedScaleFactor=1.0 -unit.2.0.port.-1.b.11.tokencount=0 -unit.2.0.port.-1.b.11.unsignedOffset=0.0 -unit.2.0.port.-1.b.11.unsignedPrecision=0 -unit.2.0.port.-1.b.11.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.11.visible=1 -unit.2.0.port.-1.b.12.alias=next_state -unit.2.0.port.-1.b.12.channellist=84 85 86 -unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.12.name=DataPort -unit.2.0.port.-1.b.12.orderindex=-1 -unit.2.0.port.-1.b.12.radix=Hex -unit.2.0.port.-1.b.12.signedOffset=0.0 -unit.2.0.port.-1.b.12.signedPrecision=0 -unit.2.0.port.-1.b.12.signedScaleFactor=1.0 -unit.2.0.port.-1.b.12.tokencount=0 -unit.2.0.port.-1.b.12.unsignedOffset=0.0 -unit.2.0.port.-1.b.12.unsignedPrecision=0 -unit.2.0.port.-1.b.12.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.12.visible=1 -unit.2.0.port.-1.b.13.alias=pc -unit.2.0.port.-1.b.13.channellist=52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 -unit.2.0.port.-1.b.13.color=java.awt.Color[r\=204,g\=0,b\=51] -unit.2.0.port.-1.b.13.name=DataPort -unit.2.0.port.-1.b.13.orderindex=-1 -unit.2.0.port.-1.b.13.radix=Hex -unit.2.0.port.-1.b.13.signedOffset=0.0 -unit.2.0.port.-1.b.13.signedPrecision=0 -unit.2.0.port.-1.b.13.signedScaleFactor=1.0 -unit.2.0.port.-1.b.13.tokencount=0 -unit.2.0.port.-1.b.13.unsignedOffset=0.0 -unit.2.0.port.-1.b.13.unsignedPrecision=0 -unit.2.0.port.-1.b.13.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.13.visible=1 -unit.2.0.port.-1.b.14.alias=state -unit.2.0.port.-1.b.14.channellist=87 88 89 -unit.2.0.port.-1.b.14.color=java.awt.Color[r\=0,g\=51,b\=204] -unit.2.0.port.-1.b.14.name=DataPort -unit.2.0.port.-1.b.14.orderindex=-1 -unit.2.0.port.-1.b.14.radix=Hex -unit.2.0.port.-1.b.14.signedOffset=0.0 -unit.2.0.port.-1.b.14.signedPrecision=0 -unit.2.0.port.-1.b.14.signedScaleFactor=1.0 -unit.2.0.port.-1.b.14.tokencount=0 -unit.2.0.port.-1.b.14.unsignedOffset=0.0 -unit.2.0.port.-1.b.14.unsignedPrecision=0 -unit.2.0.port.-1.b.14.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.14.visible=1 -unit.2.0.port.-1.b.15.alias=t -unit.2.0.port.-1.b.15.channellist=78 79 80 -unit.2.0.port.-1.b.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.15.name=DataPort -unit.2.0.port.-1.b.15.orderindex=-1 -unit.2.0.port.-1.b.15.radix=Hex -unit.2.0.port.-1.b.15.signedOffset=0.0 -unit.2.0.port.-1.b.15.signedPrecision=0 -unit.2.0.port.-1.b.15.signedScaleFactor=1.0 -unit.2.0.port.-1.b.15.tokencount=0 -unit.2.0.port.-1.b.15.unsignedOffset=0.0 -unit.2.0.port.-1.b.15.unsignedPrecision=0 -unit.2.0.port.-1.b.15.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.15.visible=1 -unit.2.0.port.-1.b.16.alias=x -unit.2.0.port.-1.b.16.channellist=138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 -unit.2.0.port.-1.b.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.16.name=DataPort -unit.2.0.port.-1.b.16.orderindex=-1 -unit.2.0.port.-1.b.16.radix=Hex -unit.2.0.port.-1.b.16.signedOffset=0.0 -unit.2.0.port.-1.b.16.signedPrecision=0 -unit.2.0.port.-1.b.16.signedScaleFactor=1.0 -unit.2.0.port.-1.b.16.tokencount=0 -unit.2.0.port.-1.b.16.unsignedOffset=0.0 -unit.2.0.port.-1.b.16.unsignedPrecision=0 -unit.2.0.port.-1.b.16.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.16.visible=1 -unit.2.0.port.-1.b.17.alias=y -unit.2.0.port.-1.b.17.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 -unit.2.0.port.-1.b.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.17.name=DataPort -unit.2.0.port.-1.b.17.orderindex=-1 -unit.2.0.port.-1.b.17.radix=Hex -unit.2.0.port.-1.b.17.signedOffset=0.0 -unit.2.0.port.-1.b.17.signedPrecision=0 -unit.2.0.port.-1.b.17.signedScaleFactor=1.0 -unit.2.0.port.-1.b.17.tokencount=0 -unit.2.0.port.-1.b.17.unsignedOffset=0.0 -unit.2.0.port.-1.b.17.unsignedPrecision=0 -unit.2.0.port.-1.b.17.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.17.visible=1 -unit.2.0.port.-1.b.18.alias=y -unit.2.0.port.-1.b.18.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 -unit.2.0.port.-1.b.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.18.name=DataPort -unit.2.0.port.-1.b.18.orderindex=-1 -unit.2.0.port.-1.b.18.radix=Hex -unit.2.0.port.-1.b.18.signedOffset=0.0 -unit.2.0.port.-1.b.18.signedPrecision=0 -unit.2.0.port.-1.b.18.signedScaleFactor=1.0 -unit.2.0.port.-1.b.18.tokencount=0 -unit.2.0.port.-1.b.18.unsignedOffset=0.0 -unit.2.0.port.-1.b.18.unsignedPrecision=0 -unit.2.0.port.-1.b.18.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.18.visible=1 -unit.2.0.port.-1.b.19.alias=y -unit.2.0.port.-1.b.19.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 -unit.2.0.port.-1.b.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.19.name=DataPort -unit.2.0.port.-1.b.19.orderindex=-1 -unit.2.0.port.-1.b.19.radix=Hex -unit.2.0.port.-1.b.19.signedOffset=0.0 -unit.2.0.port.-1.b.19.signedPrecision=0 -unit.2.0.port.-1.b.19.signedScaleFactor=1.0 -unit.2.0.port.-1.b.19.tokencount=0 -unit.2.0.port.-1.b.19.unsignedOffset=0.0 -unit.2.0.port.-1.b.19.unsignedPrecision=0 -unit.2.0.port.-1.b.19.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.19.visible=1 -unit.2.0.port.-1.b.2.alias=addr_d -unit.2.0.port.-1.b.2.channellist=90 91 92 93 -unit.2.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.2.name=DataPort -unit.2.0.port.-1.b.2.orderindex=-1 -unit.2.0.port.-1.b.2.radix=Hex -unit.2.0.port.-1.b.2.signedOffset=0.0 -unit.2.0.port.-1.b.2.signedPrecision=0 -unit.2.0.port.-1.b.2.signedScaleFactor=1.0 -unit.2.0.port.-1.b.2.tokencount=0 -unit.2.0.port.-1.b.2.unsignedOffset=0.0 -unit.2.0.port.-1.b.2.unsignedPrecision=0 -unit.2.0.port.-1.b.2.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.2.visible=1 -unit.2.0.port.-1.b.3.alias=adr -unit.2.0.port.-1.b.3.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 -unit.2.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.3.name=DataPort -unit.2.0.port.-1.b.3.orderindex=-1 -unit.2.0.port.-1.b.3.radix=Hex -unit.2.0.port.-1.b.3.signedOffset=0.0 -unit.2.0.port.-1.b.3.signedPrecision=0 -unit.2.0.port.-1.b.3.signedScaleFactor=1.0 -unit.2.0.port.-1.b.3.tokencount=0 -unit.2.0.port.-1.b.3.unsignedOffset=0.0 -unit.2.0.port.-1.b.3.unsignedPrecision=0 -unit.2.0.port.-1.b.3.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.3.visible=1 -unit.2.0.port.-1.b.4.alias=aluo -unit.2.0.port.-1.b.4.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 -unit.2.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.4.name=DataPort -unit.2.0.port.-1.b.4.orderindex=-1 -unit.2.0.port.-1.b.4.radix=Hex -unit.2.0.port.-1.b.4.signedOffset=0.0 -unit.2.0.port.-1.b.4.signedPrecision=0 -unit.2.0.port.-1.b.4.signedScaleFactor=1.0 -unit.2.0.port.-1.b.4.tokencount=0 -unit.2.0.port.-1.b.4.unsignedOffset=0.0 -unit.2.0.port.-1.b.4.unsignedPrecision=0 -unit.2.0.port.-1.b.4.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.4.visible=1 -unit.2.0.port.-1.b.5.alias=cnt -unit.2.0.port.-1.b.5.channellist=216 217 218 -unit.2.0.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.5.name=DataPort -unit.2.0.port.-1.b.5.orderindex=-1 -unit.2.0.port.-1.b.5.radix=Hex -unit.2.0.port.-1.b.5.signedOffset=0.0 -unit.2.0.port.-1.b.5.signedPrecision=0 -unit.2.0.port.-1.b.5.signedScaleFactor=1.0 -unit.2.0.port.-1.b.5.tokencount=0 -unit.2.0.port.-1.b.5.unsignedOffset=0.0 -unit.2.0.port.-1.b.5.unsignedPrecision=0 -unit.2.0.port.-1.b.5.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.5.visible=1 -unit.2.0.port.-1.b.6.alias=cnt_time -unit.2.0.port.-1.b.6.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 -unit.2.0.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.6.name=DataPort -unit.2.0.port.-1.b.6.orderindex=-1 -unit.2.0.port.-1.b.6.radix=Hex -unit.2.0.port.-1.b.6.signedOffset=0.0 -unit.2.0.port.-1.b.6.signedPrecision=0 -unit.2.0.port.-1.b.6.signedScaleFactor=1.0 -unit.2.0.port.-1.b.6.tokencount=0 -unit.2.0.port.-1.b.6.unsignedOffset=0.0 -unit.2.0.port.-1.b.6.unsignedPrecision=0 -unit.2.0.port.-1.b.6.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.6.visible=1 -unit.2.0.port.-1.b.7.alias=d -unit.2.0.port.-1.b.7.channellist=106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 -unit.2.0.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.7.name=DataPort -unit.2.0.port.-1.b.7.orderindex=-1 -unit.2.0.port.-1.b.7.radix=Hex -unit.2.0.port.-1.b.7.signedOffset=0.0 -unit.2.0.port.-1.b.7.signedPrecision=0 -unit.2.0.port.-1.b.7.signedScaleFactor=1.0 -unit.2.0.port.-1.b.7.tokencount=0 -unit.2.0.port.-1.b.7.unsignedOffset=0.0 -unit.2.0.port.-1.b.7.unsignedPrecision=0 -unit.2.0.port.-1.b.7.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.7.visible=1 -unit.2.0.port.-1.b.8.alias=dat_i -unit.2.0.port.-1.b.8.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 -unit.2.0.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.8.name=DataPort -unit.2.0.port.-1.b.8.orderindex=-1 -unit.2.0.port.-1.b.8.radix=Hex -unit.2.0.port.-1.b.8.signedOffset=0.0 -unit.2.0.port.-1.b.8.signedPrecision=0 -unit.2.0.port.-1.b.8.signedScaleFactor=1.0 -unit.2.0.port.-1.b.8.tokencount=0 -unit.2.0.port.-1.b.8.unsignedOffset=0.0 -unit.2.0.port.-1.b.8.unsignedPrecision=0 -unit.2.0.port.-1.b.8.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.8.visible=1 -unit.2.0.port.-1.b.9.alias=dat_o -unit.2.0.port.-1.b.9.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 -unit.2.0.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.b.9.name=DataPort -unit.2.0.port.-1.b.9.orderindex=-1 -unit.2.0.port.-1.b.9.radix=Hex -unit.2.0.port.-1.b.9.signedOffset=0.0 -unit.2.0.port.-1.b.9.signedPrecision=0 -unit.2.0.port.-1.b.9.signedScaleFactor=1.0 -unit.2.0.port.-1.b.9.tokencount=0 -unit.2.0.port.-1.b.9.unsignedOffset=0.0 -unit.2.0.port.-1.b.9.unsignedPrecision=0 -unit.2.0.port.-1.b.9.unsignedScaleFactor=1.0 -unit.2.0.port.-1.b.9.visible=1 -unit.2.0.port.-1.buscount=18 -unit.2.0.port.-1.channelcount=256 -unit.2.0.port.-1.s.0.alias= -unit.2.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.0.name=DataPort[0] -unit.2.0.port.-1.s.0.orderindex=-1 -unit.2.0.port.-1.s.0.visible=1 -unit.2.0.port.-1.s.1.alias= -unit.2.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.1.name=DataPort[1] -unit.2.0.port.-1.s.1.orderindex=-1 -unit.2.0.port.-1.s.1.visible=1 -unit.2.0.port.-1.s.10.alias= -unit.2.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.10.name=DataPort[10] -unit.2.0.port.-1.s.10.orderindex=-1 -unit.2.0.port.-1.s.10.visible=1 -unit.2.0.port.-1.s.100.alias= -unit.2.0.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.100.name=DataPort[100] -unit.2.0.port.-1.s.100.orderindex=-1 -unit.2.0.port.-1.s.100.visible=1 -unit.2.0.port.-1.s.101.alias= -unit.2.0.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.101.name=DataPort[101] -unit.2.0.port.-1.s.101.orderindex=-1 -unit.2.0.port.-1.s.101.visible=1 -unit.2.0.port.-1.s.102.alias= -unit.2.0.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.102.name=DataPort[102] -unit.2.0.port.-1.s.102.orderindex=-1 -unit.2.0.port.-1.s.102.visible=1 -unit.2.0.port.-1.s.103.alias= -unit.2.0.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.103.name=DataPort[103] -unit.2.0.port.-1.s.103.orderindex=-1 -unit.2.0.port.-1.s.103.visible=1 -unit.2.0.port.-1.s.104.alias=inta -unit.2.0.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.104.name=DataPort[104] -unit.2.0.port.-1.s.104.orderindex=-1 -unit.2.0.port.-1.s.104.visible=1 -unit.2.0.port.-1.s.105.alias=intr -unit.2.0.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.105.name=DataPort[105] -unit.2.0.port.-1.s.105.orderindex=-1 -unit.2.0.port.-1.s.105.visible=1 -unit.2.0.port.-1.s.106.alias= -unit.2.0.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.106.name=DataPort[106] -unit.2.0.port.-1.s.106.orderindex=-1 -unit.2.0.port.-1.s.106.visible=1 -unit.2.0.port.-1.s.107.alias= -unit.2.0.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.107.name=DataPort[107] -unit.2.0.port.-1.s.107.orderindex=-1 -unit.2.0.port.-1.s.107.visible=1 -unit.2.0.port.-1.s.108.alias= -unit.2.0.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.108.name=DataPort[108] -unit.2.0.port.-1.s.108.orderindex=-1 -unit.2.0.port.-1.s.108.visible=1 -unit.2.0.port.-1.s.109.alias= -unit.2.0.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.109.name=DataPort[109] -unit.2.0.port.-1.s.109.orderindex=-1 -unit.2.0.port.-1.s.109.visible=1 -unit.2.0.port.-1.s.11.alias= -unit.2.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.11.name=DataPort[11] -unit.2.0.port.-1.s.11.orderindex=-1 -unit.2.0.port.-1.s.11.visible=1 -unit.2.0.port.-1.s.110.alias= -unit.2.0.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.110.name=DataPort[110] -unit.2.0.port.-1.s.110.orderindex=-1 -unit.2.0.port.-1.s.110.visible=1 -unit.2.0.port.-1.s.111.alias= -unit.2.0.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.111.name=DataPort[111] -unit.2.0.port.-1.s.111.orderindex=-1 -unit.2.0.port.-1.s.111.visible=1 -unit.2.0.port.-1.s.112.alias= -unit.2.0.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.112.name=DataPort[112] -unit.2.0.port.-1.s.112.orderindex=-1 -unit.2.0.port.-1.s.112.visible=1 -unit.2.0.port.-1.s.113.alias= -unit.2.0.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.113.name=DataPort[113] -unit.2.0.port.-1.s.113.orderindex=-1 -unit.2.0.port.-1.s.113.visible=1 -unit.2.0.port.-1.s.114.alias= -unit.2.0.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.114.name=DataPort[114] -unit.2.0.port.-1.s.114.orderindex=-1 -unit.2.0.port.-1.s.114.visible=1 -unit.2.0.port.-1.s.115.alias= -unit.2.0.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.115.name=DataPort[115] -unit.2.0.port.-1.s.115.orderindex=-1 -unit.2.0.port.-1.s.115.visible=1 -unit.2.0.port.-1.s.116.alias= -unit.2.0.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.116.name=DataPort[116] -unit.2.0.port.-1.s.116.orderindex=-1 -unit.2.0.port.-1.s.116.visible=1 -unit.2.0.port.-1.s.117.alias= -unit.2.0.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.117.name=DataPort[117] -unit.2.0.port.-1.s.117.orderindex=-1 -unit.2.0.port.-1.s.117.visible=1 -unit.2.0.port.-1.s.118.alias= -unit.2.0.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.118.name=DataPort[118] -unit.2.0.port.-1.s.118.orderindex=-1 -unit.2.0.port.-1.s.118.visible=1 -unit.2.0.port.-1.s.119.alias= -unit.2.0.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.119.name=DataPort[119] -unit.2.0.port.-1.s.119.orderindex=-1 -unit.2.0.port.-1.s.119.visible=1 -unit.2.0.port.-1.s.12.alias= -unit.2.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.12.name=DataPort[12] -unit.2.0.port.-1.s.12.orderindex=-1 -unit.2.0.port.-1.s.12.visible=1 -unit.2.0.port.-1.s.120.alias= -unit.2.0.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.120.name=DataPort[120] -unit.2.0.port.-1.s.120.orderindex=-1 -unit.2.0.port.-1.s.120.visible=1 -unit.2.0.port.-1.s.121.alias= -unit.2.0.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.121.name=DataPort[121] -unit.2.0.port.-1.s.121.orderindex=-1 -unit.2.0.port.-1.s.121.visible=1 -unit.2.0.port.-1.s.122.alias= -unit.2.0.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.122.name=DataPort[122] -unit.2.0.port.-1.s.122.orderindex=-1 -unit.2.0.port.-1.s.122.visible=1 -unit.2.0.port.-1.s.123.alias= -unit.2.0.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.123.name=DataPort[123] -unit.2.0.port.-1.s.123.orderindex=-1 -unit.2.0.port.-1.s.123.visible=1 -unit.2.0.port.-1.s.124.alias= -unit.2.0.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.124.name=DataPort[124] -unit.2.0.port.-1.s.124.orderindex=-1 -unit.2.0.port.-1.s.124.visible=1 -unit.2.0.port.-1.s.125.alias= -unit.2.0.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.125.name=DataPort[125] -unit.2.0.port.-1.s.125.orderindex=-1 -unit.2.0.port.-1.s.125.visible=1 -unit.2.0.port.-1.s.126.alias= -unit.2.0.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.126.name=DataPort[126] -unit.2.0.port.-1.s.126.orderindex=-1 -unit.2.0.port.-1.s.126.visible=1 -unit.2.0.port.-1.s.127.alias= -unit.2.0.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.127.name=DataPort[127] -unit.2.0.port.-1.s.127.orderindex=-1 -unit.2.0.port.-1.s.127.visible=1 -unit.2.0.port.-1.s.128.alias= -unit.2.0.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.128.name=DataPort[128] -unit.2.0.port.-1.s.128.orderindex=-1 -unit.2.0.port.-1.s.128.visible=1 -unit.2.0.port.-1.s.129.alias= -unit.2.0.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.129.name=DataPort[129] -unit.2.0.port.-1.s.129.orderindex=-1 -unit.2.0.port.-1.s.129.visible=1 -unit.2.0.port.-1.s.13.alias= -unit.2.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.13.name=DataPort[13] -unit.2.0.port.-1.s.13.orderindex=-1 -unit.2.0.port.-1.s.13.visible=1 -unit.2.0.port.-1.s.130.alias= -unit.2.0.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.130.name=DataPort[130] -unit.2.0.port.-1.s.130.orderindex=-1 -unit.2.0.port.-1.s.130.visible=1 -unit.2.0.port.-1.s.131.alias= -unit.2.0.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.131.name=DataPort[131] -unit.2.0.port.-1.s.131.orderindex=-1 -unit.2.0.port.-1.s.131.visible=1 -unit.2.0.port.-1.s.132.alias= -unit.2.0.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.132.name=DataPort[132] -unit.2.0.port.-1.s.132.orderindex=-1 -unit.2.0.port.-1.s.132.visible=1 -unit.2.0.port.-1.s.133.alias= -unit.2.0.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.133.name=DataPort[133] -unit.2.0.port.-1.s.133.orderindex=-1 -unit.2.0.port.-1.s.133.visible=1 -unit.2.0.port.-1.s.134.alias= -unit.2.0.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.134.name=DataPort[134] -unit.2.0.port.-1.s.134.orderindex=-1 -unit.2.0.port.-1.s.134.visible=1 -unit.2.0.port.-1.s.135.alias= -unit.2.0.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.135.name=DataPort[135] -unit.2.0.port.-1.s.135.orderindex=-1 -unit.2.0.port.-1.s.135.visible=1 -unit.2.0.port.-1.s.136.alias= -unit.2.0.port.-1.s.136.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.136.name=DataPort[136] -unit.2.0.port.-1.s.136.orderindex=-1 -unit.2.0.port.-1.s.136.visible=1 -unit.2.0.port.-1.s.137.alias= -unit.2.0.port.-1.s.137.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.137.name=DataPort[137] -unit.2.0.port.-1.s.137.orderindex=-1 -unit.2.0.port.-1.s.137.visible=1 -unit.2.0.port.-1.s.138.alias= -unit.2.0.port.-1.s.138.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.138.name=DataPort[138] -unit.2.0.port.-1.s.138.orderindex=-1 -unit.2.0.port.-1.s.138.visible=1 -unit.2.0.port.-1.s.139.alias= -unit.2.0.port.-1.s.139.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.139.name=DataPort[139] -unit.2.0.port.-1.s.139.orderindex=-1 -unit.2.0.port.-1.s.139.visible=1 -unit.2.0.port.-1.s.14.alias= -unit.2.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.14.name=DataPort[14] -unit.2.0.port.-1.s.14.orderindex=-1 -unit.2.0.port.-1.s.14.visible=1 -unit.2.0.port.-1.s.140.alias= -unit.2.0.port.-1.s.140.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.140.name=DataPort[140] -unit.2.0.port.-1.s.140.orderindex=-1 -unit.2.0.port.-1.s.140.visible=1 -unit.2.0.port.-1.s.141.alias= -unit.2.0.port.-1.s.141.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.141.name=DataPort[141] -unit.2.0.port.-1.s.141.orderindex=-1 -unit.2.0.port.-1.s.141.visible=1 -unit.2.0.port.-1.s.142.alias= -unit.2.0.port.-1.s.142.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.142.name=DataPort[142] -unit.2.0.port.-1.s.142.orderindex=-1 -unit.2.0.port.-1.s.142.visible=1 -unit.2.0.port.-1.s.143.alias= -unit.2.0.port.-1.s.143.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.143.name=DataPort[143] -unit.2.0.port.-1.s.143.orderindex=-1 -unit.2.0.port.-1.s.143.visible=1 -unit.2.0.port.-1.s.144.alias= -unit.2.0.port.-1.s.144.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.144.name=DataPort[144] -unit.2.0.port.-1.s.144.orderindex=-1 -unit.2.0.port.-1.s.144.visible=1 -unit.2.0.port.-1.s.145.alias= -unit.2.0.port.-1.s.145.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.145.name=DataPort[145] -unit.2.0.port.-1.s.145.orderindex=-1 -unit.2.0.port.-1.s.145.visible=1 -unit.2.0.port.-1.s.146.alias= -unit.2.0.port.-1.s.146.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.146.name=DataPort[146] -unit.2.0.port.-1.s.146.orderindex=-1 -unit.2.0.port.-1.s.146.visible=1 -unit.2.0.port.-1.s.147.alias= -unit.2.0.port.-1.s.147.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.147.name=DataPort[147] -unit.2.0.port.-1.s.147.orderindex=-1 -unit.2.0.port.-1.s.147.visible=1 -unit.2.0.port.-1.s.148.alias= -unit.2.0.port.-1.s.148.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.148.name=DataPort[148] -unit.2.0.port.-1.s.148.orderindex=-1 -unit.2.0.port.-1.s.148.visible=1 -unit.2.0.port.-1.s.149.alias= -unit.2.0.port.-1.s.149.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.149.name=DataPort[149] -unit.2.0.port.-1.s.149.orderindex=-1 -unit.2.0.port.-1.s.149.visible=1 -unit.2.0.port.-1.s.15.alias= -unit.2.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.15.name=DataPort[15] -unit.2.0.port.-1.s.15.orderindex=-1 -unit.2.0.port.-1.s.15.visible=1 -unit.2.0.port.-1.s.150.alias= -unit.2.0.port.-1.s.150.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.150.name=DataPort[150] -unit.2.0.port.-1.s.150.orderindex=-1 -unit.2.0.port.-1.s.150.visible=1 -unit.2.0.port.-1.s.151.alias= -unit.2.0.port.-1.s.151.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.151.name=DataPort[151] -unit.2.0.port.-1.s.151.orderindex=-1 -unit.2.0.port.-1.s.151.visible=1 -unit.2.0.port.-1.s.152.alias= -unit.2.0.port.-1.s.152.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.152.name=DataPort[152] -unit.2.0.port.-1.s.152.orderindex=-1 -unit.2.0.port.-1.s.152.visible=1 -unit.2.0.port.-1.s.153.alias= -unit.2.0.port.-1.s.153.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.153.name=DataPort[153] -unit.2.0.port.-1.s.153.orderindex=-1 -unit.2.0.port.-1.s.153.visible=1 -unit.2.0.port.-1.s.154.alias= -unit.2.0.port.-1.s.154.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.154.name=DataPort[154] -unit.2.0.port.-1.s.154.orderindex=-1 -unit.2.0.port.-1.s.154.visible=1 -unit.2.0.port.-1.s.155.alias= -unit.2.0.port.-1.s.155.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.155.name=DataPort[155] -unit.2.0.port.-1.s.155.orderindex=-1 -unit.2.0.port.-1.s.155.visible=1 -unit.2.0.port.-1.s.156.alias= -unit.2.0.port.-1.s.156.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.156.name=DataPort[156] -unit.2.0.port.-1.s.156.orderindex=-1 -unit.2.0.port.-1.s.156.visible=1 -unit.2.0.port.-1.s.157.alias= -unit.2.0.port.-1.s.157.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.157.name=DataPort[157] -unit.2.0.port.-1.s.157.orderindex=-1 -unit.2.0.port.-1.s.157.visible=1 -unit.2.0.port.-1.s.158.alias= -unit.2.0.port.-1.s.158.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.158.name=DataPort[158] -unit.2.0.port.-1.s.158.orderindex=-1 -unit.2.0.port.-1.s.158.visible=1 -unit.2.0.port.-1.s.159.alias= -unit.2.0.port.-1.s.159.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.159.name=DataPort[159] -unit.2.0.port.-1.s.159.orderindex=-1 -unit.2.0.port.-1.s.159.visible=1 -unit.2.0.port.-1.s.16.alias= -unit.2.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.16.name=DataPort[16] -unit.2.0.port.-1.s.16.orderindex=-1 -unit.2.0.port.-1.s.16.visible=1 -unit.2.0.port.-1.s.160.alias= -unit.2.0.port.-1.s.160.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.160.name=DataPort[160] -unit.2.0.port.-1.s.160.orderindex=-1 -unit.2.0.port.-1.s.160.visible=1 -unit.2.0.port.-1.s.161.alias= -unit.2.0.port.-1.s.161.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.161.name=DataPort[161] -unit.2.0.port.-1.s.161.orderindex=-1 -unit.2.0.port.-1.s.161.visible=1 -unit.2.0.port.-1.s.162.alias= -unit.2.0.port.-1.s.162.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.162.name=DataPort[162] -unit.2.0.port.-1.s.162.orderindex=-1 -unit.2.0.port.-1.s.162.visible=1 -unit.2.0.port.-1.s.163.alias= -unit.2.0.port.-1.s.163.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.163.name=DataPort[163] -unit.2.0.port.-1.s.163.orderindex=-1 -unit.2.0.port.-1.s.163.visible=1 -unit.2.0.port.-1.s.164.alias= -unit.2.0.port.-1.s.164.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.164.name=DataPort[164] -unit.2.0.port.-1.s.164.orderindex=-1 -unit.2.0.port.-1.s.164.visible=1 -unit.2.0.port.-1.s.165.alias= -unit.2.0.port.-1.s.165.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.165.name=DataPort[165] -unit.2.0.port.-1.s.165.orderindex=-1 -unit.2.0.port.-1.s.165.visible=1 -unit.2.0.port.-1.s.166.alias= -unit.2.0.port.-1.s.166.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.166.name=DataPort[166] -unit.2.0.port.-1.s.166.orderindex=-1 -unit.2.0.port.-1.s.166.visible=1 -unit.2.0.port.-1.s.167.alias= -unit.2.0.port.-1.s.167.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.167.name=DataPort[167] -unit.2.0.port.-1.s.167.orderindex=-1 -unit.2.0.port.-1.s.167.visible=1 -unit.2.0.port.-1.s.168.alias= -unit.2.0.port.-1.s.168.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.168.name=DataPort[168] -unit.2.0.port.-1.s.168.orderindex=-1 -unit.2.0.port.-1.s.168.visible=1 -unit.2.0.port.-1.s.169.alias= -unit.2.0.port.-1.s.169.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.169.name=DataPort[169] -unit.2.0.port.-1.s.169.orderindex=-1 -unit.2.0.port.-1.s.169.visible=1 -unit.2.0.port.-1.s.17.alias= -unit.2.0.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.17.name=DataPort[17] -unit.2.0.port.-1.s.17.orderindex=-1 -unit.2.0.port.-1.s.17.visible=1 -unit.2.0.port.-1.s.170.alias= -unit.2.0.port.-1.s.170.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.170.name=DataPort[170] -unit.2.0.port.-1.s.170.orderindex=-1 -unit.2.0.port.-1.s.170.visible=1 -unit.2.0.port.-1.s.171.alias= -unit.2.0.port.-1.s.171.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.171.name=DataPort[171] -unit.2.0.port.-1.s.171.orderindex=-1 -unit.2.0.port.-1.s.171.visible=1 -unit.2.0.port.-1.s.172.alias= -unit.2.0.port.-1.s.172.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.172.name=DataPort[172] -unit.2.0.port.-1.s.172.orderindex=-1 -unit.2.0.port.-1.s.172.visible=1 -unit.2.0.port.-1.s.173.alias= -unit.2.0.port.-1.s.173.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.173.name=DataPort[173] -unit.2.0.port.-1.s.173.orderindex=-1 -unit.2.0.port.-1.s.173.visible=1 -unit.2.0.port.-1.s.174.alias= -unit.2.0.port.-1.s.174.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.174.name=DataPort[174] -unit.2.0.port.-1.s.174.orderindex=-1 -unit.2.0.port.-1.s.174.visible=1 -unit.2.0.port.-1.s.175.alias= -unit.2.0.port.-1.s.175.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.175.name=DataPort[175] -unit.2.0.port.-1.s.175.orderindex=-1 -unit.2.0.port.-1.s.175.visible=1 -unit.2.0.port.-1.s.176.alias= -unit.2.0.port.-1.s.176.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.176.name=DataPort[176] -unit.2.0.port.-1.s.176.orderindex=-1 -unit.2.0.port.-1.s.176.visible=1 -unit.2.0.port.-1.s.177.alias= -unit.2.0.port.-1.s.177.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.177.name=DataPort[177] -unit.2.0.port.-1.s.177.orderindex=-1 -unit.2.0.port.-1.s.177.visible=1 -unit.2.0.port.-1.s.178.alias= -unit.2.0.port.-1.s.178.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.178.name=DataPort[178] -unit.2.0.port.-1.s.178.orderindex=-1 -unit.2.0.port.-1.s.178.visible=1 -unit.2.0.port.-1.s.179.alias= -unit.2.0.port.-1.s.179.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.179.name=DataPort[179] -unit.2.0.port.-1.s.179.orderindex=-1 -unit.2.0.port.-1.s.179.visible=1 -unit.2.0.port.-1.s.18.alias= -unit.2.0.port.-1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.18.name=DataPort[18] -unit.2.0.port.-1.s.18.orderindex=-1 -unit.2.0.port.-1.s.18.visible=1 -unit.2.0.port.-1.s.180.alias= -unit.2.0.port.-1.s.180.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.180.name=DataPort[180] -unit.2.0.port.-1.s.180.orderindex=-1 -unit.2.0.port.-1.s.180.visible=1 -unit.2.0.port.-1.s.181.alias= -unit.2.0.port.-1.s.181.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.181.name=DataPort[181] -unit.2.0.port.-1.s.181.orderindex=-1 -unit.2.0.port.-1.s.181.visible=1 -unit.2.0.port.-1.s.182.alias= -unit.2.0.port.-1.s.182.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.182.name=DataPort[182] -unit.2.0.port.-1.s.182.orderindex=-1 -unit.2.0.port.-1.s.182.visible=1 -unit.2.0.port.-1.s.183.alias= -unit.2.0.port.-1.s.183.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.183.name=DataPort[183] -unit.2.0.port.-1.s.183.orderindex=-1 -unit.2.0.port.-1.s.183.visible=1 -unit.2.0.port.-1.s.184.alias= -unit.2.0.port.-1.s.184.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.184.name=DataPort[184] -unit.2.0.port.-1.s.184.orderindex=-1 -unit.2.0.port.-1.s.184.visible=1 -unit.2.0.port.-1.s.185.alias= -unit.2.0.port.-1.s.185.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.185.name=DataPort[185] -unit.2.0.port.-1.s.185.orderindex=-1 -unit.2.0.port.-1.s.185.visible=1 -unit.2.0.port.-1.s.186.alias=ace_stb -unit.2.0.port.-1.s.186.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.186.name=DataPort[186] -unit.2.0.port.-1.s.186.orderindex=-1 -unit.2.0.port.-1.s.186.visible=1 -unit.2.0.port.-1.s.187.alias=ace_ack -unit.2.0.port.-1.s.187.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.187.name=DataPort[187] -unit.2.0.port.-1.s.187.orderindex=-1 -unit.2.0.port.-1.s.187.visible=1 -unit.2.0.port.-1.s.188.alias=aceusb_oe_n_ -unit.2.0.port.-1.s.188.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.188.name=DataPort[188] -unit.2.0.port.-1.s.188.orderindex=-1 -unit.2.0.port.-1.s.188.visible=1 -unit.2.0.port.-1.s.189.alias=aceusb_we_n -unit.2.0.port.-1.s.189.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.189.name=DataPort[189] -unit.2.0.port.-1.s.189.orderindex=-1 -unit.2.0.port.-1.s.189.visible=1 -unit.2.0.port.-1.s.19.alias= -unit.2.0.port.-1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.19.name=DataPort[19] -unit.2.0.port.-1.s.19.orderindex=-1 -unit.2.0.port.-1.s.19.visible=1 -unit.2.0.port.-1.s.190.alias=ace_mpce_n_ -unit.2.0.port.-1.s.190.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.190.name=DataPort[190] -unit.2.0.port.-1.s.190.orderindex=-1 -unit.2.0.port.-1.s.190.visible=1 -unit.2.0.port.-1.s.191.alias= -unit.2.0.port.-1.s.191.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.191.name=DataPort[191] -unit.2.0.port.-1.s.191.orderindex=-1 -unit.2.0.port.-1.s.191.visible=1 -unit.2.0.port.-1.s.192.alias= -unit.2.0.port.-1.s.192.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.192.name=DataPort[192] -unit.2.0.port.-1.s.192.orderindex=-1 -unit.2.0.port.-1.s.192.visible=1 -unit.2.0.port.-1.s.193.alias= -unit.2.0.port.-1.s.193.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.193.name=DataPort[193] -unit.2.0.port.-1.s.193.orderindex=-1 -unit.2.0.port.-1.s.193.visible=1 -unit.2.0.port.-1.s.194.alias= -unit.2.0.port.-1.s.194.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.194.name=DataPort[194] -unit.2.0.port.-1.s.194.orderindex=-1 -unit.2.0.port.-1.s.194.visible=1 -unit.2.0.port.-1.s.195.alias= -unit.2.0.port.-1.s.195.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.195.name=DataPort[195] -unit.2.0.port.-1.s.195.orderindex=-1 -unit.2.0.port.-1.s.195.visible=1 -unit.2.0.port.-1.s.196.alias= -unit.2.0.port.-1.s.196.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.196.name=DataPort[196] -unit.2.0.port.-1.s.196.orderindex=-1 -unit.2.0.port.-1.s.196.visible=1 -unit.2.0.port.-1.s.197.alias= -unit.2.0.port.-1.s.197.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.197.name=DataPort[197] -unit.2.0.port.-1.s.197.orderindex=-1 -unit.2.0.port.-1.s.197.visible=1 -unit.2.0.port.-1.s.198.alias= -unit.2.0.port.-1.s.198.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.198.name=DataPort[198] -unit.2.0.port.-1.s.198.orderindex=-1 -unit.2.0.port.-1.s.198.visible=1 -unit.2.0.port.-1.s.199.alias= -unit.2.0.port.-1.s.199.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.199.name=DataPort[199] -unit.2.0.port.-1.s.199.orderindex=-1 -unit.2.0.port.-1.s.199.visible=1 -unit.2.0.port.-1.s.2.alias= -unit.2.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.2.name=DataPort[2] -unit.2.0.port.-1.s.2.orderindex=-1 -unit.2.0.port.-1.s.2.visible=1 -unit.2.0.port.-1.s.20.alias= -unit.2.0.port.-1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.20.name=DataPort[20] -unit.2.0.port.-1.s.20.orderindex=-1 -unit.2.0.port.-1.s.20.visible=1 -unit.2.0.port.-1.s.200.alias= -unit.2.0.port.-1.s.200.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.200.name=DataPort[200] -unit.2.0.port.-1.s.200.orderindex=-1 -unit.2.0.port.-1.s.200.visible=1 -unit.2.0.port.-1.s.201.alias= -unit.2.0.port.-1.s.201.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.201.name=DataPort[201] -unit.2.0.port.-1.s.201.orderindex=-1 -unit.2.0.port.-1.s.201.visible=1 -unit.2.0.port.-1.s.202.alias= -unit.2.0.port.-1.s.202.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.202.name=DataPort[202] -unit.2.0.port.-1.s.202.orderindex=-1 -unit.2.0.port.-1.s.202.visible=1 -unit.2.0.port.-1.s.203.alias= -unit.2.0.port.-1.s.203.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.203.name=DataPort[203] -unit.2.0.port.-1.s.203.orderindex=-1 -unit.2.0.port.-1.s.203.visible=1 -unit.2.0.port.-1.s.204.alias= -unit.2.0.port.-1.s.204.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.204.name=DataPort[204] -unit.2.0.port.-1.s.204.orderindex=-1 -unit.2.0.port.-1.s.204.visible=1 -unit.2.0.port.-1.s.205.alias= -unit.2.0.port.-1.s.205.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.205.name=DataPort[205] -unit.2.0.port.-1.s.205.orderindex=-1 -unit.2.0.port.-1.s.205.visible=1 -unit.2.0.port.-1.s.206.alias= -unit.2.0.port.-1.s.206.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.206.name=DataPort[206] -unit.2.0.port.-1.s.206.orderindex=-1 -unit.2.0.port.-1.s.206.visible=1 -unit.2.0.port.-1.s.207.alias=iid -unit.2.0.port.-1.s.207.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.207.name=DataPort[207] -unit.2.0.port.-1.s.207.orderindex=-1 -unit.2.0.port.-1.s.207.visible=1 -unit.2.0.port.-1.s.208.alias=irr0 -unit.2.0.port.-1.s.208.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.208.name=DataPort[208] -unit.2.0.port.-1.s.208.orderindex=-1 -unit.2.0.port.-1.s.208.visible=1 -unit.2.0.port.-1.s.209.alias=irr1 -unit.2.0.port.-1.s.209.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.209.name=DataPort[209] -unit.2.0.port.-1.s.209.orderindex=-1 -unit.2.0.port.-1.s.209.visible=1 -unit.2.0.port.-1.s.21.alias= -unit.2.0.port.-1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.21.name=DataPort[21] -unit.2.0.port.-1.s.21.orderindex=-1 -unit.2.0.port.-1.s.21.visible=1 -unit.2.0.port.-1.s.210.alias=int0 -unit.2.0.port.-1.s.210.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.210.name=DataPort[210] -unit.2.0.port.-1.s.210.orderindex=-1 -unit.2.0.port.-1.s.210.visible=1 -unit.2.0.port.-1.s.211.alias=int1 -unit.2.0.port.-1.s.211.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.211.name=DataPort[211] -unit.2.0.port.-1.s.211.orderindex=-1 -unit.2.0.port.-1.s.211.visible=1 -unit.2.0.port.-1.s.212.alias=released -unit.2.0.port.-1.s.212.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.212.name=DataPort[212] -unit.2.0.port.-1.s.212.orderindex=-1 -unit.2.0.port.-1.s.212.visible=1 -unit.2.0.port.-1.s.213.alias=rx_shift -unit.2.0.port.-1.s.213.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.213.name=DataPort[213] -unit.2.0.port.-1.s.213.orderindex=-1 -unit.2.0.port.-1.s.213.visible=1 -unit.2.0.port.-1.s.214.alias=rx_output -unit.2.0.port.-1.s.214.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.214.name=DataPort[214] -unit.2.0.port.-1.s.214.orderindex=-1 -unit.2.0.port.-1.s.214.visible=1 -unit.2.0.port.-1.s.215.alias=nada -unit.2.0.port.-1.s.215.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.215.name=DataPort[215] -unit.2.0.port.-1.s.215.orderindex=-1 -unit.2.0.port.-1.s.215.visible=1 -unit.2.0.port.-1.s.216.alias= -unit.2.0.port.-1.s.216.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.216.name=DataPort[216] -unit.2.0.port.-1.s.216.orderindex=-1 -unit.2.0.port.-1.s.216.visible=1 -unit.2.0.port.-1.s.217.alias= -unit.2.0.port.-1.s.217.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.217.name=DataPort[217] -unit.2.0.port.-1.s.217.orderindex=-1 -unit.2.0.port.-1.s.217.visible=1 -unit.2.0.port.-1.s.218.alias= -unit.2.0.port.-1.s.218.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.218.name=DataPort[218] -unit.2.0.port.-1.s.218.orderindex=-1 -unit.2.0.port.-1.s.218.visible=1 -unit.2.0.port.-1.s.219.alias=op -unit.2.0.port.-1.s.219.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.219.name=DataPort[219] -unit.2.0.port.-1.s.219.orderindex=-1 -unit.2.0.port.-1.s.219.visible=1 -unit.2.0.port.-1.s.22.alias= -unit.2.0.port.-1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.22.name=DataPort[22] -unit.2.0.port.-1.s.22.orderindex=-1 -unit.2.0.port.-1.s.22.visible=1 -unit.2.0.port.-1.s.220.alias=zbt_stb -unit.2.0.port.-1.s.220.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.220.name=DataPort[220] -unit.2.0.port.-1.s.220.orderindex=-1 -unit.2.0.port.-1.s.220.visible=1 -unit.2.0.port.-1.s.221.alias=flash_stb -unit.2.0.port.-1.s.221.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.221.name=DataPort[221] -unit.2.0.port.-1.s.221.orderindex=-1 -unit.2.0.port.-1.s.221.visible=1 -unit.2.0.port.-1.s.222.alias=flash_arena -unit.2.0.port.-1.s.222.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.222.name=DataPort[222] -unit.2.0.port.-1.s.222.orderindex=-1 -unit.2.0.port.-1.s.222.visible=1 -unit.2.0.port.-1.s.223.alias=vdu_arena -unit.2.0.port.-1.s.223.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.223.name=DataPort[223] -unit.2.0.port.-1.s.223.orderindex=-1 -unit.2.0.port.-1.s.223.visible=1 -unit.2.0.port.-1.s.224.alias=cnt_time0 -unit.2.0.port.-1.s.224.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.224.name=DataPort[224] -unit.2.0.port.-1.s.224.orderindex=-1 -unit.2.0.port.-1.s.224.visible=1 -unit.2.0.port.-1.s.225.alias=cnt_time1 -unit.2.0.port.-1.s.225.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.225.name=DataPort[225] -unit.2.0.port.-1.s.225.orderindex=-1 -unit.2.0.port.-1.s.225.visible=1 -unit.2.0.port.-1.s.226.alias=cnt_time2 -unit.2.0.port.-1.s.226.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.226.name=DataPort[226] -unit.2.0.port.-1.s.226.orderindex=-1 -unit.2.0.port.-1.s.226.visible=1 -unit.2.0.port.-1.s.227.alias=cnt_time3 -unit.2.0.port.-1.s.227.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.227.name=DataPort[227] -unit.2.0.port.-1.s.227.orderindex=-1 -unit.2.0.port.-1.s.227.visible=1 -unit.2.0.port.-1.s.228.alias=cnt_time4 -unit.2.0.port.-1.s.228.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.228.name=DataPort[228] -unit.2.0.port.-1.s.228.orderindex=-1 -unit.2.0.port.-1.s.228.visible=1 -unit.2.0.port.-1.s.229.alias= -unit.2.0.port.-1.s.229.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.229.name=DataPort[229] -unit.2.0.port.-1.s.229.orderindex=-1 -unit.2.0.port.-1.s.229.visible=1 -unit.2.0.port.-1.s.23.alias= -unit.2.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.23.name=DataPort[23] -unit.2.0.port.-1.s.23.orderindex=-1 -unit.2.0.port.-1.s.23.visible=1 -unit.2.0.port.-1.s.230.alias= -unit.2.0.port.-1.s.230.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.230.name=DataPort[230] -unit.2.0.port.-1.s.230.orderindex=-1 -unit.2.0.port.-1.s.230.visible=1 -unit.2.0.port.-1.s.231.alias= -unit.2.0.port.-1.s.231.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.231.name=DataPort[231] -unit.2.0.port.-1.s.231.orderindex=-1 -unit.2.0.port.-1.s.231.visible=1 -unit.2.0.port.-1.s.232.alias= -unit.2.0.port.-1.s.232.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.232.name=DataPort[232] -unit.2.0.port.-1.s.232.orderindex=-1 -unit.2.0.port.-1.s.232.visible=1 -unit.2.0.port.-1.s.233.alias= -unit.2.0.port.-1.s.233.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.233.name=DataPort[233] -unit.2.0.port.-1.s.233.orderindex=-1 -unit.2.0.port.-1.s.233.visible=1 -unit.2.0.port.-1.s.234.alias= -unit.2.0.port.-1.s.234.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.234.name=DataPort[234] -unit.2.0.port.-1.s.234.orderindex=-1 -unit.2.0.port.-1.s.234.visible=1 -unit.2.0.port.-1.s.235.alias= -unit.2.0.port.-1.s.235.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.235.name=DataPort[235] -unit.2.0.port.-1.s.235.orderindex=-1 -unit.2.0.port.-1.s.235.visible=1 -unit.2.0.port.-1.s.236.alias= -unit.2.0.port.-1.s.236.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.236.name=DataPort[236] -unit.2.0.port.-1.s.236.orderindex=-1 -unit.2.0.port.-1.s.236.visible=1 -unit.2.0.port.-1.s.237.alias= -unit.2.0.port.-1.s.237.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.237.name=DataPort[237] -unit.2.0.port.-1.s.237.orderindex=-1 -unit.2.0.port.-1.s.237.visible=1 -unit.2.0.port.-1.s.238.alias= -unit.2.0.port.-1.s.238.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.238.name=DataPort[238] -unit.2.0.port.-1.s.238.orderindex=-1 -unit.2.0.port.-1.s.238.visible=1 -unit.2.0.port.-1.s.239.alias= -unit.2.0.port.-1.s.239.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.239.name=DataPort[239] -unit.2.0.port.-1.s.239.orderindex=-1 -unit.2.0.port.-1.s.239.visible=1 -unit.2.0.port.-1.s.24.alias= -unit.2.0.port.-1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.24.name=DataPort[24] -unit.2.0.port.-1.s.24.orderindex=-1 -unit.2.0.port.-1.s.24.visible=1 -unit.2.0.port.-1.s.240.alias= -unit.2.0.port.-1.s.240.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.240.name=DataPort[240] -unit.2.0.port.-1.s.240.orderindex=-1 -unit.2.0.port.-1.s.240.visible=1 -unit.2.0.port.-1.s.241.alias= -unit.2.0.port.-1.s.241.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.241.name=DataPort[241] -unit.2.0.port.-1.s.241.orderindex=-1 -unit.2.0.port.-1.s.241.visible=1 -unit.2.0.port.-1.s.242.alias= -unit.2.0.port.-1.s.242.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.242.name=DataPort[242] -unit.2.0.port.-1.s.242.orderindex=-1 -unit.2.0.port.-1.s.242.visible=1 -unit.2.0.port.-1.s.243.alias= -unit.2.0.port.-1.s.243.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.243.name=DataPort[243] -unit.2.0.port.-1.s.243.orderindex=-1 -unit.2.0.port.-1.s.243.visible=1 -unit.2.0.port.-1.s.244.alias= -unit.2.0.port.-1.s.244.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.244.name=DataPort[244] -unit.2.0.port.-1.s.244.orderindex=-1 -unit.2.0.port.-1.s.244.visible=1 -unit.2.0.port.-1.s.245.alias= -unit.2.0.port.-1.s.245.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.245.name=DataPort[245] -unit.2.0.port.-1.s.245.orderindex=-1 -unit.2.0.port.-1.s.245.visible=1 -unit.2.0.port.-1.s.246.alias= -unit.2.0.port.-1.s.246.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.246.name=DataPort[246] -unit.2.0.port.-1.s.246.orderindex=-1 -unit.2.0.port.-1.s.246.visible=1 -unit.2.0.port.-1.s.247.alias= -unit.2.0.port.-1.s.247.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.247.name=DataPort[247] -unit.2.0.port.-1.s.247.orderindex=-1 -unit.2.0.port.-1.s.247.visible=1 -unit.2.0.port.-1.s.248.alias= -unit.2.0.port.-1.s.248.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.248.name=DataPort[248] -unit.2.0.port.-1.s.248.orderindex=-1 -unit.2.0.port.-1.s.248.visible=1 -unit.2.0.port.-1.s.249.alias= -unit.2.0.port.-1.s.249.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.249.name=DataPort[249] -unit.2.0.port.-1.s.249.orderindex=-1 -unit.2.0.port.-1.s.249.visible=1 -unit.2.0.port.-1.s.25.alias= -unit.2.0.port.-1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.25.name=DataPort[25] -unit.2.0.port.-1.s.25.orderindex=-1 -unit.2.0.port.-1.s.25.visible=1 -unit.2.0.port.-1.s.250.alias= -unit.2.0.port.-1.s.250.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.250.name=DataPort[250] -unit.2.0.port.-1.s.250.orderindex=-1 -unit.2.0.port.-1.s.250.visible=1 -unit.2.0.port.-1.s.251.alias= -unit.2.0.port.-1.s.251.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.251.name=DataPort[251] -unit.2.0.port.-1.s.251.orderindex=-1 -unit.2.0.port.-1.s.251.visible=1 -unit.2.0.port.-1.s.252.alias= -unit.2.0.port.-1.s.252.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.252.name=DataPort[252] -unit.2.0.port.-1.s.252.orderindex=-1 -unit.2.0.port.-1.s.252.visible=1 -unit.2.0.port.-1.s.253.alias= -unit.2.0.port.-1.s.253.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.253.name=DataPort[253] -unit.2.0.port.-1.s.253.orderindex=-1 -unit.2.0.port.-1.s.253.visible=1 -unit.2.0.port.-1.s.254.alias= -unit.2.0.port.-1.s.254.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.254.name=DataPort[254] -unit.2.0.port.-1.s.254.orderindex=-1 -unit.2.0.port.-1.s.254.visible=1 -unit.2.0.port.-1.s.255.alias= -unit.2.0.port.-1.s.255.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.255.name=DataPort[255] -unit.2.0.port.-1.s.255.orderindex=-1 -unit.2.0.port.-1.s.255.visible=1 -unit.2.0.port.-1.s.26.alias= -unit.2.0.port.-1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.26.name=DataPort[26] -unit.2.0.port.-1.s.26.orderindex=-1 -unit.2.0.port.-1.s.26.visible=1 -unit.2.0.port.-1.s.27.alias= -unit.2.0.port.-1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.27.name=DataPort[27] -unit.2.0.port.-1.s.27.orderindex=-1 -unit.2.0.port.-1.s.27.visible=1 -unit.2.0.port.-1.s.28.alias= -unit.2.0.port.-1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.28.name=DataPort[28] -unit.2.0.port.-1.s.28.orderindex=-1 -unit.2.0.port.-1.s.28.visible=1 -unit.2.0.port.-1.s.29.alias= -unit.2.0.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.29.name=DataPort[29] -unit.2.0.port.-1.s.29.orderindex=-1 -unit.2.0.port.-1.s.29.visible=1 -unit.2.0.port.-1.s.3.alias= -unit.2.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.3.name=DataPort[3] -unit.2.0.port.-1.s.3.orderindex=-1 -unit.2.0.port.-1.s.3.visible=1 -unit.2.0.port.-1.s.30.alias= -unit.2.0.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.30.name=DataPort[30] -unit.2.0.port.-1.s.30.orderindex=-1 -unit.2.0.port.-1.s.30.visible=1 -unit.2.0.port.-1.s.31.alias= -unit.2.0.port.-1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.31.name=DataPort[31] -unit.2.0.port.-1.s.31.orderindex=-1 -unit.2.0.port.-1.s.31.visible=1 -unit.2.0.port.-1.s.32.alias= -unit.2.0.port.-1.s.32.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.32.name=DataPort[32] -unit.2.0.port.-1.s.32.orderindex=-1 -unit.2.0.port.-1.s.32.visible=1 -unit.2.0.port.-1.s.33.alias= -unit.2.0.port.-1.s.33.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.33.name=DataPort[33] -unit.2.0.port.-1.s.33.orderindex=-1 -unit.2.0.port.-1.s.33.visible=1 -unit.2.0.port.-1.s.34.alias= -unit.2.0.port.-1.s.34.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.34.name=DataPort[34] -unit.2.0.port.-1.s.34.orderindex=-1 -unit.2.0.port.-1.s.34.visible=1 -unit.2.0.port.-1.s.35.alias= -unit.2.0.port.-1.s.35.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.35.name=DataPort[35] -unit.2.0.port.-1.s.35.orderindex=-1 -unit.2.0.port.-1.s.35.visible=1 -unit.2.0.port.-1.s.36.alias= -unit.2.0.port.-1.s.36.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.36.name=DataPort[36] -unit.2.0.port.-1.s.36.orderindex=-1 -unit.2.0.port.-1.s.36.visible=1 -unit.2.0.port.-1.s.37.alias= -unit.2.0.port.-1.s.37.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.37.name=DataPort[37] -unit.2.0.port.-1.s.37.orderindex=-1 -unit.2.0.port.-1.s.37.visible=1 -unit.2.0.port.-1.s.38.alias= -unit.2.0.port.-1.s.38.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.38.name=DataPort[38] -unit.2.0.port.-1.s.38.orderindex=-1 -unit.2.0.port.-1.s.38.visible=1 -unit.2.0.port.-1.s.39.alias= -unit.2.0.port.-1.s.39.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.39.name=DataPort[39] -unit.2.0.port.-1.s.39.orderindex=-1 -unit.2.0.port.-1.s.39.visible=1 -unit.2.0.port.-1.s.4.alias= -unit.2.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.4.name=DataPort[4] -unit.2.0.port.-1.s.4.orderindex=-1 -unit.2.0.port.-1.s.4.visible=1 -unit.2.0.port.-1.s.40.alias= -unit.2.0.port.-1.s.40.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.40.name=DataPort[40] -unit.2.0.port.-1.s.40.orderindex=-1 -unit.2.0.port.-1.s.40.visible=1 -unit.2.0.port.-1.s.41.alias= -unit.2.0.port.-1.s.41.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.41.name=DataPort[41] -unit.2.0.port.-1.s.41.orderindex=-1 -unit.2.0.port.-1.s.41.visible=1 -unit.2.0.port.-1.s.42.alias= -unit.2.0.port.-1.s.42.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.42.name=DataPort[42] -unit.2.0.port.-1.s.42.orderindex=-1 -unit.2.0.port.-1.s.42.visible=1 -unit.2.0.port.-1.s.43.alias= -unit.2.0.port.-1.s.43.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.43.name=DataPort[43] -unit.2.0.port.-1.s.43.orderindex=-1 -unit.2.0.port.-1.s.43.visible=1 -unit.2.0.port.-1.s.44.alias= -unit.2.0.port.-1.s.44.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.44.name=DataPort[44] -unit.2.0.port.-1.s.44.orderindex=-1 -unit.2.0.port.-1.s.44.visible=1 -unit.2.0.port.-1.s.45.alias= -unit.2.0.port.-1.s.45.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.45.name=DataPort[45] -unit.2.0.port.-1.s.45.orderindex=-1 -unit.2.0.port.-1.s.45.visible=1 -unit.2.0.port.-1.s.46.alias= -unit.2.0.port.-1.s.46.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.46.name=DataPort[46] -unit.2.0.port.-1.s.46.orderindex=-1 -unit.2.0.port.-1.s.46.visible=1 -unit.2.0.port.-1.s.47.alias= -unit.2.0.port.-1.s.47.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.47.name=DataPort[47] -unit.2.0.port.-1.s.47.orderindex=-1 -unit.2.0.port.-1.s.47.visible=1 -unit.2.0.port.-1.s.48.alias= -unit.2.0.port.-1.s.48.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.48.name=DataPort[48] -unit.2.0.port.-1.s.48.orderindex=-1 -unit.2.0.port.-1.s.48.visible=1 -unit.2.0.port.-1.s.49.alias= -unit.2.0.port.-1.s.49.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.49.name=DataPort[49] -unit.2.0.port.-1.s.49.orderindex=-1 -unit.2.0.port.-1.s.49.visible=1 -unit.2.0.port.-1.s.5.alias= -unit.2.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.5.name=DataPort[5] -unit.2.0.port.-1.s.5.orderindex=-1 -unit.2.0.port.-1.s.5.visible=1 -unit.2.0.port.-1.s.50.alias= -unit.2.0.port.-1.s.50.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.50.name=DataPort[50] -unit.2.0.port.-1.s.50.orderindex=-1 -unit.2.0.port.-1.s.50.visible=1 -unit.2.0.port.-1.s.51.alias= -unit.2.0.port.-1.s.51.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.51.name=DataPort[51] -unit.2.0.port.-1.s.51.orderindex=-1 -unit.2.0.port.-1.s.51.visible=1 -unit.2.0.port.-1.s.52.alias= -unit.2.0.port.-1.s.52.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.52.name=DataPort[52] -unit.2.0.port.-1.s.52.orderindex=-1 -unit.2.0.port.-1.s.52.visible=1 -unit.2.0.port.-1.s.53.alias= -unit.2.0.port.-1.s.53.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.53.name=DataPort[53] -unit.2.0.port.-1.s.53.orderindex=-1 -unit.2.0.port.-1.s.53.visible=1 -unit.2.0.port.-1.s.54.alias= -unit.2.0.port.-1.s.54.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.54.name=DataPort[54] -unit.2.0.port.-1.s.54.orderindex=-1 -unit.2.0.port.-1.s.54.visible=1 -unit.2.0.port.-1.s.55.alias= -unit.2.0.port.-1.s.55.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.55.name=DataPort[55] -unit.2.0.port.-1.s.55.orderindex=-1 -unit.2.0.port.-1.s.55.visible=1 -unit.2.0.port.-1.s.56.alias= -unit.2.0.port.-1.s.56.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.56.name=DataPort[56] -unit.2.0.port.-1.s.56.orderindex=-1 -unit.2.0.port.-1.s.56.visible=1 -unit.2.0.port.-1.s.57.alias= -unit.2.0.port.-1.s.57.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.57.name=DataPort[57] -unit.2.0.port.-1.s.57.orderindex=-1 -unit.2.0.port.-1.s.57.visible=1 -unit.2.0.port.-1.s.58.alias= -unit.2.0.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.58.name=DataPort[58] -unit.2.0.port.-1.s.58.orderindex=-1 -unit.2.0.port.-1.s.58.visible=1 -unit.2.0.port.-1.s.59.alias= -unit.2.0.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.59.name=DataPort[59] -unit.2.0.port.-1.s.59.orderindex=-1 -unit.2.0.port.-1.s.59.visible=1 -unit.2.0.port.-1.s.6.alias= -unit.2.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.6.name=DataPort[6] -unit.2.0.port.-1.s.6.orderindex=-1 -unit.2.0.port.-1.s.6.visible=1 -unit.2.0.port.-1.s.60.alias= -unit.2.0.port.-1.s.60.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.60.name=DataPort[60] -unit.2.0.port.-1.s.60.orderindex=-1 -unit.2.0.port.-1.s.60.visible=1 -unit.2.0.port.-1.s.61.alias= -unit.2.0.port.-1.s.61.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.61.name=DataPort[61] -unit.2.0.port.-1.s.61.orderindex=-1 -unit.2.0.port.-1.s.61.visible=1 -unit.2.0.port.-1.s.62.alias= -unit.2.0.port.-1.s.62.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.62.name=DataPort[62] -unit.2.0.port.-1.s.62.orderindex=-1 -unit.2.0.port.-1.s.62.visible=1 -unit.2.0.port.-1.s.63.alias= -unit.2.0.port.-1.s.63.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.63.name=DataPort[63] -unit.2.0.port.-1.s.63.orderindex=-1 -unit.2.0.port.-1.s.63.visible=1 -unit.2.0.port.-1.s.64.alias= -unit.2.0.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.64.name=DataPort[64] -unit.2.0.port.-1.s.64.orderindex=-1 -unit.2.0.port.-1.s.64.visible=1 -unit.2.0.port.-1.s.65.alias= -unit.2.0.port.-1.s.65.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.65.name=DataPort[65] -unit.2.0.port.-1.s.65.orderindex=-1 -unit.2.0.port.-1.s.65.visible=1 -unit.2.0.port.-1.s.66.alias= -unit.2.0.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.66.name=DataPort[66] -unit.2.0.port.-1.s.66.orderindex=-1 -unit.2.0.port.-1.s.66.visible=1 -unit.2.0.port.-1.s.67.alias= -unit.2.0.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.67.name=DataPort[67] -unit.2.0.port.-1.s.67.orderindex=-1 -unit.2.0.port.-1.s.67.visible=1 -unit.2.0.port.-1.s.68.alias= -unit.2.0.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.68.name=DataPort[68] -unit.2.0.port.-1.s.68.orderindex=-1 -unit.2.0.port.-1.s.68.visible=1 -unit.2.0.port.-1.s.69.alias= -unit.2.0.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.69.name=DataPort[69] -unit.2.0.port.-1.s.69.orderindex=-1 -unit.2.0.port.-1.s.69.visible=1 -unit.2.0.port.-1.s.7.alias= -unit.2.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.7.name=DataPort[7] -unit.2.0.port.-1.s.7.orderindex=-1 -unit.2.0.port.-1.s.7.visible=1 -unit.2.0.port.-1.s.70.alias= -unit.2.0.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.70.name=DataPort[70] -unit.2.0.port.-1.s.70.orderindex=-1 -unit.2.0.port.-1.s.70.visible=1 -unit.2.0.port.-1.s.71.alias= -unit.2.0.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.71.name=DataPort[71] -unit.2.0.port.-1.s.71.orderindex=-1 -unit.2.0.port.-1.s.71.visible=1 -unit.2.0.port.-1.s.72.alias=ack -unit.2.0.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.72.name=DataPort[72] -unit.2.0.port.-1.s.72.orderindex=-1 -unit.2.0.port.-1.s.72.visible=1 -unit.2.0.port.-1.s.73.alias=stb -unit.2.0.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.73.name=DataPort[73] -unit.2.0.port.-1.s.73.orderindex=-1 -unit.2.0.port.-1.s.73.visible=1 -unit.2.0.port.-1.s.74.alias=cyc -unit.2.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.74.name=DataPort[74] -unit.2.0.port.-1.s.74.orderindex=-1 -unit.2.0.port.-1.s.74.visible=1 -unit.2.0.port.-1.s.75.alias=tga -unit.2.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.75.name=DataPort[75] -unit.2.0.port.-1.s.75.orderindex=-1 -unit.2.0.port.-1.s.75.visible=1 -unit.2.0.port.-1.s.76.alias=we -unit.2.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.76.name=DataPort[76] -unit.2.0.port.-1.s.76.orderindex=-1 -unit.2.0.port.-1.s.76.visible=1 -unit.2.0.port.-1.s.77.alias=clk -unit.2.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.77.name=DataPort[77] -unit.2.0.port.-1.s.77.orderindex=-1 -unit.2.0.port.-1.s.77.visible=1 -unit.2.0.port.-1.s.78.alias= -unit.2.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.78.name=DataPort[78] -unit.2.0.port.-1.s.78.orderindex=-1 -unit.2.0.port.-1.s.78.visible=1 -unit.2.0.port.-1.s.79.alias= -unit.2.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.79.name=DataPort[79] -unit.2.0.port.-1.s.79.orderindex=-1 -unit.2.0.port.-1.s.79.visible=1 -unit.2.0.port.-1.s.8.alias= -unit.2.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.8.name=DataPort[8] -unit.2.0.port.-1.s.8.orderindex=-1 -unit.2.0.port.-1.s.8.visible=1 -unit.2.0.port.-1.s.80.alias= -unit.2.0.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.80.name=DataPort[80] -unit.2.0.port.-1.s.80.orderindex=-1 -unit.2.0.port.-1.s.80.visible=1 -unit.2.0.port.-1.s.81.alias= -unit.2.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.81.name=DataPort[81] -unit.2.0.port.-1.s.81.orderindex=-1 -unit.2.0.port.-1.s.81.visible=1 -unit.2.0.port.-1.s.82.alias= -unit.2.0.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.82.name=DataPort[82] -unit.2.0.port.-1.s.82.orderindex=-1 -unit.2.0.port.-1.s.82.visible=1 -unit.2.0.port.-1.s.83.alias= -unit.2.0.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.83.name=DataPort[83] -unit.2.0.port.-1.s.83.orderindex=-1 -unit.2.0.port.-1.s.83.visible=1 -unit.2.0.port.-1.s.84.alias= -unit.2.0.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.84.name=DataPort[84] -unit.2.0.port.-1.s.84.orderindex=-1 -unit.2.0.port.-1.s.84.visible=1 -unit.2.0.port.-1.s.85.alias= -unit.2.0.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.85.name=DataPort[85] -unit.2.0.port.-1.s.85.orderindex=-1 -unit.2.0.port.-1.s.85.visible=1 -unit.2.0.port.-1.s.86.alias= -unit.2.0.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.86.name=DataPort[86] -unit.2.0.port.-1.s.86.orderindex=-1 -unit.2.0.port.-1.s.86.visible=1 -unit.2.0.port.-1.s.87.alias= -unit.2.0.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.87.name=DataPort[87] -unit.2.0.port.-1.s.87.orderindex=-1 -unit.2.0.port.-1.s.87.visible=1 -unit.2.0.port.-1.s.88.alias= -unit.2.0.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.88.name=DataPort[88] -unit.2.0.port.-1.s.88.orderindex=-1 -unit.2.0.port.-1.s.88.visible=1 -unit.2.0.port.-1.s.89.alias= -unit.2.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.89.name=DataPort[89] -unit.2.0.port.-1.s.89.orderindex=-1 -unit.2.0.port.-1.s.89.visible=1 -unit.2.0.port.-1.s.9.alias= -unit.2.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.9.name=DataPort[9] -unit.2.0.port.-1.s.9.orderindex=-1 -unit.2.0.port.-1.s.9.visible=1 -unit.2.0.port.-1.s.90.alias= -unit.2.0.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.90.name=DataPort[90] -unit.2.0.port.-1.s.90.orderindex=-1 -unit.2.0.port.-1.s.90.visible=1 -unit.2.0.port.-1.s.91.alias= -unit.2.0.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.91.name=DataPort[91] -unit.2.0.port.-1.s.91.orderindex=-1 -unit.2.0.port.-1.s.91.visible=1 -unit.2.0.port.-1.s.92.alias= -unit.2.0.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.92.name=DataPort[92] -unit.2.0.port.-1.s.92.orderindex=-1 -unit.2.0.port.-1.s.92.visible=1 -unit.2.0.port.-1.s.93.alias= -unit.2.0.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.93.name=DataPort[93] -unit.2.0.port.-1.s.93.orderindex=-1 -unit.2.0.port.-1.s.93.visible=1 -unit.2.0.port.-1.s.94.alias=byte_op -unit.2.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.94.name=DataPort[94] -unit.2.0.port.-1.s.94.orderindex=-1 -unit.2.0.port.-1.s.94.visible=1 -unit.2.0.port.-1.s.95.alias= -unit.2.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.95.name=DataPort[95] -unit.2.0.port.-1.s.95.orderindex=-1 -unit.2.0.port.-1.s.95.visible=1 -unit.2.0.port.-1.s.96.alias= -unit.2.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.96.name=DataPort[96] -unit.2.0.port.-1.s.96.orderindex=-1 -unit.2.0.port.-1.s.96.visible=1 -unit.2.0.port.-1.s.97.alias= -unit.2.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.97.name=DataPort[97] -unit.2.0.port.-1.s.97.orderindex=-1 -unit.2.0.port.-1.s.97.visible=1 -unit.2.0.port.-1.s.98.alias= -unit.2.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.98.name=DataPort[98] -unit.2.0.port.-1.s.98.orderindex=-1 -unit.2.0.port.-1.s.98.visible=1 -unit.2.0.port.-1.s.99.alias= -unit.2.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.-1.s.99.name=DataPort[99] -unit.2.0.port.-1.s.99.orderindex=-1 -unit.2.0.port.-1.s.99.visible=1 -unit.2.0.port.0.b.0.alias= -unit.2.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 -unit.2.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.b.0.name=TriggerPort0 -unit.2.0.port.0.b.0.orderindex=-1 -unit.2.0.port.0.b.0.radix=Hex -unit.2.0.port.0.b.0.signedOffset=0.0 -unit.2.0.port.0.b.0.signedPrecision=0 -unit.2.0.port.0.b.0.signedScaleFactor=1.0 -unit.2.0.port.0.b.0.unsignedOffset=0.0 -unit.2.0.port.0.b.0.unsignedPrecision=0 -unit.2.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.0.b.0.visible=1 -unit.2.0.port.0.buscount=1 -unit.2.0.port.0.channelcount=20 -unit.2.0.port.0.s.0.alias= -unit.2.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.0.name=TriggerPort0[0] -unit.2.0.port.0.s.0.orderindex=-1 -unit.2.0.port.0.s.0.visible=1 -unit.2.0.port.0.s.1.alias= -unit.2.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.1.name=TriggerPort0[1] -unit.2.0.port.0.s.1.orderindex=-1 -unit.2.0.port.0.s.1.visible=1 -unit.2.0.port.0.s.10.alias= -unit.2.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.10.name=TriggerPort0[10] -unit.2.0.port.0.s.10.orderindex=-1 -unit.2.0.port.0.s.10.visible=1 -unit.2.0.port.0.s.11.alias= -unit.2.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.11.name=TriggerPort0[11] -unit.2.0.port.0.s.11.orderindex=-1 -unit.2.0.port.0.s.11.visible=1 -unit.2.0.port.0.s.12.alias= -unit.2.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.12.name=TriggerPort0[12] -unit.2.0.port.0.s.12.orderindex=-1 -unit.2.0.port.0.s.12.visible=1 -unit.2.0.port.0.s.13.alias= -unit.2.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.13.name=TriggerPort0[13] -unit.2.0.port.0.s.13.orderindex=-1 -unit.2.0.port.0.s.13.visible=1 -unit.2.0.port.0.s.14.alias= -unit.2.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.14.name=TriggerPort0[14] -unit.2.0.port.0.s.14.orderindex=-1 -unit.2.0.port.0.s.14.visible=1 -unit.2.0.port.0.s.15.alias= -unit.2.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.15.name=TriggerPort0[15] -unit.2.0.port.0.s.15.orderindex=-1 -unit.2.0.port.0.s.15.visible=1 -unit.2.0.port.0.s.16.alias= -unit.2.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.16.name=TriggerPort0[16] -unit.2.0.port.0.s.16.orderindex=-1 -unit.2.0.port.0.s.16.visible=1 -unit.2.0.port.0.s.17.alias= -unit.2.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.17.name=TriggerPort0[17] -unit.2.0.port.0.s.17.orderindex=-1 -unit.2.0.port.0.s.17.visible=1 -unit.2.0.port.0.s.18.alias= -unit.2.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.18.name=TriggerPort0[18] -unit.2.0.port.0.s.18.orderindex=-1 -unit.2.0.port.0.s.18.visible=1 -unit.2.0.port.0.s.19.alias= -unit.2.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.19.name=TriggerPort0[19] -unit.2.0.port.0.s.19.orderindex=-1 -unit.2.0.port.0.s.19.visible=1 -unit.2.0.port.0.s.2.alias= -unit.2.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.2.name=TriggerPort0[2] -unit.2.0.port.0.s.2.orderindex=-1 -unit.2.0.port.0.s.2.visible=1 -unit.2.0.port.0.s.3.alias= -unit.2.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.3.name=TriggerPort0[3] -unit.2.0.port.0.s.3.orderindex=-1 -unit.2.0.port.0.s.3.visible=1 -unit.2.0.port.0.s.4.alias= -unit.2.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.4.name=TriggerPort0[4] -unit.2.0.port.0.s.4.orderindex=-1 -unit.2.0.port.0.s.4.visible=1 -unit.2.0.port.0.s.5.alias= -unit.2.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.5.name=TriggerPort0[5] -unit.2.0.port.0.s.5.orderindex=-1 -unit.2.0.port.0.s.5.visible=1 -unit.2.0.port.0.s.6.alias= -unit.2.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.6.name=TriggerPort0[6] -unit.2.0.port.0.s.6.orderindex=-1 -unit.2.0.port.0.s.6.visible=1 -unit.2.0.port.0.s.7.alias= -unit.2.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.7.name=TriggerPort0[7] -unit.2.0.port.0.s.7.orderindex=-1 -unit.2.0.port.0.s.7.visible=1 -unit.2.0.port.0.s.8.alias= -unit.2.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.8.name=TriggerPort0[8] -unit.2.0.port.0.s.8.orderindex=-1 -unit.2.0.port.0.s.8.visible=1 -unit.2.0.port.0.s.9.alias= -unit.2.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.0.s.9.name=TriggerPort0[9] -unit.2.0.port.0.s.9.orderindex=-1 -unit.2.0.port.0.s.9.visible=1 -unit.2.0.port.1.b.0.alias= -unit.2.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.2.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.b.0.name=TriggerPort1 -unit.2.0.port.1.b.0.orderindex=-1 -unit.2.0.port.1.b.0.radix=Hex -unit.2.0.port.1.b.0.signedOffset=0.0 -unit.2.0.port.1.b.0.signedPrecision=0 -unit.2.0.port.1.b.0.signedScaleFactor=1.0 -unit.2.0.port.1.b.0.unsignedOffset=0.0 -unit.2.0.port.1.b.0.unsignedPrecision=0 -unit.2.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.1.b.0.visible=1 -unit.2.0.port.1.buscount=1 -unit.2.0.port.1.channelcount=32 -unit.2.0.port.1.s.0.alias= -unit.2.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.0.name=TriggerPort1[0] -unit.2.0.port.1.s.0.orderindex=-1 -unit.2.0.port.1.s.0.visible=1 -unit.2.0.port.1.s.1.alias= -unit.2.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.1.name=TriggerPort1[1] -unit.2.0.port.1.s.1.orderindex=-1 -unit.2.0.port.1.s.1.visible=1 -unit.2.0.port.1.s.10.alias= -unit.2.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.10.name=TriggerPort1[10] -unit.2.0.port.1.s.10.orderindex=-1 -unit.2.0.port.1.s.10.visible=1 -unit.2.0.port.1.s.11.alias= -unit.2.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.11.name=TriggerPort1[11] -unit.2.0.port.1.s.11.orderindex=-1 -unit.2.0.port.1.s.11.visible=1 -unit.2.0.port.1.s.12.alias= -unit.2.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.12.name=TriggerPort1[12] -unit.2.0.port.1.s.12.orderindex=-1 -unit.2.0.port.1.s.12.visible=1 -unit.2.0.port.1.s.13.alias= -unit.2.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.13.name=TriggerPort1[13] -unit.2.0.port.1.s.13.orderindex=-1 -unit.2.0.port.1.s.13.visible=1 -unit.2.0.port.1.s.14.alias= -unit.2.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.14.name=TriggerPort1[14] -unit.2.0.port.1.s.14.orderindex=-1 -unit.2.0.port.1.s.14.visible=1 -unit.2.0.port.1.s.15.alias= -unit.2.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.15.name=TriggerPort1[15] -unit.2.0.port.1.s.15.orderindex=-1 -unit.2.0.port.1.s.15.visible=1 -unit.2.0.port.1.s.16.alias= -unit.2.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.16.name=TriggerPort1[16] -unit.2.0.port.1.s.16.orderindex=-1 -unit.2.0.port.1.s.16.visible=1 -unit.2.0.port.1.s.17.alias= -unit.2.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.17.name=TriggerPort1[17] -unit.2.0.port.1.s.17.orderindex=-1 -unit.2.0.port.1.s.17.visible=1 -unit.2.0.port.1.s.18.alias= -unit.2.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.18.name=TriggerPort1[18] -unit.2.0.port.1.s.18.orderindex=-1 -unit.2.0.port.1.s.18.visible=1 -unit.2.0.port.1.s.19.alias= -unit.2.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.19.name=TriggerPort1[19] -unit.2.0.port.1.s.19.orderindex=-1 -unit.2.0.port.1.s.19.visible=1 -unit.2.0.port.1.s.2.alias= -unit.2.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.2.name=TriggerPort1[2] -unit.2.0.port.1.s.2.orderindex=-1 -unit.2.0.port.1.s.2.visible=1 -unit.2.0.port.1.s.20.alias= -unit.2.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.20.name=TriggerPort1[20] -unit.2.0.port.1.s.20.orderindex=-1 -unit.2.0.port.1.s.20.visible=1 -unit.2.0.port.1.s.21.alias= -unit.2.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.21.name=TriggerPort1[21] -unit.2.0.port.1.s.21.orderindex=-1 -unit.2.0.port.1.s.21.visible=1 -unit.2.0.port.1.s.22.alias= -unit.2.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.22.name=TriggerPort1[22] -unit.2.0.port.1.s.22.orderindex=-1 -unit.2.0.port.1.s.22.visible=1 -unit.2.0.port.1.s.23.alias= -unit.2.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.23.name=TriggerPort1[23] -unit.2.0.port.1.s.23.orderindex=-1 -unit.2.0.port.1.s.23.visible=1 -unit.2.0.port.1.s.24.alias= -unit.2.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.24.name=TriggerPort1[24] -unit.2.0.port.1.s.24.orderindex=-1 -unit.2.0.port.1.s.24.visible=1 -unit.2.0.port.1.s.25.alias= -unit.2.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.25.name=TriggerPort1[25] -unit.2.0.port.1.s.25.orderindex=-1 -unit.2.0.port.1.s.25.visible=1 -unit.2.0.port.1.s.26.alias= -unit.2.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.26.name=TriggerPort1[26] -unit.2.0.port.1.s.26.orderindex=-1 -unit.2.0.port.1.s.26.visible=1 -unit.2.0.port.1.s.27.alias= -unit.2.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.27.name=TriggerPort1[27] -unit.2.0.port.1.s.27.orderindex=-1 -unit.2.0.port.1.s.27.visible=1 -unit.2.0.port.1.s.28.alias= -unit.2.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.28.name=TriggerPort1[28] -unit.2.0.port.1.s.28.orderindex=-1 -unit.2.0.port.1.s.28.visible=1 -unit.2.0.port.1.s.29.alias= -unit.2.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.29.name=TriggerPort1[29] -unit.2.0.port.1.s.29.orderindex=-1 -unit.2.0.port.1.s.29.visible=1 -unit.2.0.port.1.s.3.alias= -unit.2.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.3.name=TriggerPort1[3] -unit.2.0.port.1.s.3.orderindex=-1 -unit.2.0.port.1.s.3.visible=1 -unit.2.0.port.1.s.30.alias= -unit.2.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.30.name=TriggerPort1[30] -unit.2.0.port.1.s.30.orderindex=-1 -unit.2.0.port.1.s.30.visible=1 -unit.2.0.port.1.s.31.alias= -unit.2.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.31.name=TriggerPort1[31] -unit.2.0.port.1.s.31.orderindex=-1 -unit.2.0.port.1.s.31.visible=1 -unit.2.0.port.1.s.4.alias= -unit.2.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.4.name=TriggerPort1[4] -unit.2.0.port.1.s.4.orderindex=-1 -unit.2.0.port.1.s.4.visible=1 -unit.2.0.port.1.s.5.alias= -unit.2.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.5.name=TriggerPort1[5] -unit.2.0.port.1.s.5.orderindex=-1 -unit.2.0.port.1.s.5.visible=1 -unit.2.0.port.1.s.6.alias= -unit.2.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.6.name=TriggerPort1[6] -unit.2.0.port.1.s.6.orderindex=-1 -unit.2.0.port.1.s.6.visible=1 -unit.2.0.port.1.s.7.alias= -unit.2.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.7.name=TriggerPort1[7] -unit.2.0.port.1.s.7.orderindex=-1 -unit.2.0.port.1.s.7.visible=1 -unit.2.0.port.1.s.8.alias= -unit.2.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.8.name=TriggerPort1[8] -unit.2.0.port.1.s.8.orderindex=-1 -unit.2.0.port.1.s.8.visible=1 -unit.2.0.port.1.s.9.alias= -unit.2.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.1.s.9.name=TriggerPort1[9] -unit.2.0.port.1.s.9.orderindex=-1 -unit.2.0.port.1.s.9.visible=1 -unit.2.0.port.10.b.0.alias= -unit.2.0.port.10.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 -unit.2.0.port.10.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.b.0.name=TriggerPort10 -unit.2.0.port.10.b.0.orderindex=-1 -unit.2.0.port.10.b.0.radix=Hex -unit.2.0.port.10.b.0.signedOffset=0.0 -unit.2.0.port.10.b.0.signedPrecision=0 -unit.2.0.port.10.b.0.signedScaleFactor=1.0 -unit.2.0.port.10.b.0.unsignedOffset=0.0 -unit.2.0.port.10.b.0.unsignedPrecision=0 -unit.2.0.port.10.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.10.b.0.visible=1 -unit.2.0.port.10.buscount=1 -unit.2.0.port.10.channelcount=21 -unit.2.0.port.10.s.0.alias= -unit.2.0.port.10.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.0.name=TriggerPort10[0] -unit.2.0.port.10.s.0.orderindex=-1 -unit.2.0.port.10.s.0.visible=1 -unit.2.0.port.10.s.1.alias= -unit.2.0.port.10.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.1.name=TriggerPort10[1] -unit.2.0.port.10.s.1.orderindex=-1 -unit.2.0.port.10.s.1.visible=1 -unit.2.0.port.10.s.10.alias= -unit.2.0.port.10.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.10.name=TriggerPort10[10] -unit.2.0.port.10.s.10.orderindex=-1 -unit.2.0.port.10.s.10.visible=1 -unit.2.0.port.10.s.11.alias= -unit.2.0.port.10.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.11.name=TriggerPort10[11] -unit.2.0.port.10.s.11.orderindex=-1 -unit.2.0.port.10.s.11.visible=1 -unit.2.0.port.10.s.12.alias= -unit.2.0.port.10.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.12.name=TriggerPort10[12] -unit.2.0.port.10.s.12.orderindex=-1 -unit.2.0.port.10.s.12.visible=1 -unit.2.0.port.10.s.13.alias= -unit.2.0.port.10.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.13.name=TriggerPort10[13] -unit.2.0.port.10.s.13.orderindex=-1 -unit.2.0.port.10.s.13.visible=1 -unit.2.0.port.10.s.14.alias= -unit.2.0.port.10.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.14.name=TriggerPort10[14] -unit.2.0.port.10.s.14.orderindex=-1 -unit.2.0.port.10.s.14.visible=1 -unit.2.0.port.10.s.15.alias= -unit.2.0.port.10.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.15.name=TriggerPort10[15] -unit.2.0.port.10.s.15.orderindex=-1 -unit.2.0.port.10.s.15.visible=1 -unit.2.0.port.10.s.16.alias=ace_stb -unit.2.0.port.10.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.16.name=TriggerPort10[16] -unit.2.0.port.10.s.16.orderindex=-1 -unit.2.0.port.10.s.16.visible=1 -unit.2.0.port.10.s.17.alias=ace_ack -unit.2.0.port.10.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.17.name=TriggerPort10[17] -unit.2.0.port.10.s.17.orderindex=-1 -unit.2.0.port.10.s.17.visible=1 -unit.2.0.port.10.s.18.alias=aceusb_oe_n_ -unit.2.0.port.10.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.18.name=TriggerPort10[18] -unit.2.0.port.10.s.18.orderindex=-1 -unit.2.0.port.10.s.18.visible=1 -unit.2.0.port.10.s.19.alias=aceusb_we_n -unit.2.0.port.10.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.19.name=TriggerPort10[19] -unit.2.0.port.10.s.19.orderindex=-1 -unit.2.0.port.10.s.19.visible=1 -unit.2.0.port.10.s.2.alias= -unit.2.0.port.10.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.2.name=TriggerPort10[2] -unit.2.0.port.10.s.2.orderindex=-1 -unit.2.0.port.10.s.2.visible=1 -unit.2.0.port.10.s.20.alias=ace_mpce_n_ -unit.2.0.port.10.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.20.name=TriggerPort10[20] -unit.2.0.port.10.s.20.orderindex=-1 -unit.2.0.port.10.s.20.visible=1 -unit.2.0.port.10.s.3.alias= -unit.2.0.port.10.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.3.name=TriggerPort10[3] -unit.2.0.port.10.s.3.orderindex=-1 -unit.2.0.port.10.s.3.visible=1 -unit.2.0.port.10.s.4.alias= -unit.2.0.port.10.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.4.name=TriggerPort10[4] -unit.2.0.port.10.s.4.orderindex=-1 -unit.2.0.port.10.s.4.visible=1 -unit.2.0.port.10.s.5.alias= -unit.2.0.port.10.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.5.name=TriggerPort10[5] -unit.2.0.port.10.s.5.orderindex=-1 -unit.2.0.port.10.s.5.visible=1 -unit.2.0.port.10.s.6.alias= -unit.2.0.port.10.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.6.name=TriggerPort10[6] -unit.2.0.port.10.s.6.orderindex=-1 -unit.2.0.port.10.s.6.visible=1 -unit.2.0.port.10.s.7.alias= -unit.2.0.port.10.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.7.name=TriggerPort10[7] -unit.2.0.port.10.s.7.orderindex=-1 -unit.2.0.port.10.s.7.visible=1 -unit.2.0.port.10.s.8.alias= -unit.2.0.port.10.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.8.name=TriggerPort10[8] -unit.2.0.port.10.s.8.orderindex=-1 -unit.2.0.port.10.s.8.visible=1 -unit.2.0.port.10.s.9.alias= -unit.2.0.port.10.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.10.s.9.name=TriggerPort10[9] -unit.2.0.port.10.s.9.orderindex=-1 -unit.2.0.port.10.s.9.visible=1 -unit.2.0.port.11.b.0.alias= -unit.2.0.port.11.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.2.0.port.11.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.b.0.name=TriggerPort11 -unit.2.0.port.11.b.0.orderindex=-1 -unit.2.0.port.11.b.0.radix=Hex -unit.2.0.port.11.b.0.signedOffset=0.0 -unit.2.0.port.11.b.0.signedPrecision=0 -unit.2.0.port.11.b.0.signedScaleFactor=1.0 -unit.2.0.port.11.b.0.unsignedOffset=0.0 -unit.2.0.port.11.b.0.unsignedPrecision=0 -unit.2.0.port.11.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.11.b.0.visible=1 -unit.2.0.port.11.buscount=1 -unit.2.0.port.11.channelcount=16 -unit.2.0.port.11.s.0.alias=DataPort[191] -unit.2.0.port.11.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.0.name=TriggerPort11[0] -unit.2.0.port.11.s.0.orderindex=-1 -unit.2.0.port.11.s.0.visible=1 -unit.2.0.port.11.s.1.alias= -unit.2.0.port.11.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.1.name=TriggerPort11[1] -unit.2.0.port.11.s.1.orderindex=-1 -unit.2.0.port.11.s.1.visible=1 -unit.2.0.port.11.s.10.alias= -unit.2.0.port.11.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.10.name=TriggerPort11[10] -unit.2.0.port.11.s.10.orderindex=-1 -unit.2.0.port.11.s.10.visible=1 -unit.2.0.port.11.s.11.alias= -unit.2.0.port.11.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.11.name=TriggerPort11[11] -unit.2.0.port.11.s.11.orderindex=-1 -unit.2.0.port.11.s.11.visible=1 -unit.2.0.port.11.s.12.alias= -unit.2.0.port.11.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.12.name=TriggerPort11[12] -unit.2.0.port.11.s.12.orderindex=-1 -unit.2.0.port.11.s.12.visible=1 -unit.2.0.port.11.s.13.alias= -unit.2.0.port.11.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.13.name=TriggerPort11[13] -unit.2.0.port.11.s.13.orderindex=-1 -unit.2.0.port.11.s.13.visible=1 -unit.2.0.port.11.s.14.alias= -unit.2.0.port.11.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.14.name=TriggerPort11[14] -unit.2.0.port.11.s.14.orderindex=-1 -unit.2.0.port.11.s.14.visible=1 -unit.2.0.port.11.s.15.alias= -unit.2.0.port.11.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.15.name=TriggerPort11[15] -unit.2.0.port.11.s.15.orderindex=-1 -unit.2.0.port.11.s.15.visible=1 -unit.2.0.port.11.s.2.alias= -unit.2.0.port.11.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.2.name=TriggerPort11[2] -unit.2.0.port.11.s.2.orderindex=-1 -unit.2.0.port.11.s.2.visible=1 -unit.2.0.port.11.s.3.alias= -unit.2.0.port.11.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.3.name=TriggerPort11[3] -unit.2.0.port.11.s.3.orderindex=-1 -unit.2.0.port.11.s.3.visible=1 -unit.2.0.port.11.s.4.alias= -unit.2.0.port.11.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.4.name=TriggerPort11[4] -unit.2.0.port.11.s.4.orderindex=-1 -unit.2.0.port.11.s.4.visible=1 -unit.2.0.port.11.s.5.alias= -unit.2.0.port.11.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.5.name=TriggerPort11[5] -unit.2.0.port.11.s.5.orderindex=-1 -unit.2.0.port.11.s.5.visible=1 -unit.2.0.port.11.s.6.alias= -unit.2.0.port.11.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.6.name=TriggerPort11[6] -unit.2.0.port.11.s.6.orderindex=-1 -unit.2.0.port.11.s.6.visible=1 -unit.2.0.port.11.s.7.alias= -unit.2.0.port.11.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.7.name=TriggerPort11[7] -unit.2.0.port.11.s.7.orderindex=-1 -unit.2.0.port.11.s.7.visible=1 -unit.2.0.port.11.s.8.alias= -unit.2.0.port.11.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.8.name=TriggerPort11[8] -unit.2.0.port.11.s.8.orderindex=-1 -unit.2.0.port.11.s.8.visible=1 -unit.2.0.port.11.s.9.alias= -unit.2.0.port.11.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.11.s.9.name=TriggerPort11[9] -unit.2.0.port.11.s.9.orderindex=-1 -unit.2.0.port.11.s.9.visible=1 -unit.2.0.port.12.b.0.alias= -unit.2.0.port.12.b.0.channellist=0 1 2 3 4 5 6 7 8 -unit.2.0.port.12.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.b.0.name=TriggerPort12 -unit.2.0.port.12.b.0.orderindex=-1 -unit.2.0.port.12.b.0.radix=Hex -unit.2.0.port.12.b.0.signedOffset=0.0 -unit.2.0.port.12.b.0.signedPrecision=0 -unit.2.0.port.12.b.0.signedScaleFactor=1.0 -unit.2.0.port.12.b.0.unsignedOffset=0.0 -unit.2.0.port.12.b.0.unsignedPrecision=0 -unit.2.0.port.12.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.12.b.0.visible=1 -unit.2.0.port.12.buscount=1 -unit.2.0.port.12.channelcount=9 -unit.2.0.port.12.s.0.alias=iid -unit.2.0.port.12.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.0.name=TriggerPort12[0] -unit.2.0.port.12.s.0.orderindex=-1 -unit.2.0.port.12.s.0.visible=1 -unit.2.0.port.12.s.1.alias=irr0 -unit.2.0.port.12.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.1.name=TriggerPort12[1] -unit.2.0.port.12.s.1.orderindex=-1 -unit.2.0.port.12.s.1.visible=1 -unit.2.0.port.12.s.2.alias=irr1 -unit.2.0.port.12.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.2.name=TriggerPort12[2] -unit.2.0.port.12.s.2.orderindex=-1 -unit.2.0.port.12.s.2.visible=1 -unit.2.0.port.12.s.3.alias=int0 -unit.2.0.port.12.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.3.name=TriggerPort12[3] -unit.2.0.port.12.s.3.orderindex=-1 -unit.2.0.port.12.s.3.visible=1 -unit.2.0.port.12.s.4.alias=int1 -unit.2.0.port.12.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.4.name=TriggerPort12[4] -unit.2.0.port.12.s.4.orderindex=-1 -unit.2.0.port.12.s.4.visible=1 -unit.2.0.port.12.s.5.alias=released -unit.2.0.port.12.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.5.name=TriggerPort12[5] -unit.2.0.port.12.s.5.orderindex=-1 -unit.2.0.port.12.s.5.visible=1 -unit.2.0.port.12.s.6.alias=rx_shift -unit.2.0.port.12.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.6.name=TriggerPort12[6] -unit.2.0.port.12.s.6.orderindex=-1 -unit.2.0.port.12.s.6.visible=1 -unit.2.0.port.12.s.7.alias=rx_output -unit.2.0.port.12.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.7.name=TriggerPort12[7] -unit.2.0.port.12.s.7.orderindex=-1 -unit.2.0.port.12.s.7.visible=1 -unit.2.0.port.12.s.8.alias=nada -unit.2.0.port.12.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.12.s.8.name=TriggerPort12[8] -unit.2.0.port.12.s.8.orderindex=-1 -unit.2.0.port.12.s.8.visible=1 -unit.2.0.port.13.b.0.alias= -unit.2.0.port.13.b.0.channellist=0 1 2 -unit.2.0.port.13.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.13.b.0.name=TriggerPort13 -unit.2.0.port.13.b.0.orderindex=-1 -unit.2.0.port.13.b.0.radix=Hex -unit.2.0.port.13.b.0.signedOffset=0.0 -unit.2.0.port.13.b.0.signedPrecision=0 -unit.2.0.port.13.b.0.signedScaleFactor=1.0 -unit.2.0.port.13.b.0.unsignedOffset=0.0 -unit.2.0.port.13.b.0.unsignedPrecision=0 -unit.2.0.port.13.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.13.b.0.visible=1 -unit.2.0.port.13.buscount=1 -unit.2.0.port.13.channelcount=3 -unit.2.0.port.13.s.0.alias=DataPort[216] -unit.2.0.port.13.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.13.s.0.name=TriggerPort13[0] -unit.2.0.port.13.s.0.orderindex=-1 -unit.2.0.port.13.s.0.visible=1 -unit.2.0.port.13.s.1.alias= -unit.2.0.port.13.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.13.s.1.name=TriggerPort13[1] -unit.2.0.port.13.s.1.orderindex=-1 -unit.2.0.port.13.s.1.visible=1 -unit.2.0.port.13.s.2.alias= -unit.2.0.port.13.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.13.s.2.name=TriggerPort13[2] -unit.2.0.port.13.s.2.orderindex=-1 -unit.2.0.port.13.s.2.visible=1 -unit.2.0.port.14.b.0.alias= -unit.2.0.port.14.b.0.channellist=0 1 2 3 4 -unit.2.0.port.14.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.b.0.name=TriggerPort14 -unit.2.0.port.14.b.0.orderindex=-1 -unit.2.0.port.14.b.0.radix=Hex -unit.2.0.port.14.b.0.signedOffset=0.0 -unit.2.0.port.14.b.0.signedPrecision=0 -unit.2.0.port.14.b.0.signedScaleFactor=1.0 -unit.2.0.port.14.b.0.unsignedOffset=0.0 -unit.2.0.port.14.b.0.unsignedPrecision=0 -unit.2.0.port.14.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.14.b.0.visible=1 -unit.2.0.port.14.buscount=1 -unit.2.0.port.14.channelcount=5 -unit.2.0.port.14.s.0.alias=op -unit.2.0.port.14.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.s.0.name=TriggerPort14[0] -unit.2.0.port.14.s.0.orderindex=-1 -unit.2.0.port.14.s.0.visible=1 -unit.2.0.port.14.s.1.alias=zbt_stb -unit.2.0.port.14.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.s.1.name=TriggerPort14[1] -unit.2.0.port.14.s.1.orderindex=-1 -unit.2.0.port.14.s.1.visible=1 -unit.2.0.port.14.s.2.alias=flash_stb -unit.2.0.port.14.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.s.2.name=TriggerPort14[2] -unit.2.0.port.14.s.2.orderindex=-1 -unit.2.0.port.14.s.2.visible=1 -unit.2.0.port.14.s.3.alias=flash_arena -unit.2.0.port.14.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.s.3.name=TriggerPort14[3] -unit.2.0.port.14.s.3.orderindex=-1 -unit.2.0.port.14.s.3.visible=1 -unit.2.0.port.14.s.4.alias=vdu_arena -unit.2.0.port.14.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.14.s.4.name=TriggerPort14[4] -unit.2.0.port.14.s.4.orderindex=-1 -unit.2.0.port.14.s.4.visible=1 -unit.2.0.port.15.b.0.alias= -unit.2.0.port.15.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.2.0.port.15.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.b.0.name=TriggerPort15 -unit.2.0.port.15.b.0.orderindex=-1 -unit.2.0.port.15.b.0.radix=Hex -unit.2.0.port.15.b.0.signedOffset=0.0 -unit.2.0.port.15.b.0.signedPrecision=0 -unit.2.0.port.15.b.0.signedScaleFactor=1.0 -unit.2.0.port.15.b.0.unsignedOffset=0.0 -unit.2.0.port.15.b.0.unsignedPrecision=0 -unit.2.0.port.15.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.15.b.0.visible=1 -unit.2.0.port.15.buscount=1 -unit.2.0.port.15.channelcount=32 -unit.2.0.port.15.s.0.alias=cnt_time0 -unit.2.0.port.15.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.0.name=TriggerPort15[0] -unit.2.0.port.15.s.0.orderindex=-1 -unit.2.0.port.15.s.0.visible=1 -unit.2.0.port.15.s.1.alias=cnt_time1 -unit.2.0.port.15.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.1.name=TriggerPort15[1] -unit.2.0.port.15.s.1.orderindex=-1 -unit.2.0.port.15.s.1.visible=1 -unit.2.0.port.15.s.10.alias= -unit.2.0.port.15.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.10.name=TriggerPort15[10] -unit.2.0.port.15.s.10.orderindex=-1 -unit.2.0.port.15.s.10.visible=1 -unit.2.0.port.15.s.11.alias= -unit.2.0.port.15.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.11.name=TriggerPort15[11] -unit.2.0.port.15.s.11.orderindex=-1 -unit.2.0.port.15.s.11.visible=1 -unit.2.0.port.15.s.12.alias= -unit.2.0.port.15.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.12.name=TriggerPort15[12] -unit.2.0.port.15.s.12.orderindex=-1 -unit.2.0.port.15.s.12.visible=1 -unit.2.0.port.15.s.13.alias= -unit.2.0.port.15.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.13.name=TriggerPort15[13] -unit.2.0.port.15.s.13.orderindex=-1 -unit.2.0.port.15.s.13.visible=1 -unit.2.0.port.15.s.14.alias= -unit.2.0.port.15.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.14.name=TriggerPort15[14] -unit.2.0.port.15.s.14.orderindex=-1 -unit.2.0.port.15.s.14.visible=1 -unit.2.0.port.15.s.15.alias= -unit.2.0.port.15.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.15.name=TriggerPort15[15] -unit.2.0.port.15.s.15.orderindex=-1 -unit.2.0.port.15.s.15.visible=1 -unit.2.0.port.15.s.16.alias= -unit.2.0.port.15.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.16.name=TriggerPort15[16] -unit.2.0.port.15.s.16.orderindex=-1 -unit.2.0.port.15.s.16.visible=1 -unit.2.0.port.15.s.17.alias= -unit.2.0.port.15.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.17.name=TriggerPort15[17] -unit.2.0.port.15.s.17.orderindex=-1 -unit.2.0.port.15.s.17.visible=1 -unit.2.0.port.15.s.18.alias= -unit.2.0.port.15.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.18.name=TriggerPort15[18] -unit.2.0.port.15.s.18.orderindex=-1 -unit.2.0.port.15.s.18.visible=1 -unit.2.0.port.15.s.19.alias= -unit.2.0.port.15.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.19.name=TriggerPort15[19] -unit.2.0.port.15.s.19.orderindex=-1 -unit.2.0.port.15.s.19.visible=1 -unit.2.0.port.15.s.2.alias=cnt_time2 -unit.2.0.port.15.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.2.name=TriggerPort15[2] -unit.2.0.port.15.s.2.orderindex=-1 -unit.2.0.port.15.s.2.visible=1 -unit.2.0.port.15.s.20.alias= -unit.2.0.port.15.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.20.name=TriggerPort15[20] -unit.2.0.port.15.s.20.orderindex=-1 -unit.2.0.port.15.s.20.visible=1 -unit.2.0.port.15.s.21.alias= -unit.2.0.port.15.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.21.name=TriggerPort15[21] -unit.2.0.port.15.s.21.orderindex=-1 -unit.2.0.port.15.s.21.visible=1 -unit.2.0.port.15.s.22.alias= -unit.2.0.port.15.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.22.name=TriggerPort15[22] -unit.2.0.port.15.s.22.orderindex=-1 -unit.2.0.port.15.s.22.visible=1 -unit.2.0.port.15.s.23.alias= -unit.2.0.port.15.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.23.name=TriggerPort15[23] -unit.2.0.port.15.s.23.orderindex=-1 -unit.2.0.port.15.s.23.visible=1 -unit.2.0.port.15.s.24.alias= -unit.2.0.port.15.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.24.name=TriggerPort15[24] -unit.2.0.port.15.s.24.orderindex=-1 -unit.2.0.port.15.s.24.visible=1 -unit.2.0.port.15.s.25.alias= -unit.2.0.port.15.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.25.name=TriggerPort15[25] -unit.2.0.port.15.s.25.orderindex=-1 -unit.2.0.port.15.s.25.visible=1 -unit.2.0.port.15.s.26.alias= -unit.2.0.port.15.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.26.name=TriggerPort15[26] -unit.2.0.port.15.s.26.orderindex=-1 -unit.2.0.port.15.s.26.visible=1 -unit.2.0.port.15.s.27.alias= -unit.2.0.port.15.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.27.name=TriggerPort15[27] -unit.2.0.port.15.s.27.orderindex=-1 -unit.2.0.port.15.s.27.visible=1 -unit.2.0.port.15.s.28.alias= -unit.2.0.port.15.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.28.name=TriggerPort15[28] -unit.2.0.port.15.s.28.orderindex=-1 -unit.2.0.port.15.s.28.visible=1 -unit.2.0.port.15.s.29.alias= -unit.2.0.port.15.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.29.name=TriggerPort15[29] -unit.2.0.port.15.s.29.orderindex=-1 -unit.2.0.port.15.s.29.visible=1 -unit.2.0.port.15.s.3.alias=cnt_time3 -unit.2.0.port.15.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.3.name=TriggerPort15[3] -unit.2.0.port.15.s.3.orderindex=-1 -unit.2.0.port.15.s.3.visible=1 -unit.2.0.port.15.s.30.alias= -unit.2.0.port.15.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.30.name=TriggerPort15[30] -unit.2.0.port.15.s.30.orderindex=-1 -unit.2.0.port.15.s.30.visible=1 -unit.2.0.port.15.s.31.alias= -unit.2.0.port.15.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.31.name=TriggerPort15[31] -unit.2.0.port.15.s.31.orderindex=-1 -unit.2.0.port.15.s.31.visible=1 -unit.2.0.port.15.s.4.alias=cnt_time4 -unit.2.0.port.15.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.4.name=TriggerPort15[4] -unit.2.0.port.15.s.4.orderindex=-1 -unit.2.0.port.15.s.4.visible=1 -unit.2.0.port.15.s.5.alias=DataPort[229] -unit.2.0.port.15.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.5.name=TriggerPort15[5] -unit.2.0.port.15.s.5.orderindex=-1 -unit.2.0.port.15.s.5.visible=1 -unit.2.0.port.15.s.6.alias= -unit.2.0.port.15.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.6.name=TriggerPort15[6] -unit.2.0.port.15.s.6.orderindex=-1 -unit.2.0.port.15.s.6.visible=1 -unit.2.0.port.15.s.7.alias= -unit.2.0.port.15.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.7.name=TriggerPort15[7] -unit.2.0.port.15.s.7.orderindex=-1 -unit.2.0.port.15.s.7.visible=1 -unit.2.0.port.15.s.8.alias= -unit.2.0.port.15.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.8.name=TriggerPort15[8] -unit.2.0.port.15.s.8.orderindex=-1 -unit.2.0.port.15.s.8.visible=1 -unit.2.0.port.15.s.9.alias= -unit.2.0.port.15.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.15.s.9.name=TriggerPort15[9] -unit.2.0.port.15.s.9.orderindex=-1 -unit.2.0.port.15.s.9.visible=1 -unit.2.0.port.2.b.0.alias= -unit.2.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 -unit.2.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.b.0.name=TriggerPort2 -unit.2.0.port.2.b.0.orderindex=-1 -unit.2.0.port.2.b.0.radix=Hex -unit.2.0.port.2.b.0.signedOffset=0.0 -unit.2.0.port.2.b.0.signedPrecision=0 -unit.2.0.port.2.b.0.signedScaleFactor=1.0 -unit.2.0.port.2.b.0.unsignedOffset=0.0 -unit.2.0.port.2.b.0.unsignedPrecision=0 -unit.2.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.2.b.0.visible=1 -unit.2.0.port.2.buscount=1 -unit.2.0.port.2.channelcount=20 -unit.2.0.port.2.s.0.alias= -unit.2.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.0.name=TriggerPort2[0] -unit.2.0.port.2.s.0.orderindex=-1 -unit.2.0.port.2.s.0.visible=1 -unit.2.0.port.2.s.1.alias= -unit.2.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.1.name=TriggerPort2[1] -unit.2.0.port.2.s.1.orderindex=-1 -unit.2.0.port.2.s.1.visible=1 -unit.2.0.port.2.s.10.alias= -unit.2.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.10.name=TriggerPort2[10] -unit.2.0.port.2.s.10.orderindex=-1 -unit.2.0.port.2.s.10.visible=1 -unit.2.0.port.2.s.11.alias= -unit.2.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.11.name=TriggerPort2[11] -unit.2.0.port.2.s.11.orderindex=-1 -unit.2.0.port.2.s.11.visible=1 -unit.2.0.port.2.s.12.alias= -unit.2.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.12.name=TriggerPort2[12] -unit.2.0.port.2.s.12.orderindex=-1 -unit.2.0.port.2.s.12.visible=1 -unit.2.0.port.2.s.13.alias= -unit.2.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.13.name=TriggerPort2[13] -unit.2.0.port.2.s.13.orderindex=-1 -unit.2.0.port.2.s.13.visible=1 -unit.2.0.port.2.s.14.alias= -unit.2.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.14.name=TriggerPort2[14] -unit.2.0.port.2.s.14.orderindex=-1 -unit.2.0.port.2.s.14.visible=1 -unit.2.0.port.2.s.15.alias= -unit.2.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.15.name=TriggerPort2[15] -unit.2.0.port.2.s.15.orderindex=-1 -unit.2.0.port.2.s.15.visible=1 -unit.2.0.port.2.s.16.alias= -unit.2.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.16.name=TriggerPort2[16] -unit.2.0.port.2.s.16.orderindex=-1 -unit.2.0.port.2.s.16.visible=1 -unit.2.0.port.2.s.17.alias= -unit.2.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.17.name=TriggerPort2[17] -unit.2.0.port.2.s.17.orderindex=-1 -unit.2.0.port.2.s.17.visible=1 -unit.2.0.port.2.s.18.alias= -unit.2.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.18.name=TriggerPort2[18] -unit.2.0.port.2.s.18.orderindex=-1 -unit.2.0.port.2.s.18.visible=1 -unit.2.0.port.2.s.19.alias= -unit.2.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.19.name=TriggerPort2[19] -unit.2.0.port.2.s.19.orderindex=-1 -unit.2.0.port.2.s.19.visible=1 -unit.2.0.port.2.s.2.alias= -unit.2.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.2.name=TriggerPort2[2] -unit.2.0.port.2.s.2.orderindex=-1 -unit.2.0.port.2.s.2.visible=1 -unit.2.0.port.2.s.3.alias= -unit.2.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.3.name=TriggerPort2[3] -unit.2.0.port.2.s.3.orderindex=-1 -unit.2.0.port.2.s.3.visible=1 -unit.2.0.port.2.s.4.alias= -unit.2.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.4.name=TriggerPort2[4] -unit.2.0.port.2.s.4.orderindex=-1 -unit.2.0.port.2.s.4.visible=1 -unit.2.0.port.2.s.5.alias= -unit.2.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.5.name=TriggerPort2[5] -unit.2.0.port.2.s.5.orderindex=-1 -unit.2.0.port.2.s.5.visible=1 -unit.2.0.port.2.s.6.alias= -unit.2.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.6.name=TriggerPort2[6] -unit.2.0.port.2.s.6.orderindex=-1 -unit.2.0.port.2.s.6.visible=1 -unit.2.0.port.2.s.7.alias= -unit.2.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.7.name=TriggerPort2[7] -unit.2.0.port.2.s.7.orderindex=-1 -unit.2.0.port.2.s.7.visible=1 -unit.2.0.port.2.s.8.alias= -unit.2.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.8.name=TriggerPort2[8] -unit.2.0.port.2.s.8.orderindex=-1 -unit.2.0.port.2.s.8.visible=1 -unit.2.0.port.2.s.9.alias= -unit.2.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.2.s.9.name=TriggerPort2[9] -unit.2.0.port.2.s.9.orderindex=-1 -unit.2.0.port.2.s.9.visible=1 -unit.2.0.port.3.b.0.alias= -unit.2.0.port.3.b.0.channellist=0 1 2 3 4 5 -unit.2.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.b.0.name=TriggerPort3 -unit.2.0.port.3.b.0.orderindex=-1 -unit.2.0.port.3.b.0.radix=Hex -unit.2.0.port.3.b.0.signedOffset=0.0 -unit.2.0.port.3.b.0.signedPrecision=0 -unit.2.0.port.3.b.0.signedScaleFactor=1.0 -unit.2.0.port.3.b.0.unsignedOffset=0.0 -unit.2.0.port.3.b.0.unsignedPrecision=0 -unit.2.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.3.b.0.visible=1 -unit.2.0.port.3.buscount=1 -unit.2.0.port.3.channelcount=6 -unit.2.0.port.3.s.0.alias=ack -unit.2.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.0.name=TriggerPort3[0] -unit.2.0.port.3.s.0.orderindex=-1 -unit.2.0.port.3.s.0.visible=1 -unit.2.0.port.3.s.1.alias=stb -unit.2.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.1.name=TriggerPort3[1] -unit.2.0.port.3.s.1.orderindex=-1 -unit.2.0.port.3.s.1.visible=1 -unit.2.0.port.3.s.2.alias=cyc -unit.2.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.2.name=TriggerPort3[2] -unit.2.0.port.3.s.2.orderindex=-1 -unit.2.0.port.3.s.2.visible=1 -unit.2.0.port.3.s.3.alias=tga -unit.2.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.3.name=TriggerPort3[3] -unit.2.0.port.3.s.3.orderindex=-1 -unit.2.0.port.3.s.3.visible=1 -unit.2.0.port.3.s.4.alias=we -unit.2.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.4.name=TriggerPort3[4] -unit.2.0.port.3.s.4.orderindex=-1 -unit.2.0.port.3.s.4.visible=1 -unit.2.0.port.3.s.5.alias=clk -unit.2.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.3.s.5.name=TriggerPort3[5] -unit.2.0.port.3.s.5.orderindex=-1 -unit.2.0.port.3.s.5.visible=1 -unit.2.0.port.4.b.0.alias= -unit.2.0.port.4.b.0.channellist=0 1 2 3 4 5 -unit.2.0.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.b.0.name=TriggerPort4 -unit.2.0.port.4.b.0.orderindex=-1 -unit.2.0.port.4.b.0.radix=Hex -unit.2.0.port.4.b.0.signedOffset=0.0 -unit.2.0.port.4.b.0.signedPrecision=0 -unit.2.0.port.4.b.0.signedScaleFactor=1.0 -unit.2.0.port.4.b.0.unsignedOffset=0.0 -unit.2.0.port.4.b.0.unsignedPrecision=0 -unit.2.0.port.4.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.4.b.0.visible=1 -unit.2.0.port.4.buscount=1 -unit.2.0.port.4.channelcount=6 -unit.2.0.port.4.s.0.alias=DataPort[78] -unit.2.0.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.0.name=TriggerPort4[0] -unit.2.0.port.4.s.0.orderindex=-1 -unit.2.0.port.4.s.0.visible=1 -unit.2.0.port.4.s.1.alias= -unit.2.0.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.1.name=TriggerPort4[1] -unit.2.0.port.4.s.1.orderindex=-1 -unit.2.0.port.4.s.1.visible=1 -unit.2.0.port.4.s.10.alias= -unit.2.0.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.10.name=TriggerPort4[10] -unit.2.0.port.4.s.10.orderindex=-1 -unit.2.0.port.4.s.10.visible=1 -unit.2.0.port.4.s.11.alias= -unit.2.0.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.11.name=TriggerPort4[11] -unit.2.0.port.4.s.11.orderindex=-1 -unit.2.0.port.4.s.11.visible=1 -unit.2.0.port.4.s.12.alias= -unit.2.0.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.12.name=TriggerPort4[12] -unit.2.0.port.4.s.12.orderindex=-1 -unit.2.0.port.4.s.12.visible=1 -unit.2.0.port.4.s.13.alias= -unit.2.0.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.13.name=TriggerPort4[13] -unit.2.0.port.4.s.13.orderindex=-1 -unit.2.0.port.4.s.13.visible=1 -unit.2.0.port.4.s.14.alias= -unit.2.0.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.14.name=TriggerPort4[14] -unit.2.0.port.4.s.14.orderindex=-1 -unit.2.0.port.4.s.14.visible=1 -unit.2.0.port.4.s.15.alias= -unit.2.0.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.15.name=TriggerPort4[15] -unit.2.0.port.4.s.15.orderindex=-1 -unit.2.0.port.4.s.15.visible=1 -unit.2.0.port.4.s.2.alias= -unit.2.0.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.2.name=TriggerPort4[2] -unit.2.0.port.4.s.2.orderindex=-1 -unit.2.0.port.4.s.2.visible=1 -unit.2.0.port.4.s.3.alias= -unit.2.0.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.3.name=TriggerPort4[3] -unit.2.0.port.4.s.3.orderindex=-1 -unit.2.0.port.4.s.3.visible=1 -unit.2.0.port.4.s.4.alias= -unit.2.0.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.4.name=TriggerPort4[4] -unit.2.0.port.4.s.4.orderindex=-1 -unit.2.0.port.4.s.4.visible=1 -unit.2.0.port.4.s.5.alias= -unit.2.0.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.5.name=TriggerPort4[5] -unit.2.0.port.4.s.5.orderindex=-1 -unit.2.0.port.4.s.5.visible=1 -unit.2.0.port.4.s.6.alias= -unit.2.0.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.6.name=TriggerPort4[6] -unit.2.0.port.4.s.6.orderindex=-1 -unit.2.0.port.4.s.6.visible=1 -unit.2.0.port.4.s.7.alias= -unit.2.0.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.7.name=TriggerPort4[7] -unit.2.0.port.4.s.7.orderindex=-1 -unit.2.0.port.4.s.7.visible=1 -unit.2.0.port.4.s.8.alias= -unit.2.0.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.8.name=TriggerPort4[8] -unit.2.0.port.4.s.8.orderindex=-1 -unit.2.0.port.4.s.8.visible=1 -unit.2.0.port.4.s.9.alias= -unit.2.0.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.4.s.9.name=TriggerPort4[9] -unit.2.0.port.4.s.9.orderindex=-1 -unit.2.0.port.4.s.9.visible=1 -unit.2.0.port.5.b.0.alias= -unit.2.0.port.5.b.0.channellist=0 1 2 3 4 5 -unit.2.0.port.5.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.b.0.name=TriggerPort5 -unit.2.0.port.5.b.0.orderindex=-1 -unit.2.0.port.5.b.0.radix=Hex -unit.2.0.port.5.b.0.signedOffset=0.0 -unit.2.0.port.5.b.0.signedPrecision=0 -unit.2.0.port.5.b.0.signedScaleFactor=1.0 -unit.2.0.port.5.b.0.unsignedOffset=0.0 -unit.2.0.port.5.b.0.unsignedPrecision=0 -unit.2.0.port.5.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.5.b.0.visible=1 -unit.2.0.port.5.buscount=1 -unit.2.0.port.5.channelcount=6 -unit.2.0.port.5.s.0.alias= -unit.2.0.port.5.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.0.name=TriggerPort5[0] -unit.2.0.port.5.s.0.orderindex=-1 -unit.2.0.port.5.s.0.visible=1 -unit.2.0.port.5.s.1.alias= -unit.2.0.port.5.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.1.name=TriggerPort5[1] -unit.2.0.port.5.s.1.orderindex=-1 -unit.2.0.port.5.s.1.visible=1 -unit.2.0.port.5.s.2.alias= -unit.2.0.port.5.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.2.name=TriggerPort5[2] -unit.2.0.port.5.s.2.orderindex=-1 -unit.2.0.port.5.s.2.visible=1 -unit.2.0.port.5.s.3.alias= -unit.2.0.port.5.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.3.name=TriggerPort5[3] -unit.2.0.port.5.s.3.orderindex=-1 -unit.2.0.port.5.s.3.visible=1 -unit.2.0.port.5.s.4.alias= -unit.2.0.port.5.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.4.name=TriggerPort5[4] -unit.2.0.port.5.s.4.orderindex=-1 -unit.2.0.port.5.s.4.visible=1 -unit.2.0.port.5.s.5.alias= -unit.2.0.port.5.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.5.s.5.name=TriggerPort5[5] -unit.2.0.port.5.s.5.orderindex=-1 -unit.2.0.port.5.s.5.visible=1 -unit.2.0.port.6.b.0.alias= -unit.2.0.port.6.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.2.0.port.6.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.b.0.name=TriggerPort6 -unit.2.0.port.6.b.0.orderindex=-1 -unit.2.0.port.6.b.0.radix=Hex -unit.2.0.port.6.b.0.signedOffset=0.0 -unit.2.0.port.6.b.0.signedPrecision=0 -unit.2.0.port.6.b.0.signedScaleFactor=1.0 -unit.2.0.port.6.b.0.unsignedOffset=0.0 -unit.2.0.port.6.b.0.unsignedPrecision=0 -unit.2.0.port.6.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.6.b.0.visible=1 -unit.2.0.port.6.buscount=1 -unit.2.0.port.6.channelcount=16 -unit.2.0.port.6.s.0.alias= -unit.2.0.port.6.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.0.name=TriggerPort6[0] -unit.2.0.port.6.s.0.orderindex=-1 -unit.2.0.port.6.s.0.visible=1 -unit.2.0.port.6.s.1.alias= -unit.2.0.port.6.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.1.name=TriggerPort6[1] -unit.2.0.port.6.s.1.orderindex=-1 -unit.2.0.port.6.s.1.visible=1 -unit.2.0.port.6.s.10.alias= -unit.2.0.port.6.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.10.name=TriggerPort6[10] -unit.2.0.port.6.s.10.orderindex=-1 -unit.2.0.port.6.s.10.visible=1 -unit.2.0.port.6.s.11.alias= -unit.2.0.port.6.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.11.name=TriggerPort6[11] -unit.2.0.port.6.s.11.orderindex=-1 -unit.2.0.port.6.s.11.visible=1 -unit.2.0.port.6.s.12.alias= -unit.2.0.port.6.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.12.name=TriggerPort6[12] -unit.2.0.port.6.s.12.orderindex=-1 -unit.2.0.port.6.s.12.visible=1 -unit.2.0.port.6.s.13.alias= -unit.2.0.port.6.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.13.name=TriggerPort6[13] -unit.2.0.port.6.s.13.orderindex=-1 -unit.2.0.port.6.s.13.visible=1 -unit.2.0.port.6.s.14.alias=inta -unit.2.0.port.6.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.14.name=TriggerPort6[14] -unit.2.0.port.6.s.14.orderindex=-1 -unit.2.0.port.6.s.14.visible=1 -unit.2.0.port.6.s.15.alias=intr -unit.2.0.port.6.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.15.name=TriggerPort6[15] -unit.2.0.port.6.s.15.orderindex=-1 -unit.2.0.port.6.s.15.visible=1 -unit.2.0.port.6.s.2.alias= -unit.2.0.port.6.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.2.name=TriggerPort6[2] -unit.2.0.port.6.s.2.orderindex=-1 -unit.2.0.port.6.s.2.visible=1 -unit.2.0.port.6.s.3.alias= -unit.2.0.port.6.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.3.name=TriggerPort6[3] -unit.2.0.port.6.s.3.orderindex=-1 -unit.2.0.port.6.s.3.visible=1 -unit.2.0.port.6.s.4.alias=byte_op -unit.2.0.port.6.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.4.name=TriggerPort6[4] -unit.2.0.port.6.s.4.orderindex=-1 -unit.2.0.port.6.s.4.visible=1 -unit.2.0.port.6.s.5.alias=DataPort[95] -unit.2.0.port.6.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.5.name=TriggerPort6[5] -unit.2.0.port.6.s.5.orderindex=-1 -unit.2.0.port.6.s.5.visible=1 -unit.2.0.port.6.s.6.alias= -unit.2.0.port.6.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.6.name=TriggerPort6[6] -unit.2.0.port.6.s.6.orderindex=-1 -unit.2.0.port.6.s.6.visible=1 -unit.2.0.port.6.s.7.alias= -unit.2.0.port.6.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.7.name=TriggerPort6[7] -unit.2.0.port.6.s.7.orderindex=-1 -unit.2.0.port.6.s.7.visible=1 -unit.2.0.port.6.s.8.alias= -unit.2.0.port.6.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.8.name=TriggerPort6[8] -unit.2.0.port.6.s.8.orderindex=-1 -unit.2.0.port.6.s.8.visible=1 -unit.2.0.port.6.s.9.alias= -unit.2.0.port.6.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.6.s.9.name=TriggerPort6[9] -unit.2.0.port.6.s.9.orderindex=-1 -unit.2.0.port.6.s.9.visible=1 -unit.2.0.port.7.b.0.alias= -unit.2.0.port.7.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.2.0.port.7.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.b.0.name=TriggerPort7 -unit.2.0.port.7.b.0.orderindex=-1 -unit.2.0.port.7.b.0.radix=Hex -unit.2.0.port.7.b.0.signedOffset=0.0 -unit.2.0.port.7.b.0.signedPrecision=0 -unit.2.0.port.7.b.0.signedScaleFactor=1.0 -unit.2.0.port.7.b.0.unsignedOffset=0.0 -unit.2.0.port.7.b.0.unsignedPrecision=0 -unit.2.0.port.7.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.7.b.0.visible=1 -unit.2.0.port.7.buscount=1 -unit.2.0.port.7.channelcount=16 -unit.2.0.port.7.s.0.alias=DataPort[106] -unit.2.0.port.7.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.0.name=TriggerPort7[0] -unit.2.0.port.7.s.0.orderindex=-1 -unit.2.0.port.7.s.0.visible=1 -unit.2.0.port.7.s.1.alias= -unit.2.0.port.7.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.1.name=TriggerPort7[1] -unit.2.0.port.7.s.1.orderindex=-1 -unit.2.0.port.7.s.1.visible=1 -unit.2.0.port.7.s.10.alias= -unit.2.0.port.7.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.10.name=TriggerPort7[10] -unit.2.0.port.7.s.10.orderindex=-1 -unit.2.0.port.7.s.10.visible=1 -unit.2.0.port.7.s.11.alias= -unit.2.0.port.7.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.11.name=TriggerPort7[11] -unit.2.0.port.7.s.11.orderindex=-1 -unit.2.0.port.7.s.11.visible=1 -unit.2.0.port.7.s.12.alias= -unit.2.0.port.7.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.12.name=TriggerPort7[12] -unit.2.0.port.7.s.12.orderindex=-1 -unit.2.0.port.7.s.12.visible=1 -unit.2.0.port.7.s.13.alias= -unit.2.0.port.7.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.13.name=TriggerPort7[13] -unit.2.0.port.7.s.13.orderindex=-1 -unit.2.0.port.7.s.13.visible=1 -unit.2.0.port.7.s.14.alias= -unit.2.0.port.7.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.14.name=TriggerPort7[14] -unit.2.0.port.7.s.14.orderindex=-1 -unit.2.0.port.7.s.14.visible=1 -unit.2.0.port.7.s.15.alias= -unit.2.0.port.7.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.15.name=TriggerPort7[15] -unit.2.0.port.7.s.15.orderindex=-1 -unit.2.0.port.7.s.15.visible=1 -unit.2.0.port.7.s.2.alias= -unit.2.0.port.7.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.2.name=TriggerPort7[2] -unit.2.0.port.7.s.2.orderindex=-1 -unit.2.0.port.7.s.2.visible=1 -unit.2.0.port.7.s.3.alias= -unit.2.0.port.7.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.3.name=TriggerPort7[3] -unit.2.0.port.7.s.3.orderindex=-1 -unit.2.0.port.7.s.3.visible=1 -unit.2.0.port.7.s.4.alias= -unit.2.0.port.7.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.4.name=TriggerPort7[4] -unit.2.0.port.7.s.4.orderindex=-1 -unit.2.0.port.7.s.4.visible=1 -unit.2.0.port.7.s.5.alias= -unit.2.0.port.7.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.5.name=TriggerPort7[5] -unit.2.0.port.7.s.5.orderindex=-1 -unit.2.0.port.7.s.5.visible=1 -unit.2.0.port.7.s.6.alias= -unit.2.0.port.7.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.6.name=TriggerPort7[6] -unit.2.0.port.7.s.6.orderindex=-1 -unit.2.0.port.7.s.6.visible=1 -unit.2.0.port.7.s.7.alias= -unit.2.0.port.7.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.7.name=TriggerPort7[7] -unit.2.0.port.7.s.7.orderindex=-1 -unit.2.0.port.7.s.7.visible=1 -unit.2.0.port.7.s.8.alias= -unit.2.0.port.7.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.8.name=TriggerPort7[8] -unit.2.0.port.7.s.8.orderindex=-1 -unit.2.0.port.7.s.8.visible=1 -unit.2.0.port.7.s.9.alias= -unit.2.0.port.7.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.7.s.9.name=TriggerPort7[9] -unit.2.0.port.7.s.9.orderindex=-1 -unit.2.0.port.7.s.9.visible=1 -unit.2.0.port.8.b.0.alias= -unit.2.0.port.8.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.2.0.port.8.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.b.0.name=TriggerPort8 -unit.2.0.port.8.b.0.orderindex=-1 -unit.2.0.port.8.b.0.radix=Hex -unit.2.0.port.8.b.0.signedOffset=0.0 -unit.2.0.port.8.b.0.signedPrecision=0 -unit.2.0.port.8.b.0.signedScaleFactor=1.0 -unit.2.0.port.8.b.0.unsignedOffset=0.0 -unit.2.0.port.8.b.0.unsignedPrecision=0 -unit.2.0.port.8.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.8.b.0.visible=1 -unit.2.0.port.8.buscount=1 -unit.2.0.port.8.channelcount=32 -unit.2.0.port.8.s.0.alias= -unit.2.0.port.8.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.0.name=TriggerPort8[0] -unit.2.0.port.8.s.0.orderindex=-1 -unit.2.0.port.8.s.0.visible=1 -unit.2.0.port.8.s.1.alias= -unit.2.0.port.8.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.1.name=TriggerPort8[1] -unit.2.0.port.8.s.1.orderindex=-1 -unit.2.0.port.8.s.1.visible=1 -unit.2.0.port.8.s.10.alias= -unit.2.0.port.8.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.10.name=TriggerPort8[10] -unit.2.0.port.8.s.10.orderindex=-1 -unit.2.0.port.8.s.10.visible=1 -unit.2.0.port.8.s.11.alias= -unit.2.0.port.8.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.11.name=TriggerPort8[11] -unit.2.0.port.8.s.11.orderindex=-1 -unit.2.0.port.8.s.11.visible=1 -unit.2.0.port.8.s.12.alias= -unit.2.0.port.8.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.12.name=TriggerPort8[12] -unit.2.0.port.8.s.12.orderindex=-1 -unit.2.0.port.8.s.12.visible=1 -unit.2.0.port.8.s.13.alias= -unit.2.0.port.8.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.13.name=TriggerPort8[13] -unit.2.0.port.8.s.13.orderindex=-1 -unit.2.0.port.8.s.13.visible=1 -unit.2.0.port.8.s.14.alias= -unit.2.0.port.8.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.14.name=TriggerPort8[14] -unit.2.0.port.8.s.14.orderindex=-1 -unit.2.0.port.8.s.14.visible=1 -unit.2.0.port.8.s.15.alias= -unit.2.0.port.8.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.15.name=TriggerPort8[15] -unit.2.0.port.8.s.15.orderindex=-1 -unit.2.0.port.8.s.15.visible=1 -unit.2.0.port.8.s.16.alias= -unit.2.0.port.8.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.16.name=TriggerPort8[16] -unit.2.0.port.8.s.16.orderindex=-1 -unit.2.0.port.8.s.16.visible=1 -unit.2.0.port.8.s.17.alias= -unit.2.0.port.8.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.17.name=TriggerPort8[17] -unit.2.0.port.8.s.17.orderindex=-1 -unit.2.0.port.8.s.17.visible=1 -unit.2.0.port.8.s.18.alias= -unit.2.0.port.8.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.18.name=TriggerPort8[18] -unit.2.0.port.8.s.18.orderindex=-1 -unit.2.0.port.8.s.18.visible=1 -unit.2.0.port.8.s.19.alias= -unit.2.0.port.8.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.19.name=TriggerPort8[19] -unit.2.0.port.8.s.19.orderindex=-1 -unit.2.0.port.8.s.19.visible=1 -unit.2.0.port.8.s.2.alias= -unit.2.0.port.8.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.2.name=TriggerPort8[2] -unit.2.0.port.8.s.2.orderindex=-1 -unit.2.0.port.8.s.2.visible=1 -unit.2.0.port.8.s.20.alias= -unit.2.0.port.8.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.20.name=TriggerPort8[20] -unit.2.0.port.8.s.20.orderindex=-1 -unit.2.0.port.8.s.20.visible=1 -unit.2.0.port.8.s.21.alias= -unit.2.0.port.8.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.21.name=TriggerPort8[21] -unit.2.0.port.8.s.21.orderindex=-1 -unit.2.0.port.8.s.21.visible=1 -unit.2.0.port.8.s.22.alias= -unit.2.0.port.8.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.22.name=TriggerPort8[22] -unit.2.0.port.8.s.22.orderindex=-1 -unit.2.0.port.8.s.22.visible=1 -unit.2.0.port.8.s.23.alias= -unit.2.0.port.8.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.23.name=TriggerPort8[23] -unit.2.0.port.8.s.23.orderindex=-1 -unit.2.0.port.8.s.23.visible=1 -unit.2.0.port.8.s.24.alias= -unit.2.0.port.8.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.24.name=TriggerPort8[24] -unit.2.0.port.8.s.24.orderindex=-1 -unit.2.0.port.8.s.24.visible=1 -unit.2.0.port.8.s.25.alias= -unit.2.0.port.8.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.25.name=TriggerPort8[25] -unit.2.0.port.8.s.25.orderindex=-1 -unit.2.0.port.8.s.25.visible=1 -unit.2.0.port.8.s.26.alias= -unit.2.0.port.8.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.26.name=TriggerPort8[26] -unit.2.0.port.8.s.26.orderindex=-1 -unit.2.0.port.8.s.26.visible=1 -unit.2.0.port.8.s.27.alias= -unit.2.0.port.8.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.27.name=TriggerPort8[27] -unit.2.0.port.8.s.27.orderindex=-1 -unit.2.0.port.8.s.27.visible=1 -unit.2.0.port.8.s.28.alias= -unit.2.0.port.8.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.28.name=TriggerPort8[28] -unit.2.0.port.8.s.28.orderindex=-1 -unit.2.0.port.8.s.28.visible=1 -unit.2.0.port.8.s.29.alias= -unit.2.0.port.8.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.29.name=TriggerPort8[29] -unit.2.0.port.8.s.29.orderindex=-1 -unit.2.0.port.8.s.29.visible=1 -unit.2.0.port.8.s.3.alias= -unit.2.0.port.8.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.3.name=TriggerPort8[3] -unit.2.0.port.8.s.3.orderindex=-1 -unit.2.0.port.8.s.3.visible=1 -unit.2.0.port.8.s.30.alias= -unit.2.0.port.8.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.30.name=TriggerPort8[30] -unit.2.0.port.8.s.30.orderindex=-1 -unit.2.0.port.8.s.30.visible=1 -unit.2.0.port.8.s.31.alias= -unit.2.0.port.8.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.31.name=TriggerPort8[31] -unit.2.0.port.8.s.31.orderindex=-1 -unit.2.0.port.8.s.31.visible=1 -unit.2.0.port.8.s.4.alias= -unit.2.0.port.8.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.4.name=TriggerPort8[4] -unit.2.0.port.8.s.4.orderindex=-1 -unit.2.0.port.8.s.4.visible=1 -unit.2.0.port.8.s.5.alias= -unit.2.0.port.8.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.5.name=TriggerPort8[5] -unit.2.0.port.8.s.5.orderindex=-1 -unit.2.0.port.8.s.5.visible=1 -unit.2.0.port.8.s.6.alias= -unit.2.0.port.8.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.6.name=TriggerPort8[6] -unit.2.0.port.8.s.6.orderindex=-1 -unit.2.0.port.8.s.6.visible=1 -unit.2.0.port.8.s.7.alias= -unit.2.0.port.8.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.7.name=TriggerPort8[7] -unit.2.0.port.8.s.7.orderindex=-1 -unit.2.0.port.8.s.7.visible=1 -unit.2.0.port.8.s.8.alias= -unit.2.0.port.8.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.8.name=TriggerPort8[8] -unit.2.0.port.8.s.8.orderindex=-1 -unit.2.0.port.8.s.8.visible=1 -unit.2.0.port.8.s.9.alias= -unit.2.0.port.8.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.8.s.9.name=TriggerPort8[9] -unit.2.0.port.8.s.9.orderindex=-1 -unit.2.0.port.8.s.9.visible=1 -unit.2.0.port.9.b.0.alias= -unit.2.0.port.9.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.2.0.port.9.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.b.0.name=TriggerPort9 -unit.2.0.port.9.b.0.orderindex=-1 -unit.2.0.port.9.b.0.radix=Hex -unit.2.0.port.9.b.0.signedOffset=0.0 -unit.2.0.port.9.b.0.signedPrecision=0 -unit.2.0.port.9.b.0.signedScaleFactor=1.0 -unit.2.0.port.9.b.0.unsignedOffset=0.0 -unit.2.0.port.9.b.0.unsignedPrecision=0 -unit.2.0.port.9.b.0.unsignedScaleFactor=1.0 -unit.2.0.port.9.b.0.visible=1 -unit.2.0.port.9.buscount=1 -unit.2.0.port.9.channelcount=16 -unit.2.0.port.9.s.0.alias= -unit.2.0.port.9.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.0.name=TriggerPort9[0] -unit.2.0.port.9.s.0.orderindex=-1 -unit.2.0.port.9.s.0.visible=1 -unit.2.0.port.9.s.1.alias= -unit.2.0.port.9.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.1.name=TriggerPort9[1] -unit.2.0.port.9.s.1.orderindex=-1 -unit.2.0.port.9.s.1.visible=1 -unit.2.0.port.9.s.10.alias= -unit.2.0.port.9.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.10.name=TriggerPort9[10] -unit.2.0.port.9.s.10.orderindex=-1 -unit.2.0.port.9.s.10.visible=1 -unit.2.0.port.9.s.11.alias= -unit.2.0.port.9.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.11.name=TriggerPort9[11] -unit.2.0.port.9.s.11.orderindex=-1 -unit.2.0.port.9.s.11.visible=1 -unit.2.0.port.9.s.12.alias= -unit.2.0.port.9.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.12.name=TriggerPort9[12] -unit.2.0.port.9.s.12.orderindex=-1 -unit.2.0.port.9.s.12.visible=1 -unit.2.0.port.9.s.13.alias= -unit.2.0.port.9.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.13.name=TriggerPort9[13] -unit.2.0.port.9.s.13.orderindex=-1 -unit.2.0.port.9.s.13.visible=1 -unit.2.0.port.9.s.14.alias= -unit.2.0.port.9.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.14.name=TriggerPort9[14] -unit.2.0.port.9.s.14.orderindex=-1 -unit.2.0.port.9.s.14.visible=1 -unit.2.0.port.9.s.15.alias= -unit.2.0.port.9.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.15.name=TriggerPort9[15] -unit.2.0.port.9.s.15.orderindex=-1 -unit.2.0.port.9.s.15.visible=1 -unit.2.0.port.9.s.16.alias= -unit.2.0.port.9.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.16.name=TriggerPort9[16] -unit.2.0.port.9.s.16.orderindex=-1 -unit.2.0.port.9.s.16.visible=1 -unit.2.0.port.9.s.17.alias= -unit.2.0.port.9.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.17.name=TriggerPort9[17] -unit.2.0.port.9.s.17.orderindex=-1 -unit.2.0.port.9.s.17.visible=1 -unit.2.0.port.9.s.18.alias= -unit.2.0.port.9.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.18.name=TriggerPort9[18] -unit.2.0.port.9.s.18.orderindex=-1 -unit.2.0.port.9.s.18.visible=1 -unit.2.0.port.9.s.19.alias= -unit.2.0.port.9.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.19.name=TriggerPort9[19] -unit.2.0.port.9.s.19.orderindex=-1 -unit.2.0.port.9.s.19.visible=1 -unit.2.0.port.9.s.2.alias= -unit.2.0.port.9.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.2.name=TriggerPort9[2] -unit.2.0.port.9.s.2.orderindex=-1 -unit.2.0.port.9.s.2.visible=1 -unit.2.0.port.9.s.20.alias= -unit.2.0.port.9.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.20.name=TriggerPort9[20] -unit.2.0.port.9.s.20.orderindex=-1 -unit.2.0.port.9.s.20.visible=1 -unit.2.0.port.9.s.21.alias= -unit.2.0.port.9.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.21.name=TriggerPort9[21] -unit.2.0.port.9.s.21.orderindex=-1 -unit.2.0.port.9.s.21.visible=1 -unit.2.0.port.9.s.22.alias= -unit.2.0.port.9.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.22.name=TriggerPort9[22] -unit.2.0.port.9.s.22.orderindex=-1 -unit.2.0.port.9.s.22.visible=1 -unit.2.0.port.9.s.23.alias= -unit.2.0.port.9.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.23.name=TriggerPort9[23] -unit.2.0.port.9.s.23.orderindex=-1 -unit.2.0.port.9.s.23.visible=1 -unit.2.0.port.9.s.24.alias= -unit.2.0.port.9.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.24.name=TriggerPort9[24] -unit.2.0.port.9.s.24.orderindex=-1 -unit.2.0.port.9.s.24.visible=1 -unit.2.0.port.9.s.25.alias= -unit.2.0.port.9.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.25.name=TriggerPort9[25] -unit.2.0.port.9.s.25.orderindex=-1 -unit.2.0.port.9.s.25.visible=1 -unit.2.0.port.9.s.26.alias= -unit.2.0.port.9.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.26.name=TriggerPort9[26] -unit.2.0.port.9.s.26.orderindex=-1 -unit.2.0.port.9.s.26.visible=1 -unit.2.0.port.9.s.27.alias= -unit.2.0.port.9.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.27.name=TriggerPort9[27] -unit.2.0.port.9.s.27.orderindex=-1 -unit.2.0.port.9.s.27.visible=1 -unit.2.0.port.9.s.28.alias= -unit.2.0.port.9.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.28.name=TriggerPort9[28] -unit.2.0.port.9.s.28.orderindex=-1 -unit.2.0.port.9.s.28.visible=1 -unit.2.0.port.9.s.29.alias= -unit.2.0.port.9.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.29.name=TriggerPort9[29] -unit.2.0.port.9.s.29.orderindex=-1 -unit.2.0.port.9.s.29.visible=1 -unit.2.0.port.9.s.3.alias= -unit.2.0.port.9.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.3.name=TriggerPort9[3] -unit.2.0.port.9.s.3.orderindex=-1 -unit.2.0.port.9.s.3.visible=1 -unit.2.0.port.9.s.30.alias= -unit.2.0.port.9.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.30.name=TriggerPort9[30] -unit.2.0.port.9.s.30.orderindex=-1 -unit.2.0.port.9.s.30.visible=1 -unit.2.0.port.9.s.31.alias= -unit.2.0.port.9.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.31.name=TriggerPort9[31] -unit.2.0.port.9.s.31.orderindex=-1 -unit.2.0.port.9.s.31.visible=1 -unit.2.0.port.9.s.4.alias= -unit.2.0.port.9.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.4.name=TriggerPort9[4] -unit.2.0.port.9.s.4.orderindex=-1 -unit.2.0.port.9.s.4.visible=1 -unit.2.0.port.9.s.5.alias= -unit.2.0.port.9.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.5.name=TriggerPort9[5] -unit.2.0.port.9.s.5.orderindex=-1 -unit.2.0.port.9.s.5.visible=1 -unit.2.0.port.9.s.6.alias= -unit.2.0.port.9.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.6.name=TriggerPort9[6] -unit.2.0.port.9.s.6.orderindex=-1 -unit.2.0.port.9.s.6.visible=1 -unit.2.0.port.9.s.7.alias= -unit.2.0.port.9.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.7.name=TriggerPort9[7] -unit.2.0.port.9.s.7.orderindex=-1 -unit.2.0.port.9.s.7.visible=1 -unit.2.0.port.9.s.8.alias= -unit.2.0.port.9.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.8.name=TriggerPort9[8] -unit.2.0.port.9.s.8.orderindex=-1 -unit.2.0.port.9.s.8.visible=1 -unit.2.0.port.9.s.9.alias= -unit.2.0.port.9.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.2.0.port.9.s.9.name=TriggerPort9[9] -unit.2.0.port.9.s.9.orderindex=-1 -unit.2.0.port.9.s.9.visible=1 -unit.2.0.portcount=16 -unit.2.0.samplesPerTrigger=1 -unit.2.0.triggerCapture=1 -unit.2.0.triggerNSamplesTS=0 -unit.2.0.triggerPosition=0 -unit.2.0.triggerWindowCount=1 -unit.2.0.triggerWindowDepth=1024 -unit.2.0.triggerWindowTS=0 -unit.2.0.username=MyILA0 -unit.2.0.waveform.count=45 -unit.2.0.waveform.posn.0.channel=2147483646 -unit.2.0.waveform.posn.0.name=aluo -unit.2.0.waveform.posn.0.radix=1 -unit.2.0.waveform.posn.0.type=bus -unit.2.0.waveform.posn.1.channel=2147483646 -unit.2.0.waveform.posn.1.name=x -unit.2.0.waveform.posn.1.radix=1 -unit.2.0.waveform.posn.1.type=bus -unit.2.0.waveform.posn.10.channel=2147483646 -unit.2.0.waveform.posn.10.name=dat_i -unit.2.0.waveform.posn.10.radix=1 -unit.2.0.waveform.posn.10.type=bus -unit.2.0.waveform.posn.100.channel=2147483646 -unit.2.0.waveform.posn.100.name=x -unit.2.0.waveform.posn.100.radix=1 -unit.2.0.waveform.posn.100.type=bus -unit.2.0.waveform.posn.101.channel=2147483646 -unit.2.0.waveform.posn.101.name=x -unit.2.0.waveform.posn.101.radix=1 -unit.2.0.waveform.posn.101.type=bus -unit.2.0.waveform.posn.102.channel=2147483646 -unit.2.0.waveform.posn.102.name=x -unit.2.0.waveform.posn.102.radix=1 -unit.2.0.waveform.posn.102.type=bus -unit.2.0.waveform.posn.103.channel=2147483646 -unit.2.0.waveform.posn.103.name=x -unit.2.0.waveform.posn.103.radix=1 -unit.2.0.waveform.posn.103.type=bus -unit.2.0.waveform.posn.104.channel=2147483646 -unit.2.0.waveform.posn.104.name=x -unit.2.0.waveform.posn.104.radix=1 -unit.2.0.waveform.posn.104.type=bus -unit.2.0.waveform.posn.105.channel=2147483646 -unit.2.0.waveform.posn.105.name=x -unit.2.0.waveform.posn.105.radix=1 -unit.2.0.waveform.posn.105.type=bus -unit.2.0.waveform.posn.106.channel=2147483646 -unit.2.0.waveform.posn.106.name=x -unit.2.0.waveform.posn.106.radix=1 -unit.2.0.waveform.posn.106.type=bus -unit.2.0.waveform.posn.107.channel=2147483646 -unit.2.0.waveform.posn.107.name=x -unit.2.0.waveform.posn.107.radix=1 -unit.2.0.waveform.posn.107.type=bus -unit.2.0.waveform.posn.108.channel=2147483646 -unit.2.0.waveform.posn.108.name=x -unit.2.0.waveform.posn.108.radix=1 -unit.2.0.waveform.posn.108.type=bus -unit.2.0.waveform.posn.109.channel=2147483646 -unit.2.0.waveform.posn.109.name=x -unit.2.0.waveform.posn.109.radix=1 -unit.2.0.waveform.posn.109.type=bus -unit.2.0.waveform.posn.11.channel=2147483646 -unit.2.0.waveform.posn.11.name=dat_o -unit.2.0.waveform.posn.11.radix=1 -unit.2.0.waveform.posn.11.type=bus -unit.2.0.waveform.posn.110.channel=2147483646 -unit.2.0.waveform.posn.110.name=x -unit.2.0.waveform.posn.110.radix=1 -unit.2.0.waveform.posn.110.type=bus -unit.2.0.waveform.posn.111.channel=2147483646 -unit.2.0.waveform.posn.111.name=x -unit.2.0.waveform.posn.111.radix=1 -unit.2.0.waveform.posn.111.type=bus -unit.2.0.waveform.posn.112.channel=2147483646 -unit.2.0.waveform.posn.112.name=x -unit.2.0.waveform.posn.112.radix=1 -unit.2.0.waveform.posn.112.type=bus -unit.2.0.waveform.posn.113.channel=2147483646 -unit.2.0.waveform.posn.113.name=x -unit.2.0.waveform.posn.113.radix=1 -unit.2.0.waveform.posn.113.type=bus -unit.2.0.waveform.posn.114.channel=2147483646 -unit.2.0.waveform.posn.114.name=x -unit.2.0.waveform.posn.114.radix=1 -unit.2.0.waveform.posn.114.type=bus -unit.2.0.waveform.posn.115.channel=2147483646 -unit.2.0.waveform.posn.115.name=x -unit.2.0.waveform.posn.115.radix=1 -unit.2.0.waveform.posn.115.type=bus -unit.2.0.waveform.posn.116.channel=2147483646 -unit.2.0.waveform.posn.116.name=x -unit.2.0.waveform.posn.116.radix=1 -unit.2.0.waveform.posn.116.type=bus -unit.2.0.waveform.posn.117.channel=2147483646 -unit.2.0.waveform.posn.117.name=x -unit.2.0.waveform.posn.117.radix=1 -unit.2.0.waveform.posn.117.type=bus -unit.2.0.waveform.posn.118.channel=2147483646 -unit.2.0.waveform.posn.118.name=x -unit.2.0.waveform.posn.118.radix=1 -unit.2.0.waveform.posn.118.type=bus -unit.2.0.waveform.posn.119.channel=2147483646 -unit.2.0.waveform.posn.119.name=x -unit.2.0.waveform.posn.119.radix=1 -unit.2.0.waveform.posn.119.type=bus -unit.2.0.waveform.posn.12.channel=72 -unit.2.0.waveform.posn.12.name=ack -unit.2.0.waveform.posn.12.radix=1 -unit.2.0.waveform.posn.12.type=signal -unit.2.0.waveform.posn.120.channel=2147483646 -unit.2.0.waveform.posn.120.name=x -unit.2.0.waveform.posn.120.radix=1 -unit.2.0.waveform.posn.120.type=bus -unit.2.0.waveform.posn.121.channel=2147483646 -unit.2.0.waveform.posn.121.name=x -unit.2.0.waveform.posn.121.radix=1 -unit.2.0.waveform.posn.121.type=bus -unit.2.0.waveform.posn.122.channel=2147483646 -unit.2.0.waveform.posn.122.name=x -unit.2.0.waveform.posn.122.radix=1 -unit.2.0.waveform.posn.122.type=bus -unit.2.0.waveform.posn.123.channel=2147483646 -unit.2.0.waveform.posn.123.name=x -unit.2.0.waveform.posn.123.radix=1 -unit.2.0.waveform.posn.123.type=bus -unit.2.0.waveform.posn.124.channel=2147483646 -unit.2.0.waveform.posn.124.name=x -unit.2.0.waveform.posn.124.radix=1 -unit.2.0.waveform.posn.124.type=bus -unit.2.0.waveform.posn.125.channel=2147483646 -unit.2.0.waveform.posn.125.name=x -unit.2.0.waveform.posn.125.radix=1 -unit.2.0.waveform.posn.125.type=bus -unit.2.0.waveform.posn.126.channel=2147483646 -unit.2.0.waveform.posn.126.name=x -unit.2.0.waveform.posn.126.radix=1 -unit.2.0.waveform.posn.126.type=bus -unit.2.0.waveform.posn.127.channel=2147483646 -unit.2.0.waveform.posn.127.name=x -unit.2.0.waveform.posn.127.radix=1 -unit.2.0.waveform.posn.127.type=bus -unit.2.0.waveform.posn.128.channel=2147483646 -unit.2.0.waveform.posn.128.name=x -unit.2.0.waveform.posn.128.radix=1 -unit.2.0.waveform.posn.128.type=bus -unit.2.0.waveform.posn.129.channel=2147483646 -unit.2.0.waveform.posn.129.name=x -unit.2.0.waveform.posn.129.radix=1 -unit.2.0.waveform.posn.129.type=bus -unit.2.0.waveform.posn.13.channel=73 -unit.2.0.waveform.posn.13.name=stb -unit.2.0.waveform.posn.13.radix=1 -unit.2.0.waveform.posn.13.type=signal -unit.2.0.waveform.posn.130.channel=2147483646 -unit.2.0.waveform.posn.130.name=x -unit.2.0.waveform.posn.130.radix=1 -unit.2.0.waveform.posn.130.type=bus -unit.2.0.waveform.posn.131.channel=2147483646 -unit.2.0.waveform.posn.131.name=x -unit.2.0.waveform.posn.131.radix=1 -unit.2.0.waveform.posn.131.type=bus -unit.2.0.waveform.posn.132.channel=2147483646 -unit.2.0.waveform.posn.132.name=x -unit.2.0.waveform.posn.132.radix=1 -unit.2.0.waveform.posn.132.type=bus -unit.2.0.waveform.posn.133.channel=2147483646 -unit.2.0.waveform.posn.133.name=x -unit.2.0.waveform.posn.133.radix=1 -unit.2.0.waveform.posn.133.type=bus -unit.2.0.waveform.posn.134.channel=2147483646 -unit.2.0.waveform.posn.134.name=x -unit.2.0.waveform.posn.134.radix=1 -unit.2.0.waveform.posn.134.type=bus -unit.2.0.waveform.posn.135.channel=2147483646 -unit.2.0.waveform.posn.135.name=x -unit.2.0.waveform.posn.135.radix=1 -unit.2.0.waveform.posn.135.type=bus -unit.2.0.waveform.posn.136.channel=2147483646 -unit.2.0.waveform.posn.136.name=x -unit.2.0.waveform.posn.136.radix=1 -unit.2.0.waveform.posn.136.type=bus -unit.2.0.waveform.posn.137.channel=2147483646 -unit.2.0.waveform.posn.137.name=x -unit.2.0.waveform.posn.137.radix=1 -unit.2.0.waveform.posn.137.type=bus -unit.2.0.waveform.posn.138.channel=2147483646 -unit.2.0.waveform.posn.138.name=x -unit.2.0.waveform.posn.138.radix=1 -unit.2.0.waveform.posn.138.type=bus -unit.2.0.waveform.posn.139.channel=2147483646 -unit.2.0.waveform.posn.139.name=x -unit.2.0.waveform.posn.139.radix=1 -unit.2.0.waveform.posn.139.type=bus -unit.2.0.waveform.posn.14.channel=74 -unit.2.0.waveform.posn.14.name=cyc -unit.2.0.waveform.posn.14.radix=1 -unit.2.0.waveform.posn.14.type=signal -unit.2.0.waveform.posn.140.channel=2147483646 -unit.2.0.waveform.posn.140.name=x -unit.2.0.waveform.posn.140.radix=1 -unit.2.0.waveform.posn.140.type=bus -unit.2.0.waveform.posn.141.channel=2147483646 -unit.2.0.waveform.posn.141.name=x -unit.2.0.waveform.posn.141.radix=1 -unit.2.0.waveform.posn.141.type=bus -unit.2.0.waveform.posn.142.channel=2147483646 -unit.2.0.waveform.posn.142.name=x -unit.2.0.waveform.posn.142.radix=1 -unit.2.0.waveform.posn.142.type=bus -unit.2.0.waveform.posn.143.channel=2147483646 -unit.2.0.waveform.posn.143.name=x -unit.2.0.waveform.posn.143.radix=1 -unit.2.0.waveform.posn.143.type=bus -unit.2.0.waveform.posn.144.channel=2147483646 -unit.2.0.waveform.posn.144.name=x -unit.2.0.waveform.posn.144.radix=1 -unit.2.0.waveform.posn.144.type=bus -unit.2.0.waveform.posn.145.channel=2147483646 -unit.2.0.waveform.posn.145.name=x -unit.2.0.waveform.posn.145.radix=1 -unit.2.0.waveform.posn.145.type=bus -unit.2.0.waveform.posn.146.channel=2147483646 -unit.2.0.waveform.posn.146.name=x -unit.2.0.waveform.posn.146.radix=1 -unit.2.0.waveform.posn.146.type=bus -unit.2.0.waveform.posn.147.channel=2147483646 -unit.2.0.waveform.posn.147.name=x -unit.2.0.waveform.posn.147.radix=1 -unit.2.0.waveform.posn.147.type=bus -unit.2.0.waveform.posn.148.channel=2147483646 -unit.2.0.waveform.posn.148.name=x -unit.2.0.waveform.posn.148.radix=1 -unit.2.0.waveform.posn.148.type=bus -unit.2.0.waveform.posn.149.channel=2147483646 -unit.2.0.waveform.posn.149.name=x -unit.2.0.waveform.posn.149.radix=1 -unit.2.0.waveform.posn.149.type=bus -unit.2.0.waveform.posn.15.channel=75 -unit.2.0.waveform.posn.15.name=tga -unit.2.0.waveform.posn.15.radix=1 -unit.2.0.waveform.posn.15.type=signal -unit.2.0.waveform.posn.150.channel=2147483646 -unit.2.0.waveform.posn.150.name=x -unit.2.0.waveform.posn.150.radix=1 -unit.2.0.waveform.posn.150.type=bus -unit.2.0.waveform.posn.151.channel=2147483646 -unit.2.0.waveform.posn.151.name=x -unit.2.0.waveform.posn.151.radix=1 -unit.2.0.waveform.posn.151.type=bus -unit.2.0.waveform.posn.152.channel=2147483646 -unit.2.0.waveform.posn.152.name=x -unit.2.0.waveform.posn.152.radix=1 -unit.2.0.waveform.posn.152.type=bus -unit.2.0.waveform.posn.153.channel=2147483646 -unit.2.0.waveform.posn.153.name=x -unit.2.0.waveform.posn.153.radix=1 -unit.2.0.waveform.posn.153.type=bus -unit.2.0.waveform.posn.154.channel=2147483646 -unit.2.0.waveform.posn.154.name=x -unit.2.0.waveform.posn.154.radix=1 -unit.2.0.waveform.posn.154.type=bus -unit.2.0.waveform.posn.155.channel=2147483646 -unit.2.0.waveform.posn.155.name=x -unit.2.0.waveform.posn.155.radix=1 -unit.2.0.waveform.posn.155.type=bus -unit.2.0.waveform.posn.156.channel=2147483646 -unit.2.0.waveform.posn.156.name=x -unit.2.0.waveform.posn.156.radix=1 -unit.2.0.waveform.posn.156.type=bus -unit.2.0.waveform.posn.157.channel=2147483646 -unit.2.0.waveform.posn.157.name=x -unit.2.0.waveform.posn.157.radix=1 -unit.2.0.waveform.posn.157.type=bus -unit.2.0.waveform.posn.158.channel=2147483646 -unit.2.0.waveform.posn.158.name=x -unit.2.0.waveform.posn.158.radix=1 -unit.2.0.waveform.posn.158.type=bus -unit.2.0.waveform.posn.159.channel=2147483646 -unit.2.0.waveform.posn.159.name=x -unit.2.0.waveform.posn.159.radix=1 -unit.2.0.waveform.posn.159.type=bus -unit.2.0.waveform.posn.16.channel=76 -unit.2.0.waveform.posn.16.name=we -unit.2.0.waveform.posn.16.radix=1 -unit.2.0.waveform.posn.16.type=signal -unit.2.0.waveform.posn.160.channel=2147483646 -unit.2.0.waveform.posn.160.name=x -unit.2.0.waveform.posn.160.radix=1 -unit.2.0.waveform.posn.160.type=bus -unit.2.0.waveform.posn.161.channel=2147483646 -unit.2.0.waveform.posn.161.name=x -unit.2.0.waveform.posn.161.radix=1 -unit.2.0.waveform.posn.161.type=bus -unit.2.0.waveform.posn.162.channel=2147483646 -unit.2.0.waveform.posn.162.name=x -unit.2.0.waveform.posn.162.radix=1 -unit.2.0.waveform.posn.162.type=bus -unit.2.0.waveform.posn.163.channel=2147483646 -unit.2.0.waveform.posn.163.name=x -unit.2.0.waveform.posn.163.radix=1 -unit.2.0.waveform.posn.163.type=bus -unit.2.0.waveform.posn.164.channel=2147483646 -unit.2.0.waveform.posn.164.name=x -unit.2.0.waveform.posn.164.radix=1 -unit.2.0.waveform.posn.164.type=bus -unit.2.0.waveform.posn.165.channel=2147483646 -unit.2.0.waveform.posn.165.name=x -unit.2.0.waveform.posn.165.radix=1 -unit.2.0.waveform.posn.165.type=bus -unit.2.0.waveform.posn.166.channel=2147483646 -unit.2.0.waveform.posn.166.name=x -unit.2.0.waveform.posn.166.radix=1 -unit.2.0.waveform.posn.166.type=bus -unit.2.0.waveform.posn.167.channel=2147483646 -unit.2.0.waveform.posn.167.name=x -unit.2.0.waveform.posn.167.radix=1 -unit.2.0.waveform.posn.167.type=bus -unit.2.0.waveform.posn.168.channel=2147483646 -unit.2.0.waveform.posn.168.name=x -unit.2.0.waveform.posn.168.radix=1 -unit.2.0.waveform.posn.168.type=bus -unit.2.0.waveform.posn.169.channel=2147483646 -unit.2.0.waveform.posn.169.name=x -unit.2.0.waveform.posn.169.radix=1 -unit.2.0.waveform.posn.169.type=bus -unit.2.0.waveform.posn.17.channel=77 -unit.2.0.waveform.posn.17.name=clk -unit.2.0.waveform.posn.17.radix=1 -unit.2.0.waveform.posn.17.type=signal -unit.2.0.waveform.posn.170.channel=2147483646 -unit.2.0.waveform.posn.170.name=x -unit.2.0.waveform.posn.170.radix=1 -unit.2.0.waveform.posn.170.type=bus -unit.2.0.waveform.posn.171.channel=2147483646 -unit.2.0.waveform.posn.171.name=x -unit.2.0.waveform.posn.171.radix=1 -unit.2.0.waveform.posn.171.type=bus -unit.2.0.waveform.posn.172.channel=2147483646 -unit.2.0.waveform.posn.172.name=x -unit.2.0.waveform.posn.172.radix=1 -unit.2.0.waveform.posn.172.type=bus -unit.2.0.waveform.posn.173.channel=2147483646 -unit.2.0.waveform.posn.173.name=x -unit.2.0.waveform.posn.173.radix=1 -unit.2.0.waveform.posn.173.type=bus -unit.2.0.waveform.posn.174.channel=2147483646 -unit.2.0.waveform.posn.174.name=x -unit.2.0.waveform.posn.174.radix=1 -unit.2.0.waveform.posn.174.type=bus -unit.2.0.waveform.posn.175.channel=2147483646 -unit.2.0.waveform.posn.175.name=x -unit.2.0.waveform.posn.175.radix=1 -unit.2.0.waveform.posn.175.type=bus -unit.2.0.waveform.posn.176.channel=2147483646 -unit.2.0.waveform.posn.176.name=x -unit.2.0.waveform.posn.176.radix=1 -unit.2.0.waveform.posn.176.type=bus -unit.2.0.waveform.posn.177.channel=2147483646 -unit.2.0.waveform.posn.177.name=x -unit.2.0.waveform.posn.177.radix=1 -unit.2.0.waveform.posn.177.type=bus -unit.2.0.waveform.posn.178.channel=2147483646 -unit.2.0.waveform.posn.178.name=x -unit.2.0.waveform.posn.178.radix=1 -unit.2.0.waveform.posn.178.type=bus -unit.2.0.waveform.posn.179.channel=2147483646 -unit.2.0.waveform.posn.179.name=x -unit.2.0.waveform.posn.179.radix=1 -unit.2.0.waveform.posn.179.type=bus -unit.2.0.waveform.posn.18.channel=2147483646 -unit.2.0.waveform.posn.18.name=cnt -unit.2.0.waveform.posn.18.radix=1 -unit.2.0.waveform.posn.18.type=bus -unit.2.0.waveform.posn.180.channel=2147483646 -unit.2.0.waveform.posn.180.name=x -unit.2.0.waveform.posn.180.radix=1 -unit.2.0.waveform.posn.180.type=bus -unit.2.0.waveform.posn.181.channel=2147483646 -unit.2.0.waveform.posn.181.name=x -unit.2.0.waveform.posn.181.radix=1 -unit.2.0.waveform.posn.181.type=bus -unit.2.0.waveform.posn.182.channel=2147483646 -unit.2.0.waveform.posn.182.name=x -unit.2.0.waveform.posn.182.radix=1 -unit.2.0.waveform.posn.182.type=bus -unit.2.0.waveform.posn.183.channel=2147483646 -unit.2.0.waveform.posn.183.name=x -unit.2.0.waveform.posn.183.radix=1 -unit.2.0.waveform.posn.183.type=bus -unit.2.0.waveform.posn.184.channel=2147483646 -unit.2.0.waveform.posn.184.name=x -unit.2.0.waveform.posn.184.radix=1 -unit.2.0.waveform.posn.184.type=bus -unit.2.0.waveform.posn.185.channel=2147483646 -unit.2.0.waveform.posn.185.name=x -unit.2.0.waveform.posn.185.radix=1 -unit.2.0.waveform.posn.185.type=bus -unit.2.0.waveform.posn.186.channel=2147483646 -unit.2.0.waveform.posn.186.name=x -unit.2.0.waveform.posn.186.radix=1 -unit.2.0.waveform.posn.186.type=bus -unit.2.0.waveform.posn.187.channel=2147483646 -unit.2.0.waveform.posn.187.name=x -unit.2.0.waveform.posn.187.radix=1 -unit.2.0.waveform.posn.187.type=bus -unit.2.0.waveform.posn.188.channel=2147483646 -unit.2.0.waveform.posn.188.name=x -unit.2.0.waveform.posn.188.radix=1 -unit.2.0.waveform.posn.188.type=bus -unit.2.0.waveform.posn.189.channel=2147483646 -unit.2.0.waveform.posn.189.name=x -unit.2.0.waveform.posn.189.radix=1 -unit.2.0.waveform.posn.189.type=bus -unit.2.0.waveform.posn.19.channel=219 -unit.2.0.waveform.posn.19.name=op -unit.2.0.waveform.posn.19.radix=1 -unit.2.0.waveform.posn.19.type=signal -unit.2.0.waveform.posn.190.channel=2147483646 -unit.2.0.waveform.posn.190.name=x -unit.2.0.waveform.posn.190.radix=1 -unit.2.0.waveform.posn.190.type=bus -unit.2.0.waveform.posn.191.channel=2147483646 -unit.2.0.waveform.posn.191.name=x -unit.2.0.waveform.posn.191.radix=1 -unit.2.0.waveform.posn.191.type=bus -unit.2.0.waveform.posn.192.channel=2147483646 -unit.2.0.waveform.posn.192.name=x -unit.2.0.waveform.posn.192.radix=1 -unit.2.0.waveform.posn.192.type=bus -unit.2.0.waveform.posn.193.channel=2147483646 -unit.2.0.waveform.posn.193.name=x -unit.2.0.waveform.posn.193.radix=1 -unit.2.0.waveform.posn.193.type=bus -unit.2.0.waveform.posn.194.channel=2147483646 -unit.2.0.waveform.posn.194.name=x -unit.2.0.waveform.posn.194.radix=1 -unit.2.0.waveform.posn.194.type=bus -unit.2.0.waveform.posn.195.channel=2147483646 -unit.2.0.waveform.posn.195.name=x -unit.2.0.waveform.posn.195.radix=1 -unit.2.0.waveform.posn.195.type=bus -unit.2.0.waveform.posn.196.channel=2147483646 -unit.2.0.waveform.posn.196.name=x -unit.2.0.waveform.posn.196.radix=1 -unit.2.0.waveform.posn.196.type=bus -unit.2.0.waveform.posn.197.channel=2147483646 -unit.2.0.waveform.posn.197.name=x -unit.2.0.waveform.posn.197.radix=1 -unit.2.0.waveform.posn.197.type=bus -unit.2.0.waveform.posn.198.channel=2147483646 -unit.2.0.waveform.posn.198.name=x -unit.2.0.waveform.posn.198.radix=1 -unit.2.0.waveform.posn.198.type=bus -unit.2.0.waveform.posn.199.channel=2147483646 -unit.2.0.waveform.posn.199.name=x -unit.2.0.waveform.posn.199.radix=1 -unit.2.0.waveform.posn.199.type=bus -unit.2.0.waveform.posn.2.channel=2147483646 -unit.2.0.waveform.posn.2.name=y -unit.2.0.waveform.posn.2.radix=1 -unit.2.0.waveform.posn.2.type=bus -unit.2.0.waveform.posn.20.channel=220 -unit.2.0.waveform.posn.20.name=zbt_stb -unit.2.0.waveform.posn.20.radix=1 -unit.2.0.waveform.posn.20.type=signal -unit.2.0.waveform.posn.200.channel=2147483646 -unit.2.0.waveform.posn.200.name=x -unit.2.0.waveform.posn.200.radix=1 -unit.2.0.waveform.posn.200.type=bus -unit.2.0.waveform.posn.201.channel=2147483646 -unit.2.0.waveform.posn.201.name=x -unit.2.0.waveform.posn.201.radix=1 -unit.2.0.waveform.posn.201.type=bus -unit.2.0.waveform.posn.202.channel=2147483646 -unit.2.0.waveform.posn.202.name=x -unit.2.0.waveform.posn.202.radix=1 -unit.2.0.waveform.posn.202.type=bus -unit.2.0.waveform.posn.203.channel=2147483646 -unit.2.0.waveform.posn.203.name=x -unit.2.0.waveform.posn.203.radix=1 -unit.2.0.waveform.posn.203.type=bus -unit.2.0.waveform.posn.204.channel=2147483646 -unit.2.0.waveform.posn.204.name=x -unit.2.0.waveform.posn.204.radix=1 -unit.2.0.waveform.posn.204.type=bus -unit.2.0.waveform.posn.205.channel=2147483646 -unit.2.0.waveform.posn.205.name=x -unit.2.0.waveform.posn.205.radix=1 -unit.2.0.waveform.posn.205.type=bus -unit.2.0.waveform.posn.206.channel=2147483646 -unit.2.0.waveform.posn.206.name=x -unit.2.0.waveform.posn.206.radix=1 -unit.2.0.waveform.posn.206.type=bus -unit.2.0.waveform.posn.207.channel=2147483646 -unit.2.0.waveform.posn.207.name=x -unit.2.0.waveform.posn.207.radix=1 -unit.2.0.waveform.posn.207.type=bus -unit.2.0.waveform.posn.208.channel=2147483646 -unit.2.0.waveform.posn.208.name=x -unit.2.0.waveform.posn.208.radix=1 -unit.2.0.waveform.posn.208.type=bus -unit.2.0.waveform.posn.209.channel=2147483646 -unit.2.0.waveform.posn.209.name=x -unit.2.0.waveform.posn.209.radix=1 -unit.2.0.waveform.posn.209.type=bus -unit.2.0.waveform.posn.21.channel=221 -unit.2.0.waveform.posn.21.name=flash_stb -unit.2.0.waveform.posn.21.radix=1 -unit.2.0.waveform.posn.21.type=signal -unit.2.0.waveform.posn.210.channel=2147483646 -unit.2.0.waveform.posn.210.name=x -unit.2.0.waveform.posn.210.radix=1 -unit.2.0.waveform.posn.210.type=bus -unit.2.0.waveform.posn.211.channel=2147483646 -unit.2.0.waveform.posn.211.name=x -unit.2.0.waveform.posn.211.radix=1 -unit.2.0.waveform.posn.211.type=bus -unit.2.0.waveform.posn.212.channel=2147483646 -unit.2.0.waveform.posn.212.name=x -unit.2.0.waveform.posn.212.radix=1 -unit.2.0.waveform.posn.212.type=bus -unit.2.0.waveform.posn.213.channel=2147483646 -unit.2.0.waveform.posn.213.name=x -unit.2.0.waveform.posn.213.radix=1 -unit.2.0.waveform.posn.213.type=bus -unit.2.0.waveform.posn.214.channel=2147483646 -unit.2.0.waveform.posn.214.name=x -unit.2.0.waveform.posn.214.radix=1 -unit.2.0.waveform.posn.214.type=bus -unit.2.0.waveform.posn.215.channel=2147483646 -unit.2.0.waveform.posn.215.name=x -unit.2.0.waveform.posn.215.radix=1 -unit.2.0.waveform.posn.215.type=bus -unit.2.0.waveform.posn.216.channel=2147483646 -unit.2.0.waveform.posn.216.name=x -unit.2.0.waveform.posn.216.radix=1 -unit.2.0.waveform.posn.216.type=bus -unit.2.0.waveform.posn.217.channel=2147483646 -unit.2.0.waveform.posn.217.name=x -unit.2.0.waveform.posn.217.radix=1 -unit.2.0.waveform.posn.217.type=bus -unit.2.0.waveform.posn.218.channel=2147483646 -unit.2.0.waveform.posn.218.name=x -unit.2.0.waveform.posn.218.radix=1 -unit.2.0.waveform.posn.218.type=bus -unit.2.0.waveform.posn.219.channel=2147483646 -unit.2.0.waveform.posn.219.name=x -unit.2.0.waveform.posn.219.radix=1 -unit.2.0.waveform.posn.219.type=bus -unit.2.0.waveform.posn.22.channel=222 -unit.2.0.waveform.posn.22.name=flash_arena -unit.2.0.waveform.posn.22.radix=1 -unit.2.0.waveform.posn.22.type=signal -unit.2.0.waveform.posn.220.channel=2147483646 -unit.2.0.waveform.posn.220.name=x -unit.2.0.waveform.posn.220.radix=1 -unit.2.0.waveform.posn.220.type=bus -unit.2.0.waveform.posn.221.channel=2147483646 -unit.2.0.waveform.posn.221.name=x -unit.2.0.waveform.posn.221.radix=1 -unit.2.0.waveform.posn.221.type=bus -unit.2.0.waveform.posn.222.channel=2147483646 -unit.2.0.waveform.posn.222.name=x -unit.2.0.waveform.posn.222.radix=1 -unit.2.0.waveform.posn.222.type=bus -unit.2.0.waveform.posn.223.channel=2147483646 -unit.2.0.waveform.posn.223.name=x -unit.2.0.waveform.posn.223.radix=1 -unit.2.0.waveform.posn.223.type=bus -unit.2.0.waveform.posn.224.channel=2147483646 -unit.2.0.waveform.posn.224.name=x -unit.2.0.waveform.posn.224.radix=1 -unit.2.0.waveform.posn.224.type=bus -unit.2.0.waveform.posn.225.channel=2147483646 -unit.2.0.waveform.posn.225.name=x -unit.2.0.waveform.posn.225.radix=1 -unit.2.0.waveform.posn.225.type=bus -unit.2.0.waveform.posn.226.channel=2147483646 -unit.2.0.waveform.posn.226.name=x -unit.2.0.waveform.posn.226.radix=1 -unit.2.0.waveform.posn.226.type=bus -unit.2.0.waveform.posn.227.channel=2147483646 -unit.2.0.waveform.posn.227.name=x -unit.2.0.waveform.posn.227.radix=1 -unit.2.0.waveform.posn.227.type=bus -unit.2.0.waveform.posn.228.channel=2147483646 -unit.2.0.waveform.posn.228.name=x -unit.2.0.waveform.posn.228.radix=1 -unit.2.0.waveform.posn.228.type=bus -unit.2.0.waveform.posn.229.channel=2147483646 -unit.2.0.waveform.posn.229.name=x -unit.2.0.waveform.posn.229.radix=1 -unit.2.0.waveform.posn.229.type=bus -unit.2.0.waveform.posn.23.channel=223 -unit.2.0.waveform.posn.23.name=vdu_arena -unit.2.0.waveform.posn.23.radix=1 -unit.2.0.waveform.posn.23.type=signal -unit.2.0.waveform.posn.230.channel=2147483646 -unit.2.0.waveform.posn.230.name=x -unit.2.0.waveform.posn.230.radix=1 -unit.2.0.waveform.posn.230.type=bus -unit.2.0.waveform.posn.231.channel=2147483646 -unit.2.0.waveform.posn.231.name=x -unit.2.0.waveform.posn.231.radix=1 -unit.2.0.waveform.posn.231.type=bus -unit.2.0.waveform.posn.232.channel=2147483646 -unit.2.0.waveform.posn.232.name=x -unit.2.0.waveform.posn.232.radix=1 -unit.2.0.waveform.posn.232.type=bus -unit.2.0.waveform.posn.233.channel=2147483646 -unit.2.0.waveform.posn.233.name=x -unit.2.0.waveform.posn.233.radix=1 -unit.2.0.waveform.posn.233.type=bus -unit.2.0.waveform.posn.234.channel=2147483646 -unit.2.0.waveform.posn.234.name=x -unit.2.0.waveform.posn.234.radix=1 -unit.2.0.waveform.posn.234.type=bus -unit.2.0.waveform.posn.235.channel=2147483646 -unit.2.0.waveform.posn.235.name=x -unit.2.0.waveform.posn.235.radix=1 -unit.2.0.waveform.posn.235.type=bus -unit.2.0.waveform.posn.236.channel=2147483646 -unit.2.0.waveform.posn.236.name=x -unit.2.0.waveform.posn.236.radix=1 -unit.2.0.waveform.posn.236.type=bus -unit.2.0.waveform.posn.237.channel=2147483646 -unit.2.0.waveform.posn.237.name=x -unit.2.0.waveform.posn.237.radix=1 -unit.2.0.waveform.posn.237.type=bus -unit.2.0.waveform.posn.238.channel=2147483646 -unit.2.0.waveform.posn.238.name=x -unit.2.0.waveform.posn.238.radix=1 -unit.2.0.waveform.posn.238.type=bus -unit.2.0.waveform.posn.239.channel=2147483646 -unit.2.0.waveform.posn.239.name=x -unit.2.0.waveform.posn.239.radix=1 -unit.2.0.waveform.posn.239.type=bus -unit.2.0.waveform.posn.24.channel=2147483646 -unit.2.0.waveform.posn.24.name=d -unit.2.0.waveform.posn.24.radix=1 -unit.2.0.waveform.posn.24.type=bus -unit.2.0.waveform.posn.240.channel=2147483646 -unit.2.0.waveform.posn.240.name=x -unit.2.0.waveform.posn.240.radix=1 -unit.2.0.waveform.posn.240.type=bus -unit.2.0.waveform.posn.241.channel=2147483646 -unit.2.0.waveform.posn.241.name=x -unit.2.0.waveform.posn.241.radix=1 -unit.2.0.waveform.posn.241.type=bus -unit.2.0.waveform.posn.242.channel=2147483646 -unit.2.0.waveform.posn.242.name=x -unit.2.0.waveform.posn.242.radix=1 -unit.2.0.waveform.posn.242.type=bus -unit.2.0.waveform.posn.243.channel=2147483646 -unit.2.0.waveform.posn.243.name=x -unit.2.0.waveform.posn.243.radix=1 -unit.2.0.waveform.posn.243.type=bus -unit.2.0.waveform.posn.244.channel=2147483646 -unit.2.0.waveform.posn.244.name=x -unit.2.0.waveform.posn.244.radix=1 -unit.2.0.waveform.posn.244.type=bus -unit.2.0.waveform.posn.245.channel=2147483646 -unit.2.0.waveform.posn.245.name=x -unit.2.0.waveform.posn.245.radix=1 -unit.2.0.waveform.posn.245.type=bus -unit.2.0.waveform.posn.246.channel=2147483646 -unit.2.0.waveform.posn.246.name=x -unit.2.0.waveform.posn.246.radix=1 -unit.2.0.waveform.posn.246.type=bus -unit.2.0.waveform.posn.247.channel=2147483646 -unit.2.0.waveform.posn.247.name=x -unit.2.0.waveform.posn.247.radix=1 -unit.2.0.waveform.posn.247.type=bus -unit.2.0.waveform.posn.248.channel=2147483646 -unit.2.0.waveform.posn.248.name=x -unit.2.0.waveform.posn.248.radix=1 -unit.2.0.waveform.posn.248.type=bus -unit.2.0.waveform.posn.249.channel=2147483646 -unit.2.0.waveform.posn.249.name=x -unit.2.0.waveform.posn.249.radix=1 -unit.2.0.waveform.posn.249.type=bus -unit.2.0.waveform.posn.25.channel=2147483646 -unit.2.0.waveform.posn.25.name=addr_d -unit.2.0.waveform.posn.25.radix=1 -unit.2.0.waveform.posn.25.type=bus -unit.2.0.waveform.posn.250.channel=2147483646 -unit.2.0.waveform.posn.250.name=x -unit.2.0.waveform.posn.250.radix=1 -unit.2.0.waveform.posn.250.type=bus -unit.2.0.waveform.posn.251.channel=2147483646 -unit.2.0.waveform.posn.251.name=x -unit.2.0.waveform.posn.251.radix=1 -unit.2.0.waveform.posn.251.type=bus -unit.2.0.waveform.posn.252.channel=2147483646 -unit.2.0.waveform.posn.252.name=x -unit.2.0.waveform.posn.252.radix=1 -unit.2.0.waveform.posn.252.type=bus -unit.2.0.waveform.posn.253.channel=2147483646 -unit.2.0.waveform.posn.253.name=x -unit.2.0.waveform.posn.253.radix=1 -unit.2.0.waveform.posn.253.type=bus -unit.2.0.waveform.posn.254.channel=2147483646 -unit.2.0.waveform.posn.254.name=x -unit.2.0.waveform.posn.254.radix=1 -unit.2.0.waveform.posn.254.type=bus -unit.2.0.waveform.posn.255.channel=2147483646 -unit.2.0.waveform.posn.255.name=x -unit.2.0.waveform.posn.255.radix=1 -unit.2.0.waveform.posn.255.type=bus -unit.2.0.waveform.posn.256.channel=2147483646 -unit.2.0.waveform.posn.256.name=x -unit.2.0.waveform.posn.256.radix=1 -unit.2.0.waveform.posn.256.type=bus -unit.2.0.waveform.posn.257.channel=2147483646 -unit.2.0.waveform.posn.257.name=x -unit.2.0.waveform.posn.257.radix=1 -unit.2.0.waveform.posn.257.type=bus -unit.2.0.waveform.posn.258.channel=2147483646 -unit.2.0.waveform.posn.258.name=x -unit.2.0.waveform.posn.258.radix=1 -unit.2.0.waveform.posn.258.type=bus -unit.2.0.waveform.posn.259.channel=2147483646 -unit.2.0.waveform.posn.259.name=x -unit.2.0.waveform.posn.259.radix=1 -unit.2.0.waveform.posn.259.type=bus -unit.2.0.waveform.posn.26.channel=94 -unit.2.0.waveform.posn.26.name=byte_op -unit.2.0.waveform.posn.26.radix=1 -unit.2.0.waveform.posn.26.type=signal -unit.2.0.waveform.posn.260.channel=2147483646 -unit.2.0.waveform.posn.260.name=x -unit.2.0.waveform.posn.260.radix=1 -unit.2.0.waveform.posn.260.type=bus -unit.2.0.waveform.posn.261.channel=2147483646 -unit.2.0.waveform.posn.261.name=x -unit.2.0.waveform.posn.261.radix=1 -unit.2.0.waveform.posn.261.type=bus -unit.2.0.waveform.posn.262.channel=2147483646 -unit.2.0.waveform.posn.262.name=x -unit.2.0.waveform.posn.262.radix=1 -unit.2.0.waveform.posn.262.type=bus -unit.2.0.waveform.posn.263.channel=2147483646 -unit.2.0.waveform.posn.263.name=x -unit.2.0.waveform.posn.263.radix=1 -unit.2.0.waveform.posn.263.type=bus -unit.2.0.waveform.posn.264.channel=2147483646 -unit.2.0.waveform.posn.264.name=x -unit.2.0.waveform.posn.264.radix=1 -unit.2.0.waveform.posn.264.type=bus -unit.2.0.waveform.posn.265.channel=2147483646 -unit.2.0.waveform.posn.265.name=x -unit.2.0.waveform.posn.265.radix=1 -unit.2.0.waveform.posn.265.type=bus -unit.2.0.waveform.posn.266.channel=2147483646 -unit.2.0.waveform.posn.266.name=x -unit.2.0.waveform.posn.266.radix=1 -unit.2.0.waveform.posn.266.type=bus -unit.2.0.waveform.posn.267.channel=2147483646 -unit.2.0.waveform.posn.267.name=x -unit.2.0.waveform.posn.267.radix=1 -unit.2.0.waveform.posn.267.type=bus -unit.2.0.waveform.posn.268.channel=2147483646 -unit.2.0.waveform.posn.268.name=x -unit.2.0.waveform.posn.268.radix=1 -unit.2.0.waveform.posn.268.type=bus -unit.2.0.waveform.posn.269.channel=2147483646 -unit.2.0.waveform.posn.269.name=x -unit.2.0.waveform.posn.269.radix=1 -unit.2.0.waveform.posn.269.type=bus -unit.2.0.waveform.posn.27.channel=104 -unit.2.0.waveform.posn.27.name=inta -unit.2.0.waveform.posn.27.radix=1 -unit.2.0.waveform.posn.27.type=signal -unit.2.0.waveform.posn.270.channel=2147483646 -unit.2.0.waveform.posn.270.name=x -unit.2.0.waveform.posn.270.radix=1 -unit.2.0.waveform.posn.270.type=bus -unit.2.0.waveform.posn.271.channel=2147483646 -unit.2.0.waveform.posn.271.name=x -unit.2.0.waveform.posn.271.radix=1 -unit.2.0.waveform.posn.271.type=bus -unit.2.0.waveform.posn.272.channel=2147483646 -unit.2.0.waveform.posn.272.name=x -unit.2.0.waveform.posn.272.radix=1 -unit.2.0.waveform.posn.272.type=bus -unit.2.0.waveform.posn.273.channel=2147483646 -unit.2.0.waveform.posn.273.name=x -unit.2.0.waveform.posn.273.radix=1 -unit.2.0.waveform.posn.273.type=bus -unit.2.0.waveform.posn.274.channel=2147483646 -unit.2.0.waveform.posn.274.name=x -unit.2.0.waveform.posn.274.radix=1 -unit.2.0.waveform.posn.274.type=bus -unit.2.0.waveform.posn.275.channel=2147483646 -unit.2.0.waveform.posn.275.name=x -unit.2.0.waveform.posn.275.radix=1 -unit.2.0.waveform.posn.275.type=bus -unit.2.0.waveform.posn.276.channel=2147483646 -unit.2.0.waveform.posn.276.name=x -unit.2.0.waveform.posn.276.radix=1 -unit.2.0.waveform.posn.276.type=bus -unit.2.0.waveform.posn.277.channel=2147483646 -unit.2.0.waveform.posn.277.name=x -unit.2.0.waveform.posn.277.radix=1 -unit.2.0.waveform.posn.277.type=bus -unit.2.0.waveform.posn.278.channel=2147483646 -unit.2.0.waveform.posn.278.name=x -unit.2.0.waveform.posn.278.radix=1 -unit.2.0.waveform.posn.278.type=bus -unit.2.0.waveform.posn.279.channel=2147483646 -unit.2.0.waveform.posn.279.name=x -unit.2.0.waveform.posn.279.radix=1 -unit.2.0.waveform.posn.279.type=bus -unit.2.0.waveform.posn.28.channel=105 -unit.2.0.waveform.posn.28.name=intr -unit.2.0.waveform.posn.28.radix=1 -unit.2.0.waveform.posn.28.type=signal -unit.2.0.waveform.posn.280.channel=2147483646 -unit.2.0.waveform.posn.280.name=x -unit.2.0.waveform.posn.280.radix=1 -unit.2.0.waveform.posn.280.type=bus -unit.2.0.waveform.posn.281.channel=2147483646 -unit.2.0.waveform.posn.281.name=x -unit.2.0.waveform.posn.281.radix=1 -unit.2.0.waveform.posn.281.type=bus -unit.2.0.waveform.posn.282.channel=2147483646 -unit.2.0.waveform.posn.282.name=x -unit.2.0.waveform.posn.282.radix=1 -unit.2.0.waveform.posn.282.type=bus -unit.2.0.waveform.posn.283.channel=2147483646 -unit.2.0.waveform.posn.283.name=x -unit.2.0.waveform.posn.283.radix=1 -unit.2.0.waveform.posn.283.type=bus -unit.2.0.waveform.posn.284.channel=2147483646 -unit.2.0.waveform.posn.284.name=x -unit.2.0.waveform.posn.284.radix=1 -unit.2.0.waveform.posn.284.type=bus -unit.2.0.waveform.posn.285.channel=2147483646 -unit.2.0.waveform.posn.285.name=x -unit.2.0.waveform.posn.285.radix=1 -unit.2.0.waveform.posn.285.type=bus -unit.2.0.waveform.posn.286.channel=2147483646 -unit.2.0.waveform.posn.286.name=x -unit.2.0.waveform.posn.286.radix=1 -unit.2.0.waveform.posn.286.type=bus -unit.2.0.waveform.posn.287.channel=2147483646 -unit.2.0.waveform.posn.287.name=x -unit.2.0.waveform.posn.287.radix=1 -unit.2.0.waveform.posn.287.type=bus -unit.2.0.waveform.posn.288.channel=2147483646 -unit.2.0.waveform.posn.288.name=x -unit.2.0.waveform.posn.288.radix=1 -unit.2.0.waveform.posn.288.type=bus -unit.2.0.waveform.posn.289.channel=2147483646 -unit.2.0.waveform.posn.289.name=x -unit.2.0.waveform.posn.289.radix=1 -unit.2.0.waveform.posn.289.type=bus -unit.2.0.waveform.posn.29.channel=2147483646 -unit.2.0.waveform.posn.29.name=cnt_time -unit.2.0.waveform.posn.29.radix=1 -unit.2.0.waveform.posn.29.type=bus -unit.2.0.waveform.posn.290.channel=2147483646 -unit.2.0.waveform.posn.290.name=x -unit.2.0.waveform.posn.290.radix=1 -unit.2.0.waveform.posn.290.type=bus -unit.2.0.waveform.posn.291.channel=2147483646 -unit.2.0.waveform.posn.291.name=x -unit.2.0.waveform.posn.291.radix=1 -unit.2.0.waveform.posn.291.type=bus -unit.2.0.waveform.posn.292.channel=2147483646 -unit.2.0.waveform.posn.292.name=x -unit.2.0.waveform.posn.292.radix=1 -unit.2.0.waveform.posn.292.type=bus -unit.2.0.waveform.posn.293.channel=2147483646 -unit.2.0.waveform.posn.293.name=x -unit.2.0.waveform.posn.293.radix=1 -unit.2.0.waveform.posn.293.type=bus -unit.2.0.waveform.posn.294.channel=2147483646 -unit.2.0.waveform.posn.294.name=x -unit.2.0.waveform.posn.294.radix=1 -unit.2.0.waveform.posn.294.type=bus -unit.2.0.waveform.posn.295.channel=2147483646 -unit.2.0.waveform.posn.295.name=x -unit.2.0.waveform.posn.295.radix=1 -unit.2.0.waveform.posn.295.type=bus -unit.2.0.waveform.posn.296.channel=2147483646 -unit.2.0.waveform.posn.296.name=x -unit.2.0.waveform.posn.296.radix=1 -unit.2.0.waveform.posn.296.type=bus -unit.2.0.waveform.posn.297.channel=2147483646 -unit.2.0.waveform.posn.297.name=x -unit.2.0.waveform.posn.297.radix=1 -unit.2.0.waveform.posn.297.type=bus -unit.2.0.waveform.posn.298.channel=2147483646 -unit.2.0.waveform.posn.298.name=x -unit.2.0.waveform.posn.298.radix=1 -unit.2.0.waveform.posn.298.type=bus -unit.2.0.waveform.posn.299.channel=2147483646 -unit.2.0.waveform.posn.299.name=x -unit.2.0.waveform.posn.299.radix=1 -unit.2.0.waveform.posn.299.type=bus -unit.2.0.waveform.posn.3.channel=2147483646 -unit.2.0.waveform.posn.3.name=pc -unit.2.0.waveform.posn.3.radix=1 -unit.2.0.waveform.posn.3.type=bus -unit.2.0.waveform.posn.30.channel=2147483646 -unit.2.0.waveform.posn.30.name=ace_dat_o -unit.2.0.waveform.posn.30.radix=1 -unit.2.0.waveform.posn.30.type=bus -unit.2.0.waveform.posn.300.channel=2147483646 -unit.2.0.waveform.posn.300.name=x -unit.2.0.waveform.posn.300.radix=1 -unit.2.0.waveform.posn.300.type=bus -unit.2.0.waveform.posn.301.channel=2147483646 -unit.2.0.waveform.posn.301.name=x -unit.2.0.waveform.posn.301.radix=1 -unit.2.0.waveform.posn.301.type=bus -unit.2.0.waveform.posn.302.channel=2147483646 -unit.2.0.waveform.posn.302.name=x -unit.2.0.waveform.posn.302.radix=1 -unit.2.0.waveform.posn.302.type=bus -unit.2.0.waveform.posn.303.channel=2147483646 -unit.2.0.waveform.posn.303.name=x -unit.2.0.waveform.posn.303.radix=1 -unit.2.0.waveform.posn.303.type=bus -unit.2.0.waveform.posn.304.channel=2147483646 -unit.2.0.waveform.posn.304.name=x -unit.2.0.waveform.posn.304.radix=1 -unit.2.0.waveform.posn.304.type=bus -unit.2.0.waveform.posn.305.channel=2147483646 -unit.2.0.waveform.posn.305.name=x -unit.2.0.waveform.posn.305.radix=1 -unit.2.0.waveform.posn.305.type=bus -unit.2.0.waveform.posn.306.channel=2147483646 -unit.2.0.waveform.posn.306.name=x -unit.2.0.waveform.posn.306.radix=1 -unit.2.0.waveform.posn.306.type=bus -unit.2.0.waveform.posn.307.channel=2147483646 -unit.2.0.waveform.posn.307.name=x -unit.2.0.waveform.posn.307.radix=1 -unit.2.0.waveform.posn.307.type=bus -unit.2.0.waveform.posn.308.channel=2147483646 -unit.2.0.waveform.posn.308.name=x -unit.2.0.waveform.posn.308.radix=1 -unit.2.0.waveform.posn.308.type=bus -unit.2.0.waveform.posn.309.channel=2147483646 -unit.2.0.waveform.posn.309.name=x -unit.2.0.waveform.posn.309.radix=1 -unit.2.0.waveform.posn.309.type=bus -unit.2.0.waveform.posn.31.channel=186 -unit.2.0.waveform.posn.31.name=ace_stb -unit.2.0.waveform.posn.31.radix=1 -unit.2.0.waveform.posn.31.type=signal -unit.2.0.waveform.posn.310.channel=2147483646 -unit.2.0.waveform.posn.310.name=x -unit.2.0.waveform.posn.310.radix=1 -unit.2.0.waveform.posn.310.type=bus -unit.2.0.waveform.posn.311.channel=2147483646 -unit.2.0.waveform.posn.311.name=x -unit.2.0.waveform.posn.311.radix=1 -unit.2.0.waveform.posn.311.type=bus -unit.2.0.waveform.posn.312.channel=2147483646 -unit.2.0.waveform.posn.312.name=x -unit.2.0.waveform.posn.312.radix=1 -unit.2.0.waveform.posn.312.type=bus -unit.2.0.waveform.posn.313.channel=2147483646 -unit.2.0.waveform.posn.313.name=x -unit.2.0.waveform.posn.313.radix=1 -unit.2.0.waveform.posn.313.type=bus -unit.2.0.waveform.posn.314.channel=2147483646 -unit.2.0.waveform.posn.314.name=x -unit.2.0.waveform.posn.314.radix=1 -unit.2.0.waveform.posn.314.type=bus -unit.2.0.waveform.posn.315.channel=2147483646 -unit.2.0.waveform.posn.315.name=x -unit.2.0.waveform.posn.315.radix=1 -unit.2.0.waveform.posn.315.type=bus -unit.2.0.waveform.posn.316.channel=2147483646 -unit.2.0.waveform.posn.316.name=y -unit.2.0.waveform.posn.316.radix=1 -unit.2.0.waveform.posn.316.type=bus -unit.2.0.waveform.posn.32.channel=187 -unit.2.0.waveform.posn.32.name=ace_ack -unit.2.0.waveform.posn.32.radix=1 -unit.2.0.waveform.posn.32.type=signal -unit.2.0.waveform.posn.33.channel=188 -unit.2.0.waveform.posn.33.name=aceusb_oe_n_ -unit.2.0.waveform.posn.33.radix=1 -unit.2.0.waveform.posn.33.type=signal -unit.2.0.waveform.posn.34.channel=189 -unit.2.0.waveform.posn.34.name=aceusb_we_n -unit.2.0.waveform.posn.34.radix=1 -unit.2.0.waveform.posn.34.type=signal -unit.2.0.waveform.posn.35.channel=190 -unit.2.0.waveform.posn.35.name=ace_mpce_n_ -unit.2.0.waveform.posn.35.radix=1 -unit.2.0.waveform.posn.35.type=signal -unit.2.0.waveform.posn.36.channel=2147483646 -unit.2.0.waveform.posn.36.name=aceusb_d_ -unit.2.0.waveform.posn.36.radix=1 -unit.2.0.waveform.posn.36.type=bus -unit.2.0.waveform.posn.37.channel=214 -unit.2.0.waveform.posn.37.name=rx_output -unit.2.0.waveform.posn.37.radix=1 -unit.2.0.waveform.posn.37.type=signal -unit.2.0.waveform.posn.38.channel=207 -unit.2.0.waveform.posn.38.name=iid -unit.2.0.waveform.posn.38.radix=1 -unit.2.0.waveform.posn.38.type=signal -unit.2.0.waveform.posn.39.channel=208 -unit.2.0.waveform.posn.39.name=irr0 -unit.2.0.waveform.posn.39.radix=1 -unit.2.0.waveform.posn.39.type=signal -unit.2.0.waveform.posn.4.channel=2147483646 -unit.2.0.waveform.posn.4.name=state -unit.2.0.waveform.posn.4.radix=1 -unit.2.0.waveform.posn.4.type=bus -unit.2.0.waveform.posn.40.channel=209 -unit.2.0.waveform.posn.40.name=irr1 -unit.2.0.waveform.posn.40.radix=1 -unit.2.0.waveform.posn.40.type=signal -unit.2.0.waveform.posn.41.channel=210 -unit.2.0.waveform.posn.41.name=int0 -unit.2.0.waveform.posn.41.radix=1 -unit.2.0.waveform.posn.41.type=signal -unit.2.0.waveform.posn.42.channel=211 -unit.2.0.waveform.posn.42.name=int1 -unit.2.0.waveform.posn.42.radix=1 -unit.2.0.waveform.posn.42.type=signal -unit.2.0.waveform.posn.43.channel=212 -unit.2.0.waveform.posn.43.name=released -unit.2.0.waveform.posn.43.radix=1 -unit.2.0.waveform.posn.43.type=signal -unit.2.0.waveform.posn.44.channel=213 -unit.2.0.waveform.posn.44.name=rx_shift -unit.2.0.waveform.posn.44.radix=1 -unit.2.0.waveform.posn.44.type=signal -unit.2.0.waveform.posn.45.channel=2147483646 -unit.2.0.waveform.posn.45.name=x -unit.2.0.waveform.posn.45.radix=1 -unit.2.0.waveform.posn.45.type=bus -unit.2.0.waveform.posn.46.channel=2147483646 -unit.2.0.waveform.posn.46.name=x -unit.2.0.waveform.posn.46.radix=1 -unit.2.0.waveform.posn.46.type=bus -unit.2.0.waveform.posn.47.channel=2147483646 -unit.2.0.waveform.posn.47.name=x -unit.2.0.waveform.posn.47.radix=1 -unit.2.0.waveform.posn.47.type=bus -unit.2.0.waveform.posn.48.channel=2147483646 -unit.2.0.waveform.posn.48.name=x -unit.2.0.waveform.posn.48.radix=1 -unit.2.0.waveform.posn.48.type=bus -unit.2.0.waveform.posn.49.channel=2147483646 -unit.2.0.waveform.posn.49.name=x -unit.2.0.waveform.posn.49.radix=1 -unit.2.0.waveform.posn.49.type=bus -unit.2.0.waveform.posn.5.channel=2147483646 -unit.2.0.waveform.posn.5.name=flags -unit.2.0.waveform.posn.5.radix=1 -unit.2.0.waveform.posn.5.type=bus -unit.2.0.waveform.posn.50.channel=2147483646 -unit.2.0.waveform.posn.50.name=x -unit.2.0.waveform.posn.50.radix=1 -unit.2.0.waveform.posn.50.type=bus -unit.2.0.waveform.posn.51.channel=2147483646 -unit.2.0.waveform.posn.51.name=x -unit.2.0.waveform.posn.51.radix=1 -unit.2.0.waveform.posn.51.type=bus -unit.2.0.waveform.posn.52.channel=2147483646 -unit.2.0.waveform.posn.52.name=x -unit.2.0.waveform.posn.52.radix=1 -unit.2.0.waveform.posn.52.type=bus -unit.2.0.waveform.posn.53.channel=2147483646 -unit.2.0.waveform.posn.53.name=x -unit.2.0.waveform.posn.53.radix=1 -unit.2.0.waveform.posn.53.type=bus -unit.2.0.waveform.posn.54.channel=2147483646 -unit.2.0.waveform.posn.54.name=x -unit.2.0.waveform.posn.54.radix=1 -unit.2.0.waveform.posn.54.type=bus -unit.2.0.waveform.posn.55.channel=2147483646 -unit.2.0.waveform.posn.55.name=x -unit.2.0.waveform.posn.55.radix=1 -unit.2.0.waveform.posn.55.type=bus -unit.2.0.waveform.posn.56.channel=2147483646 -unit.2.0.waveform.posn.56.name=x -unit.2.0.waveform.posn.56.radix=1 -unit.2.0.waveform.posn.56.type=bus -unit.2.0.waveform.posn.57.channel=2147483646 -unit.2.0.waveform.posn.57.name=x -unit.2.0.waveform.posn.57.radix=1 -unit.2.0.waveform.posn.57.type=bus -unit.2.0.waveform.posn.58.channel=2147483646 -unit.2.0.waveform.posn.58.name=x -unit.2.0.waveform.posn.58.radix=1 -unit.2.0.waveform.posn.58.type=bus -unit.2.0.waveform.posn.59.channel=2147483646 -unit.2.0.waveform.posn.59.name=x -unit.2.0.waveform.posn.59.radix=1 -unit.2.0.waveform.posn.59.type=bus -unit.2.0.waveform.posn.6.channel=2147483646 -unit.2.0.waveform.posn.6.name=next_state -unit.2.0.waveform.posn.6.radix=1 -unit.2.0.waveform.posn.6.type=bus -unit.2.0.waveform.posn.60.channel=2147483646 -unit.2.0.waveform.posn.60.name=x -unit.2.0.waveform.posn.60.radix=1 -unit.2.0.waveform.posn.60.type=bus -unit.2.0.waveform.posn.61.channel=2147483646 -unit.2.0.waveform.posn.61.name=x -unit.2.0.waveform.posn.61.radix=1 -unit.2.0.waveform.posn.61.type=bus -unit.2.0.waveform.posn.62.channel=2147483646 -unit.2.0.waveform.posn.62.name=x -unit.2.0.waveform.posn.62.radix=1 -unit.2.0.waveform.posn.62.type=bus -unit.2.0.waveform.posn.63.channel=2147483646 -unit.2.0.waveform.posn.63.name=x -unit.2.0.waveform.posn.63.radix=1 -unit.2.0.waveform.posn.63.type=bus -unit.2.0.waveform.posn.64.channel=2147483646 -unit.2.0.waveform.posn.64.name=x -unit.2.0.waveform.posn.64.radix=1 -unit.2.0.waveform.posn.64.type=bus -unit.2.0.waveform.posn.65.channel=2147483646 -unit.2.0.waveform.posn.65.name=x -unit.2.0.waveform.posn.65.radix=1 -unit.2.0.waveform.posn.65.type=bus -unit.2.0.waveform.posn.66.channel=2147483646 -unit.2.0.waveform.posn.66.name=x -unit.2.0.waveform.posn.66.radix=1 -unit.2.0.waveform.posn.66.type=bus -unit.2.0.waveform.posn.67.channel=2147483646 -unit.2.0.waveform.posn.67.name=x -unit.2.0.waveform.posn.67.radix=1 -unit.2.0.waveform.posn.67.type=bus -unit.2.0.waveform.posn.68.channel=2147483646 -unit.2.0.waveform.posn.68.name=x -unit.2.0.waveform.posn.68.radix=1 -unit.2.0.waveform.posn.68.type=bus -unit.2.0.waveform.posn.69.channel=2147483646 -unit.2.0.waveform.posn.69.name=x -unit.2.0.waveform.posn.69.radix=1 -unit.2.0.waveform.posn.69.type=bus -unit.2.0.waveform.posn.7.channel=2147483646 -unit.2.0.waveform.posn.7.name=func -unit.2.0.waveform.posn.7.radix=1 -unit.2.0.waveform.posn.7.type=bus -unit.2.0.waveform.posn.70.channel=2147483646 -unit.2.0.waveform.posn.70.name=x -unit.2.0.waveform.posn.70.radix=1 -unit.2.0.waveform.posn.70.type=bus -unit.2.0.waveform.posn.71.channel=2147483646 -unit.2.0.waveform.posn.71.name=x -unit.2.0.waveform.posn.71.radix=1 -unit.2.0.waveform.posn.71.type=bus -unit.2.0.waveform.posn.72.channel=2147483646 -unit.2.0.waveform.posn.72.name=x -unit.2.0.waveform.posn.72.radix=1 -unit.2.0.waveform.posn.72.type=bus -unit.2.0.waveform.posn.73.channel=2147483646 -unit.2.0.waveform.posn.73.name=x -unit.2.0.waveform.posn.73.radix=1 -unit.2.0.waveform.posn.73.type=bus -unit.2.0.waveform.posn.74.channel=2147483646 -unit.2.0.waveform.posn.74.name=x -unit.2.0.waveform.posn.74.radix=1 -unit.2.0.waveform.posn.74.type=bus -unit.2.0.waveform.posn.75.channel=2147483646 -unit.2.0.waveform.posn.75.name=x -unit.2.0.waveform.posn.75.radix=1 -unit.2.0.waveform.posn.75.type=bus -unit.2.0.waveform.posn.76.channel=2147483646 -unit.2.0.waveform.posn.76.name=x -unit.2.0.waveform.posn.76.radix=1 -unit.2.0.waveform.posn.76.type=bus -unit.2.0.waveform.posn.77.channel=2147483646 -unit.2.0.waveform.posn.77.name=x -unit.2.0.waveform.posn.77.radix=1 -unit.2.0.waveform.posn.77.type=bus -unit.2.0.waveform.posn.78.channel=2147483646 -unit.2.0.waveform.posn.78.name=x -unit.2.0.waveform.posn.78.radix=1 -unit.2.0.waveform.posn.78.type=bus -unit.2.0.waveform.posn.79.channel=2147483646 -unit.2.0.waveform.posn.79.name=x -unit.2.0.waveform.posn.79.radix=1 -unit.2.0.waveform.posn.79.type=bus -unit.2.0.waveform.posn.8.channel=2147483646 -unit.2.0.waveform.posn.8.name=t -unit.2.0.waveform.posn.8.radix=1 -unit.2.0.waveform.posn.8.type=bus -unit.2.0.waveform.posn.80.channel=2147483646 -unit.2.0.waveform.posn.80.name=x -unit.2.0.waveform.posn.80.radix=1 -unit.2.0.waveform.posn.80.type=bus -unit.2.0.waveform.posn.81.channel=2147483646 -unit.2.0.waveform.posn.81.name=x -unit.2.0.waveform.posn.81.radix=1 -unit.2.0.waveform.posn.81.type=bus -unit.2.0.waveform.posn.82.channel=2147483646 -unit.2.0.waveform.posn.82.name=x -unit.2.0.waveform.posn.82.radix=1 -unit.2.0.waveform.posn.82.type=bus -unit.2.0.waveform.posn.83.channel=2147483646 -unit.2.0.waveform.posn.83.name=x -unit.2.0.waveform.posn.83.radix=1 -unit.2.0.waveform.posn.83.type=bus -unit.2.0.waveform.posn.84.channel=2147483646 -unit.2.0.waveform.posn.84.name=x -unit.2.0.waveform.posn.84.radix=1 -unit.2.0.waveform.posn.84.type=bus -unit.2.0.waveform.posn.85.channel=2147483646 -unit.2.0.waveform.posn.85.name=x -unit.2.0.waveform.posn.85.radix=1 -unit.2.0.waveform.posn.85.type=bus -unit.2.0.waveform.posn.86.channel=2147483646 -unit.2.0.waveform.posn.86.name=x -unit.2.0.waveform.posn.86.radix=1 -unit.2.0.waveform.posn.86.type=bus -unit.2.0.waveform.posn.87.channel=2147483646 -unit.2.0.waveform.posn.87.name=x -unit.2.0.waveform.posn.87.radix=1 -unit.2.0.waveform.posn.87.type=bus -unit.2.0.waveform.posn.88.channel=2147483646 -unit.2.0.waveform.posn.88.name=x -unit.2.0.waveform.posn.88.radix=1 -unit.2.0.waveform.posn.88.type=bus -unit.2.0.waveform.posn.89.channel=2147483646 -unit.2.0.waveform.posn.89.name=x -unit.2.0.waveform.posn.89.radix=1 -unit.2.0.waveform.posn.89.type=bus -unit.2.0.waveform.posn.9.channel=2147483646 -unit.2.0.waveform.posn.9.name=adr -unit.2.0.waveform.posn.9.radix=1 -unit.2.0.waveform.posn.9.type=bus -unit.2.0.waveform.posn.90.channel=2147483646 -unit.2.0.waveform.posn.90.name=x -unit.2.0.waveform.posn.90.radix=1 -unit.2.0.waveform.posn.90.type=bus -unit.2.0.waveform.posn.91.channel=2147483646 -unit.2.0.waveform.posn.91.name=x -unit.2.0.waveform.posn.91.radix=1 -unit.2.0.waveform.posn.91.type=bus -unit.2.0.waveform.posn.92.channel=2147483646 -unit.2.0.waveform.posn.92.name=x -unit.2.0.waveform.posn.92.radix=1 -unit.2.0.waveform.posn.92.type=bus -unit.2.0.waveform.posn.93.channel=2147483646 -unit.2.0.waveform.posn.93.name=x -unit.2.0.waveform.posn.93.radix=1 -unit.2.0.waveform.posn.93.type=bus -unit.2.0.waveform.posn.94.channel=2147483646 -unit.2.0.waveform.posn.94.name=x -unit.2.0.waveform.posn.94.radix=1 -unit.2.0.waveform.posn.94.type=bus -unit.2.0.waveform.posn.95.channel=2147483646 -unit.2.0.waveform.posn.95.name=x -unit.2.0.waveform.posn.95.radix=1 -unit.2.0.waveform.posn.95.type=bus -unit.2.0.waveform.posn.96.channel=2147483646 -unit.2.0.waveform.posn.96.name=x -unit.2.0.waveform.posn.96.radix=1 -unit.2.0.waveform.posn.96.type=bus -unit.2.0.waveform.posn.97.channel=2147483646 -unit.2.0.waveform.posn.97.name=x -unit.2.0.waveform.posn.97.radix=1 -unit.2.0.waveform.posn.97.type=bus -unit.2.0.waveform.posn.98.channel=2147483646 -unit.2.0.waveform.posn.98.name=x -unit.2.0.waveform.posn.98.radix=1 -unit.2.0.waveform.posn.98.type=bus -unit.2.0.waveform.posn.99.channel=2147483646 -unit.2.0.waveform.posn.99.name=x -unit.2.0.waveform.posn.99.radix=1 -unit.2.0.waveform.posn.99.type=bus Index: trunk/impl/virtex4-ml403ep/test/ml403-flash.ucf =================================================================== --- trunk/impl/virtex4-ml403ep/test/ml403-flash.ucf (revision 53) +++ trunk/impl/virtex4-ml403ep/test/ml403-flash.ucf (nonexistent) @@ -1,56 +0,0 @@ -NET sys_clk_in TNM_NET = "sys_clk_in"; -TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; - -NET sys_clk_in LOC = AE14; -NET sys_clk_in IOSTANDARD = LVCMOS33; - -NET trx LOC = W1; - -#NET flash_addr[24] LOC = T21; -#NET flash_addr[23] LOC = U20; -#NET flash_addr[22] LOC = T19; -NET flash_addr[20] LOC = AC5; -NET flash_addr[19] LOC = AB5; -NET flash_addr[18] LOC = AC4; -NET flash_addr[17] LOC = AB4; -NET flash_addr[16] LOC = AB3; -NET flash_addr[15] LOC = AA4; -NET flash_addr[14] LOC = AA3; -NET flash_addr[13] LOC = W5; -NET flash_addr[12] LOC = W6; -NET flash_addr[11] LOC = W3; -NET flash_addr[10] LOC = AF3; -NET flash_addr[9] LOC = AE3; -NET flash_addr[8] LOC = AD2; -NET flash_addr[7] LOC = AD1; -NET flash_addr[6] LOC = AC2; -NET flash_addr[5] LOC = AC1; -NET flash_addr[4] LOC = AB2; -NET flash_addr[3] LOC = AB1; -NET flash_addr[2] LOC = AA1; -NET flash_addr[1] LOC = Y2; -NET flash_addr[0] LOC = Y1; -#NET flash_addr[0] LOC = T20; - -NET flash_data[15] LOC = AA14; -NET flash_data[14] LOC = AB14; -NET flash_data[13] LOC = AC12; -NET flash_data[12] LOC = AC11; -NET flash_data[11] LOC = AA16; -NET flash_data[10] LOC = AA15; -NET flash_data[9] LOC = AB13; -NET flash_data[8] LOC = AA13; -NET flash_data[7] LOC = AC14; -NET flash_data[6] LOC = AD14; -NET flash_data[5] LOC = AA12; -NET flash_data[4] LOC = AA11; -NET flash_data[3] LOC = AC16; -NET flash_data[2] LOC = AC15; -NET flash_data[1] LOC = AC13; -NET flash_data[0] LOC = AD13; - -NET flash_oe_n LOC = AC6; -NET flash_we_n LOC = AB6; -#NET flash_byte_n LOC = N22; -NET flash_ce2 LOC = W7; -#NET flash_audio_reset_n LOC = AD10; Index: trunk/impl/virtex4-ml403ep/test/flash_dump.v =================================================================== --- trunk/impl/virtex4-ml403ep/test/flash_dump.v (revision 53) +++ trunk/impl/virtex4-ml403ep/test/flash_dump.v (nonexistent) @@ -1,150 +0,0 @@ -//`define HIGH_BIOS 13'h0000 -`define HIGH_BIOS 13'h00FF - -module flash_dump ( - input sys_clk_in, - output trx, - - output [20:0] flash_addr, - input [15:0] flash_data, - output flash_we_n, - output flash_oe_n, - output flash_ce2 - ); - - reg clk_9600; - reg [11:0] count_uart; - reg [ 6:0] dada_wr; - reg [ 7:0] estat; - reg [ 7:0] addr; - reg [ 2:0] espacios; - reg [ 6:0] char; - reg [ 3:0] nibble; - reg [ 7:0] col; - reg trx_req; - reg [ 7:0] adr0; - - wire clk_60M; - wire rst, lock; - wire trx_ack; - wire [15:0] rd_data; - - reg [15:0] ram[0:255]; - reg [15:0] dades; - - reg [ 3:0] count; - - // Instanciacions de mòduls - clocks c0 ( - .CLKIN_IN (sys_clk_in), - .CLKFX_OUT (clk_60M), - .LOCKED_OUT (lock) - ); - - uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx, - rst, clk_9600); - - // Assignacions contínues - assign rst = ~lock; - - assign flash_addr = { `HIGH_BIOS, adr0 }; - assign rd_data = flash_data; - assign flash_we_n = 1'b1; - assign flash_oe_n = 1'b0; - assign flash_ce2 = 1'b1; - - // Descripció del comportament - // count_uart - always @(posedge clk_60M) - if (rst) count_uart <= 12'h0; - else count_uart <= (count_uart==12'd3124) ? - 12'd0 : count_uart + 12'd1; - - // clk_9600 - always @(posedge clk_60M) - if (rst) clk_9600 <= 1'b0; - else clk_9600 <= (count_uart==12'd0) ? - !clk_9600 : clk_9600; - - // adr0 - always @(posedge clk_60M) - if (rst) adr0 <= 8'h00; - else adr0 <= (adr0==8'hff || count!=4'hf) ? adr0 - : (adr0 + 8'h01); - // count - always @(posedge clk_60M) - if (rst) count <= 4'h0; - else count <= count + 4'h1; - - // ram - always @(posedge clk_60M) ram[adr0] <= rd_data; - - // dades - always @(posedge clk_60M) - if (rst) dades <= 16'h0; - else dades <= ram[addr]; - - always @(posedge clk_60M) - if (adr0!=8'hff) - begin - dada_wr <= 7'h30; - trx_req <= 0; - estat <= 8'd0; - addr <= 8'h00; - espacios <= 3'd2; - char <= 7'd00; - nibble <= 4'd0; - col <= 8'd79; - end - else - case (estat) - 8'd00: if (~trx_ack) - begin estat <= 8'd01; - if (espacios > 3'd0) - begin char <= 7'h20; espacios <= espacios - 3'd1; end - else - begin - char <= ascii(nibble); espacios <= 3'd4; - nibble <= nibble + 4'd1; - end - end - 8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end - 8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end - 8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end - else estat <= 8'd04; - - 8'd04: if (~trx_ack) estat <= 8'd05; - 8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end - 8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end - - 8'd15: if (~trx_ack) estat <= 8'd20; - 8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end - 8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end - - 8'd30: if (~trx_ack) estat <= 8'd35; - 8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end - 8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end - - 8'd45: if (~trx_ack) estat <= 8'd50; - 8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end - 8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end - - 8'd60: if (~trx_ack) estat <= 8'd65; - 8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end - 8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end - - 8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90; - else if (~trx_ack) estat <= 8'd80; - 8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end - 8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end - - 8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end - else estat <= 8'd95; - 8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15; - endcase - - function [6:0] ascii(input [3:0] num); - if (num <= 4'd9) ascii = 7'h30 + num; - else ascii = 7'd87 + num; - endfunction -endmodule Index: trunk/boards/virtex4-ml403ep/sim/t.do =================================================================== --- trunk/boards/virtex4-ml403ep/sim/t.do (nonexistent) +++ trunk/boards/virtex4-ml403ep/sim/t.do (revision 54) @@ -0,0 +1,72 @@ +quit -sim +vdel -all -lib work +vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims +vlib work +vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../../../soc/aceusb/rtl/aceusb_access.v ../../../soc/timer.v ../../../soc/simple_pic.v ../../../soc/aceusb/rtl/aceusb_sync.v ../../../soc/aceusb/rtl/aceusb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v +vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v +vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl +add wave -label clk100 /testbench/clk +add wave -label clk /testbench/kotku/zet_proc/wb_clk_i +add wave -label rst /testbench/kotku/rst +add wave -label pc -radix hexadecimal /testbench/kotku/zet_proc/fetch0/pc +add wave -divider fetch +add wave -label state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/state +add wave -label next_state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/next_state +add wave -label opcode -radix hexadecimal /testbench/kotku/zet_proc/fetch0/opcode +add wave -label modrm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/modrm +add wave -label seq_addr /testbench/kotku/zet_proc/fetch0/decode0/seq_addr +add wave -label end_seq /testbench/kotku/zet_proc/fetch0/end_seq +add wave -label need_modrm /testbench/kotku/zet_proc/fetch0/need_modrm +add wave -label need_off /testbench/kotku/zet_proc/fetch0/need_off +add wave -label off_size /testbench/kotku/zet_proc/fetch0/off_size +add wave -label need_imm /testbench/kotku/zet_proc/fetch0/need_imm +add wave -label imm_size /testbench/kotku/zet_proc/fetch0/imm_size +add wave -label ir /testbench/kotku/zet_proc/fetch0/ir +add wave -label imm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/imm +add wave -label off -radix hexadecimal /testbench/kotku/zet_proc/fetch0/off +add wave -divider regfile +add wave -label ax -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[0\] +add wave -label cx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\] +add wave -label dx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[2\] +add wave -label si -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[6\] +add wave -label tmp -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[13\] +add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d\[15:0\] +add wave -label wr -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/wr +add wave -divider wb_master +add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs +add wave -label ns -radix hexadecimal /testbench/kotku/zet_proc/wm0/ns +add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op +add wave -label wb_block /testbench/kotku/zet_proc/wb_block +add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o +add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i +add wave -label adr -radix hexadecimal /testbench/kotku/adr +add wave -label odd_word -radix hexadecimal /testbench/kotku/zet_proc/wm0/odd_word +add wave -label byte_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_byte_o +add wave -label sel_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_sel_o +add wave -label stb_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_stb_o +add wave -label cyc_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_cyc_o +add wave -label ack_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_ack_i +add wave -label we_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_we_o +add wave -label tga_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_tga_o +add wave -label cpu_dat_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_dat_i +add wave -divider flash +add wave -radix hexadecimal /sf_addr +add wave -radix hexadecimal /sf_data +add wave -radix hexadecimal /sf_oe +add wave -radix hexadecimal /sf_we +add wave -radix hexadecimal /f_ce +add wave -divider alu +add wave -label x -radix hexadecimal /testbench/kotku/zet_proc/exec0/a +add wave -label y -radix hexadecimal /testbench/kotku/zet_proc/exec0/bus_b +add wave -label t -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/t +add wave -label func -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/func +add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d +add wave -label addr_a /testbench/kotku/zet_proc/exec0/reg0/addr_a +add wave -label addr_d /testbench/kotku/zet_proc/exec0/reg0/addr_d +add wave -label wr /testbench/kotku/zet_proc/exec0/reg0/wr +add wave -label we /testbench/kotku/we +add wave -label ack /testbench/kotku/ack +add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec +add wave -divider zbt +add wave -radix hexadecimal -r /testbench/kotku/zbt0/* +run 50us Index: trunk/boards/virtex4-ml403ep/sim/flash_stub.v =================================================================== --- trunk/boards/virtex4-ml403ep/sim/flash_stub.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/sim/flash_stub.v (revision 54) @@ -0,0 +1,26 @@ +`timescale 1ns/10ps + +module flash_stub ( + input [20:0] flash_addr_, + output [31:0] flash_data_, + input flash_oe_n_, + input flash_we_n_, + input flash_ce2_ + ); + + // Registers and nets + reg [31:0] rom[2**21-1:0]; + reg [31:0] dat_o; + + // Continous assignments + assign flash_data_ = flash_ce2_ ? dat_o : 32'hzzzzzzzz; + + // Behaviour + initial $readmemh("00_mov.ml403", rom, 21'h0); + initial $readmemh("hd.ml403", rom, 21'h100000); + + always @(*) dat_o <= #110 + (!flash_oe_n_ & flash_we_n_ & flash_ce2_) ? + rom[flash_addr_] : 32'hzzzzzzzz; + +endmodule Index: trunk/boards/virtex4-ml403ep/sim/test_kotku.v =================================================================== --- trunk/boards/virtex4-ml403ep/sim/test_kotku.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/sim/test_kotku.v (revision 54) @@ -0,0 +1,102 @@ +`timescale 1ns/10ps + +module testbench; + + // Net and register declarations + wire lcd_clk; + wire [ 1:0] lcd_r, lcd_g, lcd_b; + wire lcd_hsync; + wire lcd_vsync; + reg clk; + reg but; + reg ace_clk; + wire s_clk; + wire [20:0] sf_addr; + wire [31:0] sf_data; + wire sf_oe; + wire sf_we; + wire [ 3:0] s_bw; + wire s_ce; + wire s_adv; + wire f_ce; + + wire [ 6:1] aceusb_a_; + wire [15:0] aceusb_d_; + wire aceusb_oe_n_; + wire aceusb_we_n_; + wire ace_mpce_n_; + wire usb_cs_n_; + wire usb_hpi_reset_n_; + + // Module instances + kotku_ml403 kotku ( + .tft_lcd_clk_ (lcd_clk), + .tft_lcd_r_ (lcd_r), + .tft_lcd_g_ (lcd_g), + .tft_lcd_b_ (lcd_b), + .tft_lcd_hsync_ (lcd_hsync), + .tft_lcd_vsync_ (lcd_vsync), + + .sys_clk_in_ (clk), + + .sram_clk_ (s_clk), + .sram_flash_addr_ (sf_addr), + .sram_flash_data_ (sf_data), + .sram_flash_oe_n_ (sf_oe), + .sram_flash_we_n_ (sf_we), + .sram_bw_ (s_bw), + .sram_cen_ (s_ce), + .sram_adv_ld_n_ (s_adv), + .flash_ce2_ (f_ce), + + .aceusb_a_ (aceusb_a_), + .aceusb_d_ (aceusb_d_), + .aceusb_oe_n_ (aceusb_oe_n_), + .aceusb_we_n_ (aceusb_we_n_), + + .ace_clkin_ (ace_clk), + .ace_mpce_n_ (ace_mpce_n_), + + .usb_cs_n_ (usb_cs_n_), + .usb_hpi_reset_n_ (usb_hpi_reset_n_) + ); + + flash_stub fs0 ( + .flash_addr_ (sf_addr), + .flash_data_ (sf_data), + .flash_oe_n_ (sf_oe), + .flash_we_n_ (sf_we), + .flash_ce2_ (f_ce) + ); + + cy7c1354 zbt ( + .d (sf_data), + .clk (s_clk), + .a (sf_addr[17:0]), + .bws (s_bw), + .we_b (sf_we), + .adv_lb (s_adv), + .ce1b (s_ce), + .ce2 (1'b1), + .ce3b (1'b0), + .oeb (sf_oe), + .cenb (1'b0), + .mode (1'b0) + ); + + // Behaviour + // Clock generation + always #5 clk = ~clk; + always #15 ace_clk = ~ace_clk; + + initial + begin + clk <= 1'b0; + ace_clk <= 1'b0; + but <= 1'b0; + #100000 but <= 1'b1; + #700000 but <= 1'b0; + #700000 but <= 1'b1; + end + +endmodule Index: trunk/boards/virtex4-ml403ep/sim/s.do =================================================================== --- trunk/boards/virtex4-ml403ep/sim/s.do (nonexistent) +++ trunk/boards/virtex4-ml403ep/sim/s.do (revision 54) @@ -0,0 +1,48 @@ +vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl +add wave -label clk100 /testbench/clk +add wave -label clk /testbench/kotku/clk +add wave -label rst /testbench/kotku/rst +add wave -label pc -radix hexadecimal /testbench/kotku/zet_proc/fetch0/pc +add wave -divider fetch +add wave -label state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/state +add wave -label next_state -radix hexadecimal /testbench/kotku/zet_proc/fetch0/next_state +add wave -label opcode -radix hexadecimal /testbench/kotku/zet_proc/fetch0/opcode +add wave -label modrm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/modrm +add wave -label seq_addr /testbench/kotku/zet_proc/fetch0/decode0/seq_addr +add wave -label end_seq /testbench/kotku/zet_proc/fetch0/end_seq +add wave -label need_modrm /testbench/kotku/zet_proc/fetch0/need_modrm +add wave -label need_off /testbench/kotku/zet_proc/fetch0/need_off +add wave -label need_imm /testbench/kotku/zet_proc/fetch0/need_imm +add wave -label ir /testbench/kotku/zet_proc/fetch0/ir +add wave -label imm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/imm +add wave -label off -radix hexadecimal /testbench/kotku/zet_proc/fetch0/off +add wave -divider mem +add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs +add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op +add wave -label block /testbench/kotku/zet_proc/wm0/cpu_block +add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o +add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i +add wave -label adr -radix hexadecimal /testbench/kotku/adr +add wave -label byte_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_byte_o +add wave -label sel_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_sel_o +add wave -label stb_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_stb_o +add wave -label cyc_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_cyc_o +add wave -label ack_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_ack_i +add wave -label we_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_we_o +add wave -label tga_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_tga_o +add wave -label cpu_dat_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_dat_i +add wave -divider alu +add wave -label x -radix hexadecimal /testbench/kotku/zet_proc/exec0/a +add wave -label y -radix hexadecimal /testbench/kotku/zet_proc/exec0/bus_b +add wave -label t -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/t +add wave -label func -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/func +add wave -label r\[1\] -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\] +add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d +add wave -label addr_a /testbench/kotku/zet_proc/exec0/reg0/addr_a +add wave -label addr_d /testbench/kotku/zet_proc/exec0/reg0/addr_d +add wave -label wr /testbench/kotku/zet_proc/exec0/reg0/wr +add wave -label we /testbench/kotku/we +add wave -label ack /testbench/kotku/ack +add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec +add memory /testbench/zbt/mem +run 3ms Index: trunk/boards/virtex4-ml403ep/sim/CY7C1354BV25.v =================================================================== --- trunk/boards/virtex4-ml403ep/sim/CY7C1354BV25.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/sim/CY7C1354BV25.v (revision 54) @@ -0,0 +1,487 @@ +//************************************************************************ +//************************************************************************ +//** This model is the property of Cypress Semiconductor Corp and is ** +//** protected by the US copyright laws, any unauthorized copying and ** +//** distribution is prohibited. Cypress reserves the right to change ** +//** any of the functional specifications without any prior notice. ** +//** Cypress is not liable for any damages which may result from the ** +//** use of this functional model. ** +//** ** +//** File Name : CY7C1354BV25 ** +//** ** +//** Revision : 1.1 - 01/30/2004 ** +//** ** +//** The timings are to be selected by the user depending upon the ** +//** frequency of operation from the datasheet. ** +//** ** +//** Model : CY7C1354BV25 - 256K x 36 NoBL Pipelined SRAM ** +//** Queries : MPD Applications ** +//** e-mail: mpd_apps@cypress.com ** +//************************************************************************ +//************************************************************************ + +`timescale 1ns / 10ps + +// NOTE : Any setup/hold errors will force input signal to x state +// or if results indeterminant (write addr) core is reset x + +// define fixed values + +`define wordsize (36 -1) // +`define no_words (262144 -1) // 256K x 36 RAM + +module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); + +inout [31:0] d; +input clk, // clock input (R) + we_b, // byte write enable(L) + adv_lb, // burst(H)/load(L) address + ce1b, // chip enable(L) + ce2, // chip enable(H) + ce3b, // chip enable(L) + oeb, // async output enable(L)(read) + cenb, // clock enable(L) + mode; // interleave(H)/linear(L) burst +input [3:0] bws; // byte write select(L) +input [18:0] a; // address bus + +// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** +// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** + +//********************************************************************** +// This model is configured for 166 MHz Operation (CY7C1354-166). +//********************************************************************** + `define teohz #3.5 + `define teolz #0 + `define tchz #3.5 + `define tclz #1.5 + + `define tco #3.5 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 + +/********************************************************************** +// Timings for 225MHz +//********************************************************************** + `define teohz #2.8 + `define teolz #0 + `define tchz #2.8 + `define tclz #1.25 + + `define tco #2.8 + `define tdoh #1.25 + + `define tas 1.4 + `define tah 0.4 + +//*********************************************************************** +// Timings for 200MHz +//********************************************************************** + `define teohz #3.2 + `define teolz #0 + `define tchz #3.2 + `define tclz #1.5 + + `define tco #3.2 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 +***********************************************************************/ + +reg notifier; // error support reg's +reg noti1_0; +reg noti1_1; +reg noti1_2; +reg noti1_3; +reg noti1_4; +reg noti1_5; +reg noti1_6; +reg noti2; + + +wire chipen; // combined chip enable (high for an active chip) + +reg chipen_d; // _d = delayed +reg chipen_o; // _o = operational = delayed sig or _d sig + +wire writestate; // holds 1 if any of writebus is low +reg writestate_d; +reg writestate_o; + +wire loadcyc; // holds 1 for load cycles (setup and hold checks) +wire writecyc; // holds 1 for write cycles (setup and hold checks) +wire [3:0] bws; // holds the bws values + +wire [3:0] writebusb; // holds the "internal" bws bus based on we_b +reg [3:0] writebusb_d; +reg [3:0] writebusb_o; + +wire [2:0] operation; // holds chipen, adv_ld and writestate +reg [2:0] operation_d; +reg [2:0] operation_o; + +wire [17:0] a; // address input bus +reg [17:0] a_d; +reg [17:0] a_o; + +reg [`wordsize:0] do; // data output reg +reg [`wordsize:0] di; // data input bus +reg [`wordsize:0] dd; // data delayed bus + +wire tristate; // tristate output (on a bytewise basis) when asserted +reg cetri; // register set by chip disable which sets the tristate +reg oetri; // register set by oe which sets the tristate +reg enable; // register to make the ram enabled when equal to 1 +reg [17:0] addreg; // register to hold the input address +reg [`wordsize:0] pipereg; // register for the output data + +reg [`wordsize:0] mem [0:`no_words]; // RAM array + +reg [`wordsize:0] writeword; // temporary holding register for the write data +reg burstinit; // register to hold a[0] for burst type +reg [18:0] i; // temporary register used to write to all mem locs. +reg writetri; // tristate +reg lw, bw; // pipelined write functions +reg we_bl; + + +wire [31:0] d = !tristate ? + {do[34:27],do[25:18],do[16:9],do[7:0]} + : 32'bz ; // data bus + +assign chipen = (adv_lb == 1 ) ? chipen_d : + ~ce1b & ce2 & ~ce3b ; + +assign writestate = ~& writebusb; + +assign operation = {chipen, adv_lb, writestate}; + +assign writebusb[3:0] = ( we_b ==0 & adv_lb ==0) ? bws[3:0]: + ( we_b ==1 & adv_lb ==0) ? 4'b1111 : + ( we_bl ==0 & adv_lb ==1) ? bws[3:0]: + ( we_bl ==1 & adv_lb ==1) ? 4'b1111 : + 4'bxxxx ; + +assign loadcyc = chipen & !cenb; + +assign writecyc = writestate_d & enable & ~cenb & chipen; // check + +assign tristate = cetri | writetri | oetri; + +pullup (mode); + +// formers for notices/errors etc +// +//$display("NOTICE : xxx :"); +//$display("WARNING : xxx :"); +//$display("ERROR *** : xxx :"); + + +// initialize the output to be tri-state, ram to be disabled + +initial + begin +// signals + + writetri = 0; + cetri = 1; + enable = 0; + lw = 0; + bw = 0; + +// error signals + + notifier = 0; + noti1_0 = 0; + noti1_1 = 0; + noti1_2 = 0; + noti1_3 = 0; + noti1_4 = 0; + noti1_5 = 0; + noti1_6 = 0; + noti2 = 0; + +end + + + +// asynchronous OE + +always @(oeb) +begin + if (oeb == 1) + oetri <= `teohz 1; + else + oetri <= `teolz 0; +end + +// *** SETUP / HOLD VIOLATIONS *** + +always @(noti2) +begin +$display("NOTICE : 020 : Data bus corruption"); + force d =36'bx; + #1; + release d; +end + +always @(noti1_0) +begin +$display("NOTICE : 010 : Byte write corruption"); + force bws = 4'bx; + #1; + release bws; +end + +always @(noti1_1) +begin +$display("NOTICE : 011 : Byte enable corruption"); + force we_b = 1'bx; + #1; + release we_b; +end + +always @(noti1_2) +begin +$display("NOTICE : 012 : CE1B corruption"); + force ce1b =1'bx; + #1; + release ce1b; +end + +always @(noti1_3) +begin +$display("NOTICE : 013 : CE2 corruption"); + force ce2 =1'bx; + #1; + release ce2; +end + +always @(noti1_4) +begin +$display("NOTICE : 014 : CE3B corruption"); + force ce3b =1'bx; + #1; + release ce3b; +end + +always @(noti1_5) +begin +$display("NOTICE : 015 : CENB corruption"); + force cenb =1'bx; + #1; + release cenb; +end + +always @(noti1_6) +begin +$display("NOTICE : 016 : ADV_LB corruption"); + force adv_lb = 1'bx; + #1; + release adv_lb; +end + +// synchronous functions from clk edge + +always @(posedge clk) +if (!cenb) +begin +#0.01; + // latch conditions on adv_lb + + if (adv_lb) + we_bl <= we_bl; + else + we_bl <= we_b; + + chipen_d <= chipen; + + + chipen_o <= chipen; + writestate_o <= writestate; + writestate_d <= writestate_o; + writebusb_o <= writebusb; + writebusb_d <= writebusb_o; + operation_o <= operation; + a_o <= a; + a_d <= a_o; + di = {1'b0,d[31:24], + 1'b0,d[23:16], + 1'b0,d[15:8], + 1'b0,d[7:0]}; + + // execute previously pipelined fns + + if (lw) begin + loadwrite; + lw =0; + end + + if (bw) begin + burstwrite; + bw =0; + end + + // decode input/piplined state + + casex (operation_o) + 3'b0?? : turnoff; + 3'b101 : setlw; + 3'b111 : setbw; + 3'b100 : loadread; + 3'b110 : burstread; + default : unknown; // output unknown values and display an error message + endcase + + do <= `tco pipereg; + +end + +// *** task section *** + +task read; +begin + if (enable) cetri <= `tclz 0; + do <= `tdoh 36'hx; + writetri <= `tchz 0; + pipereg = mem[addreg]; +end +endtask + +task write; +begin + if (enable) cetri <= `tclz 0; + writeword = mem[addreg]; // set up a word to hold the data for the current location + /* overwrite the current word for the bytes being written to */ + if (!writebusb_d[3]) writeword[35:27] = di[35:27]; + if (!writebusb_d[2]) writeword[26:18] = di[26:18]; + if (!writebusb_d[1]) writeword[17:9] = di[17:9]; + if (!writebusb_d[0]) writeword[8:0] = di[8:0]; + writeword = writeword & writeword; //convert z to x states + mem[addreg] = writeword; // store the new word into the memory location + //writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setlw; +begin + lw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setbw; +begin + bw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task loadread; +begin + burstinit = a_o[0]; + addreg = a_o; + enable = 1; + read; +end +endtask + +task loadwrite; +begin + burstinit = a_d[0]; + addreg = a_d; + enable = 1; + write; +end +endtask + +task burstread; +begin + burst; + read; +end +endtask + +task burstwrite; +begin + burst; + write; +end +endtask + +task unknown; +begin + do = 36'bx; + // $display ("Unknown function: Operation = %b\n", operation); +end +endtask + +task turnoff; +begin + enable = 0; + cetri <= `tchz 1; + pipereg = 36'h0; +end +endtask + +task burst; +begin + if (burstinit == 0 || mode == 0) + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b01; + 2'b01: addreg[1:0] = 2'b10; + 2'b10: addreg[1:0] = 2'b11; + 2'b11: addreg[1:0] = 2'b00; + default: addreg[1:0] = 2'bxx; + endcase + end + else + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b11; + 2'b01: addreg[1:0] = 2'b00; + 2'b10: addreg[1:0] = 2'b01; + 2'b11: addreg[1:0] = 2'b10; + default: addreg[1:0] = 2'bxx; + endcase + end +end +endtask + +// IO checks +/* +specify +// specify the setup and hold checks + +// notifier will wipe memory as result is indeterminent + +$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); + +// noti1 should make ip = 'bx; + +$setuphold(posedge clk, bws, `tas, `tah, noti1_0); + +$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); +$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); +$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); +$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); + +// noti2 should make d = 36'hxxxxxxxxx; + +$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); +//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2); + +// add extra tests here. + +$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); +$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); + +endspecify +*/ +endmodule + + Index: trunk/boards/virtex4-ml403ep/mem/flash_cntrl.v =================================================================== --- trunk/boards/virtex4-ml403ep/mem/flash_cntrl.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/mem/flash_cntrl.v (revision 54) @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2008 Zeus Gomez Marmolejo + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +module flash_cntrl #( + parameter timeout = 2 // read timeout (default: 2 cycles) + ) ( + // Wishbone slave interface + input wb_clk_i, + input wb_rst_i, + input [15:0] wb_dat_i, + output [15:0] wb_dat_o, + input [16:1] wb_adr_i, + input wb_we_i, + input wb_tga_i, + input wb_stb_i, + input wb_cyc_i, + output wb_ack_o, + + // Pad signals + output reg [20:0] flash_addr_, + input [15:0] flash_data_, + output flash_we_n_, + output reg flash_ce2_ + ); + + // Registers and nets + reg [ 11:0] base; + reg [timeout-1:0] sft_cnt; + + wire op; + wire opbase; + + // Continuous assignments + assign wb_dat_o = flash_data_; + assign flash_we_n_ = 1'b1; + assign op = wb_cyc_i & wb_stb_i; + assign opbase = op & wb_tga_i & wb_we_i; + assign wb_ack_o = sft_cnt[timeout-1]; + + // Behaviour + // flash_addr, 21 bits + always @(posedge wb_clk_i) + flash_addr_ <= wb_tga_i ? { 1'b1, base, wb_adr_i[8:1] } + : { 5'h0, wb_adr_i[16:1] }; + + always @(posedge wb_clk_i) flash_ce2_ <= op; + + // sft_cnt + always @(posedge wb_clk_i) + sft_cnt <= wb_rst_i ? 0 + : (op ? ((|sft_cnt) ? { sft_cnt[timeout-2:0], 1'b0 } + : { sft_cnt[timeout-2:0], 1'b1 }) : 0); + + // base + always @(posedge wb_clk_i) + base <= wb_rst_i ? 12'h0: ((opbase) ? wb_dat_i[11:0] : base); +endmodule Index: trunk/boards/virtex4-ml403ep/mem/zbt_cntrl.v =================================================================== --- trunk/boards/virtex4-ml403ep/mem/zbt_cntrl.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/mem/zbt_cntrl.v (revision 54) @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2008 Zeus Gomez Marmolejo + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +`include "defines.v" + +module zbt_cntrl ( +`ifdef DEBUG + output reg [2:0] cnt, + output op, +`endif + + // Wishbone slave interface + input wb_clk_i, + input wb_rst_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [19:1] wb_adr_i, + input wb_we_i, + input [ 1:0] wb_sel_i, + input wb_stb_i, + input wb_cyc_i, + output wb_ack_o, + + // Pad signals + output sram_clk_, + output reg [20:0] sram_addr_, + inout [31:0] sram_data_, + output reg sram_we_n_, + output reg [ 3:0] sram_bw_, + output reg sram_cen_, + output sram_adv_ld_n_ + ); + + // Registers and nets + reg [31:0] wr; + wire nload; + +`ifndef DEBUG + reg [ 3:0] cnt; + wire op; +`endif + + // Continuous assignments + assign op = wb_stb_i & wb_cyc_i; + assign nload = |cnt; + + assign sram_clk_ = wb_clk_i; + assign sram_adv_ld_n_ = 1'b0; + assign sram_data_ = (op && wb_we_i) ? wr : 32'hzzzzzzzz; + assign wb_ack_o = cnt[3]; + + // Behaviour + // cnt + always @(posedge wb_clk_i) + cnt <= wb_rst_i ? 4'b0 + : { cnt[2:0], nload ? 1'b0 : op }; + + // wb_dat_o + always @(posedge wb_clk_i) + wb_dat_o <= cnt[2] ? (wb_adr_i[1] ? sram_data_[31:16] + : sram_data_[15:0]) : wb_dat_o; + + // sram_addr_ + always @(posedge wb_clk_i) + sram_addr_ <= op ? { 3'b0, wb_adr_i[19:2] } : sram_addr_; + + // sram_we_n_ + always @(posedge wb_clk_i) + sram_we_n_ <= wb_we_i ? (nload ? 1'b1 : !op) : 1'b1; + + // sram_bw_ + always @(posedge wb_clk_i) + sram_bw_ <= wb_adr_i[1] ? { ~wb_sel_i, 2'b11 } + : { 2'b11, ~wb_sel_i }; + + // sram_cen_ + always @(posedge wb_clk_i) + sram_cen_ <= wb_rst_i ? 1'b1 : !op; + + // wr + always @(posedge wb_clk_i) + wr <= op ? (wb_adr_i[1] ? { wb_dat_i, 16'h0 } + : { 16'h0, wb_dat_i }) : wr; +endmodule Index: trunk/boards/virtex4-ml403ep/test/base.cpj =================================================================== --- trunk/boards/virtex4-ml403ep/test/base.cpj (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/base.cpj (revision 54) @@ -0,0 +1,4690 @@ +#ChipScope Pro Analyzer Project File, Version 3.0 +#Wed Mar 11 23:37:50 GMT+01:00 2009 +device.2.configFileDir=/home/zeus/tmp +device.2.configFilename=kotku_ml403.bit +deviceChain.deviceName0=System_ACE_CF +deviceChain.deviceName1=XCF32P +deviceChain.deviceName2=XC4VFX12 +deviceChain.deviceName3=XC9500XL +deviceChain.iRLength0=8 +deviceChain.iRLength1=16 +deviceChain.iRLength2=10 +deviceChain.iRLength3=8 +deviceChain.name0=MyDevice0 +deviceChain.name1=MyDevice1 +deviceChain.name2=MyDevice2 +deviceChain.name3=MyDevice3 +deviceIds=0a001093f505909321e5809359608093 +mdiAreaHeight=0.828042328042328 +mdiAreaHeightLast=0.828042328042328 +mdiCount=2 +mdiDevice0=2 +mdiDevice1=2 +mdiType0=1 +mdiType1=0 +mdiUnit0=0 +mdiUnit1=0 +navigatorHeight=0.42724867724867727 +navigatorHeightLast=0.15873015873015872 +navigatorWidth=0.17054263565891473 +navigatorWidthLast=0.11937984496124031 +unit.-1.-1.username= +unit.1.-1.username= +unit.2.-1.username= +unit.2.0.0.HEIGHT0=0.7977528 +unit.2.0.0.TriggerRow0=1 +unit.2.0.0.TriggerRow1=1 +unit.2.0.0.TriggerRow2=1 +unit.2.0.0.WIDTH0=0.58587784 +unit.2.0.0.X0=0.2509542 +unit.2.0.0.Y0=0.072231136 +unit.2.0.1.HEIGHT1=1.0 +unit.2.0.1.WIDTH1=1.0 +unit.2.0.1.X1=0.0 +unit.2.0.1.Y1=0.0 +unit.2.0.MFBitsA0=00110101110111001000 +unit.2.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +unit.2.0.MFBitsA10=XXXXXXXXXXXXXXXXXXXXX +unit.2.0.MFBitsA11=XXXXXXXXXXXXXXXX +unit.2.0.MFBitsA12=XXXXXX1XX +unit.2.0.MFBitsA13=XXX +unit.2.0.MFBitsA14=XXXXX +unit.2.0.MFBitsA15=00000000001100011111001000000000 +unit.2.0.MFBitsA2=11100001100101111111 +unit.2.0.MFBitsA3=X1XX1X +unit.2.0.MFBitsA4=XXXXXX +unit.2.0.MFBitsA5=XXX000 +unit.2.0.MFBitsA6=XXXXXXXXXXXXXX1X +unit.2.0.MFBitsA7=XXXXXXXXXXXXXXXX +unit.2.0.MFBitsA8=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +unit.2.0.MFBitsA9=XXXXXXXXXXXXXXXX +unit.2.0.MFBitsB0=00000000000000000000 +unit.2.0.MFBitsB1=00000000000000000000000000000000 +unit.2.0.MFBitsB10=000000000000000000000 +unit.2.0.MFBitsB11=0000000000000000 +unit.2.0.MFBitsB12=000000000 +unit.2.0.MFBitsB13=000 +unit.2.0.MFBitsB14=00000 +unit.2.0.MFBitsB15=00000000000000000000000000000000 +unit.2.0.MFBitsB2=00000000000000000000 +unit.2.0.MFBitsB3=000000 +unit.2.0.MFBitsB4=000000 +unit.2.0.MFBitsB5=000000 +unit.2.0.MFBitsB6=0000000000000000 +unit.2.0.MFBitsB7=0000000000000000 +unit.2.0.MFBitsB8=00000000000000000000000000000000 +unit.2.0.MFBitsB9=0000000000000000 +unit.2.0.MFCompareA0=0 +unit.2.0.MFCompareA1=0 +unit.2.0.MFCompareA10=0 +unit.2.0.MFCompareA11=0 +unit.2.0.MFCompareA12=0 +unit.2.0.MFCompareA13=0 +unit.2.0.MFCompareA14=0 +unit.2.0.MFCompareA15=2 +unit.2.0.MFCompareA2=0 +unit.2.0.MFCompareA3=0 +unit.2.0.MFCompareA4=0 +unit.2.0.MFCompareA5=0 +unit.2.0.MFCompareA6=0 +unit.2.0.MFCompareA7=0 +unit.2.0.MFCompareA8=0 +unit.2.0.MFCompareA9=0 +unit.2.0.MFCompareB0=999 +unit.2.0.MFCompareB1=999 +unit.2.0.MFCompareB10=999 +unit.2.0.MFCompareB11=999 +unit.2.0.MFCompareB12=999 +unit.2.0.MFCompareB13=999 +unit.2.0.MFCompareB14=999 +unit.2.0.MFCompareB15=999 +unit.2.0.MFCompareB2=999 +unit.2.0.MFCompareB3=999 +unit.2.0.MFCompareB4=999 +unit.2.0.MFCompareB5=999 +unit.2.0.MFCompareB6=999 +unit.2.0.MFCompareB7=999 +unit.2.0.MFCompareB8=999 +unit.2.0.MFCompareB9=999 +unit.2.0.MFCount=16 +unit.2.0.MFDisplay0=1 +unit.2.0.MFDisplay1=1 +unit.2.0.MFDisplay10=1 +unit.2.0.MFDisplay11=0 +unit.2.0.MFDisplay12=0 +unit.2.0.MFDisplay13=0 +unit.2.0.MFDisplay14=0 +unit.2.0.MFDisplay15=1 +unit.2.0.MFDisplay2=1 +unit.2.0.MFDisplay3=0 +unit.2.0.MFDisplay4=0 +unit.2.0.MFDisplay5=0 +unit.2.0.MFDisplay6=0 +unit.2.0.MFDisplay7=1 +unit.2.0.MFDisplay8=0 +unit.2.0.MFDisplay9=0 +unit.2.0.MFEventType0=3 +unit.2.0.MFEventType1=3 +unit.2.0.MFEventType10=3 +unit.2.0.MFEventType11=3 +unit.2.0.MFEventType12=3 +unit.2.0.MFEventType13=3 +unit.2.0.MFEventType14=3 +unit.2.0.MFEventType15=3 +unit.2.0.MFEventType2=3 +unit.2.0.MFEventType3=3 +unit.2.0.MFEventType4=3 +unit.2.0.MFEventType5=3 +unit.2.0.MFEventType6=3 +unit.2.0.MFEventType7=3 +unit.2.0.MFEventType8=3 +unit.2.0.MFEventType9=3 +unit.2.0.SQCondition=All Data +unit.2.0.SQContiguous0=0 +unit.2.0.SequencerOn=0 +unit.2.0.TCActive=0 +unit.2.0.TCAdvanced0=0 +unit.2.0.TCCondition0_0=M12 +unit.2.0.TCCondition0_1= +unit.2.0.TCConditionType0=0 +unit.2.0.TCCount=1 +unit.2.0.TCEventCount0=1 +unit.2.0.TCEventType0=3 +unit.2.0.TCName0=TriggerCondition0 +unit.2.0.TCOutputEnable0=0 +unit.2.0.TCOutputHigh0=1 +unit.2.0.TCOutputMode0=0 +unit.2.0.browser_tree_state=1 +unit.2.0.browser_tree_state=1 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=1 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=1 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.browser_tree_state=0 +unit.2.0.coretype=ILA +unit.2.0.eventCount0=1 +unit.2.0.eventCount1=1 +unit.2.0.eventCount10=1 +unit.2.0.eventCount11=1 +unit.2.0.eventCount12=1 +unit.2.0.eventCount13=1 +unit.2.0.eventCount14=1 +unit.2.0.eventCount15=1 +unit.2.0.eventCount2=1 +unit.2.0.eventCount3=1 +unit.2.0.eventCount4=1 +unit.2.0.eventCount5=1 +unit.2.0.eventCount6=1 +unit.2.0.eventCount7=1 +unit.2.0.eventCount8=1 +unit.2.0.eventCount9=1 +unit.2.0.export.format=2 +unit.2.0.export.signals=Waveform Signals/Buses +unit.2.0.export.unitName=DEV\:2 MyDevice2 (XC4VFX12) UNIT\:0 MyILA0 (ILA) +unit.2.0.port.-1.b.0.alias=aceusb_d_ +unit.2.0.port.-1.b.0.channellist=191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 +unit.2.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.0.name=DataPort +unit.2.0.port.-1.b.0.orderindex=-1 +unit.2.0.port.-1.b.0.radix=Hex +unit.2.0.port.-1.b.0.signedOffset=0.0 +unit.2.0.port.-1.b.0.signedPrecision=0 +unit.2.0.port.-1.b.0.signedScaleFactor=1.0 +unit.2.0.port.-1.b.0.tokencount=0 +unit.2.0.port.-1.b.0.unsignedOffset=0.0 +unit.2.0.port.-1.b.0.unsignedPrecision=0 +unit.2.0.port.-1.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.0.visible=1 +unit.2.0.port.-1.b.1.alias=ace_dat_o +unit.2.0.port.-1.b.1.channellist=170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 +unit.2.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.1.name=DataPort +unit.2.0.port.-1.b.1.orderindex=-1 +unit.2.0.port.-1.b.1.radix=Hex +unit.2.0.port.-1.b.1.signedOffset=0.0 +unit.2.0.port.-1.b.1.signedPrecision=0 +unit.2.0.port.-1.b.1.signedScaleFactor=1.0 +unit.2.0.port.-1.b.1.tokencount=0 +unit.2.0.port.-1.b.1.unsignedOffset=0.0 +unit.2.0.port.-1.b.1.unsignedPrecision=0 +unit.2.0.port.-1.b.1.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.1.visible=1 +unit.2.0.port.-1.b.10.alias=flags +unit.2.0.port.-1.b.10.channellist=95 96 97 98 99 100 101 102 103 +unit.2.0.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.10.name=DataPort +unit.2.0.port.-1.b.10.orderindex=-1 +unit.2.0.port.-1.b.10.radix=Hex +unit.2.0.port.-1.b.10.signedOffset=0.0 +unit.2.0.port.-1.b.10.signedPrecision=0 +unit.2.0.port.-1.b.10.signedScaleFactor=1.0 +unit.2.0.port.-1.b.10.tokencount=0 +unit.2.0.port.-1.b.10.unsignedOffset=0.0 +unit.2.0.port.-1.b.10.unsignedPrecision=0 +unit.2.0.port.-1.b.10.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.10.visible=1 +unit.2.0.port.-1.b.11.alias=func +unit.2.0.port.-1.b.11.channellist=81 82 83 +unit.2.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.11.name=DataPort +unit.2.0.port.-1.b.11.orderindex=-1 +unit.2.0.port.-1.b.11.radix=Hex +unit.2.0.port.-1.b.11.signedOffset=0.0 +unit.2.0.port.-1.b.11.signedPrecision=0 +unit.2.0.port.-1.b.11.signedScaleFactor=1.0 +unit.2.0.port.-1.b.11.tokencount=0 +unit.2.0.port.-1.b.11.unsignedOffset=0.0 +unit.2.0.port.-1.b.11.unsignedPrecision=0 +unit.2.0.port.-1.b.11.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.11.visible=1 +unit.2.0.port.-1.b.12.alias=next_state +unit.2.0.port.-1.b.12.channellist=84 85 86 +unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.12.name=DataPort +unit.2.0.port.-1.b.12.orderindex=-1 +unit.2.0.port.-1.b.12.radix=Hex +unit.2.0.port.-1.b.12.signedOffset=0.0 +unit.2.0.port.-1.b.12.signedPrecision=0 +unit.2.0.port.-1.b.12.signedScaleFactor=1.0 +unit.2.0.port.-1.b.12.tokencount=0 +unit.2.0.port.-1.b.12.unsignedOffset=0.0 +unit.2.0.port.-1.b.12.unsignedPrecision=0 +unit.2.0.port.-1.b.12.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.12.visible=1 +unit.2.0.port.-1.b.13.alias=pc +unit.2.0.port.-1.b.13.channellist=52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 +unit.2.0.port.-1.b.13.color=java.awt.Color[r\=204,g\=0,b\=51] +unit.2.0.port.-1.b.13.name=DataPort +unit.2.0.port.-1.b.13.orderindex=-1 +unit.2.0.port.-1.b.13.radix=Hex +unit.2.0.port.-1.b.13.signedOffset=0.0 +unit.2.0.port.-1.b.13.signedPrecision=0 +unit.2.0.port.-1.b.13.signedScaleFactor=1.0 +unit.2.0.port.-1.b.13.tokencount=0 +unit.2.0.port.-1.b.13.unsignedOffset=0.0 +unit.2.0.port.-1.b.13.unsignedPrecision=0 +unit.2.0.port.-1.b.13.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.13.visible=1 +unit.2.0.port.-1.b.14.alias=state +unit.2.0.port.-1.b.14.channellist=87 88 89 +unit.2.0.port.-1.b.14.color=java.awt.Color[r\=0,g\=51,b\=204] +unit.2.0.port.-1.b.14.name=DataPort +unit.2.0.port.-1.b.14.orderindex=-1 +unit.2.0.port.-1.b.14.radix=Hex +unit.2.0.port.-1.b.14.signedOffset=0.0 +unit.2.0.port.-1.b.14.signedPrecision=0 +unit.2.0.port.-1.b.14.signedScaleFactor=1.0 +unit.2.0.port.-1.b.14.tokencount=0 +unit.2.0.port.-1.b.14.unsignedOffset=0.0 +unit.2.0.port.-1.b.14.unsignedPrecision=0 +unit.2.0.port.-1.b.14.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.14.visible=1 +unit.2.0.port.-1.b.15.alias=t +unit.2.0.port.-1.b.15.channellist=78 79 80 +unit.2.0.port.-1.b.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.15.name=DataPort +unit.2.0.port.-1.b.15.orderindex=-1 +unit.2.0.port.-1.b.15.radix=Hex +unit.2.0.port.-1.b.15.signedOffset=0.0 +unit.2.0.port.-1.b.15.signedPrecision=0 +unit.2.0.port.-1.b.15.signedScaleFactor=1.0 +unit.2.0.port.-1.b.15.tokencount=0 +unit.2.0.port.-1.b.15.unsignedOffset=0.0 +unit.2.0.port.-1.b.15.unsignedPrecision=0 +unit.2.0.port.-1.b.15.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.15.visible=1 +unit.2.0.port.-1.b.16.alias=x +unit.2.0.port.-1.b.16.channellist=138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 +unit.2.0.port.-1.b.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.16.name=DataPort +unit.2.0.port.-1.b.16.orderindex=-1 +unit.2.0.port.-1.b.16.radix=Hex +unit.2.0.port.-1.b.16.signedOffset=0.0 +unit.2.0.port.-1.b.16.signedPrecision=0 +unit.2.0.port.-1.b.16.signedScaleFactor=1.0 +unit.2.0.port.-1.b.16.tokencount=0 +unit.2.0.port.-1.b.16.unsignedOffset=0.0 +unit.2.0.port.-1.b.16.unsignedPrecision=0 +unit.2.0.port.-1.b.16.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.16.visible=1 +unit.2.0.port.-1.b.17.alias=y +unit.2.0.port.-1.b.17.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 +unit.2.0.port.-1.b.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.17.name=DataPort +unit.2.0.port.-1.b.17.orderindex=-1 +unit.2.0.port.-1.b.17.radix=Hex +unit.2.0.port.-1.b.17.signedOffset=0.0 +unit.2.0.port.-1.b.17.signedPrecision=0 +unit.2.0.port.-1.b.17.signedScaleFactor=1.0 +unit.2.0.port.-1.b.17.tokencount=0 +unit.2.0.port.-1.b.17.unsignedOffset=0.0 +unit.2.0.port.-1.b.17.unsignedPrecision=0 +unit.2.0.port.-1.b.17.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.17.visible=1 +unit.2.0.port.-1.b.18.alias=y +unit.2.0.port.-1.b.18.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 +unit.2.0.port.-1.b.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.18.name=DataPort +unit.2.0.port.-1.b.18.orderindex=-1 +unit.2.0.port.-1.b.18.radix=Hex +unit.2.0.port.-1.b.18.signedOffset=0.0 +unit.2.0.port.-1.b.18.signedPrecision=0 +unit.2.0.port.-1.b.18.signedScaleFactor=1.0 +unit.2.0.port.-1.b.18.tokencount=0 +unit.2.0.port.-1.b.18.unsignedOffset=0.0 +unit.2.0.port.-1.b.18.unsignedPrecision=0 +unit.2.0.port.-1.b.18.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.18.visible=1 +unit.2.0.port.-1.b.19.alias=y +unit.2.0.port.-1.b.19.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 +unit.2.0.port.-1.b.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.19.name=DataPort +unit.2.0.port.-1.b.19.orderindex=-1 +unit.2.0.port.-1.b.19.radix=Hex +unit.2.0.port.-1.b.19.signedOffset=0.0 +unit.2.0.port.-1.b.19.signedPrecision=0 +unit.2.0.port.-1.b.19.signedScaleFactor=1.0 +unit.2.0.port.-1.b.19.tokencount=0 +unit.2.0.port.-1.b.19.unsignedOffset=0.0 +unit.2.0.port.-1.b.19.unsignedPrecision=0 +unit.2.0.port.-1.b.19.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.19.visible=1 +unit.2.0.port.-1.b.2.alias=addr_d +unit.2.0.port.-1.b.2.channellist=90 91 92 93 +unit.2.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.2.name=DataPort +unit.2.0.port.-1.b.2.orderindex=-1 +unit.2.0.port.-1.b.2.radix=Hex +unit.2.0.port.-1.b.2.signedOffset=0.0 +unit.2.0.port.-1.b.2.signedPrecision=0 +unit.2.0.port.-1.b.2.signedScaleFactor=1.0 +unit.2.0.port.-1.b.2.tokencount=0 +unit.2.0.port.-1.b.2.unsignedOffset=0.0 +unit.2.0.port.-1.b.2.unsignedPrecision=0 +unit.2.0.port.-1.b.2.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.2.visible=1 +unit.2.0.port.-1.b.3.alias=adr +unit.2.0.port.-1.b.3.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +unit.2.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.3.name=DataPort +unit.2.0.port.-1.b.3.orderindex=-1 +unit.2.0.port.-1.b.3.radix=Hex +unit.2.0.port.-1.b.3.signedOffset=0.0 +unit.2.0.port.-1.b.3.signedPrecision=0 +unit.2.0.port.-1.b.3.signedScaleFactor=1.0 +unit.2.0.port.-1.b.3.tokencount=0 +unit.2.0.port.-1.b.3.unsignedOffset=0.0 +unit.2.0.port.-1.b.3.unsignedPrecision=0 +unit.2.0.port.-1.b.3.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.3.visible=1 +unit.2.0.port.-1.b.4.alias=aluo +unit.2.0.port.-1.b.4.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 +unit.2.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.4.name=DataPort +unit.2.0.port.-1.b.4.orderindex=-1 +unit.2.0.port.-1.b.4.radix=Hex +unit.2.0.port.-1.b.4.signedOffset=0.0 +unit.2.0.port.-1.b.4.signedPrecision=0 +unit.2.0.port.-1.b.4.signedScaleFactor=1.0 +unit.2.0.port.-1.b.4.tokencount=0 +unit.2.0.port.-1.b.4.unsignedOffset=0.0 +unit.2.0.port.-1.b.4.unsignedPrecision=0 +unit.2.0.port.-1.b.4.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.4.visible=1 +unit.2.0.port.-1.b.5.alias=cnt +unit.2.0.port.-1.b.5.channellist=216 217 218 +unit.2.0.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.5.name=DataPort +unit.2.0.port.-1.b.5.orderindex=-1 +unit.2.0.port.-1.b.5.radix=Hex +unit.2.0.port.-1.b.5.signedOffset=0.0 +unit.2.0.port.-1.b.5.signedPrecision=0 +unit.2.0.port.-1.b.5.signedScaleFactor=1.0 +unit.2.0.port.-1.b.5.tokencount=0 +unit.2.0.port.-1.b.5.unsignedOffset=0.0 +unit.2.0.port.-1.b.5.unsignedPrecision=0 +unit.2.0.port.-1.b.5.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.5.visible=1 +unit.2.0.port.-1.b.6.alias=cnt_time +unit.2.0.port.-1.b.6.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 +unit.2.0.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.6.name=DataPort +unit.2.0.port.-1.b.6.orderindex=-1 +unit.2.0.port.-1.b.6.radix=Hex +unit.2.0.port.-1.b.6.signedOffset=0.0 +unit.2.0.port.-1.b.6.signedPrecision=0 +unit.2.0.port.-1.b.6.signedScaleFactor=1.0 +unit.2.0.port.-1.b.6.tokencount=0 +unit.2.0.port.-1.b.6.unsignedOffset=0.0 +unit.2.0.port.-1.b.6.unsignedPrecision=0 +unit.2.0.port.-1.b.6.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.6.visible=1 +unit.2.0.port.-1.b.7.alias=d +unit.2.0.port.-1.b.7.channellist=106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 +unit.2.0.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.7.name=DataPort +unit.2.0.port.-1.b.7.orderindex=-1 +unit.2.0.port.-1.b.7.radix=Hex +unit.2.0.port.-1.b.7.signedOffset=0.0 +unit.2.0.port.-1.b.7.signedPrecision=0 +unit.2.0.port.-1.b.7.signedScaleFactor=1.0 +unit.2.0.port.-1.b.7.tokencount=0 +unit.2.0.port.-1.b.7.unsignedOffset=0.0 +unit.2.0.port.-1.b.7.unsignedPrecision=0 +unit.2.0.port.-1.b.7.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.7.visible=1 +unit.2.0.port.-1.b.8.alias=dat_i +unit.2.0.port.-1.b.8.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 +unit.2.0.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.8.name=DataPort +unit.2.0.port.-1.b.8.orderindex=-1 +unit.2.0.port.-1.b.8.radix=Hex +unit.2.0.port.-1.b.8.signedOffset=0.0 +unit.2.0.port.-1.b.8.signedPrecision=0 +unit.2.0.port.-1.b.8.signedScaleFactor=1.0 +unit.2.0.port.-1.b.8.tokencount=0 +unit.2.0.port.-1.b.8.unsignedOffset=0.0 +unit.2.0.port.-1.b.8.unsignedPrecision=0 +unit.2.0.port.-1.b.8.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.8.visible=1 +unit.2.0.port.-1.b.9.alias=dat_o +unit.2.0.port.-1.b.9.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 +unit.2.0.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.b.9.name=DataPort +unit.2.0.port.-1.b.9.orderindex=-1 +unit.2.0.port.-1.b.9.radix=Hex +unit.2.0.port.-1.b.9.signedOffset=0.0 +unit.2.0.port.-1.b.9.signedPrecision=0 +unit.2.0.port.-1.b.9.signedScaleFactor=1.0 +unit.2.0.port.-1.b.9.tokencount=0 +unit.2.0.port.-1.b.9.unsignedOffset=0.0 +unit.2.0.port.-1.b.9.unsignedPrecision=0 +unit.2.0.port.-1.b.9.unsignedScaleFactor=1.0 +unit.2.0.port.-1.b.9.visible=1 +unit.2.0.port.-1.buscount=18 +unit.2.0.port.-1.channelcount=256 +unit.2.0.port.-1.s.0.alias= +unit.2.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.0.name=DataPort[0] +unit.2.0.port.-1.s.0.orderindex=-1 +unit.2.0.port.-1.s.0.visible=1 +unit.2.0.port.-1.s.1.alias= +unit.2.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.1.name=DataPort[1] +unit.2.0.port.-1.s.1.orderindex=-1 +unit.2.0.port.-1.s.1.visible=1 +unit.2.0.port.-1.s.10.alias= +unit.2.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.10.name=DataPort[10] +unit.2.0.port.-1.s.10.orderindex=-1 +unit.2.0.port.-1.s.10.visible=1 +unit.2.0.port.-1.s.100.alias= +unit.2.0.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.100.name=DataPort[100] +unit.2.0.port.-1.s.100.orderindex=-1 +unit.2.0.port.-1.s.100.visible=1 +unit.2.0.port.-1.s.101.alias= +unit.2.0.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.101.name=DataPort[101] +unit.2.0.port.-1.s.101.orderindex=-1 +unit.2.0.port.-1.s.101.visible=1 +unit.2.0.port.-1.s.102.alias= +unit.2.0.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.102.name=DataPort[102] +unit.2.0.port.-1.s.102.orderindex=-1 +unit.2.0.port.-1.s.102.visible=1 +unit.2.0.port.-1.s.103.alias= +unit.2.0.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.103.name=DataPort[103] +unit.2.0.port.-1.s.103.orderindex=-1 +unit.2.0.port.-1.s.103.visible=1 +unit.2.0.port.-1.s.104.alias=inta +unit.2.0.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.104.name=DataPort[104] +unit.2.0.port.-1.s.104.orderindex=-1 +unit.2.0.port.-1.s.104.visible=1 +unit.2.0.port.-1.s.105.alias=intr +unit.2.0.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.105.name=DataPort[105] +unit.2.0.port.-1.s.105.orderindex=-1 +unit.2.0.port.-1.s.105.visible=1 +unit.2.0.port.-1.s.106.alias= +unit.2.0.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.106.name=DataPort[106] +unit.2.0.port.-1.s.106.orderindex=-1 +unit.2.0.port.-1.s.106.visible=1 +unit.2.0.port.-1.s.107.alias= +unit.2.0.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.107.name=DataPort[107] +unit.2.0.port.-1.s.107.orderindex=-1 +unit.2.0.port.-1.s.107.visible=1 +unit.2.0.port.-1.s.108.alias= +unit.2.0.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.108.name=DataPort[108] +unit.2.0.port.-1.s.108.orderindex=-1 +unit.2.0.port.-1.s.108.visible=1 +unit.2.0.port.-1.s.109.alias= +unit.2.0.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.109.name=DataPort[109] +unit.2.0.port.-1.s.109.orderindex=-1 +unit.2.0.port.-1.s.109.visible=1 +unit.2.0.port.-1.s.11.alias= +unit.2.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.11.name=DataPort[11] +unit.2.0.port.-1.s.11.orderindex=-1 +unit.2.0.port.-1.s.11.visible=1 +unit.2.0.port.-1.s.110.alias= +unit.2.0.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.110.name=DataPort[110] +unit.2.0.port.-1.s.110.orderindex=-1 +unit.2.0.port.-1.s.110.visible=1 +unit.2.0.port.-1.s.111.alias= +unit.2.0.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.111.name=DataPort[111] +unit.2.0.port.-1.s.111.orderindex=-1 +unit.2.0.port.-1.s.111.visible=1 +unit.2.0.port.-1.s.112.alias= +unit.2.0.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.112.name=DataPort[112] +unit.2.0.port.-1.s.112.orderindex=-1 +unit.2.0.port.-1.s.112.visible=1 +unit.2.0.port.-1.s.113.alias= +unit.2.0.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.113.name=DataPort[113] +unit.2.0.port.-1.s.113.orderindex=-1 +unit.2.0.port.-1.s.113.visible=1 +unit.2.0.port.-1.s.114.alias= +unit.2.0.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.114.name=DataPort[114] +unit.2.0.port.-1.s.114.orderindex=-1 +unit.2.0.port.-1.s.114.visible=1 +unit.2.0.port.-1.s.115.alias= +unit.2.0.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.115.name=DataPort[115] +unit.2.0.port.-1.s.115.orderindex=-1 +unit.2.0.port.-1.s.115.visible=1 +unit.2.0.port.-1.s.116.alias= +unit.2.0.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.116.name=DataPort[116] +unit.2.0.port.-1.s.116.orderindex=-1 +unit.2.0.port.-1.s.116.visible=1 +unit.2.0.port.-1.s.117.alias= +unit.2.0.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.117.name=DataPort[117] +unit.2.0.port.-1.s.117.orderindex=-1 +unit.2.0.port.-1.s.117.visible=1 +unit.2.0.port.-1.s.118.alias= +unit.2.0.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.118.name=DataPort[118] +unit.2.0.port.-1.s.118.orderindex=-1 +unit.2.0.port.-1.s.118.visible=1 +unit.2.0.port.-1.s.119.alias= +unit.2.0.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.119.name=DataPort[119] +unit.2.0.port.-1.s.119.orderindex=-1 +unit.2.0.port.-1.s.119.visible=1 +unit.2.0.port.-1.s.12.alias= +unit.2.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.12.name=DataPort[12] +unit.2.0.port.-1.s.12.orderindex=-1 +unit.2.0.port.-1.s.12.visible=1 +unit.2.0.port.-1.s.120.alias= +unit.2.0.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.120.name=DataPort[120] +unit.2.0.port.-1.s.120.orderindex=-1 +unit.2.0.port.-1.s.120.visible=1 +unit.2.0.port.-1.s.121.alias= +unit.2.0.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.121.name=DataPort[121] +unit.2.0.port.-1.s.121.orderindex=-1 +unit.2.0.port.-1.s.121.visible=1 +unit.2.0.port.-1.s.122.alias= +unit.2.0.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.122.name=DataPort[122] +unit.2.0.port.-1.s.122.orderindex=-1 +unit.2.0.port.-1.s.122.visible=1 +unit.2.0.port.-1.s.123.alias= +unit.2.0.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.123.name=DataPort[123] +unit.2.0.port.-1.s.123.orderindex=-1 +unit.2.0.port.-1.s.123.visible=1 +unit.2.0.port.-1.s.124.alias= +unit.2.0.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.124.name=DataPort[124] +unit.2.0.port.-1.s.124.orderindex=-1 +unit.2.0.port.-1.s.124.visible=1 +unit.2.0.port.-1.s.125.alias= +unit.2.0.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.125.name=DataPort[125] +unit.2.0.port.-1.s.125.orderindex=-1 +unit.2.0.port.-1.s.125.visible=1 +unit.2.0.port.-1.s.126.alias= +unit.2.0.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.126.name=DataPort[126] +unit.2.0.port.-1.s.126.orderindex=-1 +unit.2.0.port.-1.s.126.visible=1 +unit.2.0.port.-1.s.127.alias= +unit.2.0.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.127.name=DataPort[127] +unit.2.0.port.-1.s.127.orderindex=-1 +unit.2.0.port.-1.s.127.visible=1 +unit.2.0.port.-1.s.128.alias= +unit.2.0.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.128.name=DataPort[128] +unit.2.0.port.-1.s.128.orderindex=-1 +unit.2.0.port.-1.s.128.visible=1 +unit.2.0.port.-1.s.129.alias= +unit.2.0.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.129.name=DataPort[129] +unit.2.0.port.-1.s.129.orderindex=-1 +unit.2.0.port.-1.s.129.visible=1 +unit.2.0.port.-1.s.13.alias= +unit.2.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.13.name=DataPort[13] +unit.2.0.port.-1.s.13.orderindex=-1 +unit.2.0.port.-1.s.13.visible=1 +unit.2.0.port.-1.s.130.alias= +unit.2.0.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.130.name=DataPort[130] +unit.2.0.port.-1.s.130.orderindex=-1 +unit.2.0.port.-1.s.130.visible=1 +unit.2.0.port.-1.s.131.alias= +unit.2.0.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.131.name=DataPort[131] +unit.2.0.port.-1.s.131.orderindex=-1 +unit.2.0.port.-1.s.131.visible=1 +unit.2.0.port.-1.s.132.alias= +unit.2.0.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.132.name=DataPort[132] +unit.2.0.port.-1.s.132.orderindex=-1 +unit.2.0.port.-1.s.132.visible=1 +unit.2.0.port.-1.s.133.alias= +unit.2.0.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.133.name=DataPort[133] +unit.2.0.port.-1.s.133.orderindex=-1 +unit.2.0.port.-1.s.133.visible=1 +unit.2.0.port.-1.s.134.alias= +unit.2.0.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.134.name=DataPort[134] +unit.2.0.port.-1.s.134.orderindex=-1 +unit.2.0.port.-1.s.134.visible=1 +unit.2.0.port.-1.s.135.alias= +unit.2.0.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.135.name=DataPort[135] +unit.2.0.port.-1.s.135.orderindex=-1 +unit.2.0.port.-1.s.135.visible=1 +unit.2.0.port.-1.s.136.alias= +unit.2.0.port.-1.s.136.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.136.name=DataPort[136] +unit.2.0.port.-1.s.136.orderindex=-1 +unit.2.0.port.-1.s.136.visible=1 +unit.2.0.port.-1.s.137.alias= +unit.2.0.port.-1.s.137.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.137.name=DataPort[137] +unit.2.0.port.-1.s.137.orderindex=-1 +unit.2.0.port.-1.s.137.visible=1 +unit.2.0.port.-1.s.138.alias= +unit.2.0.port.-1.s.138.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.138.name=DataPort[138] +unit.2.0.port.-1.s.138.orderindex=-1 +unit.2.0.port.-1.s.138.visible=1 +unit.2.0.port.-1.s.139.alias= +unit.2.0.port.-1.s.139.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.139.name=DataPort[139] +unit.2.0.port.-1.s.139.orderindex=-1 +unit.2.0.port.-1.s.139.visible=1 +unit.2.0.port.-1.s.14.alias= +unit.2.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.14.name=DataPort[14] +unit.2.0.port.-1.s.14.orderindex=-1 +unit.2.0.port.-1.s.14.visible=1 +unit.2.0.port.-1.s.140.alias= +unit.2.0.port.-1.s.140.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.140.name=DataPort[140] +unit.2.0.port.-1.s.140.orderindex=-1 +unit.2.0.port.-1.s.140.visible=1 +unit.2.0.port.-1.s.141.alias= +unit.2.0.port.-1.s.141.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.141.name=DataPort[141] +unit.2.0.port.-1.s.141.orderindex=-1 +unit.2.0.port.-1.s.141.visible=1 +unit.2.0.port.-1.s.142.alias= +unit.2.0.port.-1.s.142.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.142.name=DataPort[142] +unit.2.0.port.-1.s.142.orderindex=-1 +unit.2.0.port.-1.s.142.visible=1 +unit.2.0.port.-1.s.143.alias= +unit.2.0.port.-1.s.143.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.143.name=DataPort[143] +unit.2.0.port.-1.s.143.orderindex=-1 +unit.2.0.port.-1.s.143.visible=1 +unit.2.0.port.-1.s.144.alias= +unit.2.0.port.-1.s.144.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.144.name=DataPort[144] +unit.2.0.port.-1.s.144.orderindex=-1 +unit.2.0.port.-1.s.144.visible=1 +unit.2.0.port.-1.s.145.alias= +unit.2.0.port.-1.s.145.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.145.name=DataPort[145] +unit.2.0.port.-1.s.145.orderindex=-1 +unit.2.0.port.-1.s.145.visible=1 +unit.2.0.port.-1.s.146.alias= +unit.2.0.port.-1.s.146.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.146.name=DataPort[146] +unit.2.0.port.-1.s.146.orderindex=-1 +unit.2.0.port.-1.s.146.visible=1 +unit.2.0.port.-1.s.147.alias= +unit.2.0.port.-1.s.147.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.147.name=DataPort[147] +unit.2.0.port.-1.s.147.orderindex=-1 +unit.2.0.port.-1.s.147.visible=1 +unit.2.0.port.-1.s.148.alias= +unit.2.0.port.-1.s.148.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.148.name=DataPort[148] +unit.2.0.port.-1.s.148.orderindex=-1 +unit.2.0.port.-1.s.148.visible=1 +unit.2.0.port.-1.s.149.alias= +unit.2.0.port.-1.s.149.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.149.name=DataPort[149] +unit.2.0.port.-1.s.149.orderindex=-1 +unit.2.0.port.-1.s.149.visible=1 +unit.2.0.port.-1.s.15.alias= +unit.2.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.15.name=DataPort[15] +unit.2.0.port.-1.s.15.orderindex=-1 +unit.2.0.port.-1.s.15.visible=1 +unit.2.0.port.-1.s.150.alias= +unit.2.0.port.-1.s.150.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.150.name=DataPort[150] +unit.2.0.port.-1.s.150.orderindex=-1 +unit.2.0.port.-1.s.150.visible=1 +unit.2.0.port.-1.s.151.alias= +unit.2.0.port.-1.s.151.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.151.name=DataPort[151] +unit.2.0.port.-1.s.151.orderindex=-1 +unit.2.0.port.-1.s.151.visible=1 +unit.2.0.port.-1.s.152.alias= +unit.2.0.port.-1.s.152.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.152.name=DataPort[152] +unit.2.0.port.-1.s.152.orderindex=-1 +unit.2.0.port.-1.s.152.visible=1 +unit.2.0.port.-1.s.153.alias= +unit.2.0.port.-1.s.153.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.153.name=DataPort[153] +unit.2.0.port.-1.s.153.orderindex=-1 +unit.2.0.port.-1.s.153.visible=1 +unit.2.0.port.-1.s.154.alias= +unit.2.0.port.-1.s.154.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.154.name=DataPort[154] +unit.2.0.port.-1.s.154.orderindex=-1 +unit.2.0.port.-1.s.154.visible=1 +unit.2.0.port.-1.s.155.alias= +unit.2.0.port.-1.s.155.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.155.name=DataPort[155] +unit.2.0.port.-1.s.155.orderindex=-1 +unit.2.0.port.-1.s.155.visible=1 +unit.2.0.port.-1.s.156.alias= +unit.2.0.port.-1.s.156.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.156.name=DataPort[156] +unit.2.0.port.-1.s.156.orderindex=-1 +unit.2.0.port.-1.s.156.visible=1 +unit.2.0.port.-1.s.157.alias= +unit.2.0.port.-1.s.157.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.157.name=DataPort[157] +unit.2.0.port.-1.s.157.orderindex=-1 +unit.2.0.port.-1.s.157.visible=1 +unit.2.0.port.-1.s.158.alias= +unit.2.0.port.-1.s.158.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.158.name=DataPort[158] +unit.2.0.port.-1.s.158.orderindex=-1 +unit.2.0.port.-1.s.158.visible=1 +unit.2.0.port.-1.s.159.alias= +unit.2.0.port.-1.s.159.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.159.name=DataPort[159] +unit.2.0.port.-1.s.159.orderindex=-1 +unit.2.0.port.-1.s.159.visible=1 +unit.2.0.port.-1.s.16.alias= +unit.2.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.16.name=DataPort[16] +unit.2.0.port.-1.s.16.orderindex=-1 +unit.2.0.port.-1.s.16.visible=1 +unit.2.0.port.-1.s.160.alias= +unit.2.0.port.-1.s.160.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.160.name=DataPort[160] +unit.2.0.port.-1.s.160.orderindex=-1 +unit.2.0.port.-1.s.160.visible=1 +unit.2.0.port.-1.s.161.alias= +unit.2.0.port.-1.s.161.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.161.name=DataPort[161] +unit.2.0.port.-1.s.161.orderindex=-1 +unit.2.0.port.-1.s.161.visible=1 +unit.2.0.port.-1.s.162.alias= +unit.2.0.port.-1.s.162.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.162.name=DataPort[162] +unit.2.0.port.-1.s.162.orderindex=-1 +unit.2.0.port.-1.s.162.visible=1 +unit.2.0.port.-1.s.163.alias= +unit.2.0.port.-1.s.163.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.163.name=DataPort[163] +unit.2.0.port.-1.s.163.orderindex=-1 +unit.2.0.port.-1.s.163.visible=1 +unit.2.0.port.-1.s.164.alias= +unit.2.0.port.-1.s.164.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.164.name=DataPort[164] +unit.2.0.port.-1.s.164.orderindex=-1 +unit.2.0.port.-1.s.164.visible=1 +unit.2.0.port.-1.s.165.alias= +unit.2.0.port.-1.s.165.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.165.name=DataPort[165] +unit.2.0.port.-1.s.165.orderindex=-1 +unit.2.0.port.-1.s.165.visible=1 +unit.2.0.port.-1.s.166.alias= +unit.2.0.port.-1.s.166.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.166.name=DataPort[166] +unit.2.0.port.-1.s.166.orderindex=-1 +unit.2.0.port.-1.s.166.visible=1 +unit.2.0.port.-1.s.167.alias= +unit.2.0.port.-1.s.167.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.167.name=DataPort[167] +unit.2.0.port.-1.s.167.orderindex=-1 +unit.2.0.port.-1.s.167.visible=1 +unit.2.0.port.-1.s.168.alias= +unit.2.0.port.-1.s.168.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.168.name=DataPort[168] +unit.2.0.port.-1.s.168.orderindex=-1 +unit.2.0.port.-1.s.168.visible=1 +unit.2.0.port.-1.s.169.alias= +unit.2.0.port.-1.s.169.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.169.name=DataPort[169] +unit.2.0.port.-1.s.169.orderindex=-1 +unit.2.0.port.-1.s.169.visible=1 +unit.2.0.port.-1.s.17.alias= +unit.2.0.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.17.name=DataPort[17] +unit.2.0.port.-1.s.17.orderindex=-1 +unit.2.0.port.-1.s.17.visible=1 +unit.2.0.port.-1.s.170.alias= +unit.2.0.port.-1.s.170.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.170.name=DataPort[170] +unit.2.0.port.-1.s.170.orderindex=-1 +unit.2.0.port.-1.s.170.visible=1 +unit.2.0.port.-1.s.171.alias= +unit.2.0.port.-1.s.171.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.171.name=DataPort[171] +unit.2.0.port.-1.s.171.orderindex=-1 +unit.2.0.port.-1.s.171.visible=1 +unit.2.0.port.-1.s.172.alias= +unit.2.0.port.-1.s.172.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.172.name=DataPort[172] +unit.2.0.port.-1.s.172.orderindex=-1 +unit.2.0.port.-1.s.172.visible=1 +unit.2.0.port.-1.s.173.alias= +unit.2.0.port.-1.s.173.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.173.name=DataPort[173] +unit.2.0.port.-1.s.173.orderindex=-1 +unit.2.0.port.-1.s.173.visible=1 +unit.2.0.port.-1.s.174.alias= +unit.2.0.port.-1.s.174.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.174.name=DataPort[174] +unit.2.0.port.-1.s.174.orderindex=-1 +unit.2.0.port.-1.s.174.visible=1 +unit.2.0.port.-1.s.175.alias= +unit.2.0.port.-1.s.175.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.175.name=DataPort[175] +unit.2.0.port.-1.s.175.orderindex=-1 +unit.2.0.port.-1.s.175.visible=1 +unit.2.0.port.-1.s.176.alias= +unit.2.0.port.-1.s.176.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.176.name=DataPort[176] +unit.2.0.port.-1.s.176.orderindex=-1 +unit.2.0.port.-1.s.176.visible=1 +unit.2.0.port.-1.s.177.alias= +unit.2.0.port.-1.s.177.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.177.name=DataPort[177] +unit.2.0.port.-1.s.177.orderindex=-1 +unit.2.0.port.-1.s.177.visible=1 +unit.2.0.port.-1.s.178.alias= +unit.2.0.port.-1.s.178.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.178.name=DataPort[178] +unit.2.0.port.-1.s.178.orderindex=-1 +unit.2.0.port.-1.s.178.visible=1 +unit.2.0.port.-1.s.179.alias= +unit.2.0.port.-1.s.179.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.179.name=DataPort[179] +unit.2.0.port.-1.s.179.orderindex=-1 +unit.2.0.port.-1.s.179.visible=1 +unit.2.0.port.-1.s.18.alias= +unit.2.0.port.-1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.18.name=DataPort[18] +unit.2.0.port.-1.s.18.orderindex=-1 +unit.2.0.port.-1.s.18.visible=1 +unit.2.0.port.-1.s.180.alias= +unit.2.0.port.-1.s.180.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.180.name=DataPort[180] +unit.2.0.port.-1.s.180.orderindex=-1 +unit.2.0.port.-1.s.180.visible=1 +unit.2.0.port.-1.s.181.alias= +unit.2.0.port.-1.s.181.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.181.name=DataPort[181] +unit.2.0.port.-1.s.181.orderindex=-1 +unit.2.0.port.-1.s.181.visible=1 +unit.2.0.port.-1.s.182.alias= +unit.2.0.port.-1.s.182.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.182.name=DataPort[182] +unit.2.0.port.-1.s.182.orderindex=-1 +unit.2.0.port.-1.s.182.visible=1 +unit.2.0.port.-1.s.183.alias= +unit.2.0.port.-1.s.183.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.183.name=DataPort[183] +unit.2.0.port.-1.s.183.orderindex=-1 +unit.2.0.port.-1.s.183.visible=1 +unit.2.0.port.-1.s.184.alias= +unit.2.0.port.-1.s.184.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.184.name=DataPort[184] +unit.2.0.port.-1.s.184.orderindex=-1 +unit.2.0.port.-1.s.184.visible=1 +unit.2.0.port.-1.s.185.alias= +unit.2.0.port.-1.s.185.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.185.name=DataPort[185] +unit.2.0.port.-1.s.185.orderindex=-1 +unit.2.0.port.-1.s.185.visible=1 +unit.2.0.port.-1.s.186.alias=ace_stb +unit.2.0.port.-1.s.186.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.186.name=DataPort[186] +unit.2.0.port.-1.s.186.orderindex=-1 +unit.2.0.port.-1.s.186.visible=1 +unit.2.0.port.-1.s.187.alias=ace_ack +unit.2.0.port.-1.s.187.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.187.name=DataPort[187] +unit.2.0.port.-1.s.187.orderindex=-1 +unit.2.0.port.-1.s.187.visible=1 +unit.2.0.port.-1.s.188.alias=aceusb_oe_n_ +unit.2.0.port.-1.s.188.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.188.name=DataPort[188] +unit.2.0.port.-1.s.188.orderindex=-1 +unit.2.0.port.-1.s.188.visible=1 +unit.2.0.port.-1.s.189.alias=aceusb_we_n +unit.2.0.port.-1.s.189.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.189.name=DataPort[189] +unit.2.0.port.-1.s.189.orderindex=-1 +unit.2.0.port.-1.s.189.visible=1 +unit.2.0.port.-1.s.19.alias= +unit.2.0.port.-1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.19.name=DataPort[19] +unit.2.0.port.-1.s.19.orderindex=-1 +unit.2.0.port.-1.s.19.visible=1 +unit.2.0.port.-1.s.190.alias=ace_mpce_n_ +unit.2.0.port.-1.s.190.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.190.name=DataPort[190] +unit.2.0.port.-1.s.190.orderindex=-1 +unit.2.0.port.-1.s.190.visible=1 +unit.2.0.port.-1.s.191.alias= +unit.2.0.port.-1.s.191.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.191.name=DataPort[191] +unit.2.0.port.-1.s.191.orderindex=-1 +unit.2.0.port.-1.s.191.visible=1 +unit.2.0.port.-1.s.192.alias= +unit.2.0.port.-1.s.192.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.192.name=DataPort[192] +unit.2.0.port.-1.s.192.orderindex=-1 +unit.2.0.port.-1.s.192.visible=1 +unit.2.0.port.-1.s.193.alias= +unit.2.0.port.-1.s.193.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.193.name=DataPort[193] +unit.2.0.port.-1.s.193.orderindex=-1 +unit.2.0.port.-1.s.193.visible=1 +unit.2.0.port.-1.s.194.alias= +unit.2.0.port.-1.s.194.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.194.name=DataPort[194] +unit.2.0.port.-1.s.194.orderindex=-1 +unit.2.0.port.-1.s.194.visible=1 +unit.2.0.port.-1.s.195.alias= +unit.2.0.port.-1.s.195.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.195.name=DataPort[195] +unit.2.0.port.-1.s.195.orderindex=-1 +unit.2.0.port.-1.s.195.visible=1 +unit.2.0.port.-1.s.196.alias= +unit.2.0.port.-1.s.196.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.196.name=DataPort[196] +unit.2.0.port.-1.s.196.orderindex=-1 +unit.2.0.port.-1.s.196.visible=1 +unit.2.0.port.-1.s.197.alias= +unit.2.0.port.-1.s.197.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.197.name=DataPort[197] +unit.2.0.port.-1.s.197.orderindex=-1 +unit.2.0.port.-1.s.197.visible=1 +unit.2.0.port.-1.s.198.alias= +unit.2.0.port.-1.s.198.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.198.name=DataPort[198] +unit.2.0.port.-1.s.198.orderindex=-1 +unit.2.0.port.-1.s.198.visible=1 +unit.2.0.port.-1.s.199.alias= +unit.2.0.port.-1.s.199.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.199.name=DataPort[199] +unit.2.0.port.-1.s.199.orderindex=-1 +unit.2.0.port.-1.s.199.visible=1 +unit.2.0.port.-1.s.2.alias= +unit.2.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.2.name=DataPort[2] +unit.2.0.port.-1.s.2.orderindex=-1 +unit.2.0.port.-1.s.2.visible=1 +unit.2.0.port.-1.s.20.alias= +unit.2.0.port.-1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.20.name=DataPort[20] +unit.2.0.port.-1.s.20.orderindex=-1 +unit.2.0.port.-1.s.20.visible=1 +unit.2.0.port.-1.s.200.alias= +unit.2.0.port.-1.s.200.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.200.name=DataPort[200] +unit.2.0.port.-1.s.200.orderindex=-1 +unit.2.0.port.-1.s.200.visible=1 +unit.2.0.port.-1.s.201.alias= +unit.2.0.port.-1.s.201.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.201.name=DataPort[201] +unit.2.0.port.-1.s.201.orderindex=-1 +unit.2.0.port.-1.s.201.visible=1 +unit.2.0.port.-1.s.202.alias= +unit.2.0.port.-1.s.202.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.202.name=DataPort[202] +unit.2.0.port.-1.s.202.orderindex=-1 +unit.2.0.port.-1.s.202.visible=1 +unit.2.0.port.-1.s.203.alias= +unit.2.0.port.-1.s.203.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.203.name=DataPort[203] +unit.2.0.port.-1.s.203.orderindex=-1 +unit.2.0.port.-1.s.203.visible=1 +unit.2.0.port.-1.s.204.alias= +unit.2.0.port.-1.s.204.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.204.name=DataPort[204] +unit.2.0.port.-1.s.204.orderindex=-1 +unit.2.0.port.-1.s.204.visible=1 +unit.2.0.port.-1.s.205.alias= +unit.2.0.port.-1.s.205.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.205.name=DataPort[205] +unit.2.0.port.-1.s.205.orderindex=-1 +unit.2.0.port.-1.s.205.visible=1 +unit.2.0.port.-1.s.206.alias= +unit.2.0.port.-1.s.206.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.206.name=DataPort[206] +unit.2.0.port.-1.s.206.orderindex=-1 +unit.2.0.port.-1.s.206.visible=1 +unit.2.0.port.-1.s.207.alias=iid +unit.2.0.port.-1.s.207.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.207.name=DataPort[207] +unit.2.0.port.-1.s.207.orderindex=-1 +unit.2.0.port.-1.s.207.visible=1 +unit.2.0.port.-1.s.208.alias=irr0 +unit.2.0.port.-1.s.208.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.208.name=DataPort[208] +unit.2.0.port.-1.s.208.orderindex=-1 +unit.2.0.port.-1.s.208.visible=1 +unit.2.0.port.-1.s.209.alias=irr1 +unit.2.0.port.-1.s.209.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.209.name=DataPort[209] +unit.2.0.port.-1.s.209.orderindex=-1 +unit.2.0.port.-1.s.209.visible=1 +unit.2.0.port.-1.s.21.alias= +unit.2.0.port.-1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.21.name=DataPort[21] +unit.2.0.port.-1.s.21.orderindex=-1 +unit.2.0.port.-1.s.21.visible=1 +unit.2.0.port.-1.s.210.alias=int0 +unit.2.0.port.-1.s.210.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.210.name=DataPort[210] +unit.2.0.port.-1.s.210.orderindex=-1 +unit.2.0.port.-1.s.210.visible=1 +unit.2.0.port.-1.s.211.alias=int1 +unit.2.0.port.-1.s.211.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.211.name=DataPort[211] +unit.2.0.port.-1.s.211.orderindex=-1 +unit.2.0.port.-1.s.211.visible=1 +unit.2.0.port.-1.s.212.alias=released +unit.2.0.port.-1.s.212.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.212.name=DataPort[212] +unit.2.0.port.-1.s.212.orderindex=-1 +unit.2.0.port.-1.s.212.visible=1 +unit.2.0.port.-1.s.213.alias=rx_shift +unit.2.0.port.-1.s.213.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.213.name=DataPort[213] +unit.2.0.port.-1.s.213.orderindex=-1 +unit.2.0.port.-1.s.213.visible=1 +unit.2.0.port.-1.s.214.alias=rx_output +unit.2.0.port.-1.s.214.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.214.name=DataPort[214] +unit.2.0.port.-1.s.214.orderindex=-1 +unit.2.0.port.-1.s.214.visible=1 +unit.2.0.port.-1.s.215.alias=nada +unit.2.0.port.-1.s.215.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.215.name=DataPort[215] +unit.2.0.port.-1.s.215.orderindex=-1 +unit.2.0.port.-1.s.215.visible=1 +unit.2.0.port.-1.s.216.alias= +unit.2.0.port.-1.s.216.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.216.name=DataPort[216] +unit.2.0.port.-1.s.216.orderindex=-1 +unit.2.0.port.-1.s.216.visible=1 +unit.2.0.port.-1.s.217.alias= +unit.2.0.port.-1.s.217.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.217.name=DataPort[217] +unit.2.0.port.-1.s.217.orderindex=-1 +unit.2.0.port.-1.s.217.visible=1 +unit.2.0.port.-1.s.218.alias= +unit.2.0.port.-1.s.218.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.218.name=DataPort[218] +unit.2.0.port.-1.s.218.orderindex=-1 +unit.2.0.port.-1.s.218.visible=1 +unit.2.0.port.-1.s.219.alias=op +unit.2.0.port.-1.s.219.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.219.name=DataPort[219] +unit.2.0.port.-1.s.219.orderindex=-1 +unit.2.0.port.-1.s.219.visible=1 +unit.2.0.port.-1.s.22.alias= +unit.2.0.port.-1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.22.name=DataPort[22] +unit.2.0.port.-1.s.22.orderindex=-1 +unit.2.0.port.-1.s.22.visible=1 +unit.2.0.port.-1.s.220.alias=zbt_stb +unit.2.0.port.-1.s.220.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.220.name=DataPort[220] +unit.2.0.port.-1.s.220.orderindex=-1 +unit.2.0.port.-1.s.220.visible=1 +unit.2.0.port.-1.s.221.alias=flash_stb +unit.2.0.port.-1.s.221.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.221.name=DataPort[221] +unit.2.0.port.-1.s.221.orderindex=-1 +unit.2.0.port.-1.s.221.visible=1 +unit.2.0.port.-1.s.222.alias=flash_arena +unit.2.0.port.-1.s.222.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.222.name=DataPort[222] +unit.2.0.port.-1.s.222.orderindex=-1 +unit.2.0.port.-1.s.222.visible=1 +unit.2.0.port.-1.s.223.alias=vdu_arena +unit.2.0.port.-1.s.223.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.223.name=DataPort[223] +unit.2.0.port.-1.s.223.orderindex=-1 +unit.2.0.port.-1.s.223.visible=1 +unit.2.0.port.-1.s.224.alias=cnt_time0 +unit.2.0.port.-1.s.224.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.224.name=DataPort[224] +unit.2.0.port.-1.s.224.orderindex=-1 +unit.2.0.port.-1.s.224.visible=1 +unit.2.0.port.-1.s.225.alias=cnt_time1 +unit.2.0.port.-1.s.225.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.225.name=DataPort[225] +unit.2.0.port.-1.s.225.orderindex=-1 +unit.2.0.port.-1.s.225.visible=1 +unit.2.0.port.-1.s.226.alias=cnt_time2 +unit.2.0.port.-1.s.226.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.226.name=DataPort[226] +unit.2.0.port.-1.s.226.orderindex=-1 +unit.2.0.port.-1.s.226.visible=1 +unit.2.0.port.-1.s.227.alias=cnt_time3 +unit.2.0.port.-1.s.227.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.227.name=DataPort[227] +unit.2.0.port.-1.s.227.orderindex=-1 +unit.2.0.port.-1.s.227.visible=1 +unit.2.0.port.-1.s.228.alias=cnt_time4 +unit.2.0.port.-1.s.228.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.228.name=DataPort[228] +unit.2.0.port.-1.s.228.orderindex=-1 +unit.2.0.port.-1.s.228.visible=1 +unit.2.0.port.-1.s.229.alias= +unit.2.0.port.-1.s.229.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.229.name=DataPort[229] +unit.2.0.port.-1.s.229.orderindex=-1 +unit.2.0.port.-1.s.229.visible=1 +unit.2.0.port.-1.s.23.alias= +unit.2.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.23.name=DataPort[23] +unit.2.0.port.-1.s.23.orderindex=-1 +unit.2.0.port.-1.s.23.visible=1 +unit.2.0.port.-1.s.230.alias= +unit.2.0.port.-1.s.230.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.230.name=DataPort[230] +unit.2.0.port.-1.s.230.orderindex=-1 +unit.2.0.port.-1.s.230.visible=1 +unit.2.0.port.-1.s.231.alias= +unit.2.0.port.-1.s.231.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.231.name=DataPort[231] +unit.2.0.port.-1.s.231.orderindex=-1 +unit.2.0.port.-1.s.231.visible=1 +unit.2.0.port.-1.s.232.alias= +unit.2.0.port.-1.s.232.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.232.name=DataPort[232] +unit.2.0.port.-1.s.232.orderindex=-1 +unit.2.0.port.-1.s.232.visible=1 +unit.2.0.port.-1.s.233.alias= +unit.2.0.port.-1.s.233.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.233.name=DataPort[233] +unit.2.0.port.-1.s.233.orderindex=-1 +unit.2.0.port.-1.s.233.visible=1 +unit.2.0.port.-1.s.234.alias= +unit.2.0.port.-1.s.234.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.234.name=DataPort[234] +unit.2.0.port.-1.s.234.orderindex=-1 +unit.2.0.port.-1.s.234.visible=1 +unit.2.0.port.-1.s.235.alias= +unit.2.0.port.-1.s.235.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.235.name=DataPort[235] +unit.2.0.port.-1.s.235.orderindex=-1 +unit.2.0.port.-1.s.235.visible=1 +unit.2.0.port.-1.s.236.alias= +unit.2.0.port.-1.s.236.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.236.name=DataPort[236] +unit.2.0.port.-1.s.236.orderindex=-1 +unit.2.0.port.-1.s.236.visible=1 +unit.2.0.port.-1.s.237.alias= +unit.2.0.port.-1.s.237.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.237.name=DataPort[237] +unit.2.0.port.-1.s.237.orderindex=-1 +unit.2.0.port.-1.s.237.visible=1 +unit.2.0.port.-1.s.238.alias= +unit.2.0.port.-1.s.238.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.238.name=DataPort[238] +unit.2.0.port.-1.s.238.orderindex=-1 +unit.2.0.port.-1.s.238.visible=1 +unit.2.0.port.-1.s.239.alias= +unit.2.0.port.-1.s.239.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.239.name=DataPort[239] +unit.2.0.port.-1.s.239.orderindex=-1 +unit.2.0.port.-1.s.239.visible=1 +unit.2.0.port.-1.s.24.alias= +unit.2.0.port.-1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.24.name=DataPort[24] +unit.2.0.port.-1.s.24.orderindex=-1 +unit.2.0.port.-1.s.24.visible=1 +unit.2.0.port.-1.s.240.alias= +unit.2.0.port.-1.s.240.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.240.name=DataPort[240] +unit.2.0.port.-1.s.240.orderindex=-1 +unit.2.0.port.-1.s.240.visible=1 +unit.2.0.port.-1.s.241.alias= +unit.2.0.port.-1.s.241.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.241.name=DataPort[241] +unit.2.0.port.-1.s.241.orderindex=-1 +unit.2.0.port.-1.s.241.visible=1 +unit.2.0.port.-1.s.242.alias= +unit.2.0.port.-1.s.242.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.242.name=DataPort[242] +unit.2.0.port.-1.s.242.orderindex=-1 +unit.2.0.port.-1.s.242.visible=1 +unit.2.0.port.-1.s.243.alias= +unit.2.0.port.-1.s.243.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.243.name=DataPort[243] +unit.2.0.port.-1.s.243.orderindex=-1 +unit.2.0.port.-1.s.243.visible=1 +unit.2.0.port.-1.s.244.alias= +unit.2.0.port.-1.s.244.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.244.name=DataPort[244] +unit.2.0.port.-1.s.244.orderindex=-1 +unit.2.0.port.-1.s.244.visible=1 +unit.2.0.port.-1.s.245.alias= +unit.2.0.port.-1.s.245.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.245.name=DataPort[245] +unit.2.0.port.-1.s.245.orderindex=-1 +unit.2.0.port.-1.s.245.visible=1 +unit.2.0.port.-1.s.246.alias= +unit.2.0.port.-1.s.246.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.246.name=DataPort[246] +unit.2.0.port.-1.s.246.orderindex=-1 +unit.2.0.port.-1.s.246.visible=1 +unit.2.0.port.-1.s.247.alias= +unit.2.0.port.-1.s.247.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.247.name=DataPort[247] +unit.2.0.port.-1.s.247.orderindex=-1 +unit.2.0.port.-1.s.247.visible=1 +unit.2.0.port.-1.s.248.alias= +unit.2.0.port.-1.s.248.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.248.name=DataPort[248] +unit.2.0.port.-1.s.248.orderindex=-1 +unit.2.0.port.-1.s.248.visible=1 +unit.2.0.port.-1.s.249.alias= +unit.2.0.port.-1.s.249.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.249.name=DataPort[249] +unit.2.0.port.-1.s.249.orderindex=-1 +unit.2.0.port.-1.s.249.visible=1 +unit.2.0.port.-1.s.25.alias= +unit.2.0.port.-1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.25.name=DataPort[25] +unit.2.0.port.-1.s.25.orderindex=-1 +unit.2.0.port.-1.s.25.visible=1 +unit.2.0.port.-1.s.250.alias= +unit.2.0.port.-1.s.250.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.250.name=DataPort[250] +unit.2.0.port.-1.s.250.orderindex=-1 +unit.2.0.port.-1.s.250.visible=1 +unit.2.0.port.-1.s.251.alias= +unit.2.0.port.-1.s.251.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.251.name=DataPort[251] +unit.2.0.port.-1.s.251.orderindex=-1 +unit.2.0.port.-1.s.251.visible=1 +unit.2.0.port.-1.s.252.alias= +unit.2.0.port.-1.s.252.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.252.name=DataPort[252] +unit.2.0.port.-1.s.252.orderindex=-1 +unit.2.0.port.-1.s.252.visible=1 +unit.2.0.port.-1.s.253.alias= +unit.2.0.port.-1.s.253.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.253.name=DataPort[253] +unit.2.0.port.-1.s.253.orderindex=-1 +unit.2.0.port.-1.s.253.visible=1 +unit.2.0.port.-1.s.254.alias= +unit.2.0.port.-1.s.254.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.254.name=DataPort[254] +unit.2.0.port.-1.s.254.orderindex=-1 +unit.2.0.port.-1.s.254.visible=1 +unit.2.0.port.-1.s.255.alias= +unit.2.0.port.-1.s.255.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.255.name=DataPort[255] +unit.2.0.port.-1.s.255.orderindex=-1 +unit.2.0.port.-1.s.255.visible=1 +unit.2.0.port.-1.s.26.alias= +unit.2.0.port.-1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.26.name=DataPort[26] +unit.2.0.port.-1.s.26.orderindex=-1 +unit.2.0.port.-1.s.26.visible=1 +unit.2.0.port.-1.s.27.alias= +unit.2.0.port.-1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.27.name=DataPort[27] +unit.2.0.port.-1.s.27.orderindex=-1 +unit.2.0.port.-1.s.27.visible=1 +unit.2.0.port.-1.s.28.alias= +unit.2.0.port.-1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.28.name=DataPort[28] +unit.2.0.port.-1.s.28.orderindex=-1 +unit.2.0.port.-1.s.28.visible=1 +unit.2.0.port.-1.s.29.alias= +unit.2.0.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.29.name=DataPort[29] +unit.2.0.port.-1.s.29.orderindex=-1 +unit.2.0.port.-1.s.29.visible=1 +unit.2.0.port.-1.s.3.alias= +unit.2.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.3.name=DataPort[3] +unit.2.0.port.-1.s.3.orderindex=-1 +unit.2.0.port.-1.s.3.visible=1 +unit.2.0.port.-1.s.30.alias= +unit.2.0.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.30.name=DataPort[30] +unit.2.0.port.-1.s.30.orderindex=-1 +unit.2.0.port.-1.s.30.visible=1 +unit.2.0.port.-1.s.31.alias= +unit.2.0.port.-1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.31.name=DataPort[31] +unit.2.0.port.-1.s.31.orderindex=-1 +unit.2.0.port.-1.s.31.visible=1 +unit.2.0.port.-1.s.32.alias= +unit.2.0.port.-1.s.32.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.32.name=DataPort[32] +unit.2.0.port.-1.s.32.orderindex=-1 +unit.2.0.port.-1.s.32.visible=1 +unit.2.0.port.-1.s.33.alias= +unit.2.0.port.-1.s.33.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.33.name=DataPort[33] +unit.2.0.port.-1.s.33.orderindex=-1 +unit.2.0.port.-1.s.33.visible=1 +unit.2.0.port.-1.s.34.alias= +unit.2.0.port.-1.s.34.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.34.name=DataPort[34] +unit.2.0.port.-1.s.34.orderindex=-1 +unit.2.0.port.-1.s.34.visible=1 +unit.2.0.port.-1.s.35.alias= +unit.2.0.port.-1.s.35.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.35.name=DataPort[35] +unit.2.0.port.-1.s.35.orderindex=-1 +unit.2.0.port.-1.s.35.visible=1 +unit.2.0.port.-1.s.36.alias= +unit.2.0.port.-1.s.36.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.36.name=DataPort[36] +unit.2.0.port.-1.s.36.orderindex=-1 +unit.2.0.port.-1.s.36.visible=1 +unit.2.0.port.-1.s.37.alias= +unit.2.0.port.-1.s.37.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.37.name=DataPort[37] +unit.2.0.port.-1.s.37.orderindex=-1 +unit.2.0.port.-1.s.37.visible=1 +unit.2.0.port.-1.s.38.alias= +unit.2.0.port.-1.s.38.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.38.name=DataPort[38] +unit.2.0.port.-1.s.38.orderindex=-1 +unit.2.0.port.-1.s.38.visible=1 +unit.2.0.port.-1.s.39.alias= +unit.2.0.port.-1.s.39.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.39.name=DataPort[39] +unit.2.0.port.-1.s.39.orderindex=-1 +unit.2.0.port.-1.s.39.visible=1 +unit.2.0.port.-1.s.4.alias= +unit.2.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.4.name=DataPort[4] +unit.2.0.port.-1.s.4.orderindex=-1 +unit.2.0.port.-1.s.4.visible=1 +unit.2.0.port.-1.s.40.alias= +unit.2.0.port.-1.s.40.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.40.name=DataPort[40] +unit.2.0.port.-1.s.40.orderindex=-1 +unit.2.0.port.-1.s.40.visible=1 +unit.2.0.port.-1.s.41.alias= +unit.2.0.port.-1.s.41.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.41.name=DataPort[41] +unit.2.0.port.-1.s.41.orderindex=-1 +unit.2.0.port.-1.s.41.visible=1 +unit.2.0.port.-1.s.42.alias= +unit.2.0.port.-1.s.42.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.42.name=DataPort[42] +unit.2.0.port.-1.s.42.orderindex=-1 +unit.2.0.port.-1.s.42.visible=1 +unit.2.0.port.-1.s.43.alias= +unit.2.0.port.-1.s.43.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.43.name=DataPort[43] +unit.2.0.port.-1.s.43.orderindex=-1 +unit.2.0.port.-1.s.43.visible=1 +unit.2.0.port.-1.s.44.alias= +unit.2.0.port.-1.s.44.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.44.name=DataPort[44] +unit.2.0.port.-1.s.44.orderindex=-1 +unit.2.0.port.-1.s.44.visible=1 +unit.2.0.port.-1.s.45.alias= +unit.2.0.port.-1.s.45.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.45.name=DataPort[45] +unit.2.0.port.-1.s.45.orderindex=-1 +unit.2.0.port.-1.s.45.visible=1 +unit.2.0.port.-1.s.46.alias= +unit.2.0.port.-1.s.46.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.46.name=DataPort[46] +unit.2.0.port.-1.s.46.orderindex=-1 +unit.2.0.port.-1.s.46.visible=1 +unit.2.0.port.-1.s.47.alias= +unit.2.0.port.-1.s.47.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.47.name=DataPort[47] +unit.2.0.port.-1.s.47.orderindex=-1 +unit.2.0.port.-1.s.47.visible=1 +unit.2.0.port.-1.s.48.alias= +unit.2.0.port.-1.s.48.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.48.name=DataPort[48] +unit.2.0.port.-1.s.48.orderindex=-1 +unit.2.0.port.-1.s.48.visible=1 +unit.2.0.port.-1.s.49.alias= +unit.2.0.port.-1.s.49.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.49.name=DataPort[49] +unit.2.0.port.-1.s.49.orderindex=-1 +unit.2.0.port.-1.s.49.visible=1 +unit.2.0.port.-1.s.5.alias= +unit.2.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.5.name=DataPort[5] +unit.2.0.port.-1.s.5.orderindex=-1 +unit.2.0.port.-1.s.5.visible=1 +unit.2.0.port.-1.s.50.alias= +unit.2.0.port.-1.s.50.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.50.name=DataPort[50] +unit.2.0.port.-1.s.50.orderindex=-1 +unit.2.0.port.-1.s.50.visible=1 +unit.2.0.port.-1.s.51.alias= +unit.2.0.port.-1.s.51.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.51.name=DataPort[51] +unit.2.0.port.-1.s.51.orderindex=-1 +unit.2.0.port.-1.s.51.visible=1 +unit.2.0.port.-1.s.52.alias= +unit.2.0.port.-1.s.52.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.52.name=DataPort[52] +unit.2.0.port.-1.s.52.orderindex=-1 +unit.2.0.port.-1.s.52.visible=1 +unit.2.0.port.-1.s.53.alias= +unit.2.0.port.-1.s.53.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.53.name=DataPort[53] +unit.2.0.port.-1.s.53.orderindex=-1 +unit.2.0.port.-1.s.53.visible=1 +unit.2.0.port.-1.s.54.alias= +unit.2.0.port.-1.s.54.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.54.name=DataPort[54] +unit.2.0.port.-1.s.54.orderindex=-1 +unit.2.0.port.-1.s.54.visible=1 +unit.2.0.port.-1.s.55.alias= +unit.2.0.port.-1.s.55.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.55.name=DataPort[55] +unit.2.0.port.-1.s.55.orderindex=-1 +unit.2.0.port.-1.s.55.visible=1 +unit.2.0.port.-1.s.56.alias= +unit.2.0.port.-1.s.56.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.56.name=DataPort[56] +unit.2.0.port.-1.s.56.orderindex=-1 +unit.2.0.port.-1.s.56.visible=1 +unit.2.0.port.-1.s.57.alias= +unit.2.0.port.-1.s.57.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.57.name=DataPort[57] +unit.2.0.port.-1.s.57.orderindex=-1 +unit.2.0.port.-1.s.57.visible=1 +unit.2.0.port.-1.s.58.alias= +unit.2.0.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.58.name=DataPort[58] +unit.2.0.port.-1.s.58.orderindex=-1 +unit.2.0.port.-1.s.58.visible=1 +unit.2.0.port.-1.s.59.alias= +unit.2.0.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.59.name=DataPort[59] +unit.2.0.port.-1.s.59.orderindex=-1 +unit.2.0.port.-1.s.59.visible=1 +unit.2.0.port.-1.s.6.alias= +unit.2.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.6.name=DataPort[6] +unit.2.0.port.-1.s.6.orderindex=-1 +unit.2.0.port.-1.s.6.visible=1 +unit.2.0.port.-1.s.60.alias= +unit.2.0.port.-1.s.60.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.60.name=DataPort[60] +unit.2.0.port.-1.s.60.orderindex=-1 +unit.2.0.port.-1.s.60.visible=1 +unit.2.0.port.-1.s.61.alias= +unit.2.0.port.-1.s.61.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.61.name=DataPort[61] +unit.2.0.port.-1.s.61.orderindex=-1 +unit.2.0.port.-1.s.61.visible=1 +unit.2.0.port.-1.s.62.alias= +unit.2.0.port.-1.s.62.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.62.name=DataPort[62] +unit.2.0.port.-1.s.62.orderindex=-1 +unit.2.0.port.-1.s.62.visible=1 +unit.2.0.port.-1.s.63.alias= +unit.2.0.port.-1.s.63.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.63.name=DataPort[63] +unit.2.0.port.-1.s.63.orderindex=-1 +unit.2.0.port.-1.s.63.visible=1 +unit.2.0.port.-1.s.64.alias= +unit.2.0.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.64.name=DataPort[64] +unit.2.0.port.-1.s.64.orderindex=-1 +unit.2.0.port.-1.s.64.visible=1 +unit.2.0.port.-1.s.65.alias= +unit.2.0.port.-1.s.65.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.65.name=DataPort[65] +unit.2.0.port.-1.s.65.orderindex=-1 +unit.2.0.port.-1.s.65.visible=1 +unit.2.0.port.-1.s.66.alias= +unit.2.0.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.66.name=DataPort[66] +unit.2.0.port.-1.s.66.orderindex=-1 +unit.2.0.port.-1.s.66.visible=1 +unit.2.0.port.-1.s.67.alias= +unit.2.0.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.67.name=DataPort[67] +unit.2.0.port.-1.s.67.orderindex=-1 +unit.2.0.port.-1.s.67.visible=1 +unit.2.0.port.-1.s.68.alias= +unit.2.0.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.68.name=DataPort[68] +unit.2.0.port.-1.s.68.orderindex=-1 +unit.2.0.port.-1.s.68.visible=1 +unit.2.0.port.-1.s.69.alias= +unit.2.0.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.69.name=DataPort[69] +unit.2.0.port.-1.s.69.orderindex=-1 +unit.2.0.port.-1.s.69.visible=1 +unit.2.0.port.-1.s.7.alias= +unit.2.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.7.name=DataPort[7] +unit.2.0.port.-1.s.7.orderindex=-1 +unit.2.0.port.-1.s.7.visible=1 +unit.2.0.port.-1.s.70.alias= +unit.2.0.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.70.name=DataPort[70] +unit.2.0.port.-1.s.70.orderindex=-1 +unit.2.0.port.-1.s.70.visible=1 +unit.2.0.port.-1.s.71.alias= +unit.2.0.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.71.name=DataPort[71] +unit.2.0.port.-1.s.71.orderindex=-1 +unit.2.0.port.-1.s.71.visible=1 +unit.2.0.port.-1.s.72.alias=ack +unit.2.0.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.72.name=DataPort[72] +unit.2.0.port.-1.s.72.orderindex=-1 +unit.2.0.port.-1.s.72.visible=1 +unit.2.0.port.-1.s.73.alias=stb +unit.2.0.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.73.name=DataPort[73] +unit.2.0.port.-1.s.73.orderindex=-1 +unit.2.0.port.-1.s.73.visible=1 +unit.2.0.port.-1.s.74.alias=cyc +unit.2.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.74.name=DataPort[74] +unit.2.0.port.-1.s.74.orderindex=-1 +unit.2.0.port.-1.s.74.visible=1 +unit.2.0.port.-1.s.75.alias=tga +unit.2.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.75.name=DataPort[75] +unit.2.0.port.-1.s.75.orderindex=-1 +unit.2.0.port.-1.s.75.visible=1 +unit.2.0.port.-1.s.76.alias=we +unit.2.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.76.name=DataPort[76] +unit.2.0.port.-1.s.76.orderindex=-1 +unit.2.0.port.-1.s.76.visible=1 +unit.2.0.port.-1.s.77.alias=clk +unit.2.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.77.name=DataPort[77] +unit.2.0.port.-1.s.77.orderindex=-1 +unit.2.0.port.-1.s.77.visible=1 +unit.2.0.port.-1.s.78.alias= +unit.2.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.78.name=DataPort[78] +unit.2.0.port.-1.s.78.orderindex=-1 +unit.2.0.port.-1.s.78.visible=1 +unit.2.0.port.-1.s.79.alias= +unit.2.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.79.name=DataPort[79] +unit.2.0.port.-1.s.79.orderindex=-1 +unit.2.0.port.-1.s.79.visible=1 +unit.2.0.port.-1.s.8.alias= +unit.2.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.8.name=DataPort[8] +unit.2.0.port.-1.s.8.orderindex=-1 +unit.2.0.port.-1.s.8.visible=1 +unit.2.0.port.-1.s.80.alias= +unit.2.0.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.80.name=DataPort[80] +unit.2.0.port.-1.s.80.orderindex=-1 +unit.2.0.port.-1.s.80.visible=1 +unit.2.0.port.-1.s.81.alias= +unit.2.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.81.name=DataPort[81] +unit.2.0.port.-1.s.81.orderindex=-1 +unit.2.0.port.-1.s.81.visible=1 +unit.2.0.port.-1.s.82.alias= +unit.2.0.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.82.name=DataPort[82] +unit.2.0.port.-1.s.82.orderindex=-1 +unit.2.0.port.-1.s.82.visible=1 +unit.2.0.port.-1.s.83.alias= +unit.2.0.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.83.name=DataPort[83] +unit.2.0.port.-1.s.83.orderindex=-1 +unit.2.0.port.-1.s.83.visible=1 +unit.2.0.port.-1.s.84.alias= +unit.2.0.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.84.name=DataPort[84] +unit.2.0.port.-1.s.84.orderindex=-1 +unit.2.0.port.-1.s.84.visible=1 +unit.2.0.port.-1.s.85.alias= +unit.2.0.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.85.name=DataPort[85] +unit.2.0.port.-1.s.85.orderindex=-1 +unit.2.0.port.-1.s.85.visible=1 +unit.2.0.port.-1.s.86.alias= +unit.2.0.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.86.name=DataPort[86] +unit.2.0.port.-1.s.86.orderindex=-1 +unit.2.0.port.-1.s.86.visible=1 +unit.2.0.port.-1.s.87.alias= +unit.2.0.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.87.name=DataPort[87] +unit.2.0.port.-1.s.87.orderindex=-1 +unit.2.0.port.-1.s.87.visible=1 +unit.2.0.port.-1.s.88.alias= +unit.2.0.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.88.name=DataPort[88] +unit.2.0.port.-1.s.88.orderindex=-1 +unit.2.0.port.-1.s.88.visible=1 +unit.2.0.port.-1.s.89.alias= +unit.2.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.89.name=DataPort[89] +unit.2.0.port.-1.s.89.orderindex=-1 +unit.2.0.port.-1.s.89.visible=1 +unit.2.0.port.-1.s.9.alias= +unit.2.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.9.name=DataPort[9] +unit.2.0.port.-1.s.9.orderindex=-1 +unit.2.0.port.-1.s.9.visible=1 +unit.2.0.port.-1.s.90.alias= +unit.2.0.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.90.name=DataPort[90] +unit.2.0.port.-1.s.90.orderindex=-1 +unit.2.0.port.-1.s.90.visible=1 +unit.2.0.port.-1.s.91.alias= +unit.2.0.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.91.name=DataPort[91] +unit.2.0.port.-1.s.91.orderindex=-1 +unit.2.0.port.-1.s.91.visible=1 +unit.2.0.port.-1.s.92.alias= +unit.2.0.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.92.name=DataPort[92] +unit.2.0.port.-1.s.92.orderindex=-1 +unit.2.0.port.-1.s.92.visible=1 +unit.2.0.port.-1.s.93.alias= +unit.2.0.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.93.name=DataPort[93] +unit.2.0.port.-1.s.93.orderindex=-1 +unit.2.0.port.-1.s.93.visible=1 +unit.2.0.port.-1.s.94.alias=byte_op +unit.2.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.94.name=DataPort[94] +unit.2.0.port.-1.s.94.orderindex=-1 +unit.2.0.port.-1.s.94.visible=1 +unit.2.0.port.-1.s.95.alias= +unit.2.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.95.name=DataPort[95] +unit.2.0.port.-1.s.95.orderindex=-1 +unit.2.0.port.-1.s.95.visible=1 +unit.2.0.port.-1.s.96.alias= +unit.2.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.96.name=DataPort[96] +unit.2.0.port.-1.s.96.orderindex=-1 +unit.2.0.port.-1.s.96.visible=1 +unit.2.0.port.-1.s.97.alias= +unit.2.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.97.name=DataPort[97] +unit.2.0.port.-1.s.97.orderindex=-1 +unit.2.0.port.-1.s.97.visible=1 +unit.2.0.port.-1.s.98.alias= +unit.2.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.98.name=DataPort[98] +unit.2.0.port.-1.s.98.orderindex=-1 +unit.2.0.port.-1.s.98.visible=1 +unit.2.0.port.-1.s.99.alias= +unit.2.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.-1.s.99.name=DataPort[99] +unit.2.0.port.-1.s.99.orderindex=-1 +unit.2.0.port.-1.s.99.visible=1 +unit.2.0.port.0.b.0.alias= +unit.2.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +unit.2.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.b.0.name=TriggerPort0 +unit.2.0.port.0.b.0.orderindex=-1 +unit.2.0.port.0.b.0.radix=Hex +unit.2.0.port.0.b.0.signedOffset=0.0 +unit.2.0.port.0.b.0.signedPrecision=0 +unit.2.0.port.0.b.0.signedScaleFactor=1.0 +unit.2.0.port.0.b.0.unsignedOffset=0.0 +unit.2.0.port.0.b.0.unsignedPrecision=0 +unit.2.0.port.0.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.0.b.0.visible=1 +unit.2.0.port.0.buscount=1 +unit.2.0.port.0.channelcount=20 +unit.2.0.port.0.s.0.alias= +unit.2.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.0.name=TriggerPort0[0] +unit.2.0.port.0.s.0.orderindex=-1 +unit.2.0.port.0.s.0.visible=1 +unit.2.0.port.0.s.1.alias= +unit.2.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.1.name=TriggerPort0[1] +unit.2.0.port.0.s.1.orderindex=-1 +unit.2.0.port.0.s.1.visible=1 +unit.2.0.port.0.s.10.alias= +unit.2.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.10.name=TriggerPort0[10] +unit.2.0.port.0.s.10.orderindex=-1 +unit.2.0.port.0.s.10.visible=1 +unit.2.0.port.0.s.11.alias= +unit.2.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.11.name=TriggerPort0[11] +unit.2.0.port.0.s.11.orderindex=-1 +unit.2.0.port.0.s.11.visible=1 +unit.2.0.port.0.s.12.alias= +unit.2.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.12.name=TriggerPort0[12] +unit.2.0.port.0.s.12.orderindex=-1 +unit.2.0.port.0.s.12.visible=1 +unit.2.0.port.0.s.13.alias= +unit.2.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.13.name=TriggerPort0[13] +unit.2.0.port.0.s.13.orderindex=-1 +unit.2.0.port.0.s.13.visible=1 +unit.2.0.port.0.s.14.alias= +unit.2.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.14.name=TriggerPort0[14] +unit.2.0.port.0.s.14.orderindex=-1 +unit.2.0.port.0.s.14.visible=1 +unit.2.0.port.0.s.15.alias= +unit.2.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.15.name=TriggerPort0[15] +unit.2.0.port.0.s.15.orderindex=-1 +unit.2.0.port.0.s.15.visible=1 +unit.2.0.port.0.s.16.alias= +unit.2.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.16.name=TriggerPort0[16] +unit.2.0.port.0.s.16.orderindex=-1 +unit.2.0.port.0.s.16.visible=1 +unit.2.0.port.0.s.17.alias= +unit.2.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.17.name=TriggerPort0[17] +unit.2.0.port.0.s.17.orderindex=-1 +unit.2.0.port.0.s.17.visible=1 +unit.2.0.port.0.s.18.alias= +unit.2.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.18.name=TriggerPort0[18] +unit.2.0.port.0.s.18.orderindex=-1 +unit.2.0.port.0.s.18.visible=1 +unit.2.0.port.0.s.19.alias= +unit.2.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.19.name=TriggerPort0[19] +unit.2.0.port.0.s.19.orderindex=-1 +unit.2.0.port.0.s.19.visible=1 +unit.2.0.port.0.s.2.alias= +unit.2.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.2.name=TriggerPort0[2] +unit.2.0.port.0.s.2.orderindex=-1 +unit.2.0.port.0.s.2.visible=1 +unit.2.0.port.0.s.3.alias= +unit.2.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.3.name=TriggerPort0[3] +unit.2.0.port.0.s.3.orderindex=-1 +unit.2.0.port.0.s.3.visible=1 +unit.2.0.port.0.s.4.alias= +unit.2.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.4.name=TriggerPort0[4] +unit.2.0.port.0.s.4.orderindex=-1 +unit.2.0.port.0.s.4.visible=1 +unit.2.0.port.0.s.5.alias= +unit.2.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.5.name=TriggerPort0[5] +unit.2.0.port.0.s.5.orderindex=-1 +unit.2.0.port.0.s.5.visible=1 +unit.2.0.port.0.s.6.alias= +unit.2.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.6.name=TriggerPort0[6] +unit.2.0.port.0.s.6.orderindex=-1 +unit.2.0.port.0.s.6.visible=1 +unit.2.0.port.0.s.7.alias= +unit.2.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.7.name=TriggerPort0[7] +unit.2.0.port.0.s.7.orderindex=-1 +unit.2.0.port.0.s.7.visible=1 +unit.2.0.port.0.s.8.alias= +unit.2.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.8.name=TriggerPort0[8] +unit.2.0.port.0.s.8.orderindex=-1 +unit.2.0.port.0.s.8.visible=1 +unit.2.0.port.0.s.9.alias= +unit.2.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.0.s.9.name=TriggerPort0[9] +unit.2.0.port.0.s.9.orderindex=-1 +unit.2.0.port.0.s.9.visible=1 +unit.2.0.port.1.b.0.alias= +unit.2.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +unit.2.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.b.0.name=TriggerPort1 +unit.2.0.port.1.b.0.orderindex=-1 +unit.2.0.port.1.b.0.radix=Hex +unit.2.0.port.1.b.0.signedOffset=0.0 +unit.2.0.port.1.b.0.signedPrecision=0 +unit.2.0.port.1.b.0.signedScaleFactor=1.0 +unit.2.0.port.1.b.0.unsignedOffset=0.0 +unit.2.0.port.1.b.0.unsignedPrecision=0 +unit.2.0.port.1.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.1.b.0.visible=1 +unit.2.0.port.1.buscount=1 +unit.2.0.port.1.channelcount=32 +unit.2.0.port.1.s.0.alias= +unit.2.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.0.name=TriggerPort1[0] +unit.2.0.port.1.s.0.orderindex=-1 +unit.2.0.port.1.s.0.visible=1 +unit.2.0.port.1.s.1.alias= +unit.2.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.1.name=TriggerPort1[1] +unit.2.0.port.1.s.1.orderindex=-1 +unit.2.0.port.1.s.1.visible=1 +unit.2.0.port.1.s.10.alias= +unit.2.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.10.name=TriggerPort1[10] +unit.2.0.port.1.s.10.orderindex=-1 +unit.2.0.port.1.s.10.visible=1 +unit.2.0.port.1.s.11.alias= +unit.2.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.11.name=TriggerPort1[11] +unit.2.0.port.1.s.11.orderindex=-1 +unit.2.0.port.1.s.11.visible=1 +unit.2.0.port.1.s.12.alias= +unit.2.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.12.name=TriggerPort1[12] +unit.2.0.port.1.s.12.orderindex=-1 +unit.2.0.port.1.s.12.visible=1 +unit.2.0.port.1.s.13.alias= +unit.2.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.13.name=TriggerPort1[13] +unit.2.0.port.1.s.13.orderindex=-1 +unit.2.0.port.1.s.13.visible=1 +unit.2.0.port.1.s.14.alias= +unit.2.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.14.name=TriggerPort1[14] +unit.2.0.port.1.s.14.orderindex=-1 +unit.2.0.port.1.s.14.visible=1 +unit.2.0.port.1.s.15.alias= +unit.2.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.15.name=TriggerPort1[15] +unit.2.0.port.1.s.15.orderindex=-1 +unit.2.0.port.1.s.15.visible=1 +unit.2.0.port.1.s.16.alias= +unit.2.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.16.name=TriggerPort1[16] +unit.2.0.port.1.s.16.orderindex=-1 +unit.2.0.port.1.s.16.visible=1 +unit.2.0.port.1.s.17.alias= +unit.2.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.17.name=TriggerPort1[17] +unit.2.0.port.1.s.17.orderindex=-1 +unit.2.0.port.1.s.17.visible=1 +unit.2.0.port.1.s.18.alias= +unit.2.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.18.name=TriggerPort1[18] +unit.2.0.port.1.s.18.orderindex=-1 +unit.2.0.port.1.s.18.visible=1 +unit.2.0.port.1.s.19.alias= +unit.2.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.19.name=TriggerPort1[19] +unit.2.0.port.1.s.19.orderindex=-1 +unit.2.0.port.1.s.19.visible=1 +unit.2.0.port.1.s.2.alias= +unit.2.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.2.name=TriggerPort1[2] +unit.2.0.port.1.s.2.orderindex=-1 +unit.2.0.port.1.s.2.visible=1 +unit.2.0.port.1.s.20.alias= +unit.2.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.20.name=TriggerPort1[20] +unit.2.0.port.1.s.20.orderindex=-1 +unit.2.0.port.1.s.20.visible=1 +unit.2.0.port.1.s.21.alias= +unit.2.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.21.name=TriggerPort1[21] +unit.2.0.port.1.s.21.orderindex=-1 +unit.2.0.port.1.s.21.visible=1 +unit.2.0.port.1.s.22.alias= +unit.2.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.22.name=TriggerPort1[22] +unit.2.0.port.1.s.22.orderindex=-1 +unit.2.0.port.1.s.22.visible=1 +unit.2.0.port.1.s.23.alias= +unit.2.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.23.name=TriggerPort1[23] +unit.2.0.port.1.s.23.orderindex=-1 +unit.2.0.port.1.s.23.visible=1 +unit.2.0.port.1.s.24.alias= +unit.2.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.24.name=TriggerPort1[24] +unit.2.0.port.1.s.24.orderindex=-1 +unit.2.0.port.1.s.24.visible=1 +unit.2.0.port.1.s.25.alias= +unit.2.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.25.name=TriggerPort1[25] +unit.2.0.port.1.s.25.orderindex=-1 +unit.2.0.port.1.s.25.visible=1 +unit.2.0.port.1.s.26.alias= +unit.2.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.26.name=TriggerPort1[26] +unit.2.0.port.1.s.26.orderindex=-1 +unit.2.0.port.1.s.26.visible=1 +unit.2.0.port.1.s.27.alias= +unit.2.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.27.name=TriggerPort1[27] +unit.2.0.port.1.s.27.orderindex=-1 +unit.2.0.port.1.s.27.visible=1 +unit.2.0.port.1.s.28.alias= +unit.2.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.28.name=TriggerPort1[28] +unit.2.0.port.1.s.28.orderindex=-1 +unit.2.0.port.1.s.28.visible=1 +unit.2.0.port.1.s.29.alias= +unit.2.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.29.name=TriggerPort1[29] +unit.2.0.port.1.s.29.orderindex=-1 +unit.2.0.port.1.s.29.visible=1 +unit.2.0.port.1.s.3.alias= +unit.2.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.3.name=TriggerPort1[3] +unit.2.0.port.1.s.3.orderindex=-1 +unit.2.0.port.1.s.3.visible=1 +unit.2.0.port.1.s.30.alias= +unit.2.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.30.name=TriggerPort1[30] +unit.2.0.port.1.s.30.orderindex=-1 +unit.2.0.port.1.s.30.visible=1 +unit.2.0.port.1.s.31.alias= +unit.2.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.31.name=TriggerPort1[31] +unit.2.0.port.1.s.31.orderindex=-1 +unit.2.0.port.1.s.31.visible=1 +unit.2.0.port.1.s.4.alias= +unit.2.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.4.name=TriggerPort1[4] +unit.2.0.port.1.s.4.orderindex=-1 +unit.2.0.port.1.s.4.visible=1 +unit.2.0.port.1.s.5.alias= +unit.2.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.5.name=TriggerPort1[5] +unit.2.0.port.1.s.5.orderindex=-1 +unit.2.0.port.1.s.5.visible=1 +unit.2.0.port.1.s.6.alias= +unit.2.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.6.name=TriggerPort1[6] +unit.2.0.port.1.s.6.orderindex=-1 +unit.2.0.port.1.s.6.visible=1 +unit.2.0.port.1.s.7.alias= +unit.2.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.7.name=TriggerPort1[7] +unit.2.0.port.1.s.7.orderindex=-1 +unit.2.0.port.1.s.7.visible=1 +unit.2.0.port.1.s.8.alias= +unit.2.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.8.name=TriggerPort1[8] +unit.2.0.port.1.s.8.orderindex=-1 +unit.2.0.port.1.s.8.visible=1 +unit.2.0.port.1.s.9.alias= +unit.2.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.1.s.9.name=TriggerPort1[9] +unit.2.0.port.1.s.9.orderindex=-1 +unit.2.0.port.1.s.9.visible=1 +unit.2.0.port.10.b.0.alias= +unit.2.0.port.10.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +unit.2.0.port.10.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.b.0.name=TriggerPort10 +unit.2.0.port.10.b.0.orderindex=-1 +unit.2.0.port.10.b.0.radix=Hex +unit.2.0.port.10.b.0.signedOffset=0.0 +unit.2.0.port.10.b.0.signedPrecision=0 +unit.2.0.port.10.b.0.signedScaleFactor=1.0 +unit.2.0.port.10.b.0.unsignedOffset=0.0 +unit.2.0.port.10.b.0.unsignedPrecision=0 +unit.2.0.port.10.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.10.b.0.visible=1 +unit.2.0.port.10.buscount=1 +unit.2.0.port.10.channelcount=21 +unit.2.0.port.10.s.0.alias= +unit.2.0.port.10.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.0.name=TriggerPort10[0] +unit.2.0.port.10.s.0.orderindex=-1 +unit.2.0.port.10.s.0.visible=1 +unit.2.0.port.10.s.1.alias= +unit.2.0.port.10.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.1.name=TriggerPort10[1] +unit.2.0.port.10.s.1.orderindex=-1 +unit.2.0.port.10.s.1.visible=1 +unit.2.0.port.10.s.10.alias= +unit.2.0.port.10.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.10.name=TriggerPort10[10] +unit.2.0.port.10.s.10.orderindex=-1 +unit.2.0.port.10.s.10.visible=1 +unit.2.0.port.10.s.11.alias= +unit.2.0.port.10.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.11.name=TriggerPort10[11] +unit.2.0.port.10.s.11.orderindex=-1 +unit.2.0.port.10.s.11.visible=1 +unit.2.0.port.10.s.12.alias= +unit.2.0.port.10.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.12.name=TriggerPort10[12] +unit.2.0.port.10.s.12.orderindex=-1 +unit.2.0.port.10.s.12.visible=1 +unit.2.0.port.10.s.13.alias= +unit.2.0.port.10.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.13.name=TriggerPort10[13] +unit.2.0.port.10.s.13.orderindex=-1 +unit.2.0.port.10.s.13.visible=1 +unit.2.0.port.10.s.14.alias= +unit.2.0.port.10.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.14.name=TriggerPort10[14] +unit.2.0.port.10.s.14.orderindex=-1 +unit.2.0.port.10.s.14.visible=1 +unit.2.0.port.10.s.15.alias= +unit.2.0.port.10.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.15.name=TriggerPort10[15] +unit.2.0.port.10.s.15.orderindex=-1 +unit.2.0.port.10.s.15.visible=1 +unit.2.0.port.10.s.16.alias=ace_stb +unit.2.0.port.10.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.16.name=TriggerPort10[16] +unit.2.0.port.10.s.16.orderindex=-1 +unit.2.0.port.10.s.16.visible=1 +unit.2.0.port.10.s.17.alias=ace_ack +unit.2.0.port.10.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.17.name=TriggerPort10[17] +unit.2.0.port.10.s.17.orderindex=-1 +unit.2.0.port.10.s.17.visible=1 +unit.2.0.port.10.s.18.alias=aceusb_oe_n_ +unit.2.0.port.10.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.18.name=TriggerPort10[18] +unit.2.0.port.10.s.18.orderindex=-1 +unit.2.0.port.10.s.18.visible=1 +unit.2.0.port.10.s.19.alias=aceusb_we_n +unit.2.0.port.10.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.19.name=TriggerPort10[19] +unit.2.0.port.10.s.19.orderindex=-1 +unit.2.0.port.10.s.19.visible=1 +unit.2.0.port.10.s.2.alias= +unit.2.0.port.10.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.2.name=TriggerPort10[2] +unit.2.0.port.10.s.2.orderindex=-1 +unit.2.0.port.10.s.2.visible=1 +unit.2.0.port.10.s.20.alias=ace_mpce_n_ +unit.2.0.port.10.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.20.name=TriggerPort10[20] +unit.2.0.port.10.s.20.orderindex=-1 +unit.2.0.port.10.s.20.visible=1 +unit.2.0.port.10.s.3.alias= +unit.2.0.port.10.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.3.name=TriggerPort10[3] +unit.2.0.port.10.s.3.orderindex=-1 +unit.2.0.port.10.s.3.visible=1 +unit.2.0.port.10.s.4.alias= +unit.2.0.port.10.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.4.name=TriggerPort10[4] +unit.2.0.port.10.s.4.orderindex=-1 +unit.2.0.port.10.s.4.visible=1 +unit.2.0.port.10.s.5.alias= +unit.2.0.port.10.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.5.name=TriggerPort10[5] +unit.2.0.port.10.s.5.orderindex=-1 +unit.2.0.port.10.s.5.visible=1 +unit.2.0.port.10.s.6.alias= +unit.2.0.port.10.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.6.name=TriggerPort10[6] +unit.2.0.port.10.s.6.orderindex=-1 +unit.2.0.port.10.s.6.visible=1 +unit.2.0.port.10.s.7.alias= +unit.2.0.port.10.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.7.name=TriggerPort10[7] +unit.2.0.port.10.s.7.orderindex=-1 +unit.2.0.port.10.s.7.visible=1 +unit.2.0.port.10.s.8.alias= +unit.2.0.port.10.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.8.name=TriggerPort10[8] +unit.2.0.port.10.s.8.orderindex=-1 +unit.2.0.port.10.s.8.visible=1 +unit.2.0.port.10.s.9.alias= +unit.2.0.port.10.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.10.s.9.name=TriggerPort10[9] +unit.2.0.port.10.s.9.orderindex=-1 +unit.2.0.port.10.s.9.visible=1 +unit.2.0.port.11.b.0.alias= +unit.2.0.port.11.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +unit.2.0.port.11.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.b.0.name=TriggerPort11 +unit.2.0.port.11.b.0.orderindex=-1 +unit.2.0.port.11.b.0.radix=Hex +unit.2.0.port.11.b.0.signedOffset=0.0 +unit.2.0.port.11.b.0.signedPrecision=0 +unit.2.0.port.11.b.0.signedScaleFactor=1.0 +unit.2.0.port.11.b.0.unsignedOffset=0.0 +unit.2.0.port.11.b.0.unsignedPrecision=0 +unit.2.0.port.11.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.11.b.0.visible=1 +unit.2.0.port.11.buscount=1 +unit.2.0.port.11.channelcount=16 +unit.2.0.port.11.s.0.alias=DataPort[191] +unit.2.0.port.11.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.0.name=TriggerPort11[0] +unit.2.0.port.11.s.0.orderindex=-1 +unit.2.0.port.11.s.0.visible=1 +unit.2.0.port.11.s.1.alias= +unit.2.0.port.11.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.1.name=TriggerPort11[1] +unit.2.0.port.11.s.1.orderindex=-1 +unit.2.0.port.11.s.1.visible=1 +unit.2.0.port.11.s.10.alias= +unit.2.0.port.11.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.10.name=TriggerPort11[10] +unit.2.0.port.11.s.10.orderindex=-1 +unit.2.0.port.11.s.10.visible=1 +unit.2.0.port.11.s.11.alias= +unit.2.0.port.11.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.11.name=TriggerPort11[11] +unit.2.0.port.11.s.11.orderindex=-1 +unit.2.0.port.11.s.11.visible=1 +unit.2.0.port.11.s.12.alias= +unit.2.0.port.11.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.12.name=TriggerPort11[12] +unit.2.0.port.11.s.12.orderindex=-1 +unit.2.0.port.11.s.12.visible=1 +unit.2.0.port.11.s.13.alias= +unit.2.0.port.11.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.13.name=TriggerPort11[13] +unit.2.0.port.11.s.13.orderindex=-1 +unit.2.0.port.11.s.13.visible=1 +unit.2.0.port.11.s.14.alias= +unit.2.0.port.11.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.14.name=TriggerPort11[14] +unit.2.0.port.11.s.14.orderindex=-1 +unit.2.0.port.11.s.14.visible=1 +unit.2.0.port.11.s.15.alias= +unit.2.0.port.11.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.15.name=TriggerPort11[15] +unit.2.0.port.11.s.15.orderindex=-1 +unit.2.0.port.11.s.15.visible=1 +unit.2.0.port.11.s.2.alias= +unit.2.0.port.11.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.2.name=TriggerPort11[2] +unit.2.0.port.11.s.2.orderindex=-1 +unit.2.0.port.11.s.2.visible=1 +unit.2.0.port.11.s.3.alias= +unit.2.0.port.11.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.3.name=TriggerPort11[3] +unit.2.0.port.11.s.3.orderindex=-1 +unit.2.0.port.11.s.3.visible=1 +unit.2.0.port.11.s.4.alias= +unit.2.0.port.11.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.4.name=TriggerPort11[4] +unit.2.0.port.11.s.4.orderindex=-1 +unit.2.0.port.11.s.4.visible=1 +unit.2.0.port.11.s.5.alias= +unit.2.0.port.11.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.5.name=TriggerPort11[5] +unit.2.0.port.11.s.5.orderindex=-1 +unit.2.0.port.11.s.5.visible=1 +unit.2.0.port.11.s.6.alias= +unit.2.0.port.11.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.6.name=TriggerPort11[6] +unit.2.0.port.11.s.6.orderindex=-1 +unit.2.0.port.11.s.6.visible=1 +unit.2.0.port.11.s.7.alias= +unit.2.0.port.11.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.7.name=TriggerPort11[7] +unit.2.0.port.11.s.7.orderindex=-1 +unit.2.0.port.11.s.7.visible=1 +unit.2.0.port.11.s.8.alias= +unit.2.0.port.11.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.8.name=TriggerPort11[8] +unit.2.0.port.11.s.8.orderindex=-1 +unit.2.0.port.11.s.8.visible=1 +unit.2.0.port.11.s.9.alias= +unit.2.0.port.11.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.11.s.9.name=TriggerPort11[9] +unit.2.0.port.11.s.9.orderindex=-1 +unit.2.0.port.11.s.9.visible=1 +unit.2.0.port.12.b.0.alias= +unit.2.0.port.12.b.0.channellist=0 1 2 3 4 5 6 7 8 +unit.2.0.port.12.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.b.0.name=TriggerPort12 +unit.2.0.port.12.b.0.orderindex=-1 +unit.2.0.port.12.b.0.radix=Hex +unit.2.0.port.12.b.0.signedOffset=0.0 +unit.2.0.port.12.b.0.signedPrecision=0 +unit.2.0.port.12.b.0.signedScaleFactor=1.0 +unit.2.0.port.12.b.0.unsignedOffset=0.0 +unit.2.0.port.12.b.0.unsignedPrecision=0 +unit.2.0.port.12.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.12.b.0.visible=1 +unit.2.0.port.12.buscount=1 +unit.2.0.port.12.channelcount=9 +unit.2.0.port.12.s.0.alias=iid +unit.2.0.port.12.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.0.name=TriggerPort12[0] +unit.2.0.port.12.s.0.orderindex=-1 +unit.2.0.port.12.s.0.visible=1 +unit.2.0.port.12.s.1.alias=irr0 +unit.2.0.port.12.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.1.name=TriggerPort12[1] +unit.2.0.port.12.s.1.orderindex=-1 +unit.2.0.port.12.s.1.visible=1 +unit.2.0.port.12.s.2.alias=irr1 +unit.2.0.port.12.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.2.name=TriggerPort12[2] +unit.2.0.port.12.s.2.orderindex=-1 +unit.2.0.port.12.s.2.visible=1 +unit.2.0.port.12.s.3.alias=int0 +unit.2.0.port.12.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.3.name=TriggerPort12[3] +unit.2.0.port.12.s.3.orderindex=-1 +unit.2.0.port.12.s.3.visible=1 +unit.2.0.port.12.s.4.alias=int1 +unit.2.0.port.12.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.4.name=TriggerPort12[4] +unit.2.0.port.12.s.4.orderindex=-1 +unit.2.0.port.12.s.4.visible=1 +unit.2.0.port.12.s.5.alias=released +unit.2.0.port.12.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.5.name=TriggerPort12[5] +unit.2.0.port.12.s.5.orderindex=-1 +unit.2.0.port.12.s.5.visible=1 +unit.2.0.port.12.s.6.alias=rx_shift +unit.2.0.port.12.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.6.name=TriggerPort12[6] +unit.2.0.port.12.s.6.orderindex=-1 +unit.2.0.port.12.s.6.visible=1 +unit.2.0.port.12.s.7.alias=rx_output +unit.2.0.port.12.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.7.name=TriggerPort12[7] +unit.2.0.port.12.s.7.orderindex=-1 +unit.2.0.port.12.s.7.visible=1 +unit.2.0.port.12.s.8.alias=nada +unit.2.0.port.12.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.12.s.8.name=TriggerPort12[8] +unit.2.0.port.12.s.8.orderindex=-1 +unit.2.0.port.12.s.8.visible=1 +unit.2.0.port.13.b.0.alias= +unit.2.0.port.13.b.0.channellist=0 1 2 +unit.2.0.port.13.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.13.b.0.name=TriggerPort13 +unit.2.0.port.13.b.0.orderindex=-1 +unit.2.0.port.13.b.0.radix=Hex +unit.2.0.port.13.b.0.signedOffset=0.0 +unit.2.0.port.13.b.0.signedPrecision=0 +unit.2.0.port.13.b.0.signedScaleFactor=1.0 +unit.2.0.port.13.b.0.unsignedOffset=0.0 +unit.2.0.port.13.b.0.unsignedPrecision=0 +unit.2.0.port.13.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.13.b.0.visible=1 +unit.2.0.port.13.buscount=1 +unit.2.0.port.13.channelcount=3 +unit.2.0.port.13.s.0.alias=DataPort[216] +unit.2.0.port.13.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.13.s.0.name=TriggerPort13[0] +unit.2.0.port.13.s.0.orderindex=-1 +unit.2.0.port.13.s.0.visible=1 +unit.2.0.port.13.s.1.alias= +unit.2.0.port.13.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.13.s.1.name=TriggerPort13[1] +unit.2.0.port.13.s.1.orderindex=-1 +unit.2.0.port.13.s.1.visible=1 +unit.2.0.port.13.s.2.alias= +unit.2.0.port.13.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.13.s.2.name=TriggerPort13[2] +unit.2.0.port.13.s.2.orderindex=-1 +unit.2.0.port.13.s.2.visible=1 +unit.2.0.port.14.b.0.alias= +unit.2.0.port.14.b.0.channellist=0 1 2 3 4 +unit.2.0.port.14.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.b.0.name=TriggerPort14 +unit.2.0.port.14.b.0.orderindex=-1 +unit.2.0.port.14.b.0.radix=Hex +unit.2.0.port.14.b.0.signedOffset=0.0 +unit.2.0.port.14.b.0.signedPrecision=0 +unit.2.0.port.14.b.0.signedScaleFactor=1.0 +unit.2.0.port.14.b.0.unsignedOffset=0.0 +unit.2.0.port.14.b.0.unsignedPrecision=0 +unit.2.0.port.14.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.14.b.0.visible=1 +unit.2.0.port.14.buscount=1 +unit.2.0.port.14.channelcount=5 +unit.2.0.port.14.s.0.alias=op +unit.2.0.port.14.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.s.0.name=TriggerPort14[0] +unit.2.0.port.14.s.0.orderindex=-1 +unit.2.0.port.14.s.0.visible=1 +unit.2.0.port.14.s.1.alias=zbt_stb +unit.2.0.port.14.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.s.1.name=TriggerPort14[1] +unit.2.0.port.14.s.1.orderindex=-1 +unit.2.0.port.14.s.1.visible=1 +unit.2.0.port.14.s.2.alias=flash_stb +unit.2.0.port.14.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.s.2.name=TriggerPort14[2] +unit.2.0.port.14.s.2.orderindex=-1 +unit.2.0.port.14.s.2.visible=1 +unit.2.0.port.14.s.3.alias=flash_arena +unit.2.0.port.14.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.s.3.name=TriggerPort14[3] +unit.2.0.port.14.s.3.orderindex=-1 +unit.2.0.port.14.s.3.visible=1 +unit.2.0.port.14.s.4.alias=vdu_arena +unit.2.0.port.14.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.14.s.4.name=TriggerPort14[4] +unit.2.0.port.14.s.4.orderindex=-1 +unit.2.0.port.14.s.4.visible=1 +unit.2.0.port.15.b.0.alias= +unit.2.0.port.15.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +unit.2.0.port.15.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.b.0.name=TriggerPort15 +unit.2.0.port.15.b.0.orderindex=-1 +unit.2.0.port.15.b.0.radix=Hex +unit.2.0.port.15.b.0.signedOffset=0.0 +unit.2.0.port.15.b.0.signedPrecision=0 +unit.2.0.port.15.b.0.signedScaleFactor=1.0 +unit.2.0.port.15.b.0.unsignedOffset=0.0 +unit.2.0.port.15.b.0.unsignedPrecision=0 +unit.2.0.port.15.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.15.b.0.visible=1 +unit.2.0.port.15.buscount=1 +unit.2.0.port.15.channelcount=32 +unit.2.0.port.15.s.0.alias=cnt_time0 +unit.2.0.port.15.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.0.name=TriggerPort15[0] +unit.2.0.port.15.s.0.orderindex=-1 +unit.2.0.port.15.s.0.visible=1 +unit.2.0.port.15.s.1.alias=cnt_time1 +unit.2.0.port.15.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.1.name=TriggerPort15[1] +unit.2.0.port.15.s.1.orderindex=-1 +unit.2.0.port.15.s.1.visible=1 +unit.2.0.port.15.s.10.alias= +unit.2.0.port.15.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.10.name=TriggerPort15[10] +unit.2.0.port.15.s.10.orderindex=-1 +unit.2.0.port.15.s.10.visible=1 +unit.2.0.port.15.s.11.alias= +unit.2.0.port.15.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.11.name=TriggerPort15[11] +unit.2.0.port.15.s.11.orderindex=-1 +unit.2.0.port.15.s.11.visible=1 +unit.2.0.port.15.s.12.alias= +unit.2.0.port.15.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.12.name=TriggerPort15[12] +unit.2.0.port.15.s.12.orderindex=-1 +unit.2.0.port.15.s.12.visible=1 +unit.2.0.port.15.s.13.alias= +unit.2.0.port.15.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.13.name=TriggerPort15[13] +unit.2.0.port.15.s.13.orderindex=-1 +unit.2.0.port.15.s.13.visible=1 +unit.2.0.port.15.s.14.alias= +unit.2.0.port.15.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.14.name=TriggerPort15[14] +unit.2.0.port.15.s.14.orderindex=-1 +unit.2.0.port.15.s.14.visible=1 +unit.2.0.port.15.s.15.alias= +unit.2.0.port.15.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.15.name=TriggerPort15[15] +unit.2.0.port.15.s.15.orderindex=-1 +unit.2.0.port.15.s.15.visible=1 +unit.2.0.port.15.s.16.alias= +unit.2.0.port.15.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.16.name=TriggerPort15[16] +unit.2.0.port.15.s.16.orderindex=-1 +unit.2.0.port.15.s.16.visible=1 +unit.2.0.port.15.s.17.alias= +unit.2.0.port.15.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.17.name=TriggerPort15[17] +unit.2.0.port.15.s.17.orderindex=-1 +unit.2.0.port.15.s.17.visible=1 +unit.2.0.port.15.s.18.alias= +unit.2.0.port.15.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.18.name=TriggerPort15[18] +unit.2.0.port.15.s.18.orderindex=-1 +unit.2.0.port.15.s.18.visible=1 +unit.2.0.port.15.s.19.alias= +unit.2.0.port.15.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.19.name=TriggerPort15[19] +unit.2.0.port.15.s.19.orderindex=-1 +unit.2.0.port.15.s.19.visible=1 +unit.2.0.port.15.s.2.alias=cnt_time2 +unit.2.0.port.15.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.2.name=TriggerPort15[2] +unit.2.0.port.15.s.2.orderindex=-1 +unit.2.0.port.15.s.2.visible=1 +unit.2.0.port.15.s.20.alias= +unit.2.0.port.15.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.20.name=TriggerPort15[20] +unit.2.0.port.15.s.20.orderindex=-1 +unit.2.0.port.15.s.20.visible=1 +unit.2.0.port.15.s.21.alias= +unit.2.0.port.15.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.21.name=TriggerPort15[21] +unit.2.0.port.15.s.21.orderindex=-1 +unit.2.0.port.15.s.21.visible=1 +unit.2.0.port.15.s.22.alias= +unit.2.0.port.15.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.22.name=TriggerPort15[22] +unit.2.0.port.15.s.22.orderindex=-1 +unit.2.0.port.15.s.22.visible=1 +unit.2.0.port.15.s.23.alias= +unit.2.0.port.15.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.23.name=TriggerPort15[23] +unit.2.0.port.15.s.23.orderindex=-1 +unit.2.0.port.15.s.23.visible=1 +unit.2.0.port.15.s.24.alias= +unit.2.0.port.15.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.24.name=TriggerPort15[24] +unit.2.0.port.15.s.24.orderindex=-1 +unit.2.0.port.15.s.24.visible=1 +unit.2.0.port.15.s.25.alias= +unit.2.0.port.15.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.25.name=TriggerPort15[25] +unit.2.0.port.15.s.25.orderindex=-1 +unit.2.0.port.15.s.25.visible=1 +unit.2.0.port.15.s.26.alias= +unit.2.0.port.15.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.26.name=TriggerPort15[26] +unit.2.0.port.15.s.26.orderindex=-1 +unit.2.0.port.15.s.26.visible=1 +unit.2.0.port.15.s.27.alias= +unit.2.0.port.15.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.27.name=TriggerPort15[27] +unit.2.0.port.15.s.27.orderindex=-1 +unit.2.0.port.15.s.27.visible=1 +unit.2.0.port.15.s.28.alias= +unit.2.0.port.15.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.28.name=TriggerPort15[28] +unit.2.0.port.15.s.28.orderindex=-1 +unit.2.0.port.15.s.28.visible=1 +unit.2.0.port.15.s.29.alias= +unit.2.0.port.15.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.29.name=TriggerPort15[29] +unit.2.0.port.15.s.29.orderindex=-1 +unit.2.0.port.15.s.29.visible=1 +unit.2.0.port.15.s.3.alias=cnt_time3 +unit.2.0.port.15.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.3.name=TriggerPort15[3] +unit.2.0.port.15.s.3.orderindex=-1 +unit.2.0.port.15.s.3.visible=1 +unit.2.0.port.15.s.30.alias= +unit.2.0.port.15.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.30.name=TriggerPort15[30] +unit.2.0.port.15.s.30.orderindex=-1 +unit.2.0.port.15.s.30.visible=1 +unit.2.0.port.15.s.31.alias= +unit.2.0.port.15.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.31.name=TriggerPort15[31] +unit.2.0.port.15.s.31.orderindex=-1 +unit.2.0.port.15.s.31.visible=1 +unit.2.0.port.15.s.4.alias=cnt_time4 +unit.2.0.port.15.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.4.name=TriggerPort15[4] +unit.2.0.port.15.s.4.orderindex=-1 +unit.2.0.port.15.s.4.visible=1 +unit.2.0.port.15.s.5.alias=DataPort[229] +unit.2.0.port.15.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.5.name=TriggerPort15[5] +unit.2.0.port.15.s.5.orderindex=-1 +unit.2.0.port.15.s.5.visible=1 +unit.2.0.port.15.s.6.alias= +unit.2.0.port.15.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.6.name=TriggerPort15[6] +unit.2.0.port.15.s.6.orderindex=-1 +unit.2.0.port.15.s.6.visible=1 +unit.2.0.port.15.s.7.alias= +unit.2.0.port.15.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.7.name=TriggerPort15[7] +unit.2.0.port.15.s.7.orderindex=-1 +unit.2.0.port.15.s.7.visible=1 +unit.2.0.port.15.s.8.alias= +unit.2.0.port.15.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.8.name=TriggerPort15[8] +unit.2.0.port.15.s.8.orderindex=-1 +unit.2.0.port.15.s.8.visible=1 +unit.2.0.port.15.s.9.alias= +unit.2.0.port.15.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.15.s.9.name=TriggerPort15[9] +unit.2.0.port.15.s.9.orderindex=-1 +unit.2.0.port.15.s.9.visible=1 +unit.2.0.port.2.b.0.alias= +unit.2.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +unit.2.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.b.0.name=TriggerPort2 +unit.2.0.port.2.b.0.orderindex=-1 +unit.2.0.port.2.b.0.radix=Hex +unit.2.0.port.2.b.0.signedOffset=0.0 +unit.2.0.port.2.b.0.signedPrecision=0 +unit.2.0.port.2.b.0.signedScaleFactor=1.0 +unit.2.0.port.2.b.0.unsignedOffset=0.0 +unit.2.0.port.2.b.0.unsignedPrecision=0 +unit.2.0.port.2.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.2.b.0.visible=1 +unit.2.0.port.2.buscount=1 +unit.2.0.port.2.channelcount=20 +unit.2.0.port.2.s.0.alias= +unit.2.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.0.name=TriggerPort2[0] +unit.2.0.port.2.s.0.orderindex=-1 +unit.2.0.port.2.s.0.visible=1 +unit.2.0.port.2.s.1.alias= +unit.2.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.1.name=TriggerPort2[1] +unit.2.0.port.2.s.1.orderindex=-1 +unit.2.0.port.2.s.1.visible=1 +unit.2.0.port.2.s.10.alias= +unit.2.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.10.name=TriggerPort2[10] +unit.2.0.port.2.s.10.orderindex=-1 +unit.2.0.port.2.s.10.visible=1 +unit.2.0.port.2.s.11.alias= +unit.2.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.11.name=TriggerPort2[11] +unit.2.0.port.2.s.11.orderindex=-1 +unit.2.0.port.2.s.11.visible=1 +unit.2.0.port.2.s.12.alias= +unit.2.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.12.name=TriggerPort2[12] +unit.2.0.port.2.s.12.orderindex=-1 +unit.2.0.port.2.s.12.visible=1 +unit.2.0.port.2.s.13.alias= +unit.2.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.13.name=TriggerPort2[13] +unit.2.0.port.2.s.13.orderindex=-1 +unit.2.0.port.2.s.13.visible=1 +unit.2.0.port.2.s.14.alias= +unit.2.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.14.name=TriggerPort2[14] +unit.2.0.port.2.s.14.orderindex=-1 +unit.2.0.port.2.s.14.visible=1 +unit.2.0.port.2.s.15.alias= +unit.2.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.15.name=TriggerPort2[15] +unit.2.0.port.2.s.15.orderindex=-1 +unit.2.0.port.2.s.15.visible=1 +unit.2.0.port.2.s.16.alias= +unit.2.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.16.name=TriggerPort2[16] +unit.2.0.port.2.s.16.orderindex=-1 +unit.2.0.port.2.s.16.visible=1 +unit.2.0.port.2.s.17.alias= +unit.2.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.17.name=TriggerPort2[17] +unit.2.0.port.2.s.17.orderindex=-1 +unit.2.0.port.2.s.17.visible=1 +unit.2.0.port.2.s.18.alias= +unit.2.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.18.name=TriggerPort2[18] +unit.2.0.port.2.s.18.orderindex=-1 +unit.2.0.port.2.s.18.visible=1 +unit.2.0.port.2.s.19.alias= +unit.2.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.19.name=TriggerPort2[19] +unit.2.0.port.2.s.19.orderindex=-1 +unit.2.0.port.2.s.19.visible=1 +unit.2.0.port.2.s.2.alias= +unit.2.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.2.name=TriggerPort2[2] +unit.2.0.port.2.s.2.orderindex=-1 +unit.2.0.port.2.s.2.visible=1 +unit.2.0.port.2.s.3.alias= +unit.2.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.3.name=TriggerPort2[3] +unit.2.0.port.2.s.3.orderindex=-1 +unit.2.0.port.2.s.3.visible=1 +unit.2.0.port.2.s.4.alias= +unit.2.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.4.name=TriggerPort2[4] +unit.2.0.port.2.s.4.orderindex=-1 +unit.2.0.port.2.s.4.visible=1 +unit.2.0.port.2.s.5.alias= +unit.2.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.5.name=TriggerPort2[5] +unit.2.0.port.2.s.5.orderindex=-1 +unit.2.0.port.2.s.5.visible=1 +unit.2.0.port.2.s.6.alias= +unit.2.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.6.name=TriggerPort2[6] +unit.2.0.port.2.s.6.orderindex=-1 +unit.2.0.port.2.s.6.visible=1 +unit.2.0.port.2.s.7.alias= +unit.2.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.7.name=TriggerPort2[7] +unit.2.0.port.2.s.7.orderindex=-1 +unit.2.0.port.2.s.7.visible=1 +unit.2.0.port.2.s.8.alias= +unit.2.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.8.name=TriggerPort2[8] +unit.2.0.port.2.s.8.orderindex=-1 +unit.2.0.port.2.s.8.visible=1 +unit.2.0.port.2.s.9.alias= +unit.2.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.2.s.9.name=TriggerPort2[9] +unit.2.0.port.2.s.9.orderindex=-1 +unit.2.0.port.2.s.9.visible=1 +unit.2.0.port.3.b.0.alias= +unit.2.0.port.3.b.0.channellist=0 1 2 3 4 5 +unit.2.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.b.0.name=TriggerPort3 +unit.2.0.port.3.b.0.orderindex=-1 +unit.2.0.port.3.b.0.radix=Hex +unit.2.0.port.3.b.0.signedOffset=0.0 +unit.2.0.port.3.b.0.signedPrecision=0 +unit.2.0.port.3.b.0.signedScaleFactor=1.0 +unit.2.0.port.3.b.0.unsignedOffset=0.0 +unit.2.0.port.3.b.0.unsignedPrecision=0 +unit.2.0.port.3.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.3.b.0.visible=1 +unit.2.0.port.3.buscount=1 +unit.2.0.port.3.channelcount=6 +unit.2.0.port.3.s.0.alias=ack +unit.2.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.0.name=TriggerPort3[0] +unit.2.0.port.3.s.0.orderindex=-1 +unit.2.0.port.3.s.0.visible=1 +unit.2.0.port.3.s.1.alias=stb +unit.2.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.1.name=TriggerPort3[1] +unit.2.0.port.3.s.1.orderindex=-1 +unit.2.0.port.3.s.1.visible=1 +unit.2.0.port.3.s.2.alias=cyc +unit.2.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.2.name=TriggerPort3[2] +unit.2.0.port.3.s.2.orderindex=-1 +unit.2.0.port.3.s.2.visible=1 +unit.2.0.port.3.s.3.alias=tga +unit.2.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.3.name=TriggerPort3[3] +unit.2.0.port.3.s.3.orderindex=-1 +unit.2.0.port.3.s.3.visible=1 +unit.2.0.port.3.s.4.alias=we +unit.2.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.4.name=TriggerPort3[4] +unit.2.0.port.3.s.4.orderindex=-1 +unit.2.0.port.3.s.4.visible=1 +unit.2.0.port.3.s.5.alias=clk +unit.2.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.3.s.5.name=TriggerPort3[5] +unit.2.0.port.3.s.5.orderindex=-1 +unit.2.0.port.3.s.5.visible=1 +unit.2.0.port.4.b.0.alias= +unit.2.0.port.4.b.0.channellist=0 1 2 3 4 5 +unit.2.0.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.b.0.name=TriggerPort4 +unit.2.0.port.4.b.0.orderindex=-1 +unit.2.0.port.4.b.0.radix=Hex +unit.2.0.port.4.b.0.signedOffset=0.0 +unit.2.0.port.4.b.0.signedPrecision=0 +unit.2.0.port.4.b.0.signedScaleFactor=1.0 +unit.2.0.port.4.b.0.unsignedOffset=0.0 +unit.2.0.port.4.b.0.unsignedPrecision=0 +unit.2.0.port.4.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.4.b.0.visible=1 +unit.2.0.port.4.buscount=1 +unit.2.0.port.4.channelcount=6 +unit.2.0.port.4.s.0.alias=DataPort[78] +unit.2.0.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.0.name=TriggerPort4[0] +unit.2.0.port.4.s.0.orderindex=-1 +unit.2.0.port.4.s.0.visible=1 +unit.2.0.port.4.s.1.alias= +unit.2.0.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.1.name=TriggerPort4[1] +unit.2.0.port.4.s.1.orderindex=-1 +unit.2.0.port.4.s.1.visible=1 +unit.2.0.port.4.s.10.alias= +unit.2.0.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.10.name=TriggerPort4[10] +unit.2.0.port.4.s.10.orderindex=-1 +unit.2.0.port.4.s.10.visible=1 +unit.2.0.port.4.s.11.alias= +unit.2.0.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.11.name=TriggerPort4[11] +unit.2.0.port.4.s.11.orderindex=-1 +unit.2.0.port.4.s.11.visible=1 +unit.2.0.port.4.s.12.alias= +unit.2.0.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.12.name=TriggerPort4[12] +unit.2.0.port.4.s.12.orderindex=-1 +unit.2.0.port.4.s.12.visible=1 +unit.2.0.port.4.s.13.alias= +unit.2.0.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.13.name=TriggerPort4[13] +unit.2.0.port.4.s.13.orderindex=-1 +unit.2.0.port.4.s.13.visible=1 +unit.2.0.port.4.s.14.alias= +unit.2.0.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.14.name=TriggerPort4[14] +unit.2.0.port.4.s.14.orderindex=-1 +unit.2.0.port.4.s.14.visible=1 +unit.2.0.port.4.s.15.alias= +unit.2.0.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.15.name=TriggerPort4[15] +unit.2.0.port.4.s.15.orderindex=-1 +unit.2.0.port.4.s.15.visible=1 +unit.2.0.port.4.s.2.alias= +unit.2.0.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.2.name=TriggerPort4[2] +unit.2.0.port.4.s.2.orderindex=-1 +unit.2.0.port.4.s.2.visible=1 +unit.2.0.port.4.s.3.alias= +unit.2.0.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.3.name=TriggerPort4[3] +unit.2.0.port.4.s.3.orderindex=-1 +unit.2.0.port.4.s.3.visible=1 +unit.2.0.port.4.s.4.alias= +unit.2.0.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.4.name=TriggerPort4[4] +unit.2.0.port.4.s.4.orderindex=-1 +unit.2.0.port.4.s.4.visible=1 +unit.2.0.port.4.s.5.alias= +unit.2.0.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.5.name=TriggerPort4[5] +unit.2.0.port.4.s.5.orderindex=-1 +unit.2.0.port.4.s.5.visible=1 +unit.2.0.port.4.s.6.alias= +unit.2.0.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.6.name=TriggerPort4[6] +unit.2.0.port.4.s.6.orderindex=-1 +unit.2.0.port.4.s.6.visible=1 +unit.2.0.port.4.s.7.alias= +unit.2.0.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.7.name=TriggerPort4[7] +unit.2.0.port.4.s.7.orderindex=-1 +unit.2.0.port.4.s.7.visible=1 +unit.2.0.port.4.s.8.alias= +unit.2.0.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.8.name=TriggerPort4[8] +unit.2.0.port.4.s.8.orderindex=-1 +unit.2.0.port.4.s.8.visible=1 +unit.2.0.port.4.s.9.alias= +unit.2.0.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.4.s.9.name=TriggerPort4[9] +unit.2.0.port.4.s.9.orderindex=-1 +unit.2.0.port.4.s.9.visible=1 +unit.2.0.port.5.b.0.alias= +unit.2.0.port.5.b.0.channellist=0 1 2 3 4 5 +unit.2.0.port.5.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.b.0.name=TriggerPort5 +unit.2.0.port.5.b.0.orderindex=-1 +unit.2.0.port.5.b.0.radix=Hex +unit.2.0.port.5.b.0.signedOffset=0.0 +unit.2.0.port.5.b.0.signedPrecision=0 +unit.2.0.port.5.b.0.signedScaleFactor=1.0 +unit.2.0.port.5.b.0.unsignedOffset=0.0 +unit.2.0.port.5.b.0.unsignedPrecision=0 +unit.2.0.port.5.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.5.b.0.visible=1 +unit.2.0.port.5.buscount=1 +unit.2.0.port.5.channelcount=6 +unit.2.0.port.5.s.0.alias= +unit.2.0.port.5.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.0.name=TriggerPort5[0] +unit.2.0.port.5.s.0.orderindex=-1 +unit.2.0.port.5.s.0.visible=1 +unit.2.0.port.5.s.1.alias= +unit.2.0.port.5.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.1.name=TriggerPort5[1] +unit.2.0.port.5.s.1.orderindex=-1 +unit.2.0.port.5.s.1.visible=1 +unit.2.0.port.5.s.2.alias= +unit.2.0.port.5.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.2.name=TriggerPort5[2] +unit.2.0.port.5.s.2.orderindex=-1 +unit.2.0.port.5.s.2.visible=1 +unit.2.0.port.5.s.3.alias= +unit.2.0.port.5.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.3.name=TriggerPort5[3] +unit.2.0.port.5.s.3.orderindex=-1 +unit.2.0.port.5.s.3.visible=1 +unit.2.0.port.5.s.4.alias= +unit.2.0.port.5.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.4.name=TriggerPort5[4] +unit.2.0.port.5.s.4.orderindex=-1 +unit.2.0.port.5.s.4.visible=1 +unit.2.0.port.5.s.5.alias= +unit.2.0.port.5.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.5.s.5.name=TriggerPort5[5] +unit.2.0.port.5.s.5.orderindex=-1 +unit.2.0.port.5.s.5.visible=1 +unit.2.0.port.6.b.0.alias= +unit.2.0.port.6.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +unit.2.0.port.6.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.b.0.name=TriggerPort6 +unit.2.0.port.6.b.0.orderindex=-1 +unit.2.0.port.6.b.0.radix=Hex +unit.2.0.port.6.b.0.signedOffset=0.0 +unit.2.0.port.6.b.0.signedPrecision=0 +unit.2.0.port.6.b.0.signedScaleFactor=1.0 +unit.2.0.port.6.b.0.unsignedOffset=0.0 +unit.2.0.port.6.b.0.unsignedPrecision=0 +unit.2.0.port.6.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.6.b.0.visible=1 +unit.2.0.port.6.buscount=1 +unit.2.0.port.6.channelcount=16 +unit.2.0.port.6.s.0.alias= +unit.2.0.port.6.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.0.name=TriggerPort6[0] +unit.2.0.port.6.s.0.orderindex=-1 +unit.2.0.port.6.s.0.visible=1 +unit.2.0.port.6.s.1.alias= +unit.2.0.port.6.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.1.name=TriggerPort6[1] +unit.2.0.port.6.s.1.orderindex=-1 +unit.2.0.port.6.s.1.visible=1 +unit.2.0.port.6.s.10.alias= +unit.2.0.port.6.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.10.name=TriggerPort6[10] +unit.2.0.port.6.s.10.orderindex=-1 +unit.2.0.port.6.s.10.visible=1 +unit.2.0.port.6.s.11.alias= +unit.2.0.port.6.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.11.name=TriggerPort6[11] +unit.2.0.port.6.s.11.orderindex=-1 +unit.2.0.port.6.s.11.visible=1 +unit.2.0.port.6.s.12.alias= +unit.2.0.port.6.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.12.name=TriggerPort6[12] +unit.2.0.port.6.s.12.orderindex=-1 +unit.2.0.port.6.s.12.visible=1 +unit.2.0.port.6.s.13.alias= +unit.2.0.port.6.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.13.name=TriggerPort6[13] +unit.2.0.port.6.s.13.orderindex=-1 +unit.2.0.port.6.s.13.visible=1 +unit.2.0.port.6.s.14.alias=inta +unit.2.0.port.6.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.14.name=TriggerPort6[14] +unit.2.0.port.6.s.14.orderindex=-1 +unit.2.0.port.6.s.14.visible=1 +unit.2.0.port.6.s.15.alias=intr +unit.2.0.port.6.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.15.name=TriggerPort6[15] +unit.2.0.port.6.s.15.orderindex=-1 +unit.2.0.port.6.s.15.visible=1 +unit.2.0.port.6.s.2.alias= +unit.2.0.port.6.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.2.name=TriggerPort6[2] +unit.2.0.port.6.s.2.orderindex=-1 +unit.2.0.port.6.s.2.visible=1 +unit.2.0.port.6.s.3.alias= +unit.2.0.port.6.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.3.name=TriggerPort6[3] +unit.2.0.port.6.s.3.orderindex=-1 +unit.2.0.port.6.s.3.visible=1 +unit.2.0.port.6.s.4.alias=byte_op +unit.2.0.port.6.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.4.name=TriggerPort6[4] +unit.2.0.port.6.s.4.orderindex=-1 +unit.2.0.port.6.s.4.visible=1 +unit.2.0.port.6.s.5.alias=DataPort[95] +unit.2.0.port.6.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.5.name=TriggerPort6[5] +unit.2.0.port.6.s.5.orderindex=-1 +unit.2.0.port.6.s.5.visible=1 +unit.2.0.port.6.s.6.alias= +unit.2.0.port.6.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.6.name=TriggerPort6[6] +unit.2.0.port.6.s.6.orderindex=-1 +unit.2.0.port.6.s.6.visible=1 +unit.2.0.port.6.s.7.alias= +unit.2.0.port.6.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.7.name=TriggerPort6[7] +unit.2.0.port.6.s.7.orderindex=-1 +unit.2.0.port.6.s.7.visible=1 +unit.2.0.port.6.s.8.alias= +unit.2.0.port.6.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.8.name=TriggerPort6[8] +unit.2.0.port.6.s.8.orderindex=-1 +unit.2.0.port.6.s.8.visible=1 +unit.2.0.port.6.s.9.alias= +unit.2.0.port.6.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.6.s.9.name=TriggerPort6[9] +unit.2.0.port.6.s.9.orderindex=-1 +unit.2.0.port.6.s.9.visible=1 +unit.2.0.port.7.b.0.alias= +unit.2.0.port.7.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +unit.2.0.port.7.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.b.0.name=TriggerPort7 +unit.2.0.port.7.b.0.orderindex=-1 +unit.2.0.port.7.b.0.radix=Hex +unit.2.0.port.7.b.0.signedOffset=0.0 +unit.2.0.port.7.b.0.signedPrecision=0 +unit.2.0.port.7.b.0.signedScaleFactor=1.0 +unit.2.0.port.7.b.0.unsignedOffset=0.0 +unit.2.0.port.7.b.0.unsignedPrecision=0 +unit.2.0.port.7.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.7.b.0.visible=1 +unit.2.0.port.7.buscount=1 +unit.2.0.port.7.channelcount=16 +unit.2.0.port.7.s.0.alias=DataPort[106] +unit.2.0.port.7.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.0.name=TriggerPort7[0] +unit.2.0.port.7.s.0.orderindex=-1 +unit.2.0.port.7.s.0.visible=1 +unit.2.0.port.7.s.1.alias= +unit.2.0.port.7.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.1.name=TriggerPort7[1] +unit.2.0.port.7.s.1.orderindex=-1 +unit.2.0.port.7.s.1.visible=1 +unit.2.0.port.7.s.10.alias= +unit.2.0.port.7.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.10.name=TriggerPort7[10] +unit.2.0.port.7.s.10.orderindex=-1 +unit.2.0.port.7.s.10.visible=1 +unit.2.0.port.7.s.11.alias= +unit.2.0.port.7.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.11.name=TriggerPort7[11] +unit.2.0.port.7.s.11.orderindex=-1 +unit.2.0.port.7.s.11.visible=1 +unit.2.0.port.7.s.12.alias= +unit.2.0.port.7.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.12.name=TriggerPort7[12] +unit.2.0.port.7.s.12.orderindex=-1 +unit.2.0.port.7.s.12.visible=1 +unit.2.0.port.7.s.13.alias= +unit.2.0.port.7.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.13.name=TriggerPort7[13] +unit.2.0.port.7.s.13.orderindex=-1 +unit.2.0.port.7.s.13.visible=1 +unit.2.0.port.7.s.14.alias= +unit.2.0.port.7.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.14.name=TriggerPort7[14] +unit.2.0.port.7.s.14.orderindex=-1 +unit.2.0.port.7.s.14.visible=1 +unit.2.0.port.7.s.15.alias= +unit.2.0.port.7.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.15.name=TriggerPort7[15] +unit.2.0.port.7.s.15.orderindex=-1 +unit.2.0.port.7.s.15.visible=1 +unit.2.0.port.7.s.2.alias= +unit.2.0.port.7.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.2.name=TriggerPort7[2] +unit.2.0.port.7.s.2.orderindex=-1 +unit.2.0.port.7.s.2.visible=1 +unit.2.0.port.7.s.3.alias= +unit.2.0.port.7.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.3.name=TriggerPort7[3] +unit.2.0.port.7.s.3.orderindex=-1 +unit.2.0.port.7.s.3.visible=1 +unit.2.0.port.7.s.4.alias= +unit.2.0.port.7.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.4.name=TriggerPort7[4] +unit.2.0.port.7.s.4.orderindex=-1 +unit.2.0.port.7.s.4.visible=1 +unit.2.0.port.7.s.5.alias= +unit.2.0.port.7.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.5.name=TriggerPort7[5] +unit.2.0.port.7.s.5.orderindex=-1 +unit.2.0.port.7.s.5.visible=1 +unit.2.0.port.7.s.6.alias= +unit.2.0.port.7.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.6.name=TriggerPort7[6] +unit.2.0.port.7.s.6.orderindex=-1 +unit.2.0.port.7.s.6.visible=1 +unit.2.0.port.7.s.7.alias= +unit.2.0.port.7.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.7.name=TriggerPort7[7] +unit.2.0.port.7.s.7.orderindex=-1 +unit.2.0.port.7.s.7.visible=1 +unit.2.0.port.7.s.8.alias= +unit.2.0.port.7.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.8.name=TriggerPort7[8] +unit.2.0.port.7.s.8.orderindex=-1 +unit.2.0.port.7.s.8.visible=1 +unit.2.0.port.7.s.9.alias= +unit.2.0.port.7.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.7.s.9.name=TriggerPort7[9] +unit.2.0.port.7.s.9.orderindex=-1 +unit.2.0.port.7.s.9.visible=1 +unit.2.0.port.8.b.0.alias= +unit.2.0.port.8.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +unit.2.0.port.8.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.b.0.name=TriggerPort8 +unit.2.0.port.8.b.0.orderindex=-1 +unit.2.0.port.8.b.0.radix=Hex +unit.2.0.port.8.b.0.signedOffset=0.0 +unit.2.0.port.8.b.0.signedPrecision=0 +unit.2.0.port.8.b.0.signedScaleFactor=1.0 +unit.2.0.port.8.b.0.unsignedOffset=0.0 +unit.2.0.port.8.b.0.unsignedPrecision=0 +unit.2.0.port.8.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.8.b.0.visible=1 +unit.2.0.port.8.buscount=1 +unit.2.0.port.8.channelcount=32 +unit.2.0.port.8.s.0.alias= +unit.2.0.port.8.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.0.name=TriggerPort8[0] +unit.2.0.port.8.s.0.orderindex=-1 +unit.2.0.port.8.s.0.visible=1 +unit.2.0.port.8.s.1.alias= +unit.2.0.port.8.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.1.name=TriggerPort8[1] +unit.2.0.port.8.s.1.orderindex=-1 +unit.2.0.port.8.s.1.visible=1 +unit.2.0.port.8.s.10.alias= +unit.2.0.port.8.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.10.name=TriggerPort8[10] +unit.2.0.port.8.s.10.orderindex=-1 +unit.2.0.port.8.s.10.visible=1 +unit.2.0.port.8.s.11.alias= +unit.2.0.port.8.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.11.name=TriggerPort8[11] +unit.2.0.port.8.s.11.orderindex=-1 +unit.2.0.port.8.s.11.visible=1 +unit.2.0.port.8.s.12.alias= +unit.2.0.port.8.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.12.name=TriggerPort8[12] +unit.2.0.port.8.s.12.orderindex=-1 +unit.2.0.port.8.s.12.visible=1 +unit.2.0.port.8.s.13.alias= +unit.2.0.port.8.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.13.name=TriggerPort8[13] +unit.2.0.port.8.s.13.orderindex=-1 +unit.2.0.port.8.s.13.visible=1 +unit.2.0.port.8.s.14.alias= +unit.2.0.port.8.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.14.name=TriggerPort8[14] +unit.2.0.port.8.s.14.orderindex=-1 +unit.2.0.port.8.s.14.visible=1 +unit.2.0.port.8.s.15.alias= +unit.2.0.port.8.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.15.name=TriggerPort8[15] +unit.2.0.port.8.s.15.orderindex=-1 +unit.2.0.port.8.s.15.visible=1 +unit.2.0.port.8.s.16.alias= +unit.2.0.port.8.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.16.name=TriggerPort8[16] +unit.2.0.port.8.s.16.orderindex=-1 +unit.2.0.port.8.s.16.visible=1 +unit.2.0.port.8.s.17.alias= +unit.2.0.port.8.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.17.name=TriggerPort8[17] +unit.2.0.port.8.s.17.orderindex=-1 +unit.2.0.port.8.s.17.visible=1 +unit.2.0.port.8.s.18.alias= +unit.2.0.port.8.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.18.name=TriggerPort8[18] +unit.2.0.port.8.s.18.orderindex=-1 +unit.2.0.port.8.s.18.visible=1 +unit.2.0.port.8.s.19.alias= +unit.2.0.port.8.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.19.name=TriggerPort8[19] +unit.2.0.port.8.s.19.orderindex=-1 +unit.2.0.port.8.s.19.visible=1 +unit.2.0.port.8.s.2.alias= +unit.2.0.port.8.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.2.name=TriggerPort8[2] +unit.2.0.port.8.s.2.orderindex=-1 +unit.2.0.port.8.s.2.visible=1 +unit.2.0.port.8.s.20.alias= +unit.2.0.port.8.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.20.name=TriggerPort8[20] +unit.2.0.port.8.s.20.orderindex=-1 +unit.2.0.port.8.s.20.visible=1 +unit.2.0.port.8.s.21.alias= +unit.2.0.port.8.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.21.name=TriggerPort8[21] +unit.2.0.port.8.s.21.orderindex=-1 +unit.2.0.port.8.s.21.visible=1 +unit.2.0.port.8.s.22.alias= +unit.2.0.port.8.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.22.name=TriggerPort8[22] +unit.2.0.port.8.s.22.orderindex=-1 +unit.2.0.port.8.s.22.visible=1 +unit.2.0.port.8.s.23.alias= +unit.2.0.port.8.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.23.name=TriggerPort8[23] +unit.2.0.port.8.s.23.orderindex=-1 +unit.2.0.port.8.s.23.visible=1 +unit.2.0.port.8.s.24.alias= +unit.2.0.port.8.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.24.name=TriggerPort8[24] +unit.2.0.port.8.s.24.orderindex=-1 +unit.2.0.port.8.s.24.visible=1 +unit.2.0.port.8.s.25.alias= +unit.2.0.port.8.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.25.name=TriggerPort8[25] +unit.2.0.port.8.s.25.orderindex=-1 +unit.2.0.port.8.s.25.visible=1 +unit.2.0.port.8.s.26.alias= +unit.2.0.port.8.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.26.name=TriggerPort8[26] +unit.2.0.port.8.s.26.orderindex=-1 +unit.2.0.port.8.s.26.visible=1 +unit.2.0.port.8.s.27.alias= +unit.2.0.port.8.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.27.name=TriggerPort8[27] +unit.2.0.port.8.s.27.orderindex=-1 +unit.2.0.port.8.s.27.visible=1 +unit.2.0.port.8.s.28.alias= +unit.2.0.port.8.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.28.name=TriggerPort8[28] +unit.2.0.port.8.s.28.orderindex=-1 +unit.2.0.port.8.s.28.visible=1 +unit.2.0.port.8.s.29.alias= +unit.2.0.port.8.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.29.name=TriggerPort8[29] +unit.2.0.port.8.s.29.orderindex=-1 +unit.2.0.port.8.s.29.visible=1 +unit.2.0.port.8.s.3.alias= +unit.2.0.port.8.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.3.name=TriggerPort8[3] +unit.2.0.port.8.s.3.orderindex=-1 +unit.2.0.port.8.s.3.visible=1 +unit.2.0.port.8.s.30.alias= +unit.2.0.port.8.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.30.name=TriggerPort8[30] +unit.2.0.port.8.s.30.orderindex=-1 +unit.2.0.port.8.s.30.visible=1 +unit.2.0.port.8.s.31.alias= +unit.2.0.port.8.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.31.name=TriggerPort8[31] +unit.2.0.port.8.s.31.orderindex=-1 +unit.2.0.port.8.s.31.visible=1 +unit.2.0.port.8.s.4.alias= +unit.2.0.port.8.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.4.name=TriggerPort8[4] +unit.2.0.port.8.s.4.orderindex=-1 +unit.2.0.port.8.s.4.visible=1 +unit.2.0.port.8.s.5.alias= +unit.2.0.port.8.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.5.name=TriggerPort8[5] +unit.2.0.port.8.s.5.orderindex=-1 +unit.2.0.port.8.s.5.visible=1 +unit.2.0.port.8.s.6.alias= +unit.2.0.port.8.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.6.name=TriggerPort8[6] +unit.2.0.port.8.s.6.orderindex=-1 +unit.2.0.port.8.s.6.visible=1 +unit.2.0.port.8.s.7.alias= +unit.2.0.port.8.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.7.name=TriggerPort8[7] +unit.2.0.port.8.s.7.orderindex=-1 +unit.2.0.port.8.s.7.visible=1 +unit.2.0.port.8.s.8.alias= +unit.2.0.port.8.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.8.name=TriggerPort8[8] +unit.2.0.port.8.s.8.orderindex=-1 +unit.2.0.port.8.s.8.visible=1 +unit.2.0.port.8.s.9.alias= +unit.2.0.port.8.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.8.s.9.name=TriggerPort8[9] +unit.2.0.port.8.s.9.orderindex=-1 +unit.2.0.port.8.s.9.visible=1 +unit.2.0.port.9.b.0.alias= +unit.2.0.port.9.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +unit.2.0.port.9.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.b.0.name=TriggerPort9 +unit.2.0.port.9.b.0.orderindex=-1 +unit.2.0.port.9.b.0.radix=Hex +unit.2.0.port.9.b.0.signedOffset=0.0 +unit.2.0.port.9.b.0.signedPrecision=0 +unit.2.0.port.9.b.0.signedScaleFactor=1.0 +unit.2.0.port.9.b.0.unsignedOffset=0.0 +unit.2.0.port.9.b.0.unsignedPrecision=0 +unit.2.0.port.9.b.0.unsignedScaleFactor=1.0 +unit.2.0.port.9.b.0.visible=1 +unit.2.0.port.9.buscount=1 +unit.2.0.port.9.channelcount=16 +unit.2.0.port.9.s.0.alias= +unit.2.0.port.9.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.0.name=TriggerPort9[0] +unit.2.0.port.9.s.0.orderindex=-1 +unit.2.0.port.9.s.0.visible=1 +unit.2.0.port.9.s.1.alias= +unit.2.0.port.9.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.1.name=TriggerPort9[1] +unit.2.0.port.9.s.1.orderindex=-1 +unit.2.0.port.9.s.1.visible=1 +unit.2.0.port.9.s.10.alias= +unit.2.0.port.9.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.10.name=TriggerPort9[10] +unit.2.0.port.9.s.10.orderindex=-1 +unit.2.0.port.9.s.10.visible=1 +unit.2.0.port.9.s.11.alias= +unit.2.0.port.9.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.11.name=TriggerPort9[11] +unit.2.0.port.9.s.11.orderindex=-1 +unit.2.0.port.9.s.11.visible=1 +unit.2.0.port.9.s.12.alias= +unit.2.0.port.9.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.12.name=TriggerPort9[12] +unit.2.0.port.9.s.12.orderindex=-1 +unit.2.0.port.9.s.12.visible=1 +unit.2.0.port.9.s.13.alias= +unit.2.0.port.9.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.13.name=TriggerPort9[13] +unit.2.0.port.9.s.13.orderindex=-1 +unit.2.0.port.9.s.13.visible=1 +unit.2.0.port.9.s.14.alias= +unit.2.0.port.9.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.14.name=TriggerPort9[14] +unit.2.0.port.9.s.14.orderindex=-1 +unit.2.0.port.9.s.14.visible=1 +unit.2.0.port.9.s.15.alias= +unit.2.0.port.9.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.15.name=TriggerPort9[15] +unit.2.0.port.9.s.15.orderindex=-1 +unit.2.0.port.9.s.15.visible=1 +unit.2.0.port.9.s.16.alias= +unit.2.0.port.9.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.16.name=TriggerPort9[16] +unit.2.0.port.9.s.16.orderindex=-1 +unit.2.0.port.9.s.16.visible=1 +unit.2.0.port.9.s.17.alias= +unit.2.0.port.9.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.17.name=TriggerPort9[17] +unit.2.0.port.9.s.17.orderindex=-1 +unit.2.0.port.9.s.17.visible=1 +unit.2.0.port.9.s.18.alias= +unit.2.0.port.9.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.18.name=TriggerPort9[18] +unit.2.0.port.9.s.18.orderindex=-1 +unit.2.0.port.9.s.18.visible=1 +unit.2.0.port.9.s.19.alias= +unit.2.0.port.9.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.19.name=TriggerPort9[19] +unit.2.0.port.9.s.19.orderindex=-1 +unit.2.0.port.9.s.19.visible=1 +unit.2.0.port.9.s.2.alias= +unit.2.0.port.9.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.2.name=TriggerPort9[2] +unit.2.0.port.9.s.2.orderindex=-1 +unit.2.0.port.9.s.2.visible=1 +unit.2.0.port.9.s.20.alias= +unit.2.0.port.9.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.20.name=TriggerPort9[20] +unit.2.0.port.9.s.20.orderindex=-1 +unit.2.0.port.9.s.20.visible=1 +unit.2.0.port.9.s.21.alias= +unit.2.0.port.9.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.21.name=TriggerPort9[21] +unit.2.0.port.9.s.21.orderindex=-1 +unit.2.0.port.9.s.21.visible=1 +unit.2.0.port.9.s.22.alias= +unit.2.0.port.9.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.22.name=TriggerPort9[22] +unit.2.0.port.9.s.22.orderindex=-1 +unit.2.0.port.9.s.22.visible=1 +unit.2.0.port.9.s.23.alias= +unit.2.0.port.9.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.23.name=TriggerPort9[23] +unit.2.0.port.9.s.23.orderindex=-1 +unit.2.0.port.9.s.23.visible=1 +unit.2.0.port.9.s.24.alias= +unit.2.0.port.9.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.24.name=TriggerPort9[24] +unit.2.0.port.9.s.24.orderindex=-1 +unit.2.0.port.9.s.24.visible=1 +unit.2.0.port.9.s.25.alias= +unit.2.0.port.9.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.25.name=TriggerPort9[25] +unit.2.0.port.9.s.25.orderindex=-1 +unit.2.0.port.9.s.25.visible=1 +unit.2.0.port.9.s.26.alias= +unit.2.0.port.9.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.26.name=TriggerPort9[26] +unit.2.0.port.9.s.26.orderindex=-1 +unit.2.0.port.9.s.26.visible=1 +unit.2.0.port.9.s.27.alias= +unit.2.0.port.9.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.27.name=TriggerPort9[27] +unit.2.0.port.9.s.27.orderindex=-1 +unit.2.0.port.9.s.27.visible=1 +unit.2.0.port.9.s.28.alias= +unit.2.0.port.9.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.28.name=TriggerPort9[28] +unit.2.0.port.9.s.28.orderindex=-1 +unit.2.0.port.9.s.28.visible=1 +unit.2.0.port.9.s.29.alias= +unit.2.0.port.9.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.29.name=TriggerPort9[29] +unit.2.0.port.9.s.29.orderindex=-1 +unit.2.0.port.9.s.29.visible=1 +unit.2.0.port.9.s.3.alias= +unit.2.0.port.9.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.3.name=TriggerPort9[3] +unit.2.0.port.9.s.3.orderindex=-1 +unit.2.0.port.9.s.3.visible=1 +unit.2.0.port.9.s.30.alias= +unit.2.0.port.9.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.30.name=TriggerPort9[30] +unit.2.0.port.9.s.30.orderindex=-1 +unit.2.0.port.9.s.30.visible=1 +unit.2.0.port.9.s.31.alias= +unit.2.0.port.9.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.31.name=TriggerPort9[31] +unit.2.0.port.9.s.31.orderindex=-1 +unit.2.0.port.9.s.31.visible=1 +unit.2.0.port.9.s.4.alias= +unit.2.0.port.9.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.4.name=TriggerPort9[4] +unit.2.0.port.9.s.4.orderindex=-1 +unit.2.0.port.9.s.4.visible=1 +unit.2.0.port.9.s.5.alias= +unit.2.0.port.9.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.5.name=TriggerPort9[5] +unit.2.0.port.9.s.5.orderindex=-1 +unit.2.0.port.9.s.5.visible=1 +unit.2.0.port.9.s.6.alias= +unit.2.0.port.9.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.6.name=TriggerPort9[6] +unit.2.0.port.9.s.6.orderindex=-1 +unit.2.0.port.9.s.6.visible=1 +unit.2.0.port.9.s.7.alias= +unit.2.0.port.9.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.7.name=TriggerPort9[7] +unit.2.0.port.9.s.7.orderindex=-1 +unit.2.0.port.9.s.7.visible=1 +unit.2.0.port.9.s.8.alias= +unit.2.0.port.9.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.8.name=TriggerPort9[8] +unit.2.0.port.9.s.8.orderindex=-1 +unit.2.0.port.9.s.8.visible=1 +unit.2.0.port.9.s.9.alias= +unit.2.0.port.9.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] +unit.2.0.port.9.s.9.name=TriggerPort9[9] +unit.2.0.port.9.s.9.orderindex=-1 +unit.2.0.port.9.s.9.visible=1 +unit.2.0.portcount=16 +unit.2.0.samplesPerTrigger=1 +unit.2.0.triggerCapture=1 +unit.2.0.triggerNSamplesTS=0 +unit.2.0.triggerPosition=0 +unit.2.0.triggerWindowCount=1 +unit.2.0.triggerWindowDepth=1024 +unit.2.0.triggerWindowTS=0 +unit.2.0.username=MyILA0 +unit.2.0.waveform.count=45 +unit.2.0.waveform.posn.0.channel=2147483646 +unit.2.0.waveform.posn.0.name=aluo +unit.2.0.waveform.posn.0.radix=1 +unit.2.0.waveform.posn.0.type=bus +unit.2.0.waveform.posn.1.channel=2147483646 +unit.2.0.waveform.posn.1.name=x +unit.2.0.waveform.posn.1.radix=1 +unit.2.0.waveform.posn.1.type=bus +unit.2.0.waveform.posn.10.channel=2147483646 +unit.2.0.waveform.posn.10.name=dat_i +unit.2.0.waveform.posn.10.radix=1 +unit.2.0.waveform.posn.10.type=bus +unit.2.0.waveform.posn.100.channel=2147483646 +unit.2.0.waveform.posn.100.name=x +unit.2.0.waveform.posn.100.radix=1 +unit.2.0.waveform.posn.100.type=bus +unit.2.0.waveform.posn.101.channel=2147483646 +unit.2.0.waveform.posn.101.name=x +unit.2.0.waveform.posn.101.radix=1 +unit.2.0.waveform.posn.101.type=bus +unit.2.0.waveform.posn.102.channel=2147483646 +unit.2.0.waveform.posn.102.name=x +unit.2.0.waveform.posn.102.radix=1 +unit.2.0.waveform.posn.102.type=bus +unit.2.0.waveform.posn.103.channel=2147483646 +unit.2.0.waveform.posn.103.name=x +unit.2.0.waveform.posn.103.radix=1 +unit.2.0.waveform.posn.103.type=bus +unit.2.0.waveform.posn.104.channel=2147483646 +unit.2.0.waveform.posn.104.name=x +unit.2.0.waveform.posn.104.radix=1 +unit.2.0.waveform.posn.104.type=bus +unit.2.0.waveform.posn.105.channel=2147483646 +unit.2.0.waveform.posn.105.name=x +unit.2.0.waveform.posn.105.radix=1 +unit.2.0.waveform.posn.105.type=bus +unit.2.0.waveform.posn.106.channel=2147483646 +unit.2.0.waveform.posn.106.name=x +unit.2.0.waveform.posn.106.radix=1 +unit.2.0.waveform.posn.106.type=bus +unit.2.0.waveform.posn.107.channel=2147483646 +unit.2.0.waveform.posn.107.name=x +unit.2.0.waveform.posn.107.radix=1 +unit.2.0.waveform.posn.107.type=bus +unit.2.0.waveform.posn.108.channel=2147483646 +unit.2.0.waveform.posn.108.name=x +unit.2.0.waveform.posn.108.radix=1 +unit.2.0.waveform.posn.108.type=bus +unit.2.0.waveform.posn.109.channel=2147483646 +unit.2.0.waveform.posn.109.name=x +unit.2.0.waveform.posn.109.radix=1 +unit.2.0.waveform.posn.109.type=bus +unit.2.0.waveform.posn.11.channel=2147483646 +unit.2.0.waveform.posn.11.name=dat_o +unit.2.0.waveform.posn.11.radix=1 +unit.2.0.waveform.posn.11.type=bus +unit.2.0.waveform.posn.110.channel=2147483646 +unit.2.0.waveform.posn.110.name=x +unit.2.0.waveform.posn.110.radix=1 +unit.2.0.waveform.posn.110.type=bus +unit.2.0.waveform.posn.111.channel=2147483646 +unit.2.0.waveform.posn.111.name=x +unit.2.0.waveform.posn.111.radix=1 +unit.2.0.waveform.posn.111.type=bus +unit.2.0.waveform.posn.112.channel=2147483646 +unit.2.0.waveform.posn.112.name=x +unit.2.0.waveform.posn.112.radix=1 +unit.2.0.waveform.posn.112.type=bus +unit.2.0.waveform.posn.113.channel=2147483646 +unit.2.0.waveform.posn.113.name=x +unit.2.0.waveform.posn.113.radix=1 +unit.2.0.waveform.posn.113.type=bus +unit.2.0.waveform.posn.114.channel=2147483646 +unit.2.0.waveform.posn.114.name=x +unit.2.0.waveform.posn.114.radix=1 +unit.2.0.waveform.posn.114.type=bus +unit.2.0.waveform.posn.115.channel=2147483646 +unit.2.0.waveform.posn.115.name=x +unit.2.0.waveform.posn.115.radix=1 +unit.2.0.waveform.posn.115.type=bus +unit.2.0.waveform.posn.116.channel=2147483646 +unit.2.0.waveform.posn.116.name=x +unit.2.0.waveform.posn.116.radix=1 +unit.2.0.waveform.posn.116.type=bus +unit.2.0.waveform.posn.117.channel=2147483646 +unit.2.0.waveform.posn.117.name=x +unit.2.0.waveform.posn.117.radix=1 +unit.2.0.waveform.posn.117.type=bus +unit.2.0.waveform.posn.118.channel=2147483646 +unit.2.0.waveform.posn.118.name=x +unit.2.0.waveform.posn.118.radix=1 +unit.2.0.waveform.posn.118.type=bus +unit.2.0.waveform.posn.119.channel=2147483646 +unit.2.0.waveform.posn.119.name=x +unit.2.0.waveform.posn.119.radix=1 +unit.2.0.waveform.posn.119.type=bus +unit.2.0.waveform.posn.12.channel=72 +unit.2.0.waveform.posn.12.name=ack +unit.2.0.waveform.posn.12.radix=1 +unit.2.0.waveform.posn.12.type=signal +unit.2.0.waveform.posn.120.channel=2147483646 +unit.2.0.waveform.posn.120.name=x +unit.2.0.waveform.posn.120.radix=1 +unit.2.0.waveform.posn.120.type=bus +unit.2.0.waveform.posn.121.channel=2147483646 +unit.2.0.waveform.posn.121.name=x +unit.2.0.waveform.posn.121.radix=1 +unit.2.0.waveform.posn.121.type=bus +unit.2.0.waveform.posn.122.channel=2147483646 +unit.2.0.waveform.posn.122.name=x +unit.2.0.waveform.posn.122.radix=1 +unit.2.0.waveform.posn.122.type=bus +unit.2.0.waveform.posn.123.channel=2147483646 +unit.2.0.waveform.posn.123.name=x +unit.2.0.waveform.posn.123.radix=1 +unit.2.0.waveform.posn.123.type=bus +unit.2.0.waveform.posn.124.channel=2147483646 +unit.2.0.waveform.posn.124.name=x +unit.2.0.waveform.posn.124.radix=1 +unit.2.0.waveform.posn.124.type=bus +unit.2.0.waveform.posn.125.channel=2147483646 +unit.2.0.waveform.posn.125.name=x +unit.2.0.waveform.posn.125.radix=1 +unit.2.0.waveform.posn.125.type=bus +unit.2.0.waveform.posn.126.channel=2147483646 +unit.2.0.waveform.posn.126.name=x +unit.2.0.waveform.posn.126.radix=1 +unit.2.0.waveform.posn.126.type=bus +unit.2.0.waveform.posn.127.channel=2147483646 +unit.2.0.waveform.posn.127.name=x +unit.2.0.waveform.posn.127.radix=1 +unit.2.0.waveform.posn.127.type=bus +unit.2.0.waveform.posn.128.channel=2147483646 +unit.2.0.waveform.posn.128.name=x +unit.2.0.waveform.posn.128.radix=1 +unit.2.0.waveform.posn.128.type=bus +unit.2.0.waveform.posn.129.channel=2147483646 +unit.2.0.waveform.posn.129.name=x +unit.2.0.waveform.posn.129.radix=1 +unit.2.0.waveform.posn.129.type=bus +unit.2.0.waveform.posn.13.channel=73 +unit.2.0.waveform.posn.13.name=stb +unit.2.0.waveform.posn.13.radix=1 +unit.2.0.waveform.posn.13.type=signal +unit.2.0.waveform.posn.130.channel=2147483646 +unit.2.0.waveform.posn.130.name=x +unit.2.0.waveform.posn.130.radix=1 +unit.2.0.waveform.posn.130.type=bus +unit.2.0.waveform.posn.131.channel=2147483646 +unit.2.0.waveform.posn.131.name=x +unit.2.0.waveform.posn.131.radix=1 +unit.2.0.waveform.posn.131.type=bus +unit.2.0.waveform.posn.132.channel=2147483646 +unit.2.0.waveform.posn.132.name=x +unit.2.0.waveform.posn.132.radix=1 +unit.2.0.waveform.posn.132.type=bus +unit.2.0.waveform.posn.133.channel=2147483646 +unit.2.0.waveform.posn.133.name=x +unit.2.0.waveform.posn.133.radix=1 +unit.2.0.waveform.posn.133.type=bus +unit.2.0.waveform.posn.134.channel=2147483646 +unit.2.0.waveform.posn.134.name=x +unit.2.0.waveform.posn.134.radix=1 +unit.2.0.waveform.posn.134.type=bus +unit.2.0.waveform.posn.135.channel=2147483646 +unit.2.0.waveform.posn.135.name=x +unit.2.0.waveform.posn.135.radix=1 +unit.2.0.waveform.posn.135.type=bus +unit.2.0.waveform.posn.136.channel=2147483646 +unit.2.0.waveform.posn.136.name=x +unit.2.0.waveform.posn.136.radix=1 +unit.2.0.waveform.posn.136.type=bus +unit.2.0.waveform.posn.137.channel=2147483646 +unit.2.0.waveform.posn.137.name=x +unit.2.0.waveform.posn.137.radix=1 +unit.2.0.waveform.posn.137.type=bus +unit.2.0.waveform.posn.138.channel=2147483646 +unit.2.0.waveform.posn.138.name=x +unit.2.0.waveform.posn.138.radix=1 +unit.2.0.waveform.posn.138.type=bus +unit.2.0.waveform.posn.139.channel=2147483646 +unit.2.0.waveform.posn.139.name=x +unit.2.0.waveform.posn.139.radix=1 +unit.2.0.waveform.posn.139.type=bus +unit.2.0.waveform.posn.14.channel=74 +unit.2.0.waveform.posn.14.name=cyc +unit.2.0.waveform.posn.14.radix=1 +unit.2.0.waveform.posn.14.type=signal +unit.2.0.waveform.posn.140.channel=2147483646 +unit.2.0.waveform.posn.140.name=x +unit.2.0.waveform.posn.140.radix=1 +unit.2.0.waveform.posn.140.type=bus +unit.2.0.waveform.posn.141.channel=2147483646 +unit.2.0.waveform.posn.141.name=x +unit.2.0.waveform.posn.141.radix=1 +unit.2.0.waveform.posn.141.type=bus +unit.2.0.waveform.posn.142.channel=2147483646 +unit.2.0.waveform.posn.142.name=x +unit.2.0.waveform.posn.142.radix=1 +unit.2.0.waveform.posn.142.type=bus +unit.2.0.waveform.posn.143.channel=2147483646 +unit.2.0.waveform.posn.143.name=x +unit.2.0.waveform.posn.143.radix=1 +unit.2.0.waveform.posn.143.type=bus +unit.2.0.waveform.posn.144.channel=2147483646 +unit.2.0.waveform.posn.144.name=x +unit.2.0.waveform.posn.144.radix=1 +unit.2.0.waveform.posn.144.type=bus +unit.2.0.waveform.posn.145.channel=2147483646 +unit.2.0.waveform.posn.145.name=x +unit.2.0.waveform.posn.145.radix=1 +unit.2.0.waveform.posn.145.type=bus +unit.2.0.waveform.posn.146.channel=2147483646 +unit.2.0.waveform.posn.146.name=x +unit.2.0.waveform.posn.146.radix=1 +unit.2.0.waveform.posn.146.type=bus +unit.2.0.waveform.posn.147.channel=2147483646 +unit.2.0.waveform.posn.147.name=x +unit.2.0.waveform.posn.147.radix=1 +unit.2.0.waveform.posn.147.type=bus +unit.2.0.waveform.posn.148.channel=2147483646 +unit.2.0.waveform.posn.148.name=x +unit.2.0.waveform.posn.148.radix=1 +unit.2.0.waveform.posn.148.type=bus +unit.2.0.waveform.posn.149.channel=2147483646 +unit.2.0.waveform.posn.149.name=x +unit.2.0.waveform.posn.149.radix=1 +unit.2.0.waveform.posn.149.type=bus +unit.2.0.waveform.posn.15.channel=75 +unit.2.0.waveform.posn.15.name=tga +unit.2.0.waveform.posn.15.radix=1 +unit.2.0.waveform.posn.15.type=signal +unit.2.0.waveform.posn.150.channel=2147483646 +unit.2.0.waveform.posn.150.name=x +unit.2.0.waveform.posn.150.radix=1 +unit.2.0.waveform.posn.150.type=bus +unit.2.0.waveform.posn.151.channel=2147483646 +unit.2.0.waveform.posn.151.name=x +unit.2.0.waveform.posn.151.radix=1 +unit.2.0.waveform.posn.151.type=bus +unit.2.0.waveform.posn.152.channel=2147483646 +unit.2.0.waveform.posn.152.name=x +unit.2.0.waveform.posn.152.radix=1 +unit.2.0.waveform.posn.152.type=bus +unit.2.0.waveform.posn.153.channel=2147483646 +unit.2.0.waveform.posn.153.name=x +unit.2.0.waveform.posn.153.radix=1 +unit.2.0.waveform.posn.153.type=bus +unit.2.0.waveform.posn.154.channel=2147483646 +unit.2.0.waveform.posn.154.name=x +unit.2.0.waveform.posn.154.radix=1 +unit.2.0.waveform.posn.154.type=bus +unit.2.0.waveform.posn.155.channel=2147483646 +unit.2.0.waveform.posn.155.name=x +unit.2.0.waveform.posn.155.radix=1 +unit.2.0.waveform.posn.155.type=bus +unit.2.0.waveform.posn.156.channel=2147483646 +unit.2.0.waveform.posn.156.name=x +unit.2.0.waveform.posn.156.radix=1 +unit.2.0.waveform.posn.156.type=bus +unit.2.0.waveform.posn.157.channel=2147483646 +unit.2.0.waveform.posn.157.name=x +unit.2.0.waveform.posn.157.radix=1 +unit.2.0.waveform.posn.157.type=bus +unit.2.0.waveform.posn.158.channel=2147483646 +unit.2.0.waveform.posn.158.name=x +unit.2.0.waveform.posn.158.radix=1 +unit.2.0.waveform.posn.158.type=bus +unit.2.0.waveform.posn.159.channel=2147483646 +unit.2.0.waveform.posn.159.name=x +unit.2.0.waveform.posn.159.radix=1 +unit.2.0.waveform.posn.159.type=bus +unit.2.0.waveform.posn.16.channel=76 +unit.2.0.waveform.posn.16.name=we +unit.2.0.waveform.posn.16.radix=1 +unit.2.0.waveform.posn.16.type=signal +unit.2.0.waveform.posn.160.channel=2147483646 +unit.2.0.waveform.posn.160.name=x +unit.2.0.waveform.posn.160.radix=1 +unit.2.0.waveform.posn.160.type=bus +unit.2.0.waveform.posn.161.channel=2147483646 +unit.2.0.waveform.posn.161.name=x +unit.2.0.waveform.posn.161.radix=1 +unit.2.0.waveform.posn.161.type=bus +unit.2.0.waveform.posn.162.channel=2147483646 +unit.2.0.waveform.posn.162.name=x +unit.2.0.waveform.posn.162.radix=1 +unit.2.0.waveform.posn.162.type=bus +unit.2.0.waveform.posn.163.channel=2147483646 +unit.2.0.waveform.posn.163.name=x +unit.2.0.waveform.posn.163.radix=1 +unit.2.0.waveform.posn.163.type=bus +unit.2.0.waveform.posn.164.channel=2147483646 +unit.2.0.waveform.posn.164.name=x +unit.2.0.waveform.posn.164.radix=1 +unit.2.0.waveform.posn.164.type=bus +unit.2.0.waveform.posn.165.channel=2147483646 +unit.2.0.waveform.posn.165.name=x +unit.2.0.waveform.posn.165.radix=1 +unit.2.0.waveform.posn.165.type=bus +unit.2.0.waveform.posn.166.channel=2147483646 +unit.2.0.waveform.posn.166.name=x +unit.2.0.waveform.posn.166.radix=1 +unit.2.0.waveform.posn.166.type=bus +unit.2.0.waveform.posn.167.channel=2147483646 +unit.2.0.waveform.posn.167.name=x +unit.2.0.waveform.posn.167.radix=1 +unit.2.0.waveform.posn.167.type=bus +unit.2.0.waveform.posn.168.channel=2147483646 +unit.2.0.waveform.posn.168.name=x +unit.2.0.waveform.posn.168.radix=1 +unit.2.0.waveform.posn.168.type=bus +unit.2.0.waveform.posn.169.channel=2147483646 +unit.2.0.waveform.posn.169.name=x +unit.2.0.waveform.posn.169.radix=1 +unit.2.0.waveform.posn.169.type=bus +unit.2.0.waveform.posn.17.channel=77 +unit.2.0.waveform.posn.17.name=clk +unit.2.0.waveform.posn.17.radix=1 +unit.2.0.waveform.posn.17.type=signal +unit.2.0.waveform.posn.170.channel=2147483646 +unit.2.0.waveform.posn.170.name=x +unit.2.0.waveform.posn.170.radix=1 +unit.2.0.waveform.posn.170.type=bus +unit.2.0.waveform.posn.171.channel=2147483646 +unit.2.0.waveform.posn.171.name=x +unit.2.0.waveform.posn.171.radix=1 +unit.2.0.waveform.posn.171.type=bus +unit.2.0.waveform.posn.172.channel=2147483646 +unit.2.0.waveform.posn.172.name=x +unit.2.0.waveform.posn.172.radix=1 +unit.2.0.waveform.posn.172.type=bus +unit.2.0.waveform.posn.173.channel=2147483646 +unit.2.0.waveform.posn.173.name=x +unit.2.0.waveform.posn.173.radix=1 +unit.2.0.waveform.posn.173.type=bus +unit.2.0.waveform.posn.174.channel=2147483646 +unit.2.0.waveform.posn.174.name=x +unit.2.0.waveform.posn.174.radix=1 +unit.2.0.waveform.posn.174.type=bus +unit.2.0.waveform.posn.175.channel=2147483646 +unit.2.0.waveform.posn.175.name=x +unit.2.0.waveform.posn.175.radix=1 +unit.2.0.waveform.posn.175.type=bus +unit.2.0.waveform.posn.176.channel=2147483646 +unit.2.0.waveform.posn.176.name=x +unit.2.0.waveform.posn.176.radix=1 +unit.2.0.waveform.posn.176.type=bus +unit.2.0.waveform.posn.177.channel=2147483646 +unit.2.0.waveform.posn.177.name=x +unit.2.0.waveform.posn.177.radix=1 +unit.2.0.waveform.posn.177.type=bus +unit.2.0.waveform.posn.178.channel=2147483646 +unit.2.0.waveform.posn.178.name=x +unit.2.0.waveform.posn.178.radix=1 +unit.2.0.waveform.posn.178.type=bus +unit.2.0.waveform.posn.179.channel=2147483646 +unit.2.0.waveform.posn.179.name=x +unit.2.0.waveform.posn.179.radix=1 +unit.2.0.waveform.posn.179.type=bus +unit.2.0.waveform.posn.18.channel=2147483646 +unit.2.0.waveform.posn.18.name=cnt +unit.2.0.waveform.posn.18.radix=1 +unit.2.0.waveform.posn.18.type=bus +unit.2.0.waveform.posn.180.channel=2147483646 +unit.2.0.waveform.posn.180.name=x +unit.2.0.waveform.posn.180.radix=1 +unit.2.0.waveform.posn.180.type=bus +unit.2.0.waveform.posn.181.channel=2147483646 +unit.2.0.waveform.posn.181.name=x +unit.2.0.waveform.posn.181.radix=1 +unit.2.0.waveform.posn.181.type=bus +unit.2.0.waveform.posn.182.channel=2147483646 +unit.2.0.waveform.posn.182.name=x +unit.2.0.waveform.posn.182.radix=1 +unit.2.0.waveform.posn.182.type=bus +unit.2.0.waveform.posn.183.channel=2147483646 +unit.2.0.waveform.posn.183.name=x +unit.2.0.waveform.posn.183.radix=1 +unit.2.0.waveform.posn.183.type=bus +unit.2.0.waveform.posn.184.channel=2147483646 +unit.2.0.waveform.posn.184.name=x +unit.2.0.waveform.posn.184.radix=1 +unit.2.0.waveform.posn.184.type=bus +unit.2.0.waveform.posn.185.channel=2147483646 +unit.2.0.waveform.posn.185.name=x +unit.2.0.waveform.posn.185.radix=1 +unit.2.0.waveform.posn.185.type=bus +unit.2.0.waveform.posn.186.channel=2147483646 +unit.2.0.waveform.posn.186.name=x +unit.2.0.waveform.posn.186.radix=1 +unit.2.0.waveform.posn.186.type=bus +unit.2.0.waveform.posn.187.channel=2147483646 +unit.2.0.waveform.posn.187.name=x +unit.2.0.waveform.posn.187.radix=1 +unit.2.0.waveform.posn.187.type=bus +unit.2.0.waveform.posn.188.channel=2147483646 +unit.2.0.waveform.posn.188.name=x +unit.2.0.waveform.posn.188.radix=1 +unit.2.0.waveform.posn.188.type=bus +unit.2.0.waveform.posn.189.channel=2147483646 +unit.2.0.waveform.posn.189.name=x +unit.2.0.waveform.posn.189.radix=1 +unit.2.0.waveform.posn.189.type=bus +unit.2.0.waveform.posn.19.channel=219 +unit.2.0.waveform.posn.19.name=op +unit.2.0.waveform.posn.19.radix=1 +unit.2.0.waveform.posn.19.type=signal +unit.2.0.waveform.posn.190.channel=2147483646 +unit.2.0.waveform.posn.190.name=x +unit.2.0.waveform.posn.190.radix=1 +unit.2.0.waveform.posn.190.type=bus +unit.2.0.waveform.posn.191.channel=2147483646 +unit.2.0.waveform.posn.191.name=x +unit.2.0.waveform.posn.191.radix=1 +unit.2.0.waveform.posn.191.type=bus +unit.2.0.waveform.posn.192.channel=2147483646 +unit.2.0.waveform.posn.192.name=x +unit.2.0.waveform.posn.192.radix=1 +unit.2.0.waveform.posn.192.type=bus +unit.2.0.waveform.posn.193.channel=2147483646 +unit.2.0.waveform.posn.193.name=x +unit.2.0.waveform.posn.193.radix=1 +unit.2.0.waveform.posn.193.type=bus +unit.2.0.waveform.posn.194.channel=2147483646 +unit.2.0.waveform.posn.194.name=x +unit.2.0.waveform.posn.194.radix=1 +unit.2.0.waveform.posn.194.type=bus +unit.2.0.waveform.posn.195.channel=2147483646 +unit.2.0.waveform.posn.195.name=x +unit.2.0.waveform.posn.195.radix=1 +unit.2.0.waveform.posn.195.type=bus +unit.2.0.waveform.posn.196.channel=2147483646 +unit.2.0.waveform.posn.196.name=x +unit.2.0.waveform.posn.196.radix=1 +unit.2.0.waveform.posn.196.type=bus +unit.2.0.waveform.posn.197.channel=2147483646 +unit.2.0.waveform.posn.197.name=x +unit.2.0.waveform.posn.197.radix=1 +unit.2.0.waveform.posn.197.type=bus +unit.2.0.waveform.posn.198.channel=2147483646 +unit.2.0.waveform.posn.198.name=x +unit.2.0.waveform.posn.198.radix=1 +unit.2.0.waveform.posn.198.type=bus +unit.2.0.waveform.posn.199.channel=2147483646 +unit.2.0.waveform.posn.199.name=x +unit.2.0.waveform.posn.199.radix=1 +unit.2.0.waveform.posn.199.type=bus +unit.2.0.waveform.posn.2.channel=2147483646 +unit.2.0.waveform.posn.2.name=y +unit.2.0.waveform.posn.2.radix=1 +unit.2.0.waveform.posn.2.type=bus +unit.2.0.waveform.posn.20.channel=220 +unit.2.0.waveform.posn.20.name=zbt_stb +unit.2.0.waveform.posn.20.radix=1 +unit.2.0.waveform.posn.20.type=signal +unit.2.0.waveform.posn.200.channel=2147483646 +unit.2.0.waveform.posn.200.name=x +unit.2.0.waveform.posn.200.radix=1 +unit.2.0.waveform.posn.200.type=bus +unit.2.0.waveform.posn.201.channel=2147483646 +unit.2.0.waveform.posn.201.name=x +unit.2.0.waveform.posn.201.radix=1 +unit.2.0.waveform.posn.201.type=bus +unit.2.0.waveform.posn.202.channel=2147483646 +unit.2.0.waveform.posn.202.name=x +unit.2.0.waveform.posn.202.radix=1 +unit.2.0.waveform.posn.202.type=bus +unit.2.0.waveform.posn.203.channel=2147483646 +unit.2.0.waveform.posn.203.name=x +unit.2.0.waveform.posn.203.radix=1 +unit.2.0.waveform.posn.203.type=bus +unit.2.0.waveform.posn.204.channel=2147483646 +unit.2.0.waveform.posn.204.name=x +unit.2.0.waveform.posn.204.radix=1 +unit.2.0.waveform.posn.204.type=bus +unit.2.0.waveform.posn.205.channel=2147483646 +unit.2.0.waveform.posn.205.name=x +unit.2.0.waveform.posn.205.radix=1 +unit.2.0.waveform.posn.205.type=bus +unit.2.0.waveform.posn.206.channel=2147483646 +unit.2.0.waveform.posn.206.name=x +unit.2.0.waveform.posn.206.radix=1 +unit.2.0.waveform.posn.206.type=bus +unit.2.0.waveform.posn.207.channel=2147483646 +unit.2.0.waveform.posn.207.name=x +unit.2.0.waveform.posn.207.radix=1 +unit.2.0.waveform.posn.207.type=bus +unit.2.0.waveform.posn.208.channel=2147483646 +unit.2.0.waveform.posn.208.name=x +unit.2.0.waveform.posn.208.radix=1 +unit.2.0.waveform.posn.208.type=bus +unit.2.0.waveform.posn.209.channel=2147483646 +unit.2.0.waveform.posn.209.name=x +unit.2.0.waveform.posn.209.radix=1 +unit.2.0.waveform.posn.209.type=bus +unit.2.0.waveform.posn.21.channel=221 +unit.2.0.waveform.posn.21.name=flash_stb +unit.2.0.waveform.posn.21.radix=1 +unit.2.0.waveform.posn.21.type=signal +unit.2.0.waveform.posn.210.channel=2147483646 +unit.2.0.waveform.posn.210.name=x +unit.2.0.waveform.posn.210.radix=1 +unit.2.0.waveform.posn.210.type=bus +unit.2.0.waveform.posn.211.channel=2147483646 +unit.2.0.waveform.posn.211.name=x +unit.2.0.waveform.posn.211.radix=1 +unit.2.0.waveform.posn.211.type=bus +unit.2.0.waveform.posn.212.channel=2147483646 +unit.2.0.waveform.posn.212.name=x +unit.2.0.waveform.posn.212.radix=1 +unit.2.0.waveform.posn.212.type=bus +unit.2.0.waveform.posn.213.channel=2147483646 +unit.2.0.waveform.posn.213.name=x +unit.2.0.waveform.posn.213.radix=1 +unit.2.0.waveform.posn.213.type=bus +unit.2.0.waveform.posn.214.channel=2147483646 +unit.2.0.waveform.posn.214.name=x +unit.2.0.waveform.posn.214.radix=1 +unit.2.0.waveform.posn.214.type=bus +unit.2.0.waveform.posn.215.channel=2147483646 +unit.2.0.waveform.posn.215.name=x +unit.2.0.waveform.posn.215.radix=1 +unit.2.0.waveform.posn.215.type=bus +unit.2.0.waveform.posn.216.channel=2147483646 +unit.2.0.waveform.posn.216.name=x +unit.2.0.waveform.posn.216.radix=1 +unit.2.0.waveform.posn.216.type=bus +unit.2.0.waveform.posn.217.channel=2147483646 +unit.2.0.waveform.posn.217.name=x +unit.2.0.waveform.posn.217.radix=1 +unit.2.0.waveform.posn.217.type=bus +unit.2.0.waveform.posn.218.channel=2147483646 +unit.2.0.waveform.posn.218.name=x +unit.2.0.waveform.posn.218.radix=1 +unit.2.0.waveform.posn.218.type=bus +unit.2.0.waveform.posn.219.channel=2147483646 +unit.2.0.waveform.posn.219.name=x +unit.2.0.waveform.posn.219.radix=1 +unit.2.0.waveform.posn.219.type=bus +unit.2.0.waveform.posn.22.channel=222 +unit.2.0.waveform.posn.22.name=flash_arena +unit.2.0.waveform.posn.22.radix=1 +unit.2.0.waveform.posn.22.type=signal +unit.2.0.waveform.posn.220.channel=2147483646 +unit.2.0.waveform.posn.220.name=x +unit.2.0.waveform.posn.220.radix=1 +unit.2.0.waveform.posn.220.type=bus +unit.2.0.waveform.posn.221.channel=2147483646 +unit.2.0.waveform.posn.221.name=x +unit.2.0.waveform.posn.221.radix=1 +unit.2.0.waveform.posn.221.type=bus +unit.2.0.waveform.posn.222.channel=2147483646 +unit.2.0.waveform.posn.222.name=x +unit.2.0.waveform.posn.222.radix=1 +unit.2.0.waveform.posn.222.type=bus +unit.2.0.waveform.posn.223.channel=2147483646 +unit.2.0.waveform.posn.223.name=x +unit.2.0.waveform.posn.223.radix=1 +unit.2.0.waveform.posn.223.type=bus +unit.2.0.waveform.posn.224.channel=2147483646 +unit.2.0.waveform.posn.224.name=x +unit.2.0.waveform.posn.224.radix=1 +unit.2.0.waveform.posn.224.type=bus +unit.2.0.waveform.posn.225.channel=2147483646 +unit.2.0.waveform.posn.225.name=x +unit.2.0.waveform.posn.225.radix=1 +unit.2.0.waveform.posn.225.type=bus +unit.2.0.waveform.posn.226.channel=2147483646 +unit.2.0.waveform.posn.226.name=x +unit.2.0.waveform.posn.226.radix=1 +unit.2.0.waveform.posn.226.type=bus +unit.2.0.waveform.posn.227.channel=2147483646 +unit.2.0.waveform.posn.227.name=x +unit.2.0.waveform.posn.227.radix=1 +unit.2.0.waveform.posn.227.type=bus +unit.2.0.waveform.posn.228.channel=2147483646 +unit.2.0.waveform.posn.228.name=x +unit.2.0.waveform.posn.228.radix=1 +unit.2.0.waveform.posn.228.type=bus +unit.2.0.waveform.posn.229.channel=2147483646 +unit.2.0.waveform.posn.229.name=x +unit.2.0.waveform.posn.229.radix=1 +unit.2.0.waveform.posn.229.type=bus +unit.2.0.waveform.posn.23.channel=223 +unit.2.0.waveform.posn.23.name=vdu_arena +unit.2.0.waveform.posn.23.radix=1 +unit.2.0.waveform.posn.23.type=signal +unit.2.0.waveform.posn.230.channel=2147483646 +unit.2.0.waveform.posn.230.name=x +unit.2.0.waveform.posn.230.radix=1 +unit.2.0.waveform.posn.230.type=bus +unit.2.0.waveform.posn.231.channel=2147483646 +unit.2.0.waveform.posn.231.name=x +unit.2.0.waveform.posn.231.radix=1 +unit.2.0.waveform.posn.231.type=bus +unit.2.0.waveform.posn.232.channel=2147483646 +unit.2.0.waveform.posn.232.name=x +unit.2.0.waveform.posn.232.radix=1 +unit.2.0.waveform.posn.232.type=bus +unit.2.0.waveform.posn.233.channel=2147483646 +unit.2.0.waveform.posn.233.name=x +unit.2.0.waveform.posn.233.radix=1 +unit.2.0.waveform.posn.233.type=bus +unit.2.0.waveform.posn.234.channel=2147483646 +unit.2.0.waveform.posn.234.name=x +unit.2.0.waveform.posn.234.radix=1 +unit.2.0.waveform.posn.234.type=bus +unit.2.0.waveform.posn.235.channel=2147483646 +unit.2.0.waveform.posn.235.name=x +unit.2.0.waveform.posn.235.radix=1 +unit.2.0.waveform.posn.235.type=bus +unit.2.0.waveform.posn.236.channel=2147483646 +unit.2.0.waveform.posn.236.name=x +unit.2.0.waveform.posn.236.radix=1 +unit.2.0.waveform.posn.236.type=bus +unit.2.0.waveform.posn.237.channel=2147483646 +unit.2.0.waveform.posn.237.name=x +unit.2.0.waveform.posn.237.radix=1 +unit.2.0.waveform.posn.237.type=bus +unit.2.0.waveform.posn.238.channel=2147483646 +unit.2.0.waveform.posn.238.name=x +unit.2.0.waveform.posn.238.radix=1 +unit.2.0.waveform.posn.238.type=bus +unit.2.0.waveform.posn.239.channel=2147483646 +unit.2.0.waveform.posn.239.name=x +unit.2.0.waveform.posn.239.radix=1 +unit.2.0.waveform.posn.239.type=bus +unit.2.0.waveform.posn.24.channel=2147483646 +unit.2.0.waveform.posn.24.name=d +unit.2.0.waveform.posn.24.radix=1 +unit.2.0.waveform.posn.24.type=bus +unit.2.0.waveform.posn.240.channel=2147483646 +unit.2.0.waveform.posn.240.name=x +unit.2.0.waveform.posn.240.radix=1 +unit.2.0.waveform.posn.240.type=bus +unit.2.0.waveform.posn.241.channel=2147483646 +unit.2.0.waveform.posn.241.name=x +unit.2.0.waveform.posn.241.radix=1 +unit.2.0.waveform.posn.241.type=bus +unit.2.0.waveform.posn.242.channel=2147483646 +unit.2.0.waveform.posn.242.name=x +unit.2.0.waveform.posn.242.radix=1 +unit.2.0.waveform.posn.242.type=bus +unit.2.0.waveform.posn.243.channel=2147483646 +unit.2.0.waveform.posn.243.name=x +unit.2.0.waveform.posn.243.radix=1 +unit.2.0.waveform.posn.243.type=bus +unit.2.0.waveform.posn.244.channel=2147483646 +unit.2.0.waveform.posn.244.name=x +unit.2.0.waveform.posn.244.radix=1 +unit.2.0.waveform.posn.244.type=bus +unit.2.0.waveform.posn.245.channel=2147483646 +unit.2.0.waveform.posn.245.name=x +unit.2.0.waveform.posn.245.radix=1 +unit.2.0.waveform.posn.245.type=bus +unit.2.0.waveform.posn.246.channel=2147483646 +unit.2.0.waveform.posn.246.name=x +unit.2.0.waveform.posn.246.radix=1 +unit.2.0.waveform.posn.246.type=bus +unit.2.0.waveform.posn.247.channel=2147483646 +unit.2.0.waveform.posn.247.name=x +unit.2.0.waveform.posn.247.radix=1 +unit.2.0.waveform.posn.247.type=bus +unit.2.0.waveform.posn.248.channel=2147483646 +unit.2.0.waveform.posn.248.name=x +unit.2.0.waveform.posn.248.radix=1 +unit.2.0.waveform.posn.248.type=bus +unit.2.0.waveform.posn.249.channel=2147483646 +unit.2.0.waveform.posn.249.name=x +unit.2.0.waveform.posn.249.radix=1 +unit.2.0.waveform.posn.249.type=bus +unit.2.0.waveform.posn.25.channel=2147483646 +unit.2.0.waveform.posn.25.name=addr_d +unit.2.0.waveform.posn.25.radix=1 +unit.2.0.waveform.posn.25.type=bus +unit.2.0.waveform.posn.250.channel=2147483646 +unit.2.0.waveform.posn.250.name=x +unit.2.0.waveform.posn.250.radix=1 +unit.2.0.waveform.posn.250.type=bus +unit.2.0.waveform.posn.251.channel=2147483646 +unit.2.0.waveform.posn.251.name=x +unit.2.0.waveform.posn.251.radix=1 +unit.2.0.waveform.posn.251.type=bus +unit.2.0.waveform.posn.252.channel=2147483646 +unit.2.0.waveform.posn.252.name=x +unit.2.0.waveform.posn.252.radix=1 +unit.2.0.waveform.posn.252.type=bus +unit.2.0.waveform.posn.253.channel=2147483646 +unit.2.0.waveform.posn.253.name=x +unit.2.0.waveform.posn.253.radix=1 +unit.2.0.waveform.posn.253.type=bus +unit.2.0.waveform.posn.254.channel=2147483646 +unit.2.0.waveform.posn.254.name=x +unit.2.0.waveform.posn.254.radix=1 +unit.2.0.waveform.posn.254.type=bus +unit.2.0.waveform.posn.255.channel=2147483646 +unit.2.0.waveform.posn.255.name=x +unit.2.0.waveform.posn.255.radix=1 +unit.2.0.waveform.posn.255.type=bus +unit.2.0.waveform.posn.256.channel=2147483646 +unit.2.0.waveform.posn.256.name=x +unit.2.0.waveform.posn.256.radix=1 +unit.2.0.waveform.posn.256.type=bus +unit.2.0.waveform.posn.257.channel=2147483646 +unit.2.0.waveform.posn.257.name=x +unit.2.0.waveform.posn.257.radix=1 +unit.2.0.waveform.posn.257.type=bus +unit.2.0.waveform.posn.258.channel=2147483646 +unit.2.0.waveform.posn.258.name=x +unit.2.0.waveform.posn.258.radix=1 +unit.2.0.waveform.posn.258.type=bus +unit.2.0.waveform.posn.259.channel=2147483646 +unit.2.0.waveform.posn.259.name=x +unit.2.0.waveform.posn.259.radix=1 +unit.2.0.waveform.posn.259.type=bus +unit.2.0.waveform.posn.26.channel=94 +unit.2.0.waveform.posn.26.name=byte_op +unit.2.0.waveform.posn.26.radix=1 +unit.2.0.waveform.posn.26.type=signal +unit.2.0.waveform.posn.260.channel=2147483646 +unit.2.0.waveform.posn.260.name=x +unit.2.0.waveform.posn.260.radix=1 +unit.2.0.waveform.posn.260.type=bus +unit.2.0.waveform.posn.261.channel=2147483646 +unit.2.0.waveform.posn.261.name=x +unit.2.0.waveform.posn.261.radix=1 +unit.2.0.waveform.posn.261.type=bus +unit.2.0.waveform.posn.262.channel=2147483646 +unit.2.0.waveform.posn.262.name=x +unit.2.0.waveform.posn.262.radix=1 +unit.2.0.waveform.posn.262.type=bus +unit.2.0.waveform.posn.263.channel=2147483646 +unit.2.0.waveform.posn.263.name=x +unit.2.0.waveform.posn.263.radix=1 +unit.2.0.waveform.posn.263.type=bus +unit.2.0.waveform.posn.264.channel=2147483646 +unit.2.0.waveform.posn.264.name=x +unit.2.0.waveform.posn.264.radix=1 +unit.2.0.waveform.posn.264.type=bus +unit.2.0.waveform.posn.265.channel=2147483646 +unit.2.0.waveform.posn.265.name=x +unit.2.0.waveform.posn.265.radix=1 +unit.2.0.waveform.posn.265.type=bus +unit.2.0.waveform.posn.266.channel=2147483646 +unit.2.0.waveform.posn.266.name=x +unit.2.0.waveform.posn.266.radix=1 +unit.2.0.waveform.posn.266.type=bus +unit.2.0.waveform.posn.267.channel=2147483646 +unit.2.0.waveform.posn.267.name=x +unit.2.0.waveform.posn.267.radix=1 +unit.2.0.waveform.posn.267.type=bus +unit.2.0.waveform.posn.268.channel=2147483646 +unit.2.0.waveform.posn.268.name=x +unit.2.0.waveform.posn.268.radix=1 +unit.2.0.waveform.posn.268.type=bus +unit.2.0.waveform.posn.269.channel=2147483646 +unit.2.0.waveform.posn.269.name=x +unit.2.0.waveform.posn.269.radix=1 +unit.2.0.waveform.posn.269.type=bus +unit.2.0.waveform.posn.27.channel=104 +unit.2.0.waveform.posn.27.name=inta +unit.2.0.waveform.posn.27.radix=1 +unit.2.0.waveform.posn.27.type=signal +unit.2.0.waveform.posn.270.channel=2147483646 +unit.2.0.waveform.posn.270.name=x +unit.2.0.waveform.posn.270.radix=1 +unit.2.0.waveform.posn.270.type=bus +unit.2.0.waveform.posn.271.channel=2147483646 +unit.2.0.waveform.posn.271.name=x +unit.2.0.waveform.posn.271.radix=1 +unit.2.0.waveform.posn.271.type=bus +unit.2.0.waveform.posn.272.channel=2147483646 +unit.2.0.waveform.posn.272.name=x +unit.2.0.waveform.posn.272.radix=1 +unit.2.0.waveform.posn.272.type=bus +unit.2.0.waveform.posn.273.channel=2147483646 +unit.2.0.waveform.posn.273.name=x +unit.2.0.waveform.posn.273.radix=1 +unit.2.0.waveform.posn.273.type=bus +unit.2.0.waveform.posn.274.channel=2147483646 +unit.2.0.waveform.posn.274.name=x +unit.2.0.waveform.posn.274.radix=1 +unit.2.0.waveform.posn.274.type=bus +unit.2.0.waveform.posn.275.channel=2147483646 +unit.2.0.waveform.posn.275.name=x +unit.2.0.waveform.posn.275.radix=1 +unit.2.0.waveform.posn.275.type=bus +unit.2.0.waveform.posn.276.channel=2147483646 +unit.2.0.waveform.posn.276.name=x +unit.2.0.waveform.posn.276.radix=1 +unit.2.0.waveform.posn.276.type=bus +unit.2.0.waveform.posn.277.channel=2147483646 +unit.2.0.waveform.posn.277.name=x +unit.2.0.waveform.posn.277.radix=1 +unit.2.0.waveform.posn.277.type=bus +unit.2.0.waveform.posn.278.channel=2147483646 +unit.2.0.waveform.posn.278.name=x +unit.2.0.waveform.posn.278.radix=1 +unit.2.0.waveform.posn.278.type=bus +unit.2.0.waveform.posn.279.channel=2147483646 +unit.2.0.waveform.posn.279.name=x +unit.2.0.waveform.posn.279.radix=1 +unit.2.0.waveform.posn.279.type=bus +unit.2.0.waveform.posn.28.channel=105 +unit.2.0.waveform.posn.28.name=intr +unit.2.0.waveform.posn.28.radix=1 +unit.2.0.waveform.posn.28.type=signal +unit.2.0.waveform.posn.280.channel=2147483646 +unit.2.0.waveform.posn.280.name=x +unit.2.0.waveform.posn.280.radix=1 +unit.2.0.waveform.posn.280.type=bus +unit.2.0.waveform.posn.281.channel=2147483646 +unit.2.0.waveform.posn.281.name=x +unit.2.0.waveform.posn.281.radix=1 +unit.2.0.waveform.posn.281.type=bus +unit.2.0.waveform.posn.282.channel=2147483646 +unit.2.0.waveform.posn.282.name=x +unit.2.0.waveform.posn.282.radix=1 +unit.2.0.waveform.posn.282.type=bus +unit.2.0.waveform.posn.283.channel=2147483646 +unit.2.0.waveform.posn.283.name=x +unit.2.0.waveform.posn.283.radix=1 +unit.2.0.waveform.posn.283.type=bus +unit.2.0.waveform.posn.284.channel=2147483646 +unit.2.0.waveform.posn.284.name=x +unit.2.0.waveform.posn.284.radix=1 +unit.2.0.waveform.posn.284.type=bus +unit.2.0.waveform.posn.285.channel=2147483646 +unit.2.0.waveform.posn.285.name=x +unit.2.0.waveform.posn.285.radix=1 +unit.2.0.waveform.posn.285.type=bus +unit.2.0.waveform.posn.286.channel=2147483646 +unit.2.0.waveform.posn.286.name=x +unit.2.0.waveform.posn.286.radix=1 +unit.2.0.waveform.posn.286.type=bus +unit.2.0.waveform.posn.287.channel=2147483646 +unit.2.0.waveform.posn.287.name=x +unit.2.0.waveform.posn.287.radix=1 +unit.2.0.waveform.posn.287.type=bus +unit.2.0.waveform.posn.288.channel=2147483646 +unit.2.0.waveform.posn.288.name=x +unit.2.0.waveform.posn.288.radix=1 +unit.2.0.waveform.posn.288.type=bus +unit.2.0.waveform.posn.289.channel=2147483646 +unit.2.0.waveform.posn.289.name=x +unit.2.0.waveform.posn.289.radix=1 +unit.2.0.waveform.posn.289.type=bus +unit.2.0.waveform.posn.29.channel=2147483646 +unit.2.0.waveform.posn.29.name=cnt_time +unit.2.0.waveform.posn.29.radix=1 +unit.2.0.waveform.posn.29.type=bus +unit.2.0.waveform.posn.290.channel=2147483646 +unit.2.0.waveform.posn.290.name=x +unit.2.0.waveform.posn.290.radix=1 +unit.2.0.waveform.posn.290.type=bus +unit.2.0.waveform.posn.291.channel=2147483646 +unit.2.0.waveform.posn.291.name=x +unit.2.0.waveform.posn.291.radix=1 +unit.2.0.waveform.posn.291.type=bus +unit.2.0.waveform.posn.292.channel=2147483646 +unit.2.0.waveform.posn.292.name=x +unit.2.0.waveform.posn.292.radix=1 +unit.2.0.waveform.posn.292.type=bus +unit.2.0.waveform.posn.293.channel=2147483646 +unit.2.0.waveform.posn.293.name=x +unit.2.0.waveform.posn.293.radix=1 +unit.2.0.waveform.posn.293.type=bus +unit.2.0.waveform.posn.294.channel=2147483646 +unit.2.0.waveform.posn.294.name=x +unit.2.0.waveform.posn.294.radix=1 +unit.2.0.waveform.posn.294.type=bus +unit.2.0.waveform.posn.295.channel=2147483646 +unit.2.0.waveform.posn.295.name=x +unit.2.0.waveform.posn.295.radix=1 +unit.2.0.waveform.posn.295.type=bus +unit.2.0.waveform.posn.296.channel=2147483646 +unit.2.0.waveform.posn.296.name=x +unit.2.0.waveform.posn.296.radix=1 +unit.2.0.waveform.posn.296.type=bus +unit.2.0.waveform.posn.297.channel=2147483646 +unit.2.0.waveform.posn.297.name=x +unit.2.0.waveform.posn.297.radix=1 +unit.2.0.waveform.posn.297.type=bus +unit.2.0.waveform.posn.298.channel=2147483646 +unit.2.0.waveform.posn.298.name=x +unit.2.0.waveform.posn.298.radix=1 +unit.2.0.waveform.posn.298.type=bus +unit.2.0.waveform.posn.299.channel=2147483646 +unit.2.0.waveform.posn.299.name=x +unit.2.0.waveform.posn.299.radix=1 +unit.2.0.waveform.posn.299.type=bus +unit.2.0.waveform.posn.3.channel=2147483646 +unit.2.0.waveform.posn.3.name=pc +unit.2.0.waveform.posn.3.radix=1 +unit.2.0.waveform.posn.3.type=bus +unit.2.0.waveform.posn.30.channel=2147483646 +unit.2.0.waveform.posn.30.name=ace_dat_o +unit.2.0.waveform.posn.30.radix=1 +unit.2.0.waveform.posn.30.type=bus +unit.2.0.waveform.posn.300.channel=2147483646 +unit.2.0.waveform.posn.300.name=x +unit.2.0.waveform.posn.300.radix=1 +unit.2.0.waveform.posn.300.type=bus +unit.2.0.waveform.posn.301.channel=2147483646 +unit.2.0.waveform.posn.301.name=x +unit.2.0.waveform.posn.301.radix=1 +unit.2.0.waveform.posn.301.type=bus +unit.2.0.waveform.posn.302.channel=2147483646 +unit.2.0.waveform.posn.302.name=x +unit.2.0.waveform.posn.302.radix=1 +unit.2.0.waveform.posn.302.type=bus +unit.2.0.waveform.posn.303.channel=2147483646 +unit.2.0.waveform.posn.303.name=x +unit.2.0.waveform.posn.303.radix=1 +unit.2.0.waveform.posn.303.type=bus +unit.2.0.waveform.posn.304.channel=2147483646 +unit.2.0.waveform.posn.304.name=x +unit.2.0.waveform.posn.304.radix=1 +unit.2.0.waveform.posn.304.type=bus +unit.2.0.waveform.posn.305.channel=2147483646 +unit.2.0.waveform.posn.305.name=x +unit.2.0.waveform.posn.305.radix=1 +unit.2.0.waveform.posn.305.type=bus +unit.2.0.waveform.posn.306.channel=2147483646 +unit.2.0.waveform.posn.306.name=x +unit.2.0.waveform.posn.306.radix=1 +unit.2.0.waveform.posn.306.type=bus +unit.2.0.waveform.posn.307.channel=2147483646 +unit.2.0.waveform.posn.307.name=x +unit.2.0.waveform.posn.307.radix=1 +unit.2.0.waveform.posn.307.type=bus +unit.2.0.waveform.posn.308.channel=2147483646 +unit.2.0.waveform.posn.308.name=x +unit.2.0.waveform.posn.308.radix=1 +unit.2.0.waveform.posn.308.type=bus +unit.2.0.waveform.posn.309.channel=2147483646 +unit.2.0.waveform.posn.309.name=x +unit.2.0.waveform.posn.309.radix=1 +unit.2.0.waveform.posn.309.type=bus +unit.2.0.waveform.posn.31.channel=186 +unit.2.0.waveform.posn.31.name=ace_stb +unit.2.0.waveform.posn.31.radix=1 +unit.2.0.waveform.posn.31.type=signal +unit.2.0.waveform.posn.310.channel=2147483646 +unit.2.0.waveform.posn.310.name=x +unit.2.0.waveform.posn.310.radix=1 +unit.2.0.waveform.posn.310.type=bus +unit.2.0.waveform.posn.311.channel=2147483646 +unit.2.0.waveform.posn.311.name=x +unit.2.0.waveform.posn.311.radix=1 +unit.2.0.waveform.posn.311.type=bus +unit.2.0.waveform.posn.312.channel=2147483646 +unit.2.0.waveform.posn.312.name=x +unit.2.0.waveform.posn.312.radix=1 +unit.2.0.waveform.posn.312.type=bus +unit.2.0.waveform.posn.313.channel=2147483646 +unit.2.0.waveform.posn.313.name=x +unit.2.0.waveform.posn.313.radix=1 +unit.2.0.waveform.posn.313.type=bus +unit.2.0.waveform.posn.314.channel=2147483646 +unit.2.0.waveform.posn.314.name=x +unit.2.0.waveform.posn.314.radix=1 +unit.2.0.waveform.posn.314.type=bus +unit.2.0.waveform.posn.315.channel=2147483646 +unit.2.0.waveform.posn.315.name=x +unit.2.0.waveform.posn.315.radix=1 +unit.2.0.waveform.posn.315.type=bus +unit.2.0.waveform.posn.316.channel=2147483646 +unit.2.0.waveform.posn.316.name=y +unit.2.0.waveform.posn.316.radix=1 +unit.2.0.waveform.posn.316.type=bus +unit.2.0.waveform.posn.32.channel=187 +unit.2.0.waveform.posn.32.name=ace_ack +unit.2.0.waveform.posn.32.radix=1 +unit.2.0.waveform.posn.32.type=signal +unit.2.0.waveform.posn.33.channel=188 +unit.2.0.waveform.posn.33.name=aceusb_oe_n_ +unit.2.0.waveform.posn.33.radix=1 +unit.2.0.waveform.posn.33.type=signal +unit.2.0.waveform.posn.34.channel=189 +unit.2.0.waveform.posn.34.name=aceusb_we_n +unit.2.0.waveform.posn.34.radix=1 +unit.2.0.waveform.posn.34.type=signal +unit.2.0.waveform.posn.35.channel=190 +unit.2.0.waveform.posn.35.name=ace_mpce_n_ +unit.2.0.waveform.posn.35.radix=1 +unit.2.0.waveform.posn.35.type=signal +unit.2.0.waveform.posn.36.channel=2147483646 +unit.2.0.waveform.posn.36.name=aceusb_d_ +unit.2.0.waveform.posn.36.radix=1 +unit.2.0.waveform.posn.36.type=bus +unit.2.0.waveform.posn.37.channel=214 +unit.2.0.waveform.posn.37.name=rx_output +unit.2.0.waveform.posn.37.radix=1 +unit.2.0.waveform.posn.37.type=signal +unit.2.0.waveform.posn.38.channel=207 +unit.2.0.waveform.posn.38.name=iid +unit.2.0.waveform.posn.38.radix=1 +unit.2.0.waveform.posn.38.type=signal +unit.2.0.waveform.posn.39.channel=208 +unit.2.0.waveform.posn.39.name=irr0 +unit.2.0.waveform.posn.39.radix=1 +unit.2.0.waveform.posn.39.type=signal +unit.2.0.waveform.posn.4.channel=2147483646 +unit.2.0.waveform.posn.4.name=state +unit.2.0.waveform.posn.4.radix=1 +unit.2.0.waveform.posn.4.type=bus +unit.2.0.waveform.posn.40.channel=209 +unit.2.0.waveform.posn.40.name=irr1 +unit.2.0.waveform.posn.40.radix=1 +unit.2.0.waveform.posn.40.type=signal +unit.2.0.waveform.posn.41.channel=210 +unit.2.0.waveform.posn.41.name=int0 +unit.2.0.waveform.posn.41.radix=1 +unit.2.0.waveform.posn.41.type=signal +unit.2.0.waveform.posn.42.channel=211 +unit.2.0.waveform.posn.42.name=int1 +unit.2.0.waveform.posn.42.radix=1 +unit.2.0.waveform.posn.42.type=signal +unit.2.0.waveform.posn.43.channel=212 +unit.2.0.waveform.posn.43.name=released +unit.2.0.waveform.posn.43.radix=1 +unit.2.0.waveform.posn.43.type=signal +unit.2.0.waveform.posn.44.channel=213 +unit.2.0.waveform.posn.44.name=rx_shift +unit.2.0.waveform.posn.44.radix=1 +unit.2.0.waveform.posn.44.type=signal +unit.2.0.waveform.posn.45.channel=2147483646 +unit.2.0.waveform.posn.45.name=x +unit.2.0.waveform.posn.45.radix=1 +unit.2.0.waveform.posn.45.type=bus +unit.2.0.waveform.posn.46.channel=2147483646 +unit.2.0.waveform.posn.46.name=x +unit.2.0.waveform.posn.46.radix=1 +unit.2.0.waveform.posn.46.type=bus +unit.2.0.waveform.posn.47.channel=2147483646 +unit.2.0.waveform.posn.47.name=x +unit.2.0.waveform.posn.47.radix=1 +unit.2.0.waveform.posn.47.type=bus +unit.2.0.waveform.posn.48.channel=2147483646 +unit.2.0.waveform.posn.48.name=x +unit.2.0.waveform.posn.48.radix=1 +unit.2.0.waveform.posn.48.type=bus +unit.2.0.waveform.posn.49.channel=2147483646 +unit.2.0.waveform.posn.49.name=x +unit.2.0.waveform.posn.49.radix=1 +unit.2.0.waveform.posn.49.type=bus +unit.2.0.waveform.posn.5.channel=2147483646 +unit.2.0.waveform.posn.5.name=flags +unit.2.0.waveform.posn.5.radix=1 +unit.2.0.waveform.posn.5.type=bus +unit.2.0.waveform.posn.50.channel=2147483646 +unit.2.0.waveform.posn.50.name=x +unit.2.0.waveform.posn.50.radix=1 +unit.2.0.waveform.posn.50.type=bus +unit.2.0.waveform.posn.51.channel=2147483646 +unit.2.0.waveform.posn.51.name=x +unit.2.0.waveform.posn.51.radix=1 +unit.2.0.waveform.posn.51.type=bus +unit.2.0.waveform.posn.52.channel=2147483646 +unit.2.0.waveform.posn.52.name=x +unit.2.0.waveform.posn.52.radix=1 +unit.2.0.waveform.posn.52.type=bus +unit.2.0.waveform.posn.53.channel=2147483646 +unit.2.0.waveform.posn.53.name=x +unit.2.0.waveform.posn.53.radix=1 +unit.2.0.waveform.posn.53.type=bus +unit.2.0.waveform.posn.54.channel=2147483646 +unit.2.0.waveform.posn.54.name=x +unit.2.0.waveform.posn.54.radix=1 +unit.2.0.waveform.posn.54.type=bus +unit.2.0.waveform.posn.55.channel=2147483646 +unit.2.0.waveform.posn.55.name=x +unit.2.0.waveform.posn.55.radix=1 +unit.2.0.waveform.posn.55.type=bus +unit.2.0.waveform.posn.56.channel=2147483646 +unit.2.0.waveform.posn.56.name=x +unit.2.0.waveform.posn.56.radix=1 +unit.2.0.waveform.posn.56.type=bus +unit.2.0.waveform.posn.57.channel=2147483646 +unit.2.0.waveform.posn.57.name=x +unit.2.0.waveform.posn.57.radix=1 +unit.2.0.waveform.posn.57.type=bus +unit.2.0.waveform.posn.58.channel=2147483646 +unit.2.0.waveform.posn.58.name=x +unit.2.0.waveform.posn.58.radix=1 +unit.2.0.waveform.posn.58.type=bus +unit.2.0.waveform.posn.59.channel=2147483646 +unit.2.0.waveform.posn.59.name=x +unit.2.0.waveform.posn.59.radix=1 +unit.2.0.waveform.posn.59.type=bus +unit.2.0.waveform.posn.6.channel=2147483646 +unit.2.0.waveform.posn.6.name=next_state +unit.2.0.waveform.posn.6.radix=1 +unit.2.0.waveform.posn.6.type=bus +unit.2.0.waveform.posn.60.channel=2147483646 +unit.2.0.waveform.posn.60.name=x +unit.2.0.waveform.posn.60.radix=1 +unit.2.0.waveform.posn.60.type=bus +unit.2.0.waveform.posn.61.channel=2147483646 +unit.2.0.waveform.posn.61.name=x +unit.2.0.waveform.posn.61.radix=1 +unit.2.0.waveform.posn.61.type=bus +unit.2.0.waveform.posn.62.channel=2147483646 +unit.2.0.waveform.posn.62.name=x +unit.2.0.waveform.posn.62.radix=1 +unit.2.0.waveform.posn.62.type=bus +unit.2.0.waveform.posn.63.channel=2147483646 +unit.2.0.waveform.posn.63.name=x +unit.2.0.waveform.posn.63.radix=1 +unit.2.0.waveform.posn.63.type=bus +unit.2.0.waveform.posn.64.channel=2147483646 +unit.2.0.waveform.posn.64.name=x +unit.2.0.waveform.posn.64.radix=1 +unit.2.0.waveform.posn.64.type=bus +unit.2.0.waveform.posn.65.channel=2147483646 +unit.2.0.waveform.posn.65.name=x +unit.2.0.waveform.posn.65.radix=1 +unit.2.0.waveform.posn.65.type=bus +unit.2.0.waveform.posn.66.channel=2147483646 +unit.2.0.waveform.posn.66.name=x +unit.2.0.waveform.posn.66.radix=1 +unit.2.0.waveform.posn.66.type=bus +unit.2.0.waveform.posn.67.channel=2147483646 +unit.2.0.waveform.posn.67.name=x +unit.2.0.waveform.posn.67.radix=1 +unit.2.0.waveform.posn.67.type=bus +unit.2.0.waveform.posn.68.channel=2147483646 +unit.2.0.waveform.posn.68.name=x +unit.2.0.waveform.posn.68.radix=1 +unit.2.0.waveform.posn.68.type=bus +unit.2.0.waveform.posn.69.channel=2147483646 +unit.2.0.waveform.posn.69.name=x +unit.2.0.waveform.posn.69.radix=1 +unit.2.0.waveform.posn.69.type=bus +unit.2.0.waveform.posn.7.channel=2147483646 +unit.2.0.waveform.posn.7.name=func +unit.2.0.waveform.posn.7.radix=1 +unit.2.0.waveform.posn.7.type=bus +unit.2.0.waveform.posn.70.channel=2147483646 +unit.2.0.waveform.posn.70.name=x +unit.2.0.waveform.posn.70.radix=1 +unit.2.0.waveform.posn.70.type=bus +unit.2.0.waveform.posn.71.channel=2147483646 +unit.2.0.waveform.posn.71.name=x +unit.2.0.waveform.posn.71.radix=1 +unit.2.0.waveform.posn.71.type=bus +unit.2.0.waveform.posn.72.channel=2147483646 +unit.2.0.waveform.posn.72.name=x +unit.2.0.waveform.posn.72.radix=1 +unit.2.0.waveform.posn.72.type=bus +unit.2.0.waveform.posn.73.channel=2147483646 +unit.2.0.waveform.posn.73.name=x +unit.2.0.waveform.posn.73.radix=1 +unit.2.0.waveform.posn.73.type=bus +unit.2.0.waveform.posn.74.channel=2147483646 +unit.2.0.waveform.posn.74.name=x +unit.2.0.waveform.posn.74.radix=1 +unit.2.0.waveform.posn.74.type=bus +unit.2.0.waveform.posn.75.channel=2147483646 +unit.2.0.waveform.posn.75.name=x +unit.2.0.waveform.posn.75.radix=1 +unit.2.0.waveform.posn.75.type=bus +unit.2.0.waveform.posn.76.channel=2147483646 +unit.2.0.waveform.posn.76.name=x +unit.2.0.waveform.posn.76.radix=1 +unit.2.0.waveform.posn.76.type=bus +unit.2.0.waveform.posn.77.channel=2147483646 +unit.2.0.waveform.posn.77.name=x +unit.2.0.waveform.posn.77.radix=1 +unit.2.0.waveform.posn.77.type=bus +unit.2.0.waveform.posn.78.channel=2147483646 +unit.2.0.waveform.posn.78.name=x +unit.2.0.waveform.posn.78.radix=1 +unit.2.0.waveform.posn.78.type=bus +unit.2.0.waveform.posn.79.channel=2147483646 +unit.2.0.waveform.posn.79.name=x +unit.2.0.waveform.posn.79.radix=1 +unit.2.0.waveform.posn.79.type=bus +unit.2.0.waveform.posn.8.channel=2147483646 +unit.2.0.waveform.posn.8.name=t +unit.2.0.waveform.posn.8.radix=1 +unit.2.0.waveform.posn.8.type=bus +unit.2.0.waveform.posn.80.channel=2147483646 +unit.2.0.waveform.posn.80.name=x +unit.2.0.waveform.posn.80.radix=1 +unit.2.0.waveform.posn.80.type=bus +unit.2.0.waveform.posn.81.channel=2147483646 +unit.2.0.waveform.posn.81.name=x +unit.2.0.waveform.posn.81.radix=1 +unit.2.0.waveform.posn.81.type=bus +unit.2.0.waveform.posn.82.channel=2147483646 +unit.2.0.waveform.posn.82.name=x +unit.2.0.waveform.posn.82.radix=1 +unit.2.0.waveform.posn.82.type=bus +unit.2.0.waveform.posn.83.channel=2147483646 +unit.2.0.waveform.posn.83.name=x +unit.2.0.waveform.posn.83.radix=1 +unit.2.0.waveform.posn.83.type=bus +unit.2.0.waveform.posn.84.channel=2147483646 +unit.2.0.waveform.posn.84.name=x +unit.2.0.waveform.posn.84.radix=1 +unit.2.0.waveform.posn.84.type=bus +unit.2.0.waveform.posn.85.channel=2147483646 +unit.2.0.waveform.posn.85.name=x +unit.2.0.waveform.posn.85.radix=1 +unit.2.0.waveform.posn.85.type=bus +unit.2.0.waveform.posn.86.channel=2147483646 +unit.2.0.waveform.posn.86.name=x +unit.2.0.waveform.posn.86.radix=1 +unit.2.0.waveform.posn.86.type=bus +unit.2.0.waveform.posn.87.channel=2147483646 +unit.2.0.waveform.posn.87.name=x +unit.2.0.waveform.posn.87.radix=1 +unit.2.0.waveform.posn.87.type=bus +unit.2.0.waveform.posn.88.channel=2147483646 +unit.2.0.waveform.posn.88.name=x +unit.2.0.waveform.posn.88.radix=1 +unit.2.0.waveform.posn.88.type=bus +unit.2.0.waveform.posn.89.channel=2147483646 +unit.2.0.waveform.posn.89.name=x +unit.2.0.waveform.posn.89.radix=1 +unit.2.0.waveform.posn.89.type=bus +unit.2.0.waveform.posn.9.channel=2147483646 +unit.2.0.waveform.posn.9.name=adr +unit.2.0.waveform.posn.9.radix=1 +unit.2.0.waveform.posn.9.type=bus +unit.2.0.waveform.posn.90.channel=2147483646 +unit.2.0.waveform.posn.90.name=x +unit.2.0.waveform.posn.90.radix=1 +unit.2.0.waveform.posn.90.type=bus +unit.2.0.waveform.posn.91.channel=2147483646 +unit.2.0.waveform.posn.91.name=x +unit.2.0.waveform.posn.91.radix=1 +unit.2.0.waveform.posn.91.type=bus +unit.2.0.waveform.posn.92.channel=2147483646 +unit.2.0.waveform.posn.92.name=x +unit.2.0.waveform.posn.92.radix=1 +unit.2.0.waveform.posn.92.type=bus +unit.2.0.waveform.posn.93.channel=2147483646 +unit.2.0.waveform.posn.93.name=x +unit.2.0.waveform.posn.93.radix=1 +unit.2.0.waveform.posn.93.type=bus +unit.2.0.waveform.posn.94.channel=2147483646 +unit.2.0.waveform.posn.94.name=x +unit.2.0.waveform.posn.94.radix=1 +unit.2.0.waveform.posn.94.type=bus +unit.2.0.waveform.posn.95.channel=2147483646 +unit.2.0.waveform.posn.95.name=x +unit.2.0.waveform.posn.95.radix=1 +unit.2.0.waveform.posn.95.type=bus +unit.2.0.waveform.posn.96.channel=2147483646 +unit.2.0.waveform.posn.96.name=x +unit.2.0.waveform.posn.96.radix=1 +unit.2.0.waveform.posn.96.type=bus +unit.2.0.waveform.posn.97.channel=2147483646 +unit.2.0.waveform.posn.97.name=x +unit.2.0.waveform.posn.97.radix=1 +unit.2.0.waveform.posn.97.type=bus +unit.2.0.waveform.posn.98.channel=2147483646 +unit.2.0.waveform.posn.98.name=x +unit.2.0.waveform.posn.98.radix=1 +unit.2.0.waveform.posn.98.type=bus +unit.2.0.waveform.posn.99.channel=2147483646 +unit.2.0.waveform.posn.99.name=x +unit.2.0.waveform.posn.99.radix=1 +unit.2.0.waveform.posn.99.type=bus Index: trunk/boards/virtex4-ml403ep/test/uart.v =================================================================== --- trunk/boards/virtex4-ml403ep/test/uart.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/uart.v (revision 54) @@ -0,0 +1,47 @@ +module uart_ctrl(wr, trx_req, trx_ack, trx, + clr, clk); + // Entrades + input [6:0] wr; + input trx_req; + input clr, clk; + + // Sortides + output reg trx_ack, trx; + + // Registres + reg [7:0] et, etrx; + reg [6:0] data_wr; + + // Algorisme de transmissi� + always @(negedge clk) + if (clr) + begin + et <= 8'd00; + etrx <= 8'd00; + trx <= 1'b1; + trx_ack <= 1'b0; + end + else + case (et) + 8'd00: if (trx_req) et <= 8'd05; + 8'd05: + if (~trx_req) + begin et <= 8'd00; etrx <= 8'd00; end + else + case (etrx) + 8'd00: begin data_wr <= wr; trx <= 1'b1; etrx <= 8'd05; end + 8'd05: begin trx <= 1'b0; etrx <= 8'd10; end // Start bit + 8'd10: begin trx <= data_wr[0]; etrx <= 8'd15; end + 8'd15: begin trx <= data_wr[1]; etrx <= 8'd20; end + 8'd20: begin trx <= data_wr[2]; etrx <= 8'd25; end + 8'd25: begin trx <= data_wr[3]; etrx <= 8'd30; end + 8'd30: begin trx <= data_wr[4]; etrx <= 8'd35; end + 8'd35: begin trx <= data_wr[5]; etrx <= 8'd40; end + 8'd40: begin trx <= data_wr[6]; etrx <= 8'd45; end + 8'd45: begin trx <= 1'b0; etrx <= 8'd50; end + 8'd50: begin trx_ack <= 1'b1; trx <= 1'b1; etrx <= 8'd00; et <= 8'd10; end + endcase + 8'd10: if (~trx_req) begin trx_ack <= 1'b0; et <= 8'd00; end + endcase + +endmodule \ No newline at end of file Index: trunk/boards/virtex4-ml403ep/test/flash_dump.v =================================================================== --- trunk/boards/virtex4-ml403ep/test/flash_dump.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/flash_dump.v (revision 54) @@ -0,0 +1,150 @@ +//`define HIGH_BIOS 13'h0000 +`define HIGH_BIOS 13'h00FF + +module flash_dump ( + input sys_clk_in, + output trx, + + output [20:0] flash_addr, + input [15:0] flash_data, + output flash_we_n, + output flash_oe_n, + output flash_ce2 + ); + + reg clk_9600; + reg [11:0] count_uart; + reg [ 6:0] dada_wr; + reg [ 7:0] estat; + reg [ 7:0] addr; + reg [ 2:0] espacios; + reg [ 6:0] char; + reg [ 3:0] nibble; + reg [ 7:0] col; + reg trx_req; + reg [ 7:0] adr0; + + wire clk_60M; + wire rst, lock; + wire trx_ack; + wire [15:0] rd_data; + + reg [15:0] ram[0:255]; + reg [15:0] dades; + + reg [ 3:0] count; + + // Instanciacions de mòduls + clocks c0 ( + .CLKIN_IN (sys_clk_in), + .CLKFX_OUT (clk_60M), + .LOCKED_OUT (lock) + ); + + uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx, + rst, clk_9600); + + // Assignacions contínues + assign rst = ~lock; + + assign flash_addr = { `HIGH_BIOS, adr0 }; + assign rd_data = flash_data; + assign flash_we_n = 1'b1; + assign flash_oe_n = 1'b0; + assign flash_ce2 = 1'b1; + + // Descripció del comportament + // count_uart + always @(posedge clk_60M) + if (rst) count_uart <= 12'h0; + else count_uart <= (count_uart==12'd3124) ? + 12'd0 : count_uart + 12'd1; + + // clk_9600 + always @(posedge clk_60M) + if (rst) clk_9600 <= 1'b0; + else clk_9600 <= (count_uart==12'd0) ? + !clk_9600 : clk_9600; + + // adr0 + always @(posedge clk_60M) + if (rst) adr0 <= 8'h00; + else adr0 <= (adr0==8'hff || count!=4'hf) ? adr0 + : (adr0 + 8'h01); + // count + always @(posedge clk_60M) + if (rst) count <= 4'h0; + else count <= count + 4'h1; + + // ram + always @(posedge clk_60M) ram[adr0] <= rd_data; + + // dades + always @(posedge clk_60M) + if (rst) dades <= 16'h0; + else dades <= ram[addr]; + + always @(posedge clk_60M) + if (adr0!=8'hff) + begin + dada_wr <= 7'h30; + trx_req <= 0; + estat <= 8'd0; + addr <= 8'h00; + espacios <= 3'd2; + char <= 7'd00; + nibble <= 4'd0; + col <= 8'd79; + end + else + case (estat) + 8'd00: if (~trx_ack) + begin estat <= 8'd01; + if (espacios > 3'd0) + begin char <= 7'h20; espacios <= espacios - 3'd1; end + else + begin + char <= ascii(nibble); espacios <= 3'd4; + nibble <= nibble + 4'd1; + end + end + 8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end + 8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end + 8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end + else estat <= 8'd04; + + 8'd04: if (~trx_ack) estat <= 8'd05; + 8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end + 8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end + + 8'd15: if (~trx_ack) estat <= 8'd20; + 8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end + 8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end + + 8'd30: if (~trx_ack) estat <= 8'd35; + 8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end + 8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end + + 8'd45: if (~trx_ack) estat <= 8'd50; + 8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end + 8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end + + 8'd60: if (~trx_ack) estat <= 8'd65; + 8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end + 8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end + + 8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90; + else if (~trx_ack) estat <= 8'd80; + 8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end + 8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end + + 8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end + else estat <= 8'd95; + 8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15; + endcase + + function [6:0] ascii(input [3:0] num); + if (num <= 4'd9) ascii = 7'h30 + num; + else ascii = 7'd87 + num; + endfunction +endmodule Index: trunk/boards/virtex4-ml403ep/test/ml403-flash.ucf =================================================================== --- trunk/boards/virtex4-ml403ep/test/ml403-flash.ucf (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/ml403-flash.ucf (revision 54) @@ -0,0 +1,56 @@ +NET sys_clk_in TNM_NET = "sys_clk_in"; +TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; + +NET sys_clk_in LOC = AE14; +NET sys_clk_in IOSTANDARD = LVCMOS33; + +NET trx LOC = W1; + +#NET flash_addr[24] LOC = T21; +#NET flash_addr[23] LOC = U20; +#NET flash_addr[22] LOC = T19; +NET flash_addr[20] LOC = AC5; +NET flash_addr[19] LOC = AB5; +NET flash_addr[18] LOC = AC4; +NET flash_addr[17] LOC = AB4; +NET flash_addr[16] LOC = AB3; +NET flash_addr[15] LOC = AA4; +NET flash_addr[14] LOC = AA3; +NET flash_addr[13] LOC = W5; +NET flash_addr[12] LOC = W6; +NET flash_addr[11] LOC = W3; +NET flash_addr[10] LOC = AF3; +NET flash_addr[9] LOC = AE3; +NET flash_addr[8] LOC = AD2; +NET flash_addr[7] LOC = AD1; +NET flash_addr[6] LOC = AC2; +NET flash_addr[5] LOC = AC1; +NET flash_addr[4] LOC = AB2; +NET flash_addr[3] LOC = AB1; +NET flash_addr[2] LOC = AA1; +NET flash_addr[1] LOC = Y2; +NET flash_addr[0] LOC = Y1; +#NET flash_addr[0] LOC = T20; + +NET flash_data[15] LOC = AA14; +NET flash_data[14] LOC = AB14; +NET flash_data[13] LOC = AC12; +NET flash_data[12] LOC = AC11; +NET flash_data[11] LOC = AA16; +NET flash_data[10] LOC = AA15; +NET flash_data[9] LOC = AB13; +NET flash_data[8] LOC = AA13; +NET flash_data[7] LOC = AC14; +NET flash_data[6] LOC = AD14; +NET flash_data[5] LOC = AA12; +NET flash_data[4] LOC = AA11; +NET flash_data[3] LOC = AC16; +NET flash_data[2] LOC = AC15; +NET flash_data[1] LOC = AC13; +NET flash_data[0] LOC = AD13; + +NET flash_oe_n LOC = AC6; +NET flash_we_n LOC = AB6; +#NET flash_byte_n LOC = N22; +NET flash_ce2 LOC = W7; +#NET flash_audio_reset_n LOC = AD10; Index: trunk/boards/virtex4-ml403ep/test/ml403-sram.ucf =================================================================== --- trunk/boards/virtex4-ml403ep/test/ml403-sram.ucf (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/ml403-sram.ucf (revision 54) @@ -0,0 +1,146 @@ +NET sys_clk_in TNM_NET = "sys_clk_in"; +TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; + +NET sys_clk_in LOC = AE14; +NET sys_clk_in IOSTANDARD = LVCMOS33; +#NET sys_rst_in LOC = D6; +#NET sys_rst_in PULLUP; +#NET sys_rst_in TIG; + +NET trx LOC = W1; +#NET trx IOSTANDARD = LVCMOS33; +#NET trx TIG; + +# GPLED 0-3 +#NET gpio[0] LOC = G5; #GPLED0 +#NET gpio[1] LOC = G6; #GPLED1 +#NET gpio[2] LOC = A11; #GPLED2 +#NET gpio[3] LOC = A12; #GPLED3 +# North-East-South-West-Center LEDs +#NET gpio[4] LOC = C6; # C LED +#NET gpio[5] LOC = F9; # W LED +#NET gpio[6] LOC = A5; # S LED +#NET gpio[7] LOC = E10; # E LED +#NET gpio[8] LOC = E2; # N LED + +#NET "gpio[*]" PULLDOWN; +#NET "gpio[*]" TIG; +#NET "gpio[*]" SLEW = SLOW; +#NET "gpio[*]" DRIVE = 2; + +NET "sram_clk" LOC = "AF7" ; #| IOSTANDARD = LVCMOS33 | DRIVE = 16 | SLEW = FAST; +NET "flash_ce" LOC = "W7" ; #| IOSTANDARD = LVDCI_33; + +#NET sram_clk_fb LOC = AD17; +#NET flash_a23 LOC = T21; +#NET sram_flash_addr[22] LOC = U20; +#NET sram_flash_addr[21] LOC = T19; +NET sram_flash_addr[20] LOC = AC5; +NET sram_flash_addr[19] LOC = AB5; +NET sram_flash_addr[18] LOC = AC4; +NET sram_flash_addr[17] LOC = AB4; + +NET sram_flash_addr[16] LOC = AB3; +NET sram_flash_addr[15] LOC = AA4; +NET sram_flash_addr[14] LOC = AA3; +NET sram_flash_addr[13] LOC = W5; +NET sram_flash_addr[12] LOC = W6; +NET sram_flash_addr[11] LOC = W3; +NET sram_flash_addr[10] LOC = AF3; +NET sram_flash_addr[9] LOC = AE3; +NET sram_flash_addr[8] LOC = AD2; +NET sram_flash_addr[7] LOC = AD1; +NET sram_flash_addr[6] LOC = AC2; +NET sram_flash_addr[5] LOC = AC1; +NET sram_flash_addr[4] LOC = AB2; +NET sram_flash_addr[3] LOC = AB1; +NET sram_flash_addr[2] LOC = AA1; +NET sram_flash_addr[1] LOC = Y2; +NET sram_flash_addr[0] LOC = Y1; +#NET sram_flash_data[31] LOC = F14; +#NET sram_flash_data[30] LOC = F13; +#NET sram_flash_data[29] LOC = F12; +#NET sram_flash_data[28] LOC = F11; +#NET sram_flash_data[27] LOC = F16; +#NET sram_flash_data[26] LOC = F15; +#NET sram_flash_data[25] LOC = D14; +#NET sram_flash_data[24] LOC = D13; +#NET sram_flash_data[23] LOC = D15; +#NET sram_flash_data[22] LOC = E14; +#NET sram_flash_data[21] LOC = C11; +#NET sram_flash_data[20] LOC = D11; +#NET sram_flash_data[19] LOC = D16; +#NET sram_flash_data[18] LOC = C16; +#NET sram_flash_data[17] LOC = E13; + +#NET sram_flash_data[16] LOC = D12; +#NET sram_flash_data[15] LOC = AA14; +#NET sram_flash_data[14] LOC = AB14; +#NET sram_flash_data[13] LOC = AC12; +#NET sram_flash_data[12] LOC = AC11; +#NET sram_flash_data[11] LOC = AA16; +#NET sram_flash_data[10] LOC = AA15; +#NET sram_flash_data[9] LOC = AB13; + +NET sram_flash_data[15] LOC = AA14; +NET sram_flash_data[14] LOC = AB14; +NET sram_flash_data[13] LOC = AC12; +NET sram_flash_data[12] LOC = AC11; +NET sram_flash_data[11] LOC = AA16; +NET sram_flash_data[10] LOC = AA15; +NET sram_flash_data[9] LOC = AB13; + +NET sram_flash_data[8] LOC = AA13; +NET sram_flash_data[7] LOC = AC14; +NET sram_flash_data[6] LOC = AD14; +NET sram_flash_data[5] LOC = AA12; +NET sram_flash_data[4] LOC = AA11; +NET sram_flash_data[3] LOC = AC16; +NET sram_flash_data[2] LOC = AC15; +NET sram_flash_data[1] LOC = AC13; +NET sram_flash_data[0] LOC = AD13; +NET sram_cen LOC = V7; +NET sram_flash_oe_n LOC = AC6; +NET sram_flash_we_n LOC = AB6; +NET sram_bw[3] LOC = Y3; #Y4; +NET sram_bw[2] LOC = Y4; #Y3; +NET sram_bw[1] LOC = Y5; #Y6; +NET sram_bw[0] LOC = Y6; #Y5; +#NET sram_adv_ld_n LOC = W4; +#NET sram_mode LOC = V26; + +#NET sram_clk_fb IOSTANDARD = LVCMOS33; + +#NET flash_a23 IOSTANDARD = LVDCI_33; +#NET sram_mode IOSTANDARD = LVDCI_33; + +#NET sram_flash_addr[*] IOSTANDARD = LVDCI_33; +#NET sram_flash_addr[*] SLEW = FAST; +#NET sram_flash_addr[*] DRIVE = 8; + +#NET sram_flash_data[*] IOSTANDARD = LVCMOS33; +#NET sram_flash_data[*] DRIVE = 12; +#NET sram_flash_data[*] SLEW = FAST; +#NET sram_flash_data[*] PULLDOWN; + +#NET sram_flash_oe_n IOSTANDARD = LVDCI_33; +#NET sram_flash_oe_n SLEW = FAST; +#NET sram_flash_oe_n DRIVE = 8; + +#NET sram_flash_we_n IOSTANDARD = LVDCI_33; +#NET sram_flash_we_n SLEW = FAST; +#NET sram_flash_we_n DRIVE = 8; + +#NET sram_bw[*] IOSTANDARD = LVDCI_33; +#NET sram_bw[*] SLEW = FAST; +#NET sram_bw[*] DRIVE = 8; + +#NET flash_ce SLEW = FAST; +#NET flash_ce DRIVE = 8; + +#NET sram_cen SLEW = FAST; +#NET sram_cen DRIVE = 8; + +#NET sram_adv_ld_n IOSTANDARD = LVDCI_33; +#NET sram_adv_ld_n SLEW = FAST; +#NET sram_adv_ld_n DRIVE = 8; Index: trunk/boards/virtex4-ml403ep/test/sram_dump.v =================================================================== --- trunk/boards/virtex4-ml403ep/test/sram_dump.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/sram_dump.v (revision 54) @@ -0,0 +1,157 @@ +`define HIGH_RAM 13'h00fd + +module sram_dump ( + input sys_clk_in, + output trx, + + output sram_clk, + output [20:0] sram_flash_addr, + inout [15:0] sram_flash_data, + output [ 3:0] sram_bw, + + output sram_cen, + output sram_flash_oe_n, + output sram_flash_we_n, + output flash_ce + ); + + reg clk_9600; + reg [11:0] count_uart; + reg [ 6:0] dada_wr; + reg [ 7:0] estat; + reg [ 7:0] addr; + reg [ 2:0] espacios; + reg [ 6:0] char; + reg [ 3:0] nibble; + reg [ 7:0] col; + reg trx_req; + reg [ 8:0] adr0; + + wire clk_60M; + wire rst, lock; + wire trx_ack; + wire [15:0] rd_data; + + reg [15:0] ram[0:255]; + reg [15:0] dades; + + reg [ 3:0] count; + + // Instanciacions de mòduls + clocks c0 ( + .CLKIN_IN (sys_clk_in), + .CLKFX_OUT (clk_60M), + .LOCKED_OUT (lock) + ); + + uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx, + rst, clk_9600); + + // Assignacions contínues + assign rst = ~lock; + + assign sram_clk = clk_60M; + assign sram_flash_addr = { `HIGH_RAM, adr0[7:0] }; + assign rd_data = sram_flash_data; + assign sram_bw = 4'b00; + //assign SRAM_ADV_LB = 1'b0; + assign sram_cen = 1'b0; + assign sram_flash_oe_n = 1'b0; + assign sram_flash_we_n = 1'b1; + assign flash_ce = 1'b0; + + // Descripció del comportament + // count_uart + always @(posedge clk_60M) + if (rst) count_uart <= 12'h0; + else count_uart <= (count_uart==12'd3124) ? + 12'd0 : count_uart + 12'd1; + + // clk_9600 + always @(posedge clk_60M) + if (rst) clk_9600 <= 1'b0; + else clk_9600 <= (count_uart==12'd0) ? + !clk_9600 : clk_9600; + + // adr0 + always @(posedge clk_60M) + if (rst) adr0 <= 9'h000; + else adr0 <= (adr0==9'h1ff || count!=4'hf) ? adr0 + : (adr0 + 8'h01); + // count + always @(posedge clk_60M) + if (rst) count <= 4'h0; + else count <= count + 4'h1; + + // ram + always @(posedge clk_60M) ram[adr0] <= rd_data; + + // dades + always @(posedge clk_60M) + if (rst) dades <= 16'h0; + else dades <= ram[addr]; + + always @(posedge clk_60M) + if (adr0!=9'h1ff) + begin + dada_wr <= 7'h30; + trx_req <= 0; + estat <= 8'd0; + addr <= 8'h00; + espacios <= 3'd2; + char <= 7'd00; + nibble <= 4'd0; + col <= 8'd79; + end + else + case (estat) + 8'd00: if (~trx_ack) + begin estat <= 8'd01; + if (espacios > 3'd0) + begin char <= 7'h20; espacios <= espacios - 3'd1; end + else + begin + char <= ascii(nibble); espacios <= 3'd4; + nibble <= nibble + 4'd1; + end + end + 8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end + 8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end + 8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end + else estat <= 8'd04; + + 8'd04: if (~trx_ack) estat <= 8'd05; + 8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end + 8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end + + 8'd15: if (~trx_ack) estat <= 8'd20; + 8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end + 8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end + + 8'd30: if (~trx_ack) estat <= 8'd35; + 8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end + 8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end + + 8'd45: if (~trx_ack) estat <= 8'd50; + 8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end + 8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end + + 8'd60: if (~trx_ack) estat <= 8'd65; + 8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end + 8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end + + 8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90; + else if (~trx_ack) estat <= 8'd80; + 8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end + 8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end + + 8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end + else estat <= 8'd95; + 8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15; + endcase + + function [6:0] ascii(input [3:0] num); + if (num <= 4'd9) ascii = 7'h30 + num; + else ascii = 7'd87 + num; + endfunction +endmodule Index: trunk/boards/virtex4-ml403ep/test/clocks.xaw =================================================================== --- trunk/boards/virtex4-ml403ep/test/clocks.xaw (nonexistent) +++ trunk/boards/virtex4-ml403ep/test/clocks.xaw (revision 54) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$8;x77=(`fgn#wkzs.reg*vugox#ugcioz,p`usW|kyx"!llnahw+~f81;96>!0026?5(6?=;0=;5>0/2346=68980=;6417%kB5@7:2;S=6=<;5,;5>3030$9"=GU_SUDBAWPCMIJJZC_\LXEMA?:;@PT^ZIIDPUH@FGA_WCOQ@7e3HX\VRAALX]GGHYT_@^HDD@H_BNH55=FZ^PTCCBV_EFQ[F6682KY[WQ@NM[\@ATXK8;:7L\XZ^MMH\YCL[UH@F?9;@PT^ZIIDPUOH_QJDFGNKAC6>2KY[WQ@NM[\@ATXNEC[JAA_139BVR\XGGFRSIJ]_HLJP415:CQS_YHFESTJOQJXUGQJDJ6:2KY[WQ@NM[\MKUSWG_F=h5NRVX\KKJ^WCC_XH\PPJ0SOZHHFFCXIGPRVIGGRAZTQWW[Q_WMj1J[WQILNUW]UC?3H]QS]O]Te9BS_YTQG^CXBAC4:@LPM2EKCOR37NBDFY3;4<=DDBLSSO[If:AOOC^XJ\LLSD@\Tb9@HN@_WMC]EIKj;BNHB]YJ]E^B\AW6;BNHB]YH]]?0OAEFN038GIMNFVNBZDJJ_C[\6g=DDBCESDLZFF33?FJLAGUBNXHH_HLPPc=DDBCESDLZFF]LQQ>4:F@IZVBZOEYAL@LE^OL@@52:FOHZ@UMX_NBNWPMNFF6>BH<2NYHT?:;EWW]ZE^KEOTOB\]EBVJKK5C_\LXEMAo4F@AWKW_XBO?0JLB\E89EFZUH][INo6HJEE@BGNYE]O30JD@PUOKWWd=AG\^TYCG[S`9EKPRX^HF^I<5F5:KAQCA?3@D_I_@NL038NLRSM[UBB][[_U[SA3=KGHNNH;5COBIF@d=KGJANHRAZT29OKR?;N68KABU02E[\B]FTD`8TMGTMVYCEKZ6;QKMLDUE]Zk0\D@FSFLGAA>VTLFDN86^\EO:8TVOIKMOH?6\\Tc9PMBC_\LXEMA84SHLDH@e<[]KYXX^PW@KWf>U^FJBYCCAZS008W\USMDUXUCMGRNLLQV5<\FZ?7Y\ZE99VW@YE]OM27X]J_CWECV3<^@O\=o5WAV]UAWUNGG;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@90T^Z9;Yfa[Lb682RoaRCnjnpUawungg;;7Ujb_LkmkwPbzzcdb85T0;2^2>]728?V96U?:7_7?dtpr:1oo`l4vdppmjh'9':?7{fkl028|f2qnq;9!<5F;695~U3i33?648512051`0=:h93;v`7f;38j<6=<2.3i76l;|Q7=??320<1=><95d496d5cn2Y=477;:8495641=l<1>ll:f:Q7=??320<1=><95d496a36:2n287>51;3xW1g=1=02:7?<277f2?4f;1=0zY6n:182>4<>sZ>j64:597827702m?09m>68;c:5>5<72=02w)k5949'63<>?2.9;777;%0;>=b<,1h1h6l;e;295=<729q/;l4;d:&e>62<,8:14?5+1381f>"6i3297)?m:59'52<0<2.:?77`<,8?1>o5+17841>"603;0(<75859'5`<2m2.:j7;j;%03>0c<,=2156*<5;58 6e=k2.8h7o4$5291`=#<<0>7):9:4a8 11=?81/8k477:&64?0d3-?965;4$4192g=#=?0=n6*:9;:4?!3e2j1/9i47;%7e>30<,?;1:i5+63846>"1;3h0(;956d9'2c"?03227)?>:79'60<2=2.9=7<6;%3g>7=#9j087d=i:18'3<<>92.315<5+7c8;3>=n=0>1/;:477:9j11<72-=264<4$6:9<2=#?>03;65f5`83>!1>20;0(:658698m07=83.<577>;%5;>=1<3`>h6=4+788:5>"0032<76g70;29 2?=181/;5477:9j3`<72-=264?4$6:9<2=l1<7*89;;2?!1?21=07d9l:18'3<<>92.<4768;:m1f?6=,>315<5+7c8;3>"5;38j7)<;:728?j54290/;4461:9l6c<72-=264?4;n13>5<#?002=65`3583>!1>20;0(?=52`98k67=83.<577>;:m06?6=,>315<54o2:94?"0133:7)9m:958 75=:h10c>750;&4=??632e>47>5$6;9=4=92.315<54}c61>5<5290;w)9n:778m32=83.<577>;%5a>=1<3f=86=4+788:5>"0j32<76sm2e83>7<729q/;l4=a:k50?6=,>315<5+7c8;3>=h?:0;6)96:838 2d=0>10qo=m:181>5<7s-=j6?o4i7694?"0133:7)9m:958?j14290/;4461:&4f?>032wx8<4?:3y>0`<4n27?>79<;%01>1560<5;n1;>5+2381a>{t:j0;6?u24d81f>;5l3=1/4<494:p7`<728q6?o483:&;5?143ty??7>50z&;5?143ty9i7>50z&;5?143twe>n4?:0y~j7b=83;pqc4}zf:;1<7?t}o11>5<6std8?7>51zm71<728qvqpsO@By0a?`e<>>i=osO@Cy3yEFWstJK \ No newline at end of file Index: trunk/boards/virtex4-ml403ep/syn/clock.v =================================================================== --- trunk/boards/virtex4-ml403ep/syn/clock.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/clock.v (revision 54) @@ -0,0 +1,87 @@ +module clock #( + parameter div = 16 // main clock divider + ) ( + input sys_clk_in_, + output clk, + output clk_100M, + output vdu_clk, + output rst + ); + + // Register declarations + reg [6:0] count; + + // Net declarations + wire ref_clk; + wire ref_clk0; + wire lock; + wire vdu_lock; + wire fpga_lock; + wire vdu_clk0; + wire fpga_fb; + wire fpga_fb0; + wire fpga_clk0; + + // Module instantiations + IBUFG ref_buf ( + .O (ref_clk), + .I (sys_clk_in_) + ); + + // DCM for the VGA - 25 Mhz + DCM_ADV vdu_dcm ( + .CLKIN (ref_clk), + .CLKFB (clk_100M), + .CLK0 (ref_clk0), + .CLKDV (vdu_clk0), + .RST (1'b0), + .LOCKED (vdu_lock) + ); + defparam vdu_dcm.CLKIN_PERIOD = 10.000; + defparam vdu_dcm.CLKDV_DIVIDE = 4; + defparam vdu_dcm.DCM_AUTOCALIBRATION = "FALSE"; + + BUFG b_clk_100M ( + .O (clk_100M), + .I (ref_clk0) + ); + + BUFG b_vdu_clk ( + .O (vdu_clk), + .I (vdu_clk0) + ); + + // fpga DCM + DCM_ADV fpga_dcm ( + .CLKIN (ref_clk), + .CLKFB (fpga_fb), + .CLK0 (fpga_fb0), + .CLKDV (fpga_clk0), + .RST (1'b0), + .LOCKED (fpga_lock) + ); + defparam fpga_dcm.CLKIN_PERIOD = 10.000; + defparam fpga_dcm.CLKDV_DIVIDE = div; + defparam fpga_dcm.DCM_AUTOCALIBRATION = "FALSE"; + + BUFG b_fpga_fb ( + .O (fpga_fb), + .I (fpga_fb0) + ); + + BUFG b_fpga_clk ( + .O (clk), + .I (fpga_clk0) + ); + + // Continuous assignments + assign rst = (count!=7'h7f); + assign lock = vdu_lock & fpga_lock; + + // Behavioral description + // count + always @(posedge clk) + if (!lock) count <= 7'b0; + else count <= (count==7'h7f) ? count : (count + 7'h1); + +endmodule Index: trunk/boards/virtex4-ml403ep/syn/kotku-dbg.prj =================================================================== --- trunk/boards/virtex4-ml403ep/syn/kotku-dbg.prj (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/kotku-dbg.prj (revision 54) @@ -0,0 +1,32 @@ +verilog work "../../../../rtl-model/util/div_uu.v" +verilog work "../../../../rtl-model/util/primitives.v" +verilog work "../../../../rtl-model/util/div_su.v" +verilog work "../../../../rtl-model/rotate.v" +verilog work "mult.v" +verilog work "icon.v" +verilog work "ila.v" +verilog work "../../../../rtl-model/regfile.v" +verilog work "../../../../rtl-model/jmp_cond.v" +verilog work "../../../../rtl-model/alu.v" +verilog work "../../../../soc/vga/rtl/ram2k_b16_attr.v" +verilog work "../../../../soc/vga/rtl/ram2k_b16.v" +verilog work "../../../../soc/vga/rtl/char_rom_b16.v" +verilog work "../../../../rtl-model/fetch.v" +verilog work "../../../../rtl-model/exec.v" +verilog work "../../../../soc/vga/rtl/vdu.v" +verilog work "../../../../soc/keyb/rtl/ps2_keyb.v" +verilog work "../../../../soc/aceusb/rtl/aceusb_access.v" +verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v" +verilog work "../../../../soc/aceusb/rtl/aceusb.v" +verilog work "../../../../soc/timer.v" +verilog work "../../../../rtl-model/cpu.v" +verilog work "../../mem/zbt_cntrl.v" +verilog work "../../mem/flash_cntrl.v" +verilog work "../../dbg/hw_dbg.v" +verilog work "../../dbg/send_serial.v" +verilog work "../../dbg/send_addr.v" +verilog work "../../dbg/pc_trace.v" +verilog work "../../dbg/clk_uart.v" +verilog work "../clock.v" +verilog work "../kotku.v" +verilog work "../../lcd/lcd_display.v" \ No newline at end of file Index: trunk/boards/virtex4-ml403ep/syn/kotku.v =================================================================== --- trunk/boards/virtex4-ml403ep/syn/kotku.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/kotku.v (revision 54) @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2008 Zeus Gomez Marmolejo + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +`timescale 1ns/10ps +`include "defines.v" + +module kotku_ml403 ( +`ifdef DEBUG + (* LOC="B6" *) input butc_, + (* LOC="F10" *) input bute_, + (* LOC="E9" *) input butw_, + (* LOC="E7" *) input butn_, + (* LOC="A6" *) input buts_, +`endif + output rs_, + output rw_, + output e_, + output [ 7:4] db_, + + output trx_, + + output tft_lcd_clk_, + output [ 1:0] tft_lcd_r_, + output [ 1:0] tft_lcd_g_, + output [ 1:0] tft_lcd_b_, + output tft_lcd_hsync_, + output tft_lcd_vsync_, + + input sys_clk_in_, + + output sram_clk_, + output [20:0] sram_flash_addr_, + inout [31:0] sram_flash_data_, + output sram_flash_oe_n_, + output sram_flash_we_n_, + output [ 3:0] sram_bw_, + output sram_cen_, + output sram_adv_ld_n_, + output flash_ce2_, + + inout ps2_clk_, + inout ps2_data_, + + output [ 6:1] aceusb_a_, + inout [15:0] aceusb_d_, + output aceusb_oe_n_, + output aceusb_we_n_, + + input ace_clkin_, + output ace_mpce_n_, + + output usb_cs_n_, + output usb_hpi_reset_n_ + ); + + // Net declarations + wire clk; + wire sys_clk; + wire rst2; + wire rst_lck; + wire [15:0] dat_i; + wire [15:0] dat_o; + wire [19:1] adr; + wire we; + wire tga; + wire stb; + wire ack; + wire [15:0] io_dat_i; + wire [ 1:0] sel; + wire cyc; + wire [ 7:0] keyb_dat_o; + wire keyb_io_arena; + wire keyb_io_status; + wire keyb_arena; + + wire [15:0] vdu_dat_o; + wire vdu_ack_o; + wire vdu_mem_arena; + wire vdu_io_arena; + wire vdu_arena; + wire [15:0] flash_dat_o; + wire flash_stb; + wire flash_ack; + wire flash_mem_arena; + wire flash_io_arena; + wire flash_arena; + wire [15:0] zbt_dat_o; + wire zbt_stb; + wire zbt_ack; + wire [20:0] flash_addr_; + wire [20:0] sram_addr_; + wire flash_we_n_; + wire sram_we_n_; + wire intr; + wire inta; + wire clk_100M; + wire rst; + wire [15:0] vdu_dat_i; + wire [11:1] vdu_adr_i; + wire vdu_we_i; + wire [ 1:0] vdu_sel_i; + wire vdu_stb_i; + wire vdu_tga_i; + + wire [19:1] zbt_adr_i; + wire zbt_we_i; + wire [ 1:0] zbt_sel_i; + wire zbt_stb_i; + + wire [15:0] ace_dat_o; + wire ace_ack; + wire ace_stb; + wire ace_io_arena; + wire ace_arena; + + wire [ 1:0] int; + wire iid; + +`ifdef DEBUG + reg [31:0] cnt_time; + wire [35:0] control0; + wire [ 5:0] funct; + wire [ 2:0] state, next_state; + wire [15:0] x, y; + wire [15:0] imm; + wire [63:0] f1, f2; + wire [15:0] m1, m2; + wire [19:0] pc; + wire [15:0] cs, ip; + wire [15:0] aluo; + wire [ 2:0] cnt; + wire op; + wire block; + wire cpu_block; + wire clk_921600; + wire [15:0] ax, dx, bp, si, es; + wire [15:0] c; + wire [ 3:0] addr_c; + wire [15:0] cpu_dat_o; + wire [15:0] d; + wire [ 3:0] addr_d; + wire byte_op; + wire [ 8:0] flags; + + wire [15:0] dbg_vdu_dat_o; + wire [11:1] dbg_vdu_adr_o; + wire dbg_vdu_we_o; + wire dbg_vdu_stb_o; + wire [ 1:0] dbg_vdu_sel_o; + wire dbg_vdu_tga_o; + + wire [19:1] dbg_zbt_adr_o; + wire dbg_zbt_we_o; + wire [ 1:0] dbg_zbt_sel_o; + wire dbg_zbt_stb_o; + + wire [ 2:0] old_zet_st; + wire [ 4:0] pack; + wire [19:0] tr_dat; + wire tr_new_pc; + wire tr_st; + wire tr_stb; + wire tr_ack; + wire addr_st; + + wire end_seq; + wire ext_int; + wire cpu_block2; + + wire [ 1:0] irr; + + wire rx_output_strobe; + wire rx_shifting_done; + wire released; +`endif + + // Register declarations + reg [15:0] io_reg; + reg [ 1:0] vdu_stb_sync; + reg [ 1:0] vdu_ack_sync; + + // Module instantiations + clock #( + .div (8) + ) c0 ( + .clk_100M (clk_100M), + .sys_clk_in_ (sys_clk_in_), + .clk (sys_clk), + .vdu_clk (tft_lcd_clk_), + .rst (rst_lck) + ); + + vdu vdu0 ( + // Wishbone signals + .wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock + .wb_rst_i (rst2), + .wb_dat_i (vdu_dat_i), + .wb_dat_o (vdu_dat_o), + .wb_adr_i (vdu_adr_i), + .wb_we_i (vdu_we_i), + .wb_tga_i (vdu_tga_i), + .wb_sel_i (vdu_sel_i), + .wb_stb_i (vdu_stb_i), + .wb_cyc_i (vdu_stb_i), + .wb_ack_o (vdu_ack_o), + + // VGA pad signals + .vga_red_o (tft_lcd_r_), + .vga_green_o (tft_lcd_g_), + .vga_blue_o (tft_lcd_b_), + .horiz_sync (tft_lcd_hsync_), + .vert_sync (tft_lcd_vsync_) + ); + + flash_cntrl #( + .timeout (4) + ) fc0 ( + // Wishbone slave interface + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_dat_i (dat_o), + .wb_dat_o (flash_dat_o), + .wb_adr_i (adr[16:1]), + .wb_we_i (we), + .wb_tga_i (tga), + .wb_stb_i (flash_stb), + .wb_cyc_i (flash_stb), + .wb_ack_o (flash_ack), + + // Pad signals + .flash_addr_ (flash_addr_), + .flash_data_ (sram_flash_data_[15:0]), + .flash_we_n_ (flash_we_n_), + .flash_ce2_ (flash_ce2_) + ); + + zbt_cntrl zbt0 ( +`ifdef DEBUG + .cnt (cnt), + .op (op), +`endif + .wb_clk_i (clk), + .wb_rst_i (rst2), + .wb_dat_i (dat_o), + .wb_dat_o (zbt_dat_o), + .wb_adr_i (zbt_adr_i), + .wb_we_i (zbt_we_i), + .wb_sel_i (zbt_sel_i), + .wb_stb_i (zbt_stb_i), + .wb_cyc_i (zbt_stb_i), + .wb_ack_o (zbt_ack), + + // Pad signals + .sram_clk_ (sram_clk_), + .sram_addr_ (sram_addr_), + .sram_data_ (sram_flash_data_), + .sram_we_n_ (sram_we_n_), + .sram_bw_ (sram_bw_), + .sram_cen_ (sram_cen_), + .sram_adv_ld_n_ (sram_adv_ld_n_) + ); + + ps2_keyb #(1500, // number of clks for 60usec. + 11, // number of bits needed for 60usec. timer + 120, // number of clks for debounce + 7 // number of bits needed for debounce timer + ) keyboard0 ( // Instance name +`ifdef DEBUG + .rx_output_strobe (rx_output_strobe), + .rx_shifting_done (rx_shifting_done), + .released (released), +`endif + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_dat_o (keyb_dat_o), + .wb_tgc_o (int[1]), + + .ps2_clk_ (ps2_clk_), + .ps2_data_ (ps2_data_) + ); + + timer #( + .res (34), + .phase (12507) + ) timer0 ( + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_tgc_o (int[0]) + ); + + simple_pic pic0 ( +`ifdef DEBUG + .irr (irr), +`endif + .clk (clk), + .rst (rst), + .int (int), + .inta (inta), + .intr (intr), + .iid (iid) + ); + + aceusb ace_cf ( + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_adr_i (adr[6:1]), + .wb_dat_i (dat_o), + .wb_dat_o (ace_dat_o), + .wb_cyc_i (ace_stb), + .wb_stb_i (ace_stb), + .wb_we_i (we), + .wb_ack_o (ace_ack), + + .aceusb_a_ (aceusb_a_), + .aceusb_d_ (aceusb_d_), + .aceusb_oe_n_ (aceusb_oe_n_), + .aceusb_we_n_ (aceusb_we_n_), + + .ace_clkin_ (ace_clkin_), + .ace_mpce_n_ (ace_mpce_n_), + + .usb_cs_n_ (usb_cs_n_), + .usb_hpi_reset_n_ (usb_hpi_reset_n_) + ); + + cpu zet_proc ( +`ifdef DEBUG + .cs (cs), + .ip (ip), + .state (state), + .next_state (next_state), + .iralu (funct), + .x (x), + .y (y), + .imm (imm), + .aluo (aluo), + .ax (ax), + .dx (dx), + .bp (bp), + .si (si), + .es (es), + .dbg_block (cpu_block), + .c (c), + .addr_c (addr_c), + .cpu_dat_o (cpu_dat_o), + .d (d), + .byte_exec (byte_op), + .addr_d (addr_d), + .flags (flags), + .end_seq (end_seq), + .ext_int (ext_int), + .cpu_block (cpu_block2), +`endif + + // Wishbone master interface + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_dat_i (dat_i), + .wb_dat_o (dat_o), + .wb_adr_o (adr), + .wb_we_o (we), + .wb_tga_o (tga), + .wb_sel_o (sel), + .wb_stb_o (stb), + .wb_cyc_o (cyc), + .wb_ack_i (ack), + .wb_tgc_i (intr), + .wb_tgc_o (inta) + ); + +`ifdef DEBUG + // Module instantiations + + icon icon0 ( + .CONTROL0 (control0) + ); + + ila ila0 ( + .CONTROL (control0), + .CLK (clk), + .TRIG0 (adr), + .TRIG1 ({dat_o,dat_i}), + .TRIG2 (pc), + .TRIG3 ({clk,we,tga,cyc,stb,ack}), + .TRIG4 (funct), + .TRIG5 ({state,next_state}), + .TRIG6 ({intr,inta,flags,byte_op,addr_d}), + .TRIG7 (d), + .TRIG8 ({x,y}), + .TRIG9 (aluo), + .TRIG10 ({ace_mpce_n_,aceusb_we_n_,aceusb_oe_n_, + ace_ack,ace_stb,ace_dat_o}), + .TRIG11 (aceusb_d_), + .TRIG12 ({1'b0,rx_output_strobe,rx_shifting_done,released,int,irr,iid}), + .TRIG13 (cnt), + .TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}), + .TRIG15 (cnt_time) + ); + + lcd_display lcd0 ( + .f1 (f1), // 1st row + .f2 (f2), // 2nd row + .m1 (m1), // 1st row mask + .m2 (m2), // 2nd row mask + + .clk (clk_100M), // 100 Mhz clock + .rst (rst_lck), + + // Pad signals + .lcd_rs_ (rs_), + .lcd_rw_ (rw_), + .lcd_e_ (e_), + .lcd_dat_ (db_) + ); + + hw_dbg dbg0 ( + .clk (clk), + .rst_lck (rst_lck), + .rst (rst), + .butc_ (butc_), + .bute_ (bute_), + .butw_ (butw_), + .butn_ (butn_), + .buts_ (buts_), + + .vdu_dat_o (dbg_vdu_dat_o), + .vdu_adr_o (dbg_vdu_adr_o), + .vdu_we_o (dbg_vdu_we_o), + .vdu_stb_o (dbg_vdu_stb_o), + .vdu_sel_o (dbg_vdu_sel_o), + .vdu_tga_o (dbg_vdu_tga_o), + .vdu_ack_i (vdu_ack_sync[1]), + + .zbt_dat_i (zbt_dat_o), + .zbt_adr_o (dbg_zbt_adr_o), + .zbt_we_o (dbg_zbt_we_o), + .zbt_sel_o (dbg_zbt_sel_o), + .zbt_stb_o (dbg_zbt_stb_o), + .zbt_ack_i (zbt_ack) + ); + + clk_uart clk0 ( + .clk_100M (clk_100M), + .rst (rst_lck), + .clk_921600 (clk_921600), + .rst2 (rst2) + ); + + pc_trace pc0 ( + .old_zet_st (old_zet_st), + + .dat (tr_dat), + .new_pc (tr_new_pc), + .st (tr_st), + .stb (tr_stb), + .ack (tr_ack), + .pack (pack), + .addr_st (addr_st), + .trx_ (trx_), + + .clk (clk), + .rst (rst2), + .pc (pc), + .zet_st (state), + .block (block) + ); + + // Continuous assignments + assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 }; + assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc }; + assign m1 = 16'b1011110111101010; + assign m2 = 16'b1111101110011111; + + assign pc = (cs << 4) + ip; + + assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o; + assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1]; + assign vdu_we_i = rst ? dbg_vdu_we_o : we; + assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel; + assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena; + assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga; + assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr; + assign zbt_we_i = rst ? dbg_zbt_we_o : we; + assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel; + assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb; +`ifdef DEBUG_TRACE + assign cpu_block = block; +`else + assign cpu_block = 1'b0; +`endif +`else + assign vdu_dat_i = dat_o; + assign vdu_adr_i = adr[11:1]; + assign vdu_we_i = we; + assign vdu_sel_i = sel; + assign vdu_stb_i = stb & cyc & vdu_arena; + assign vdu_tga_i = tga; + assign zbt_adr_i = adr; + assign zbt_we_i = we; + assign zbt_sel_i = sel; + assign zbt_stb_i = zbt_stb; + assign rst2 = rst_lck; + + assign rs_ = 1'b1; + assign e_ = 1'b0; + assign rw_ = 1'b1; + assign db_ = 4'h0; + assign trx_ = 1'b1; +`endif + +`ifdef DEBUG_TRACE + assign clk = clk_921600; +`else +// assign clk = sys_clk; + assign clk = tft_lcd_clk_; +`endif + + assign io_dat_i = flash_io_arena ? flash_dat_o + : (vdu_io_arena ? vdu_dat_o + : (keyb_io_arena ? keyb_dat_o + : (keyb_io_status ? 16'h10 + : (ace_io_arena ? ace_dat_o : 16'h0)))); + assign dat_i = inta ? { 15'b0000_0000_0000_100, iid } + : (tga ? io_dat_i + : (vdu_mem_arena ? vdu_dat_o + : (flash_mem_arena ? flash_dat_o : zbt_dat_o))); + + assign flash_mem_arena = (adr[19:16]==4'hc || adr[19:16]==4'hf); + assign vdu_mem_arena = (adr[19:12]==8'hb8); + + assign flash_io_arena = (adr[15:9]==7'b1110_000); + assign vdu_io_arena = (adr[15:4]==12'h03d) && + ((adr[3:1]==3'h2 && we) + || (adr[3:1]==3'h5 && !we)); + + assign keyb_io_arena = (adr[15:1]==15'h0030 && !we); + assign ace_io_arena = (adr[15:7]==9'b1110_0010_0); + + // MS-DOS is reading IO address 0x64 to check the inhibit bit + assign keyb_io_status = (adr[15:1]==15'h0032 && !we); + + assign flash_arena = (!tga & flash_mem_arena) + | (tga & flash_io_arena); + assign vdu_arena = (!tga & vdu_mem_arena) + | (tga & vdu_io_arena); + assign keyb_arena = (tga & keyb_io_arena); + assign ace_arena = (tga & ace_io_arena); + + assign flash_stb = flash_arena & stb & cyc; + assign zbt_stb = !vdu_mem_arena & !flash_mem_arena + & !tga & stb & cyc; + assign ace_stb = ace_arena & stb & cyc; + + assign ack = tga ? (flash_io_arena ? flash_ack + : (vdu_io_arena ? vdu_ack_o + : (ace_io_arena ? ace_ack : (stb & cyc)))) + : (vdu_mem_arena ? vdu_ack_o + : (flash_mem_arena ? flash_ack : zbt_ack)); + + assign sram_flash_oe_n_ = 1'b0; + assign sram_flash_addr_ = flash_arena ? flash_addr_ + : sram_addr_; + assign sram_flash_we_n_ = flash_arena ? flash_we_n_ + : sram_we_n_; + + // Behaviour + // vdu_stb_sync[0] + always @(posedge tft_lcd_clk_) + vdu_stb_sync[0] <= vdu_stb_i; + + // vdu_stb_sync[1] + always @(posedge clk) + vdu_stb_sync[1] <= vdu_stb_sync[0]; + + // vdu_ack_sync[0] + always @(posedge clk) vdu_ack_sync[0] <= vdu_ack_o; + + // vdu_ack_sync[1] + always @(posedge clk) vdu_ack_sync[1] <= vdu_ack_sync[0]; + + // io_reg + always @(posedge clk) + io_reg <= rst ? 16'h0 + : ((tga && stb && cyc && we && adr[15:8]==8'hf1) ? + dat_o : io_reg ); + +`ifdef DEBUG + // cnt_time + always @(posedge clk) + cnt_time <= rst ? 32'h0 : (cnt_time + 32'h1); +`else + assign rst = rst_lck; +`endif +endmodule Index: trunk/boards/virtex4-ml403ep/syn/kotku.prj =================================================================== --- trunk/boards/virtex4-ml403ep/syn/kotku.prj (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/kotku.prj (revision 54) @@ -0,0 +1,25 @@ +verilog work "../../../../rtl-model/util/div_uu.v" +verilog work "../../../../rtl-model/util/primitives.v" +verilog work "../../../../rtl-model/util/div_su.v" +verilog work "../../../../rtl-model/rotate.v" +verilog work "mult.v" +verilog work "../../../../rtl-model/regfile.v" +verilog work "../../../../rtl-model/jmp_cond.v" +verilog work "../../../../rtl-model/alu.v" +verilog work "../../../../soc/vga/rtl/ram2k_b16_attr.v" +verilog work "../../../../soc/vga/rtl/ram2k_b16.v" +verilog work "../../../../soc/vga/rtl/char_rom_b16.v" +verilog work "../../../../rtl-model/fetch.v" +verilog work "../../../../rtl-model/exec.v" +verilog work "../../../../soc/vga/rtl/vdu.v" +verilog work "../../../../soc/keyb/rtl/ps2_keyb.v" +verilog work "../../../../soc/aceusb/rtl/aceusb_access.v" +verilog work "../../../../soc/aceusb/rtl/aceusb_sync.v" +verilog work "../../../../soc/aceusb/rtl/aceusb.v" +verilog work "../../../../soc/timer.v" +verilog work "../../../../soc/simple_pic.v" +verilog work "../../../../rtl-model/cpu.v" +verilog work "../../mem/zbt_cntrl.v" +verilog work "../../mem/flash_cntrl.v" +verilog work "../clock.v" +verilog work "../kotku.v" Index: trunk/boards/virtex4-ml403ep/syn/ml403.ucf =================================================================== --- trunk/boards/virtex4-ml403ep/syn/ml403.ucf (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/ml403.ucf (revision 54) @@ -0,0 +1,210 @@ +#NET sys_clk_in_ TNM_NET = "sys_clk_in_"; +#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %; + +NET sys_clk_in_ LOC = AE14; +NET sys_clk_in_ IOSTANDARD = LVCMOS33; + +NET sram_clk_ LOC = AF7 ; +NET "sram_clk_" IOSTANDARD = LVCMOS33; +NET "sram_clk_" DRIVE = 16; +NET "sram_clk_" SLEW = FAST; + +#NET sram_flash_addr_[24] LOC = T21; +#NET sram_flash_addr_[23] LOC = U20; +#NET sram_flash_addr_[22] LOC = T19; +NET sram_flash_addr_[20] LOC = AC5; +NET sram_flash_addr_[19] LOC = AB5; +NET sram_flash_addr_[18] LOC = AC4; +NET sram_flash_addr_[17] LOC = AB4; +NET sram_flash_addr_[16] LOC = AB3; +NET sram_flash_addr_[15] LOC = AA4; +NET sram_flash_addr_[14] LOC = AA3; +NET sram_flash_addr_[13] LOC = W5; +NET sram_flash_addr_[12] LOC = W6; +NET sram_flash_addr_[11] LOC = W3; +NET sram_flash_addr_[10] LOC = AF3; +NET sram_flash_addr_[9] LOC = AE3; +NET sram_flash_addr_[8] LOC = AD2; +NET sram_flash_addr_[7] LOC = AD1; +NET sram_flash_addr_[6] LOC = AC2; +NET sram_flash_addr_[5] LOC = AC1; +NET sram_flash_addr_[4] LOC = AB2; +NET sram_flash_addr_[3] LOC = AB1; +NET sram_flash_addr_[2] LOC = AA1; +NET sram_flash_addr_[1] LOC = Y2; +NET sram_flash_addr_[0] LOC = Y1; +#NET sram_flash_addr_[0] LOC = T20; + +NET "sram_flash_addr_<*>" IOSTANDARD = LVDCI_33; +NET "sram_flash_addr_<*>" SLEW = FAST; +NET "sram_flash_addr_<*>" DRIVE = 8; + +NET sram_flash_data_[31] LOC = F14; +NET sram_flash_data_[30] LOC = F13; +NET sram_flash_data_[29] LOC = F12; +NET sram_flash_data_[28] LOC = F11; +NET sram_flash_data_[27] LOC = F16; +NET sram_flash_data_[26] LOC = F15; +NET sram_flash_data_[25] LOC = D14; +NET sram_flash_data_[24] LOC = D13; +NET sram_flash_data_[23] LOC = D15; +NET sram_flash_data_[22] LOC = E14; +NET sram_flash_data_[21] LOC = C11; +NET sram_flash_data_[20] LOC = D11; +NET sram_flash_data_[19] LOC = D16; +NET sram_flash_data_[18] LOC = C16; +NET sram_flash_data_[17] LOC = E13; +NET sram_flash_data_[16] LOC = D12; +NET sram_flash_data_[15] LOC = AA14; +NET sram_flash_data_[14] LOC = AB14; +NET sram_flash_data_[13] LOC = AC12; +NET sram_flash_data_[12] LOC = AC11; +NET sram_flash_data_[11] LOC = AA16; +NET sram_flash_data_[10] LOC = AA15; +NET sram_flash_data_[9] LOC = AB13; +NET sram_flash_data_[8] LOC = AA13; +NET sram_flash_data_[7] LOC = AC14; +NET sram_flash_data_[6] LOC = AD14; +NET sram_flash_data_[5] LOC = AA12; +NET sram_flash_data_[4] LOC = AA11; +NET sram_flash_data_[3] LOC = AC16; +NET sram_flash_data_[2] LOC = AC15; +NET sram_flash_data_[1] LOC = AC13; +NET sram_flash_data_[0] LOC = AD13; + +NET "sram_flash_data_<*>" IOSTANDARD = LVCMOS33; +NET "sram_flash_data_<*>" PULLDOWN; + +NET sram_flash_oe_n_ LOC = AC6; +NET "sram_flash_oe_n_" IOSTANDARD = LVDCI_33; +NET "sram_flash_oe_n_" SLEW = FAST; +NET "sram_flash_oe_n_" DRIVE = 8; + +NET sram_flash_we_n_ LOC = AB6; +NET "sram_flash_we_n_" IOSTANDARD = LVDCI_33; +NET "sram_flash_we_n_" SLEW = FAST; +NET "sram_flash_we_n_" DRIVE = 8; + +NET sram_bw_[3] LOC = Y3; #Y4; +NET sram_bw_[2] LOC = Y4; #Y3; +NET sram_bw_[1] LOC = Y5; #Y6; +NET sram_bw_[0] LOC = Y6; #Y5; +NET "sram_bw_<*>" IOSTANDARD = LVDCI_33; +NET "sram_bw_<*>" SLEW = FAST; +NET "sram_bw_<*>" DRIVE = 8; + +NET sram_cen_ LOC = V7; +NET "sram_cen_" IOSTANDARD = LVDCI_33; +NET "sram_cen_" SLEW = FAST; +NET "sram_cen_" DRIVE = 8; + +NET sram_adv_ld_n_ LOC = W4; +NET "sram_adv_ld_n_" IOSTANDARD = LVDCI_33; +NET "sram_adv_ld_n_" SLEW = FAST; +NET "sram_adv_ld_n_" DRIVE = 8; + +NET flash_ce2_ LOC = W7; +NET "flash_ce2_" IOSTANDARD = LVDCI_33; +NET "flash_ce2_" SLEW = FAST; +NET "flash_ce2_" DRIVE = 8; + +#NET flash_byte_n LOC = N22; +#NET flash_audio_reset_n LOC = AD10; + +NET tft_lcd_clk_ LOC = AF8 | IOSTANDARD = LVCMOS33; +NET tft_lcd_r_[0] LOC = E5 | SLEW = FAST | DRIVE = 8; # VGA_R6 +NET tft_lcd_r_[1] LOC = E6 | SLEW = FAST | DRIVE = 8; # VGA_R7 +NET tft_lcd_g_[0] LOC = H8 | SLEW = FAST | DRIVE = 8; # VGA_G6 +NET tft_lcd_g_[1] LOC = C1 | SLEW = FAST | DRIVE = 8; # VGA_G7 +NET tft_lcd_b_[0] LOC = G8 | SLEW = FAST | DRIVE = 8; # VGA_B6 +NET tft_lcd_b_[1] LOC = F8 | SLEW = FAST | DRIVE = 8; # VGA_B7 +NET tft_lcd_hsync_ LOC = C10; +NET tft_lcd_vsync_ LOC = A8; + +NET tft_lcd_clk_ SLEW = FAST; +NET tft_lcd_clk_ DRIVE = 8; + +NET tft_lcd_hsync_ SLEW = FAST; +NET tft_lcd_hsync_ DRIVE = 8; + +NET tft_lcd_vsync_ SLEW = FAST; +NET tft_lcd_vsync_ DRIVE = 8; + +NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E +NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS +NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW + +NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7 +NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6 +NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5 +NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4 + +#NET butc_ LOC = B6; # C Button +#NET butw_ LOC = E9; # W Button +#NET bute_ LOC = F10; # E Button +#NET butn_ LOC = E7; # N Button +#NET buts_ LOC = A6; # S Button + +NET trx_ LOC = W1 | IOSTANDARD = LVCMOS33; + +#NET led_[0] LOC = G5; #GPLED0 +#NET led_[1] LOC = G6; #GPLED1 +#NET led_[2] LOC = A11; #GPLED2 +#NET led_[3] LOC = A12; #GPLED3 + +# North-East-South-West-Center LEDs +#NET led_[4] LOC = C6; # C LED +#NET led_[5] LOC = F9; # W LED +#NET led_[6] LOC = A5; # S LED +#NET led_[7] LOC = E10; # E LED +#NET led_[8] LOC = E2; # N LED + +#Keyboard +NET ps2_clk_ LOC = D2; +NET ps2_clk_ SLEW = SLOW; +NET ps2_clk_ DRIVE = 2; +NET ps2_clk_ TIG; +NET ps2_data_ LOC = G9; +NET ps2_data_ SLEW = SLOW; +NET ps2_data_ DRIVE = 2; +NET ps2_data_ TIG; + +# Shared signals +NET "aceusb_a_<1>" LOC = Y10; +NET "aceusb_a_<2>" LOC = AA10; +NET "aceusb_a_<3>" LOC = AC7; +NET "aceusb_a_<4>" LOC = Y7; +NET "aceusb_a_<5>" LOC = AA9; +NET "aceusb_a_<6>" LOC = Y9; +NET "aceusb_a_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "aceusb_d_<0>" LOC = AB7; +NET "aceusb_d_<1>" LOC = AC9; +NET "aceusb_d_<2>" LOC = AB9; +NET "aceusb_d_<3>" LOC = AE6; +NET "aceusb_d_<4>" LOC = AD6; +NET "aceusb_d_<5>" LOC = AF9; +NET "aceusb_d_<6>" LOC = AE9; +NET "aceusb_d_<7>" LOC = AD8; +NET "aceusb_d_<8>" LOC = AC8; +NET "aceusb_d_<9>" LOC = AF4; +NET "aceusb_d_<10>" LOC = AE4; +NET "aceusb_d_<11>" LOC = AD3; +NET "aceusb_d_<12>" LOC = AC3; +NET "aceusb_d_<13>" LOC = AF6; +NET "aceusb_d_<14>" LOC = AF5; +NET "aceusb_d_<15>" LOC = AA7; +NET "aceusb_d_<*>" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN; +NET "aceusb_oe_n_" LOC = AA8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "aceusb_we_n_" LOC = Y8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; + +# SystemACE signals +NET "ace_clkin_" LOC = AF11; +NET "ace_clkin_" IOSTANDARD = LVCMOS33; +NET "ace_clkin_" TNM_NET = "ace_clkin_"; +TIMESPEC "TSace" = PERIOD "ace_clkin_" 30 ns HIGH 50% INPUT_JITTER 1 ns; + +NET "ace_mpce_n_" LOC = AD5 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; + +# USB signals +NET "usb_cs_n_" LOC = AF10 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "usb_hpi_reset_n_" LOC = A7 | IOSTANDARD = LVCMOS25 | TIG; Index: trunk/boards/virtex4-ml403ep/syn/Makefile =================================================================== --- trunk/boards/virtex4-ml403ep/syn/Makefile (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/Makefile (revision 54) @@ -0,0 +1,43 @@ +all: kotku_ml403.bit + +run: tmp/kotku_ml403.bit + (cd tmp/ && ../../../../bin/ml403 kotku_ml403.bit) + +debug: tmp/mult.v tmp/icon.v tmp/ila.v kotku-dbg.prj kotku-dbg.xst + (cd tmp/ && xst -ifn ../kotku-dbg.xst) + +tmp/icon.v: icon.xco + mkdir -p tmp + (cd tmp/ && coregen -b ../icon.xco) + +tmp/ila.v: ila.xco + mkdir -p tmp + (cd tmp/ && coregen -b ../ila.xco) + +Zet.ace: tmp/kotku_ml403.bit + (cd tmp/ && ../../ace/ml40x_bit2ace kotku_ml403.bit ../Zet.ace ../../ace/) + +tmp/mult.v: mult.xco + mkdir -p tmp + (cd tmp/ && coregen -b ../mult.xco) + +tmp/kotku_ml403.ngc: tmp/mult.v kotku.prj kotku.xst + (cd tmp/ && xst -ifn ../kotku.xst) + +tmp/kotku_ml403.ngd: tmp/kotku_ml403.ngc ml403.ucf tmp/mult.ngc + (cd tmp/ && ngdbuild -uc ../ml403.ucf kotku_ml403.ngc) + +tmp/kotku_ml403.ncd: tmp/kotku_ml403.ngd + (cd tmp/ && map kotku_ml403.ngd) + +tmp/kotku_ml403-par.ncd: tmp/kotku_ml403.ncd + (cd tmp/ && par -w kotku_ml403.ncd kotku_ml403-par.ncd) + +tmp/kotku_ml403.bit: tmp/kotku_ml403-par.ncd + (cd tmp/ && bitgen -w kotku_ml403-par.ncd kotku_ml403.bit) + +kotku_ml403.bit: tmp/kotku_ml403.bit + cp tmp/kotku_ml403.bit /home/zeus/tmp + +clean: + rm -fR Zet.ace tmp/ Index: trunk/boards/virtex4-ml403ep/syn/ila.xco =================================================================== --- trunk/boards/virtex4-ml403ep/syn/ila.xco (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/ila.xco (revision 54) @@ -0,0 +1,131 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Sat Feb 28 12:16:13 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc4vfx12 +SET devicefamily = virtex4 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff668 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -10 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a +# END Select +# BEGIN Parameters +CSET component_name=ila +CSET counter_width_1=32 +CSET counter_width_10=Disabled +CSET counter_width_11=16 +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=32 +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic +CSET match_type_10=basic +CSET match_type_11=basic +CSET match_type_12=basic +CSET match_type_13=basic +CSET match_type_14=basic +CSET match_type_15=basic +CSET match_type_16=range +CSET match_type_2=basic +CSET match_type_3=basic +CSET match_type_4=basic +CSET match_type_5=basic +CSET match_type_6=basic +CSET match_type_7=basic +CSET match_type_8=basic +CSET match_type_9=basic +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=16 +CSET number_of_trigger_ports=16 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=20 +CSET trigger_port_width_10=16 +CSET trigger_port_width_11=21 +CSET trigger_port_width_12=16 +CSET trigger_port_width_13=9 +CSET trigger_port_width_14=3 +CSET trigger_port_width_15=5 +CSET trigger_port_width_16=32 +CSET trigger_port_width_2=32 +CSET trigger_port_width_3=20 +CSET trigger_port_width_4=6 +CSET trigger_port_width_5=6 +CSET trigger_port_width_6=6 +CSET trigger_port_width_7=16 +CSET trigger_port_width_8=16 +CSET trigger_port_width_9=32 +CSET use_rpms=true +# END Parameters +GENERATE +# CRC: c1a9a9f1 + Index: trunk/boards/virtex4-ml403ep/syn/kotku-dbg.xst =================================================================== --- trunk/boards/virtex4-ml403ep/syn/kotku-dbg.xst (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/kotku-dbg.xst (revision 54) @@ -0,0 +1,57 @@ +run +-ifn ../kotku-dbg.prj +-ifmt mixed +-ofn kotku_ml403 +-ofmt NGC +-p xc4vfx12-10-ff668 +-top kotku_ml403 +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy NO +-netlist_hierarchy as_optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 16 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 Index: trunk/boards/virtex4-ml403ep/syn/icon.xco =================================================================== --- trunk/boards/virtex4-ml403ep/syn/icon.xco (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/icon.xco (revision 54) @@ -0,0 +1,47 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Tue Nov 11 20:50:43 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc4vfx12 +SET devicefamily = virtex4 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff668 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -10 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.03.a +# END Select +# BEGIN Parameters +CSET component_name=icon +CSET enable_jtag_bufg=true +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +GENERATE +# CRC: 7feea034 + Index: trunk/boards/virtex4-ml403ep/syn/mult.xco =================================================================== --- trunk/boards/virtex4-ml403ep/syn/mult.xco (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/mult.xco (revision 54) @@ -0,0 +1,62 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Wed Nov 12 21:43:31 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc4vfx12 +SET devicefamily = virtex4 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff668 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -12 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Multiplier family Xilinx,_Inc. 10.1 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=false +CSET component_name=mult +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=33 +CSET outputwidthlow=0 +CSET pipestages=1 +CSET portatype=Signed +CSET portawidth=17 +CSET portbtype=Signed +CSET portbwidth=17 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +GENERATE +# CRC: 39b5f86a + Index: trunk/boards/virtex4-ml403ep/syn/kotku.xst =================================================================== --- trunk/boards/virtex4-ml403ep/syn/kotku.xst (nonexistent) +++ trunk/boards/virtex4-ml403ep/syn/kotku.xst (revision 54) @@ -0,0 +1,57 @@ +run +-ifn ../kotku.prj +-ifmt mixed +-ofn kotku_ml403 +-ofmt NGC +-p xc4vfx12-10-ff668 +-top kotku_ml403 +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy NO +-netlist_hierarchy as_optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-bufg 32 +-bufr 16 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 Index: trunk/boards/virtex4-ml403ep/dbg/test_serial.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/test_serial.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/test_serial.v (revision 54) @@ -0,0 +1,48 @@ + + +module test_serial ( + input clk_, + output trx_ + ); + + // Registers and nets + wire clk_100M; + wire rst; + wire clk_921600; + wire rst2; + wire ack; + wire lock; + wire [19:0] inc_dat; + reg [19:0] dat; + + // Module instantiation + clocks c0 ( + .CLKIN_IN (clk_), + .CLK0_OUT (clk_100M), + .LOCKED_OUT (lock) + ); + + clk_uart clk0 ( + .clk_100M (clk_100M), + .rst (rst), + .clk_921600 (clk_921600), + .rst2 (rst2) + ); + + send_addr ser0 ( + .trx_ (trx_), + .wb_clk_i (clk_921600), + .wb_rst_i (rst2), + .wb_dat_i (dat), + .wb_we_i (1'b1), + .wb_stb_i (1'b1), + .wb_cyc_i (1'b1), + .wb_ack_o (ack) + ); + + assign rst = !lock; + assign inc_dat = dat + 20'h1; + + always @(posedge clk_921600) + dat <= rst2 ? 20'h12345 : (ack ? inc_dat : dat); +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/pc_trace.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/pc_trace.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/pc_trace.v (revision 54) @@ -0,0 +1,85 @@ +`timescale 1ns/10ps +`include "defines.v" + +module pc_trace ( +`ifdef DEBUG + output reg [ 2:0] old_zet_st, + output reg [19:0] dat, + output reg new_pc, + output reg st, + output reg stb, + output ack, + output [ 4:0] pack, + output addr_st, +`endif + // PAD signals + output trx_, + + input clk, + input rst, + input [19:0] pc, + input [ 2:0] zet_st, + output reg block + ); + +`ifndef DEBUG + // Registers and nets + reg [19:0] dat; + reg [ 2:0] old_zet_st; + reg new_pc; + reg st; + reg stb; + wire ack; +`endif + wire op_st; + wire rom; + + // Module instantiations + send_addr ser0 ( +`ifdef DEBUG + .pack (pack), + .st (addr_st), +`endif + .trx_ (trx_), + .wb_clk_i (clk), + .wb_rst_i (rst), + .wb_dat_i (dat), + .wb_we_i (stb), + .wb_stb_i (stb), + .wb_cyc_i (stb), + .wb_ack_o (ack) + ); + + // Continous assignments + assign op_st = (zet_st == 3'b0); + assign rom = pc[19:16]==4'hf || pc[19:16]==4'hc; + + // Behaviour + // old_zet_st + always @(posedge clk) + old_zet_st <= rst ? 3'b0 : zet_st; + + // new_pc + always @(posedge clk) + new_pc <= rst ? 1'b0 + : (op_st ? (zet_st!=old_zet_st && !rom) : 1'b0); + + // block + always @(posedge clk) + block <= rst ? 1'b0 + : (new_pc ? (st & !ack) : (ack ? 1'b0 : block)); + + // dat + always @(posedge clk) + dat <= rst ? 20'h0 + : ((new_pc & !st) ? pc : (ack ? pc : dat)); + + // stb + always @(posedge clk) + stb <= rst ? 1'b0 : (ack ? 1'b0 : (st | new_pc)); + + // st + always @(posedge clk) + st <= rst ? 1'b0 + : (st ? (ack ? (new_pc | block) : 1'b1) : new_pc); +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/sim_addr.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/sim_addr.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/sim_addr.v (revision 54) @@ -0,0 +1,46 @@ +`timescale 1ns/10ps + +module sim_addr; + + // Registers and nets + reg clk_100M; + reg rst; + reg stb; + wire clk_921600; + wire trx_; + wire rst2; + wire ack; + + // Module instantiation + clk_uart clk0 ( + .clk_100M (clk_100M), + .rst (rst), + .clk_921600 (clk_921600), + .rst2 (rst2) + ); + + send_addr ser0 ( + .trx_ (trx_), + .wb_clk_i (clk_921600), + .wb_rst_i (rst2), + .wb_dat_i (20'h4fb31), + .wb_we_i (1'b1), + .wb_stb_i (stb), + .wb_cyc_i (1'b1), + .wb_ack_o (ack) + ); + + // Behaviour + initial + begin + stb <= 1'b1; + clk_100M <= 1'b0; + rst <= 1'b1; + #400 rst <= 1'b0; + #33635 stb <= 1'b0; + #10000 stb <= 1'b1; + end + + // clk_50M + always #5 clk_100M <= !clk_100M; +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/send_addr.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/send_addr.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/send_addr.v (revision 54) @@ -0,0 +1,75 @@ +`timescale 1ns/10ps +`include "defines.v" + +module send_addr ( +`ifdef DEBUG + output reg [ 4:0] pack, + output reg st, +`endif + // Serial pad signal + output trx_, + + // Wishbone slave interface + input wb_clk_i, + input wb_rst_i, + input [19:0] wb_dat_i, + input wb_we_i, + input wb_stb_i, + input wb_cyc_i, + output wb_ack_o + ); + + // Registers and nets +`ifndef DEBUG + reg [4:0] pack; + reg st; +`endif + wire op; + wire start; + wire sack; + wire [7:0] dat; + wire [7:0] b0, b1, b2, b3, b4; + + // Module instantiation + send_serial ss0 ( + .trx_ (trx_), + + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wb_dat_i (dat), + .wb_we_i (wb_we_i), + .wb_stb_i (wb_stb_i), + .wb_cyc_i (wb_cyc_i), + .wb_ack_o (sack) + ); + + // Continuous assignments + assign op = wb_we_i & wb_stb_i & wb_cyc_i; + assign start = !st & op; + assign wb_ack_o = st & sack & pack[4]; + + assign dat = st & pack[0] ? + (pack[1] ? (pack[2] ? (pack[3] ? (pack[4] ? 8'h0a : b0) + : b1) : b2) : b3) : b4; + + assign b0 = { 1'b0, ascii(wb_dat_i[ 3: 0]) }; + assign b1 = { 1'b0, ascii(wb_dat_i[ 7: 4]) }; + assign b2 = { 1'b0, ascii(wb_dat_i[11: 8]) }; + assign b3 = { 1'b0, ascii(wb_dat_i[15:12]) }; + assign b4 = { 1'b0, ascii(wb_dat_i[19:16]) }; + + // Behaviour + // pack + always @(posedge wb_clk_i) + pack <= wb_rst_i ? 5'b0 : (start ? 5'b0 + : (st ? (sack ? { pack[3:0], 1'b1 } : pack) : 5'b0)); + + // st + always @(posedge wb_clk_i) + st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op); + + function [6:0] ascii(input [3:0] num); + if (num <= 4'd9) ascii = 7'h30 + num; + else ascii = 7'd87 + num; + endfunction +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/clk_uart.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/clk_uart.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/clk_uart.v (revision 54) @@ -0,0 +1,34 @@ + /* + * Phase accumulator clock: + * Fo = Fc * N / 2^bits + * here N: 154619 and bits: 24 + */ + +module clk_uart ( + input clk_100M, + input rst, + output clk_921600, + output rst2 + ); + + // Registers + reg [25:0] cnt; + reg [ 2:0] init; + + // Continuous assignments + assign clk_921600 = cnt[25]; + assign rst2 = init[2]; + + // Behaviour + // cnt + always @(posedge clk_100M) + cnt <= rst ? 26'd0 : cnt + 26'd154619; + + // init[0] + always @(posedge clk_100M) + init[0] <= rst ? 1'b1 : (clk_921600 ? 1'b0 : init[0]); + + // init[2:1] + always @(posedge clk_921600) + init[2:1] <= init[0] ? 2'b11 : init[1:0]; +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/sim_serial.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/sim_serial.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/sim_serial.v (revision 54) @@ -0,0 +1,46 @@ +`timescale 1ns/10ps + +module sim_serial; + + // Registers and nets + reg clk_100M; + reg rst; + reg stb; + wire clk_921600; + wire trx_; + wire rst2; + wire ack; + + // Module instantiation + clk_uart clk0 ( + .clk_100M (clk_100M), + .rst (rst), + .clk_921600 (clk_921600), + .rst2 (rst2) + ); + + send_serial ser0 ( + .trx_ (trx_), + .wb_clk_i (clk_921600), + .wb_rst_i (rst2), + .wb_dat_i (8'h4b), + .wb_we_i (1'b1), + .wb_stb_i (stb), + .wb_cyc_i (1'b1), + .wb_ack_o (ack) + ); + + // Behaviour + initial + begin + stb <= 1'b1; + clk_100M <= 1'b0; + rst <= 1'b1; + #400 rst <= 1'b0; + #95490 stb <= 1'b0; + #40000 stb <= 1'b1; + end + + // clk_50M + always #5 clk_100M <= !clk_100M; +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/send_serial.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/send_serial.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/send_serial.v (revision 54) @@ -0,0 +1,44 @@ + +module send_serial ( + // Serial pad signal + output reg trx_, + + // Wishbone slave interface + input wb_clk_i, + input wb_rst_i, + input [7:0] wb_dat_i, + input wb_we_i, + input wb_stb_i, + input wb_cyc_i, + output reg wb_ack_o + ); + + // Registers and nets + wire op; + wire start; + reg [8:0] tr; + reg st; + reg [7:0] sft; + + // Continuous assignments + assign op = wb_we_i & wb_stb_i & wb_cyc_i; + assign start = !st & op; + + // Behaviour + // trx_ + always @(posedge wb_clk_i) + trx_ <= wb_rst_i ? 1'b1 : (start ? 1'b0 : tr[0]); + + // tr + always @(posedge wb_clk_i) + tr <= wb_rst_i ? 9'h1ff + : { 1'b1, (start ? wb_dat_i : tr[8:1]) }; + + // sft, wb_ack_o + always @(posedge wb_clk_i) + { sft, wb_ack_o } <= wb_rst_i ? 9'h0 : { start, sft }; + + // st + always @(posedge wb_clk_i) + st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op); +endmodule Index: trunk/boards/virtex4-ml403ep/dbg/hw_dbg.v =================================================================== --- trunk/boards/virtex4-ml403ep/dbg/hw_dbg.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/dbg/hw_dbg.v (revision 54) @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2009 Zeus Gomez Marmolejo + * + * Nobody can figure out what this file is for... hehe + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +`timescale 1ns/10ps + +module hw_dbg ( + input clk, + input rst_lck, + output reg rst, + input butc_, + input bute_, + input butw_, + input butn_, + input buts_, + + // Wishbone master interface for the VDU + output reg [15:0] vdu_dat_o, + output reg [11:1] vdu_adr_o, + output vdu_we_o, + output vdu_stb_o, + output [ 1:0] vdu_sel_o, + output reg vdu_tga_o, + input vdu_ack_i, + + // Wishbone master interface for the ZBT SRAM + input [15:0] zbt_dat_i, + output [19:1] zbt_adr_o, + output zbt_we_o, + output [ 1:0] zbt_sel_o, + output reg zbt_stb_o, + input zbt_ack_i + ); + + // Registers and nets + reg [ 5:0] st; + reg op; + reg [ 6:0] cur; + reg mr, ml, md, mu, dm; + reg br, bl, bd, bu, bc; + reg [15:0] cnt; + reg [ 4:0] i; + reg [19:0] adr; + reg [ 2:0] sp; + reg [15:0] col; + reg [ 3:0] nibb; + reg [ 7:0] low_adr; + + wire [7:0] o; + wire cur_dump; + wire action; + wire [2:0] off; + wire [3:0] nib, inc_nib, dec_nib; + wire up_down; + wire left_right; + wire spg; + + // Module instantiations + init_msg msg0 ( + .i (i), + .o (o) + ); + + inc i0 ( + .i (nib), + .o (inc_nib) + ); + + dec d0 ( + .i (nib), + .o (dec_nib) + ); + + // Continuous assignments + assign vdu_we_o = op; + assign vdu_stb_o = op; + assign vdu_sel_o = 2'b11; + assign zbt_we_o = 1'b0; + assign zbt_sel_o = 2'b11; + assign cur_dump = (cur < 7'd25 && cur > 7'd19); + assign off = cur - 7'd20; + assign nib = off==3'd0 ? adr[19:16] + : (off==3'd1 ? adr[15:12] + : (off==3'd2 ? adr[11:8] + : (off==3'd3 ? adr[7:4] : adr[3:0]))); + + assign left_right = mr | ml; + assign up_down = mu | md; + assign action = left_right | up_down | dm; + assign spg = sp>3'b0; + assign zbt_adr_o = { adr[19:5] + low_adr[7:4], low_adr[3:0] }; + + // Behaviour + always @(posedge clk) + if (rst_lck) + begin + vdu_dat_o <= 16'd12; + vdu_adr_o <= 11'h4; + vdu_tga_o <= 1'b1; + st <= 6'd0; + op <= 1'b1; + i <= 4'h0; + zbt_stb_o <= 1'b0; + end + else + case (st) + 6'd0: if (vdu_ack_i) begin + vdu_dat_o <= { 8'h06, o }; + vdu_adr_o <= i + 5'h4; + vdu_tga_o <= 1'b0; + st <= (i==5'd21) ? 6'h2 : 6'h1; + op <= 1'b0; + i <= i + 5'h1; + end + 6'd1: if (!vdu_ack_i) begin + st <= 6'h0; + op <= 1'b1; + i <= i; + end + 6'd2: // main wait state + if (!vdu_ack_i && action) begin + vdu_dat_o <= mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1) + : ((ml && cur==7'd20) ? 7'd15 : cur - 7'b1); + vdu_adr_o <= 11'h0; + vdu_tga_o <= 1'b1; + st <= left_right ? 6'h3 : (dm ? 6'h5 : 6'h4); + op <= left_right; + col <= 16'd80; + sp <= 2'h3; + nibb <= 4'h0; + end + 6'd3: if (vdu_ack_i) begin + vdu_dat_o <= 16'h0; + vdu_adr_o <= 11'h0; + vdu_tga_o <= 1'b1; + st <= 6'h2; + op <= 1'b0; + end + 6'd4: // redraw the mem_dump counter + if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h03, itoa(nib) }; + vdu_adr_o <= cur; + vdu_tga_o <= 1'b0; + st <= 6'h3; + op <= 1'b1; + end + 6'd5: // memory dump + if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h05, spg ? 8'h20 : itoa(nibb) }; + vdu_adr_o <= col; + vdu_tga_o <= 1'b0; + st <= 6'h6; + op <= 1'b1; + sp <= spg ? (sp - 3'b1) : 3'd4; + col <= col + 16'd1; + nibb <= spg ? nibb : (nibb + 4'h2); + end + 6'd6: if (vdu_ack_i) begin + st <= (col==16'd160) ? 6'h7 : 6'h5; + op <= 1'b0; + end + 6'd7: begin + low_adr <= 8'h0; + st <= 6'h8; + end + 6'd8: if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h5, itoa(zbt_adr_o[7:4]) }; + vdu_adr_o <= col; + st <= 6'd9; + op <= 1'b1; + end + 6'd9: if (vdu_ack_i) begin + st <= 6'd10; + op <= 1'b0; + col <= col + 16'd1; + end + 6'd10: if (!zbt_ack_i) begin + st <= 6'd11; + zbt_stb_o <= 1'b1; + end + 6'd11: if (zbt_ack_i) begin + st <= 6'd12; + zbt_stb_o <= 1'b0; + end + 6'd12: if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[15:12]) }; + vdu_adr_o <= col; + st <= 6'd13; + op <= 1'b1; + end + 6'd13: if (vdu_ack_i) begin + st <= 6'd14; + op <= 1'b0; + col <= col + 16'd1; + end + 6'd14: if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[11:8]) }; + vdu_adr_o <= col; + st <= 6'd15; + op <= 1'b1; + end + 6'd15: if (vdu_ack_i) begin + st <= 6'd16; + op <= 1'b0; + col <= col + 16'd1; + end + 6'd16: if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[7:4]) }; + vdu_adr_o <= col; + st <= 6'd17; + op <= 1'b1; + end + 6'd17: if (vdu_ack_i) begin + st <= 6'd18; + op <= 1'b0; + col <= col + 16'd1; + end + 6'd18: if (!vdu_ack_i) begin + vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[3:0]) }; + vdu_adr_o <= col; + st <= 6'd19; + op <= 1'b1; + end + 6'd19: if (vdu_ack_i) begin + st <= (zbt_adr_o[4:1]==4'hf) ? 6'd22 : 6'd20; + op <= 1'b0; + col <= col + 16'd1; + low_adr <= low_adr + 8'h1; + end + 6'd20: if (!vdu_ack_i) begin + vdu_dat_o <= 16'h0720; + vdu_adr_o <= col; + st <= 6'd21; + op <= 1'b1; + end + 6'd21: if (vdu_ack_i) begin + st <= 6'd10; + op <= 1'b0; + col <= col + 16'd1; + end + 6'd22: st <= (low_adr==8'h0) ? 6'd2 : 6'd8; + endcase + + // rst + always @(posedge clk) + rst <= rst_lck ? 1'b1 : ((butc_ && cur==7'd12) ? 1'b0 : rst); + + // cur + always @(posedge clk) + cur <= rst_lck ? 7'd12 : (mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1) + : (ml ? (cur==7'd20 ? 7'd15 : cur - 7'b1) : cur)); + + // adr + always @(posedge clk) + adr <= rst_lck ? 16'h0 + : (mu ? (off==3'd0 ? { inc_nib, adr[15:0] } + : (off==3'd1 ? { adr[19:16], inc_nib, adr[11:0] } + : (off==3'd2 ? { adr[19:12], inc_nib, adr[7:0] } + : (off==3'd3 ? { adr[19:8], inc_nib, adr[3:0] } + : { adr[19:4], inc_nib })))) + : (md ? (off==3'd0 ? { dec_nib, adr[15:0] } + : (off==3'd1 ? { adr[19:16], dec_nib, adr[11:0] } + : (off==3'd2 ? { adr[19:12], dec_nib, adr[7:0] } + : (off==3'd3 ? { adr[19:8], dec_nib, adr[3:0] } + : { adr[19:4], dec_nib })))) : adr)); + + // mr - move right + always @(posedge clk) + mr <= rst_lck ? 1'b0 : (bute_ && !br + && cnt==16'h0 && cur != 7'd24); + + // br - button right + always @(posedge clk) br <= (cnt==16'h0 ? bute_ : br); + + // ml - move right + always @(posedge clk) + ml <= rst_lck ? 1'b0 : (butw_ && !bl + && cnt==16'h0 && cur != 7'd12); + + // bl - button right + always @(posedge clk) bl <= (cnt==16'h0 ? butw_ : bl); + + // md - move down + always @(posedge clk) + md <= rst_lck ? 1'b0 : (buts_ && !bd && cnt==16'h0 && cur_dump); + + // bd - button down + always @(posedge clk) bd <= (cnt==16'h0 ? buts_ : bd); + + // mu - move up + always @(posedge clk) + mu <= rst_lck ? 1'b0 : (butn_ && !bu && cnt==16'h0 && cur_dump); + + // bu - button up + always @(posedge clk) bu <= (cnt==16'h0 ? butn_ : bu); + + // dm - dump + always @(posedge clk) + dm <= rst_lck ? 1'b0 : (butc_ && !bc && cur==7'd13); + + // bc - center button + always @(posedge clk) bc <= (cnt==16'h0 ? butc_ : bc); + + // cnt - button counter + always @(posedge clk) cnt <= cnt + 1'b1; + + function [7:0] itoa; + input [3:0] i; + begin + if (i < 8'd10) itoa = i + 8'h30; + else itoa = i + 8'h57; + end + endfunction +endmodule + +module init_msg ( + input [4:0] i, + output reg [7:0] o + ); + + // Behaviour + always @(i) + case (i) + 5'h00: o <= 8'h68; // h + 5'h01: o <= 8'h77; // w + 5'h02: o <= 8'h5f; // _ + 5'h03: o <= 8'h64; // d + 5'h04: o <= 8'h62; // b + 5'h05: o <= 8'h67; // g + 5'h06: o <= 8'h20; // + 5'h07: o <= 8'h5b; // [ + 5'h08: o <= 8'h43; // C + 5'h09: o <= 8'h44; // D + 5'h0a: o <= 8'h57; // W + 5'h0b: o <= 8'h42; // B + 5'h0c: o <= 8'h5d; // ] + 5'h0d: o <= 8'h20; // + 5'h0f: o <= 8'h78; // x + default: o <= 8'h30; // 0 + endcase +endmodule + +module inc ( + input [3:0] i, + output reg [3:0] o + ); + + // Behaviour + always @(i) + case (i) + 4'h0: o <= 4'h1; + 4'h1: o <= 4'h2; + 4'h2: o <= 4'h3; + 4'h3: o <= 4'h4; + 4'h4: o <= 4'h5; + 4'h5: o <= 4'h6; + 4'h6: o <= 4'h7; + 4'h7: o <= 4'h8; + 4'h8: o <= 4'h9; + 4'h9: o <= 4'ha; + 4'ha: o <= 4'hb; + 4'hb: o <= 4'hc; + 4'hc: o <= 4'hd; + 4'hd: o <= 4'he; + 4'he: o <= 4'hf; + default: o <= 4'h0; + endcase +endmodule + +module dec ( + input [3:0] i, + output reg [3:0] o + ); + + // Behaviour + always @(i) + case (i) + 4'h0: o <= 4'hf; + 4'h1: o <= 4'h0; + 4'h2: o <= 4'h1; + 4'h3: o <= 4'h2; + 4'h4: o <= 4'h3; + 4'h5: o <= 4'h4; + 4'h6: o <= 4'h5; + 4'h7: o <= 4'h6; + 4'h8: o <= 4'h7; + 4'h9: o <= 4'h8; + 4'ha: o <= 4'h9; + 4'hb: o <= 4'ha; + 4'hc: o <= 4'hb; + 4'hd: o <= 4'hc; + 4'he: o <= 4'hd; + default: o <= 4'he; + endcase +endmodule Index: trunk/boards/virtex4-ml403ep/lcd/test_lcd_cntrl.v =================================================================== --- trunk/boards/virtex4-ml403ep/lcd/test_lcd_cntrl.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/lcd/test_lcd_cntrl.v (revision 54) @@ -0,0 +1,33 @@ +module lcd_test ( + // Pad signals + input clk_, + output rs_, + output rw_, + output e_, + inout [3:0] db_, + input but_, + output [5:0] led_ + ); + + // Registers + reg [4:0] cnt; + + // Module instantiations + lcd_display4 lcd0 ( + .clk (cnt[4]), + .rst (but_), + .f1 (64'h123456f890abcde7), + .f2 (64'h7645321dcbaef987), + .m1 (16'b0101011101011111), + .m2 (16'b1110101110101111), + + .rs_ (rs_), + .rw_ (rw_), + .e_ (e_), + .db_ (db_), + .st (led_) + ); + + // Behaviour + always @(posedge clk_) cnt <= cnt + 5'b1; +endmodule Index: trunk/boards/virtex4-ml403ep/lcd/ml403.ucf =================================================================== --- trunk/boards/virtex4-ml403ep/lcd/ml403.ucf (nonexistent) +++ trunk/boards/virtex4-ml403ep/lcd/ml403.ucf (revision 54) @@ -0,0 +1,27 @@ +NET clk_ TNM_NET = "clk_"; +TIMESPEC "TSSYSCLK" = PERIOD "clk_" 9.9 ns HIGH 50 %; + +NET clk_ LOC = AE14; +NET clk_ IOSTANDARD = LVCMOS33; + +NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E +NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS +NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW + +NET db_[3] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7 +NET db_[2] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6 +NET db_[1] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5 +NET db_[0] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4 + +NET but_ LOC = B6; # C Button + +NET led_[0] LOC = G5; #GPLED0 +NET led_[1] LOC = G6; #GPLED1 +NET led_[2] LOC = A11; #GPLED2 +NET led_[3] LOC = A12; #GPLED3 + +# North-East-South-West-Center LEDs +NET led_[4] LOC = C6; # C LED +NET led_[5] LOC = F9; # W LED +#NET led_[6] LOC = A5; # S LED +#NET led_[7] LOC = E10; # E LED Index: trunk/boards/virtex4-ml403ep/lcd/lcd_display.v =================================================================== --- trunk/boards/virtex4-ml403ep/lcd/lcd_display.v (nonexistent) +++ trunk/boards/virtex4-ml403ep/lcd/lcd_display.v (revision 54) @@ -0,0 +1,136 @@ +module lcd_display ( + input [63:0] f1, // 1st row + input [63:0] f2, // 2nd row + input [15:0] m1, // 1st row mask + input [15:0] m2, // 2nd row mask + + input clk, // 100 Mhz clock + input rst, + + // Pad signals + output reg lcd_rs_, + output reg lcd_rw_, + output reg lcd_e_, + output reg [7:4] lcd_dat_ + ); + + // Parameter definitions + parameter n = 8; + parameter k = 16; + + // Register declarations + reg [k+n+1:0] cnt = 0; + reg [ 5:0] lcd; + + // Net declarations + wire [127:0] f; + wire [ 31:0] m; + wire [ 4:0] i; + wire [ 3:0] c; + + // Module instantiations + sel128_4 sel ( + .in (f), + .sel (i), + .out (c) + ); + + // Continuous assignments + assign f = { f1, f2 }; + assign m = { m1, m2 }; + assign i = cnt[k+7:k+3]; + + // Behaviour + always @(posedge clk) + if (rst) cnt <= 26'hfffffff; + else begin + cnt <= cnt - 1; + casex (cnt[k+1+n:k+2]) + 8'hff: lcd <= 6'b000010; // function set + 8'hfe: lcd <= 6'b000010; + 8'hfd: lcd <= 6'b001000; + 8'hfc: lcd <= 6'b000000; // display on/off control + 8'hfb: lcd <= 6'b001100; + 8'hfa: lcd <= 6'b000000; // display clear + 8'hf9: lcd <= 6'b000001; + 8'hf8: lcd <= 6'b000000; // entry mode set + 8'hf7: lcd <= 6'b000110; + 8'hf6: cnt[k+1+n:k+2] <= 8'b10111111; + + 8'b101xxxx1: lcd <= { 2'b10, m[i] ? itoa1(c) : 4'h2 }; + 8'b101xxxx0: lcd <= { 2'b10, m[i] ? itoa0(c) : 4'h0 }; + 8'b10011111: lcd <= 6'h0c; + 8'b10011110: lcd <= 6'h00; + 8'b10011101: cnt[k+1+n:k+2] <= 8'b01011111; + 8'b010xxxx1: lcd <= { 2'b10, m[i] ? itoa1(c) : 4'h2 }; + 8'b010xxxx0: lcd <= { 2'b10, m[i] ? itoa0(c) : 4'h0 }; + 8'b00111111: lcd <= 6'h08; + 8'b00111110: lcd <= 6'h00; + 8'b00111101: cnt[k+1+n:k+2] <= 8'b10111111; + + default: lcd <= 6'b010000; + endcase + lcd_e_ <= ^cnt[k+1:k+0] & ~lcd_rw_; + { lcd_rs_, lcd_rw_, lcd_dat_ } <= lcd; + end + + // Function definitions + function [3:0] itoa1; + input [3:0] i; + begin + if (i < 8'd10) itoa1 = 4'h3; + else itoa1 = 4'h6; + end + endfunction + + function [3:0] itoa0; + input [3:0] i; + begin + if (i < 8'd10) itoa0 = i + 4'h0; + else itoa0 = i + 4'h7; + end + endfunction +endmodule + +module sel128_4 ( + input [127:0] in, + input [ 4:0] sel, + output reg [ 3:0] out + ); + + always @(in or sel) + case (sel) + 5'h00: out <= in[ 3: 0]; + 5'h01: out <= in[ 7: 4]; + 5'h02: out <= in[ 11: 8]; + 5'h03: out <= in[ 15: 12]; + 5'h04: out <= in[ 19: 16]; + 5'h05: out <= in[ 23: 20]; + 5'h06: out <= in[ 27: 24]; + 5'h07: out <= in[ 31: 28]; + 5'h08: out <= in[ 35: 32]; + 5'h09: out <= in[ 39: 36]; + 5'h0a: out <= in[ 43: 40]; + 5'h0b: out <= in[ 47: 44]; + 5'h0c: out <= in[ 51: 48]; + 5'h0d: out <= in[ 55: 52]; + 5'h0e: out <= in[ 59: 56]; + 5'h0f: out <= in[ 63: 60]; + 5'h10: out <= in[ 67: 64]; + 5'h11: out <= in[ 71: 68]; + 5'h12: out <= in[ 75: 72]; + 5'h13: out <= in[ 79: 76]; + 5'h14: out <= in[ 83: 80]; + 5'h15: out <= in[ 87: 84]; + 5'h16: out <= in[ 91: 88]; + 5'h17: out <= in[ 95: 92]; + 5'h18: out <= in[ 99: 96]; + 5'h19: out <= in[103:100]; + 5'h1a: out <= in[107:104]; + 5'h1b: out <= in[111:108]; + 5'h1c: out <= in[115:112]; + 5'h1d: out <= in[119:116]; + 5'h1e: out <= in[123:120]; + 5'h1f: out <= in[127:124]; + endcase +endmodule \ No newline at end of file Index: trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace.bat =================================================================== --- trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace.bat (nonexistent) +++ trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace.bat (revision 54) @@ -0,0 +1,13 @@ +echo off +if exist tmp_ml40x____datafile.bit del tmp_ml40x____datafile.bit +if exist tmp_ml40x____datafile.ace del tmp_ml40x____datafile.ace +copy /Y %XILINX%\xcfp\data\xcf32p_vo48.bsd . +copy /Y %XILINX%\xc9500xl\data\xc95144xl_tq100.bsd . +copy /Y %1 tmp_ml40x____datafile.bit +impact -batch ml40x.scr +impact -batch ml40x_svf2ace.scr +if exist tmp_ml40x____datafile.bit del tmp_ml40x____datafile.bit +if exist tmp_ml40x____datafile.svf del tmp_ml40x____datafile.svf +if exist %2 del %2 +if exist tmp_ml40x____datafile.ace ren tmp_ml40x____datafile.ace %2 +echo on Index: trunk/boards/virtex4-ml403ep/ace/ml40x_svf2ace.scr =================================================================== --- trunk/boards/virtex4-ml403ep/ace/ml40x_svf2ace.scr (nonexistent) +++ trunk/boards/virtex4-ml403ep/ace/ml40x_svf2ace.scr (revision 54) @@ -0,0 +1,7 @@ +setMode -cf +svf2ace -wtck -d -i tmp_ml40x____datafile.svf -o tmp_ml40x____datafile.ace +quit + + + + Index: trunk/boards/virtex4-ml403ep/ace/ml40x.scr =================================================================== --- trunk/boards/virtex4-ml403ep/ace/ml40x.scr (nonexistent) +++ trunk/boards/virtex4-ml403ep/ace/ml40x.scr (revision 54) @@ -0,0 +1,11 @@ +setmode -bs +setCable -p svf -file tmp_ml40x____datafile.svf +addDevice -p 1 -file xcf32p_vo48.bsd +addDevice -p 2 -file tmp_ml40x____datafile.bit +addDevice -p 3 -file xc95144xl_tq100.bsd +program -p 2 +quit + + + + Index: trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace =================================================================== --- trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace (nonexistent) +++ trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace (revision 54) @@ -0,0 +1,11 @@ +#!/bin/sh +rm -f tmp_ml40x____datafile.ace +cp -f $XILINX/xcfp/data/xcf32p_vo48.bsd . +cp -f $XILINX/xc9500xl/data/xc95144xl_tq100.bsd . +cp -f $1 tmp_ml40x____datafile.bit +$XILINX/bin/lin64/impact -batch $3/ml40x.scr +$XILINX/bin/lin64/impact -batch $3/ml40x_svf2ace.scr +rm -f tmp_ml40x____datafile.bit +rm -f tmp_ml40x____datafile.svf +rm -f $2 +mv -f tmp_ml40x____datafile.ace $2

trunk/boards/virtex4-ml403ep/ace/ml40x_bit2ace Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/boards =================================================================== --- trunk/boards (nonexistent) +++ trunk/boards (revision 54)

trunk/boards Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##