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    from Rev 84 to Rev 85
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Rev 84 → Rev 85

/zipcpu/trunk/doc/iset.html
329,7 → 329,7
<TR><TD rowspan=2>Standard</TD><TD rowspan=4>0</TD>
<TD rowspan=4 colspan=4>DR</TD>
<TD rowspan=2 colspan=5>OpCode</TD>
<TD rowspan=3 colspan=3>CND</TD><TD>0</TD>
<TD rowspan=3 colspan=3>CND</TD>
<TD>0</TD><TD colspan=18>18-bit signed immediate</TD></TR>
<TR><TD>1</TD><TD colspan=4>BR</TD><TD colspan=14>14-bit signed immediate</TD></TR>
<TR><TD>MOV</TD><TD colspan=5>5'hf</TD><TD>A</TD>
359,7 → 359,7
down so that as many bits as possible may be used to describe the immediate
value.
 
<P>As of this version of the instruction set, the instruction set now supports
<P>As of this (hopefully the last) version of the instruction set, the instruction set now supports
a compact format as well. This is the VLIW format. Using this format, two
instructions may be encoded in a single instruction word, with the instruction
encoded in the higher order bits being the "first" instruction. The three

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