OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/bench/cpp
    from Rev 69 to Rev 58
    ↔ Reverse comparison
  •

Rev 69 → Rev 58

/zippy_tb.cpp
11,7 → 11,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
79,7 → 79,7
unsigned long m_last_instruction_tickcount;
 
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
if (true) {
if (false) {
dbg_fp = fopen("dbg.txt", "w");
dbg_flag = true;
} else {
98,13 → 98,6
}
}
 
~ZIPPY_TB(void) {
if (dbg_fp)
fclose(dbg_fp);
if (m_profile_fp)
fclose(m_profile_fp);
}
 
void reset(void) {
// m_flash.debug(false);
TESTB<Vzipsystem>::reset();
136,16 → 129,14
mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
else
mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
#ifdef OPT_PIPELINED
addch( ((r == (int)(dcdA()&0x01f))
&&(dcdvalid())
addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
?'a':((c)?'<':' '));
addch( ((r == (int)(dcdB()&0x01f))
&&(dcdvalid())
addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
?'b':((c)?'<':' '));
#endif
addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
?'W':((c)?'<':' '));
214,8 → 205,9
#endif
 
#ifdef OPT_EARLY_BRANCHING
printw(" %s",
(m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)?"EB":" ");
printw(" %s%s",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
#endif
/*
236,12 → 228,12
showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
}
 
showval(ln,60, "PIC2", m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state, (m_cursor==3));
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
 
ln++;
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
showval(ln,40, "TMRC", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
 
306,13 → 298,6
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
mvprintw(ln,60,"%s",
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
?"V"
:(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
&&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
:" "));
ln++;
 
if (m_core->v__DOT__thecpu__DOT__gie)
319,16 → 304,7
attron(A_BOLD);
else
attroff(A_BOLD);
mvprintw(ln, 0, "User Registers");
mvprintw(ln, 42, "DCDR=%02x %s%s",
dcdR(),
(m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
(m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
mvprintw(ln, 62, "OPR =%02x %s%s",
m_core->v__DOT__thecpu__DOT__opR,
(m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
(m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
ln++;
mvprintw(ln, 0, "User Registers"); ln++;
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
346,48 → 322,34
 
showreg(ln, 0, "uR12", 28, (m_cursor==40));
showreg(ln,20, "uSP ", 29, (m_cursor==41));
mvprintw(ln,40, "%cuCC :%s %s%s%s%s%s%s%s",
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ",
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ",
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
mvprintw(ln,60,"%s",
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
?"V"
:(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
&&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
:" "));
 
attroff(A_BOLD);
ln+=1;
 
#ifdef OPT_SINGLE_FETCH
ln++;
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
(m_core->v__DOT__thecpu__DOT__pf_addr),
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
" ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
(m_core->v__DOT__wb_data)); ln++;
ln+=2;
#else
 
mvprintw(ln, 0, "PFCACH: v=%08x, %s, tag=%08x, pf_pc=%08x, lastpc=%08x",
m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
m_core->v__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
 
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
ln++;
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
396,7 → 358,7
(m_core->v__DOT__thecpu__DOT__pf_addr),
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
(pfstall())?"STL":" ",
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
(m_core->v__DOT__wb_data)); ln++;
#endif
 
422,7 → 384,7
ln++;
#endif
 
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
(m_core->o_wb_cyc)?"CYC":" ",
(m_core->o_wb_stb)?"STB":" ",
431,8 → 393,7
(m_core->o_wb_data),
(m_core->i_wb_ack)?"ACK":" ",
(m_core->i_wb_stall)?"STL":" ",
(m_core->i_wb_data),
(m_core->i_wb_err)?"(ER!)":" "); ln+=2;
(m_core->i_wb_data)); ln+=2;
#ifdef OPT_PIPELINED_BUS_ACCESS
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
(m_core->v__DOT__thecpu__DOT__mem_ce),
447,22 → 408,26
(m_core->v__DOT__thecpu__DOT__master_ce),
(mem_pipe_stalled()),
(!m_core->v__DOT__thecpu__DOT__op_pipe),
#ifdef OPT_PIPELINED_BUS_ACCESS
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
#else
(m_core->v__DOT__thecpu__DOT__mem_busy)
#endif
);
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
(dcdvalid()),
(m_core->v__DOT__thecpu__DOT__dcdvalid),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(m_core->v__DOT__thecpu__DOT__dcdM),
(!((m_core->v__DOT__thecpu__DOT__dcdOp
^m_core->v__DOT__thecpu__DOT__opn)&1)),
((int)(dcdB()&0x01f)
(m_core->v__DOT__thecpu__DOT__dcdB
== m_core->v__DOT__thecpu__DOT__op_B),
(m_core->v__DOT__thecpu__DOT__dcdI
(m_core->v__DOT__thecpu__DOT__r_dcdI
== m_core->v__DOT__thecpu__DOT__r_opI),
(m_core->v__DOT__thecpu__DOT__dcdI+1
(m_core->v__DOT__thecpu__DOT__r_dcdI+1
== m_core->v__DOT__thecpu__DOT__r_opI));
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
(m_core->v__DOT__thecpu__DOT__dcdI),
(m_core->v__DOT__thecpu__DOT__r_dcdI),
(m_core->v__DOT__thecpu__DOT__r_opI));
#endif
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
472,18 → 437,11
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
(m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
#else
printw(" A:xx B:xx");
#endif
printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
 
 
showins(ln, "I ",
#ifdef OPT_PIPELINED
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
#else
1,
#endif
m_core->v__DOT__thecpu__DOT__pf_valid,
//m_core->v__DOT__thecpu__DOT__instruction_gie,
m_core->v__DOT__thecpu__DOT__gie,
492,13 → 450,10
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
showins(ln, "Dc",
dcd_ce(), dcdvalid(),
m_core->v__DOT__thecpu__DOT__dcd_ce,
m_core->v__DOT__thecpu__DOT__dcdvalid,
m_core->v__DOT__thecpu__DOT__dcd_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__dcd_stalled,
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
509,7 → 464,7
mvprintw(ln-1,10,"M");
 
showins(ln, "Op",
op_ce(),
m_core->v__DOT__thecpu__DOT__op_ce,
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
528,11 → 483,7
m_core->v__DOT__thecpu__DOT__alu_ce,
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__alu_stall,
#else
0,
#endif
alu_pc()); ln++;
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
mvprintw(ln-1,10,"W");
610,15 → 561,12
printf("mem_cyc_gbl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
printf("mem_cyc_lcl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
printf("opvalid = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
printf("dcdvalid = %d\n", dcdvalid()?1:0);
printf("dcd_ce = %d\n", dcd_ce()?1:0);
#ifdef OPT_PIPELINED
printf("dcdvalid = %d\n", m_core->v__DOT__thecpu__DOT__dcdvalid);
printf("dcd_ce = %d\n", m_core->v__DOT__thecpu__DOT__dcd_ce);
printf("dcd_stalled = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
#endif
printf("pf_valid = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
#ifdef OPT_EARLY_BRANCHING
// printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
#endif
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch);
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb);
 
exit(-2);
}
749,14 → 697,7
attron(A_BOLD);
else
attroff(A_BOLD);
mvprintw(ln, 0, "User Registers");
mvprintw(ln, 42, "DCDR=%02x %s",
dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
mvprintw(ln, 62, "OPR =%02x %s%s",
m_core->v__DOT__thecpu__DOT__opR,
(m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
(m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
ln++;
mvprintw(ln, 0, "User Registers"); ln++;
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
793,11 → 734,7
ln+=3;
 
showins(ln, "I ",
#ifdef OPT_PIPELINED
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
#else
1,
#endif
m_core->v__DOT__thecpu__DOT__pf_valid,
m_core->v__DOT__thecpu__DOT__gie,
0,
805,17 → 742,14
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
showins(ln, "Dc",
dcd_ce(), dcdvalid(),
m_core->v__DOT__thecpu__DOT__dcd_ce,
m_core->v__DOT__thecpu__DOT__dcdvalid,
m_core->v__DOT__thecpu__DOT__dcd_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__dcd_stalled,
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
 
showins(ln, "Op",
op_ce(),
m_core->v__DOT__thecpu__DOT__op_ce,
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
825,14 → 759,9
m_core->v__DOT__thecpu__DOT__alu_ce,
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__alu_stall,
#else
0,
#endif
alu_pc()); ln++;
}
 
void tick(void) {
int gie = m_core->v__DOT__thecpu__DOT__gie;
/*
860,7 → 789,7
(m_core->o_dbg_data),
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
(dcdvalid())?"DCDV ":"",
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":" ",
882,11 → 811,11
 
if (dbg_fp)
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
dcd_ce(),
m_core->v__DOT__thecpu__DOT__dcd_ce,
m_core->v__DOT__thecpu__DOT__dcd_pc,
op_ce(),
m_core->v__DOT__thecpu__DOT__op_ce,
op_pc(),
dcdA()&0x01f,
m_core->v__DOT__thecpu__DOT__dcdA,
m_core->v__DOT__thecpu__DOT__opR,
m_core->v__DOT__cmd_halt,
m_core->v__DOT__cpu_halt,
899,7 → 828,7
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
m_core->v__DOT__pic_interrupt,
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
m_core->v__DOT__thecpu__DOT__wr_reg_id,
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
977,30 → 906,12
m_core->v__DOT__thecpu__DOT__upc,
m_core->v__DOT__thecpu__DOT__pf_pc);
} if (dbg_fp) {
#ifdef NEW_PREFETCH_VERSION
fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s\n",
(m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
m_core->v__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)
&&(dcdvalid())
&&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
m_core->v__DOT__thecpu__DOT__instruction_pc,
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
(m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ");
#endif
dbgins("Dc - ",
dcd_ce(), dcdvalid(),
dbgins("Dc - ", m_core->v__DOT__thecpu__DOT__dcd_ce,
m_core->v__DOT__thecpu__DOT__dcdvalid,
m_core->v__DOT__thecpu__DOT__dcd_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__dcd_stalled,
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1);
dbgins("Op - ",
op_ce(),
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
1031,11 → 942,7
m_core->v__DOT__thecpu__DOT__alu_ce,
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
#ifdef OPT_PIPELINED
m_core->v__DOT__thecpu__DOT__alu_stall,
#else
0,
#endif
alu_pc());
 
}
1068,48 → 975,9
return m_core->v__DOT__thecpu__DOT__op_pc-1;
}
 
bool dcd_ce(void) {
#ifdef OPT_PIPELINED
return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
#else
return (m_core->v__DOT__thecpu__DOT__pf_valid);
#endif
} bool dcdvalid(void) {
return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
}
bool pfstall(void) {
return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
||(m_core->v__DOT__cpu_stall));
}
unsigned dcdR(void) {
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
}
unsigned dcdA(void) {
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
}
unsigned dcdB(void) {
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
}
 
bool op_ce(void) {
#ifdef OPT_PIPELINED
return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
#else
// return (dcdvalid())&&(opvalid())
// &&(m_core->v__DOT__thecpu__DOT__op_stall);
return dcdvalid();
#endif
} bool opvalid(void) {
return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
}
 
bool mem_busy(void) {
// return m_core->v__DOT__thecpu__DOT__mem_busy;
#ifdef OPT_PIPELINED
return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
#else
return 0;
#endif
}
 
bool mem_stalled(void) {
1119,17 → 987,11
wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
 
#ifdef OPT_PIPELINED_BUS_ACCESS
//a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
a = mem_pipe_stalled();
b = (!m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
#else
a = false;
b = false;
#endif
a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
b = (m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
d = ((wr_write_pc)||(wr_write_cc));
c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
&&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
&&((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)==op_gie)
&&d);
d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1146,7 → 1008,7
}
 
#ifdef OPT_PIPELINED_BUS_ACCESS
bool mem_pipe_stalled(void) {
int mem_pipe_stalled(void) {
int r = 0;
r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1333,10 → 1195,8
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
#ifdef OPT_PIPELINED
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
#endif
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
}
break;
1347,10 → 1207,8
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
#ifdef OPT_PIPELINED
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
#endif
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
}
break;
1357,7 → 1215,7
case 32: tb->m_core->v__DOT__pic_data = v; break;
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1509,10 → 1367,9
noecho();
keypad(stdscr, true);
 
// tb->reset();
// for(int i=0; i<2; i++)
// tb->tick();
tb->m_core->v__DOT__cmd_reset = 1;
tb->reset();
for(int i=0; i<2; i++)
tb->tick();
tb->m_core->v__DOT__cmd_halt = 0;
 
int chv = 'q';
/pdump.cpp
12,7 → 12,7
// after the fact, to get a trace of what instructions the CPU executed.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/Makefile
12,7 → 12,7
#
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
# Gisselquist Tecnology, LLC
#
################################################################################
#
36,16 → 36,15
#
all: zippy_tb
 
CXX := g++
FLAGS := -Wall -Og -g
ZASM := ../../sw/zasm/z2
RTLD := ../../rtl
INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I$(ZASM)
CXX := g++
FLAGS := -Wall -Og -g
ZASM := ../../sw/zasm
RTLD := ../../rtl
INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I../../sw/zasm
SOURCES := zippy_tb.cpp memsim.cpp twoc.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp
VLIB := /usr/share/verilator/include/verilated.cpp
RAWLIB := $(VLIB) $(RTLD)/obj_dir/Vzipsystem__ALL.a
LIBS := $(RAWLIB) -lncurses
TESTF := $(ZASM)/z.out
RAWLIB := /usr/share/verilator/include/verilated.cpp ../../rtl/obj_dir/Vzipsystem__ALL.a
LIBS := $(RAWLIB) -lncurses
TESTF := ../../sw/zasm/z.out
DHRYSTONEF := ../asm/zipdhry.z
 
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h
52,9 → 51,6
zippy_tb: $(RTLD)/cpudefs.h
$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@
 
div_tb: div_tb.cpp twoc.cpp $(VLIB) $(RTLD)/obj_dir/Vdiv__ALL.a testb.h
$(CXX) $(FLAGS) $(INCS) div_tb.cpp twoc.cpp $(VLIB) $(RTLD)/obj_dir/Vdiv__ALL.a -o $@
 
pdump: pdump.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp
pdump: $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h twoc.cpp
$(CXX) $(FLAGS) $(INCS) pdump.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp twoc.cpp -o $@
/testb.h
8,7 → 8,7
// begin exercised in Verilator.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/memsim.cpp
11,7 → 11,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/memsim.h
11,7 → 11,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/twoc.h
10,7 → 10,7
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/twoc.cpp
10,7 → 10,7
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//

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