Subversion Repositories zipcpu
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Zip CPU ISA -CheatSheet
+Next Generation Zip CPU ISA
+| 31 | + | 27 | + | 23 | + | 19 | + | 15 | + | 11 | + | 7 | + | 3 | 0 | +CC | Extra | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1'Zip | 3'Cond | ||||||||||||||||||||||||||||||||
| 0 | Any | 000 | Always | Y | |||||||||||||||||||||||||||||
| 001 | Less-Than | N | |||||||||||||||||||||||||||||||
| 010 | On Zero | ||||||||||||||||||||||||||||||||
| 011 | Not Zero | ||||||||||||||||||||||||||||||||
| 100 | Greater Than | ||||||||||||||||||||||||||||||||
| 101 | Greater Than/Equal | ||||||||||||||||||||||||||||||||
| 110 | On Carry (unsigned overflow) | ||||||||||||||||||||||||||||||||
| 111 | On (signed) oVerflow | ||||||||||||||||||||||||||||||||
| 0 | +4'Reg | +5'OpCod | +Cond | +19'Op-B | +CC | ||||||||||||||||||||||||||||
| Reg | 0xxxx | Any | ALU operation | (y) | |||||||||||||||||||||||||||||
| 0 | 18-bit Immediate | +||||||||||||||||||||||||||||||||
| 1 | B-Reg | 14-bit Immediate | |||||||||||||||||||||||||||||||
| Reg | 01001 | 0 | 2'hx | LDI( | N | ||||||||||||||||||||||||||||
| Reg | 01111 | +AR | +Reg | +BR | +Move, 13-bit Imm | +N | |||||||||||||||||||||||||||
| Reg | 1000x | +Compare/Test (ALU) | +Y | ||||||||||||||||||||||||||||||
| Reg | 1001w | +Memory operation, w=write, Op-B=address | N | ||||||||||||||||||||||||||||||
| Reg | 1010x | +IDIV(U/S), RA=RA/(RB+Imm), uses alt-A | Y | ||||||||||||||||||||||||||||||
| 3'h7 | 11000 | NOOP | +N | ||||||||||||||||||||||||||||||
| 11001 | Break | ||||||||||||||||||||||||||||||||
| 11010 | Bus Lock | ||||||||||||||||||||||||||||||||
| Reg | 11fff | Floating Point operation | Y | ||||||||||||||||||||||||||||||
| Reg | 1011 | Load Immediate (23 bit Immediate, unconditional) | N | ||||||||||||||||||||||||||||||
| 1 | Any | x | 00 | Always | +|||||||||||||||||||||||||||||
| 01 | Less Than | ||||||||||||||||||||||||||||||||
| 10 | On Zero | ||||||||||||||||||||||||||||||||
| 11 | Not Zero | ||||||||||||||||||||||||||||||||
| 1 | 1 | +2'bxx | Apply condition to second half | +||||||||||||||||||||||||||||||
| 1 | +4'Reg | +5'OpCod | +Any | +0 | 4'Imm | +4'Reg | +5'OpCod | +0 | 4'Imm | +||||||||||||||||||||||||
| 1 | 4'Reg | +1 | 4'Reg | ||||||||||||||||||||||||||||||
| ALU Operation | CC | |
|---|---|---|
| A-0000 | SUB (Pairs w/ CMP) | Y |
| A-0001 | AND (Pairs w/ OR, and TST) | |
| A-0010 | ADD (Pairs w/ SUB) | |
| A-0011 | OR (Pairs w/ AND) | |
| A-0100 | XOR | |
| A-0101 | LSR | |
| A-0110 | LSL (Pairs w/ ROL) | |
| A-0111 | ASR (Pairs w/ LSR) | |
| A-1000 | MPY | |
| A-1001 | LDILO | N |
| A-1010 | MPYUHI | Y |
| A-1011 | MPYSHI | |
| A-1100 | BREV | |
| A-1101 | ||
| A-1110 | ||
| A-1111 | N | |
| FP Operation | CC | ||
|---|---|---|---|
| F-000 | FPADD | Floating point Add | Y |
| F-001 | FPSUB | Floating point Subtract & Compare | |
| F-010 | FPMPY | Floating point multiply | |
| F-011 | FPDIV | Floating point divide | |
| F-100 | FPI2F | Convert to floating point | |
| F-101 | FPF2I | Convert to integer | |
| F-110 | LH | Load Word | |
| F-111 | SH | Store Word | |
| 00000 | SUB | 10000 | CMP |
| 00001 | AND | 10001 | TEST |
| 00010 | ADD | 10010 | LOD |
| 00011 | OR | 10011 | STO |
| 00100 | XOR | 10100 | DIVU |
| 00101 | LSR | 10101 | DIVS |
| 00110 | LSL | 10110 | LDI |
| 00111 | ASR | 10111 | |
| 01000 | MPY | 11000 | FPADD |
| 01001 | LDILO | 11001 | FPSUB |
| 01010 | MPYUHI | 11010 | FPMPY |
| 01011 | MPYSHI | 11011 | FPDIV |
| 01100 | BREV | 11100 | FPI2F |
| 01101 | MOV | 11101 | FPF2I |
| 01110 | LB | 11110 | LH |
| 01111 | SB | 11111 | SH |
+
| 31 | 27 | @@ -11,12 +140,8 @@ | 11 | 7 | 3 | 0 | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 4'DR | 5'OpCode | 3'Cond | 0 | 18'Immediate | ||||||||||||||||||||||||||
| 0 | 4'DR | 5'OpCode | 3'Cond | 0 | 18'Immediate | ||||||||||||||||||||||||||
| 1 | B-Reg | 14'Immediate | |||||||||||||||||||||||||||||
| 4'DR | MOV | -3'Cond | A | B-Reg | B | 13'Immediate | |||||||||||||||||||||||||
| 4'DR | LDI | 23'Immediate | |||||||||||||||||||||||||||||
| 1 | 4'DR | 3'OpCode | A | 7'Op-B | @@ -25,7 +150,6 @@|||||||||||||||||||||||||||
| Normal instructions | Compressed | ||||
| 00000 | SUB | 10000 | CMP | 000 | SUB |
| 00001 | AND | 10001 | TEST | 001 | AND |
| 00010 | ADD | 10010 | LW | 010 | ADD |
| 00101 | LSR | 10101 | SH | 101 | SW |
| 00110 | LSL | 10110 | LB | 110 | LDI |
| 00111 | ASR | 10111 | SB | 111 | MOV |
| 01000 | BREV | 11000 | LDI | Reserved for FPU | |
| 01000 | BREV | 11000 | LDI | ||
| 01001 | LDILO | 11001 | |||
| 01010 | MPYUHI | Special Insn | 11010 | FPADD | |
| 01010 | MPYUHI | 11010 | FPADD | ||
| 01011 | MPYSHI | 11011 | FPSUB | ||
| 01100 | MPY | 11100 | BREAK | 11100 | FPMPY |
| 01101 | MOV | 11101 | LOCK | 11101 | FPDIV |
| 01110 | DIVU | 11110 | SIM | 11110 | FPI2F |
| 01111 | DIVS | 11111 | NOOP | 11111 | FPF2I |
| 01100 | MPY | 11100 | FPMPY | 11100 | BREAK |
| 01101 | MOV | 11101 | FPDIV | 11101 | LOCK |
| 01110 | DIVU | 11110 | FPI2F | 11110 | SIM |
| 01111 | DIVS | 11111 | FPF2I | 11111 | NOOP |
ASSEMBLER SUPPORTED DERIVED INSTRUCTIONS
-| Source | Derived Instructions |
|---|---|
| ADD | BRA, BLT, BZ, BC, BV, BGE, BNZ, BNC, BUSY |
| OR | RTU, WAIT, HALT, STEP |
| AND | TRAP |
| XOR | NOT |
| MOV | (Indirect) JMP, RETN |
| LW | LJMP |
| BREV | CLR |
| Multiple | JSR, LJSR, NEG, SEXTH, SEXTB |
COMPRESSED INSTRUCTION SET (CIS) EXCEPTIONS
-The CIS LDI instruction uses an 8'bit signed immediate, not 7-bit (-128 to 127). +
VLIW
+The VLIW instructions take 3-bits only for their opcode. They are designed +to use only the most used opcodes. +
LDI will use all opcode bits, and the immediate field will be dedicated to + its immediate, allowing us to load any 8-bit signed constant + (-128 to 127).
MOV will use all opcode bits, and the extra bit selecting reg/imm will be extended to be an immediate bit, so that we can have any 4'bit register offset (-8 to 7) -
To make this more usable, the compressed LW/SW instructions will assume the - register is SP if no register is given. This will allow compressed - accesses to stack offsets by between -64 to 63. +
To make this more usable, the LOD/STO instructions will assume the register + is SP if no register is given. This will allow us to offset the stack + by anything between -64 to 63. Useful enough to get just about + anything.
SIM Codes
SIM and NOOP instructions are both 32-bit instructions, and both take an 18-bit immediate. @@ -74,14 +190,34 @@ simulation (if the CPU is run within a simulation). The CPU will create an illegal instruction on any SIM opcode outside of the simulator, and ignore any NOOP instruction--no matter what - the immediate value. + the immediate. Particular immediate values include:
-
-
- OUT/SOUT: -
- NEXIT/SEXIT: with an 8-bit (signed) exit code +
- SIMEXIT: with an 8-bit (signed) exit code
- SIMNOOP: useful for testing if the simulator is present. Will cause an ILLegal instruction if the simulator is not present, but ignored otherwise. This will be the immediate value of zero. -
- NDUMP/SDUMP: dump the CPU state (all the registers) to the output +
- SIMDUMP: dump the CPU state (all the registers) to the output +
- (Console read/write can be done via UART, so not necessary here.)
8-bit bytes
+This particular change is designed to create support for 8-bit bytes. + Specifically, we added support for LH, SH, LB, and SB instructions + (Load and store 16-bits, or load and store 8-bits.) +
As a consequence, the bottom 2-bits of any address no longer traverse the + bus. +
Together
+While the VLIW instruction set works well without this change, this +change renders the 3'bit register offsets difficult to use. Two examples: +-
+
- The original VLIW allowed a JSR instruction: MOV 1(PC),R0, LOD(PC),PC. The + new version would need to be replaced with MOV 4(PC),R0 and LOD(PC),PC, + but 4 doesn't fit in 3-signed bits. +
- Further, a 3'bit offset to a LOD or STO instruction makes no sense. +
instruction set has demonstrated an amazing versatility. I will contend |
therefore and for anyone who will listen, that this instruction set |
offers a full and complete capability for whatever a user might wish |
to do with the only exception being accelerated floating-point support. |
to do with two exceptions: bytewise character access and accelerated |
floating-point support. |
\item The burst load/store approach using the wishbone pipelining mode is |
novel, and can be used to greatly increase the speed of the processor. |
\item The novel approach to interrupts greatly facilitates the development of |
At the same time, if most modern systems handle interrupt vectoring in |
software anyway, why maintain complicated hardware support for it? |
|
\item My goal of a high rate of instructions per clock may not be the proper |
measure of this CPU. For example, if instructions are being read from a |
SPI flash device, such as is common among FPGA implementations, these |
same instructions may suffer stalls of between 64 and 128 cycles per |
instruction just to read the instruction from the flash. Executing the |
instruction in a single clock cycle is no longer the appropriate |
measure. At the same time, it should be possible to use the DMA |
peripheral to copy instructions from the FLASH to a temporary memory |
location, after which they may be executed at a single instruction |
cycle per access again. |
|
\item Both GCC and binutils back ends exist for the ZipCPU. |
\item As of this version of the CPU, a newlib veresion of the C--library |
now exists. |