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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
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/zipcpu/trunk/doc
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/gfx/topng.sh
5,3 → 5,5
convert cpu.png -trim cpu.png |
gs $GSFLAGS -g640x480 -sOutputFile=system.png -r60 -- system.eps |
convert system.png -trim system.png |
gs $GSFLAGS -g640x480 -sOutputFile=regset.png -r60 -- regset.eps |
convert regset.png -trim regset.png |
/gfx/system.png
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/gfx/cpu.png
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/iset.html
1,6 → 1,8
<HTML><HEAD><TITLE>Zip CPU Instruction Set</TITLE></HEAD><BODY> |
<H1 align=center>Zip CPU Goals</H1> |
<P>The original goal of the ZIP CPU was a simple CPU. For this reason, |
<P>The original goal of the ZIP CPU was to be a very simple CPU. You might |
think of it as a poor man's alternative to the OpenRISC architecture. |
For this reason, |
all instructions have been designed to be as simple as possible, and |
are all designed to be executed in one instruction cycle per |
instruction, barring pipeline stalls. This has resulted in the choice |
261,7 → 263,7
<TH colspan=8>23..16</TH> |
<TH colspan=8>15..8</TH> |
<TH colspan=8>7..0</TH> |
<TH rowspan=2>Sets CC? (Y/N)</TH></TR> |
<TH rowspan=2>Sets CC?</TH></TR> |
<TR><!-- Opcode --> |
<TD> </TD><TD> </TD><TD> </TD><TD> </TD> |
<TD> </TD><TD> </TD><TD> </TD><TD> </TD> |
278,7 → 280,7
</TR> |
<TR><TH>CMP(Sub)</TH><TD colspan=4>4'h0</TD> |
<TD colspan=4>Data Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Operand B</TD><TD align=center rowspan=2>Y</TD></TR> |
<TD colspan=21>Operand B</TD><TD align=center rowspan=2>Yes</TD></TR> |
<TR><TH>BTST(And)</TH><TD colspan=4>4'h1</TD> |
<TD colspan=4>Data Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Operand B</TD></TR> |
287,21 → 289,21
<TD colspan=1>A-Map</TD> |
<TD colspan=4>B-Reg</TD> |
<TD colspan=1>B-Map</TD> |
<TD colspan=15>+Immediate</TD><TD align=center rowspan=2>N</TD></TR> |
<TD colspan=15>+Immediate</TD><TD align=center rowspan=10>No</TD></TR> |
<TR><TH>LODI</TH><TD colspan=4>4'h3</TD><TD colspan=4>Result Reg</TD> |
<TD colspan=24>24'bit Signed Immediate</TD></TR> |
<TR><TH>NOOP</TH><TD colspan=4>4'h4</TD><TD colspan=4>4'he</TD> |
<TD colspan=24>24'h00</TD><TD align=center>N</TD></TR> |
<TD colspan=24>24'h00</TD></TR> |
<TR><TH>BREAK</TH><TD colspan=4>4'h4</TD><TD colspan=4>4'he</TD> |
<TD colspan=24>24'h01</TD><TD align=center>N</TD></TR> |
<TD colspan=24>24'h01</TD></TR> |
<TR><TH>LODIHI</TH><TD colspan=4>4'h4</TD><TD colspan=4>4'hf</TD> |
<TD colspan=3>Conditions</TD> |
<TD>1'b1</TD><TD colspan=4>Result Reg</TD> |
<TD colspan=16>16-bit Immediate</TD><TD align=center>N</TD></TR> |
<TD colspan=16>16-bit Immediate</TD></TR> |
<TR><TH>LODILO</TH><TD colspan=4>4'h4</TD><TD colspan=4>4'hf</TD> |
<TD colspan=3>Conditions</TD> |
<TD>1'b0</TD><TD colspan=4>Result Reg</TD> |
<TD colspan=16>16-bit Immediate</TD><TD align=center>N</TD></TR> |
<TD colspan=16>16-bit Immediate</TD></TR> |
<!-- |
<TR><TH>LODIB</TH><TD colspan=4>4'h4</TD><TD colspan=4>4'hf</TD> |
<TD colspan=3>Conditions</TD> |
313,31 → 315,20
<TR><TH><FONT color=#444444><em>16-b MPY</em></FONT></TH><TD colspan=4>4'h4</TD> |
<TD colspan=4>Result Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21><font color=#444444>Operand |
B (<em>Reserved for</em>)</font></TD> |
<TD align=center>N</TD></TR> |
<TR><TH rowspan=2>ROL</TH><TD colspan=4 rowspan=2>4'h5</TD> |
<TD colspan=4 rowspan=2>Result Reg</TD> |
<TD colspan=3 rowspan=2>Conditions</TD> |
<TD colspan=2>2'b11</TD> |
<TD colspan=4>Operand Reg</TD> |
<TD colspan=6><em>6'h00, Unused/Reserved</em></TD> |
<TD>1'b0</TD> |
<TD colspan=8>Immediate</TD><TD align=center>N</TD></TR> |
<TR><!-- --> |
<TD colspan=1>1'b0</TD> |
<TD colspan=5>Rotate amount</TD> |
<TD colspan=6><em>6'h00, Unused/Reserved</em></TD> |
<TD>1'b0</TD> |
<TD colspan=8>Immediate</TD><TD align=center>N</TD></TR> |
B (<em>Reserved for</em>)</font></TD></TR> |
<TR><TH>ROL</TH><TD colspan=4>4'h5</TD> |
<TD colspan=4>Result Reg</TD> |
<TD colspan=3>Conditions</TD> |
<TD colspan=21>Operand B, truncated to 5 bits</TD></TR> |
<TR><TH>LOD</TH><TD colspan=4>4'h6</TD> |
<TD colspan=4>Resulting Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Address: Register+Immediate, or Immediate</TD><TD align=center rowspan=2>N</TD></TR> |
<TD colspan=21>Address: Register+Immediate, or Immediate</TD></TR> |
<TR><TH>STO</TH><TD colspan=4>4'h7</TD> |
<TD colspan=4>Data Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Address: Register+Immediate, or Immediate</TD></TR> |
<TR><TH>SUB</TH><TD colspan=4>4'h8</TD> |
<TD colspan=4>Result Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Operand B</TD><TD rowspan=8 align=center>Y</TD></TR> |
<TD colspan=21>Operand B</TD><TD rowspan=8 align=center>Yes</TD></TR> |
<TR><TH>AND</TH><TD colspan=4>4'h9</TD> |
<TD colspan=4>Result Reg</TD><TD colspan=3>Conditions</TD> |
<TD colspan=21>Operand B</TD></TR> |
380,10 → 371,11
<TR><TD valign=top>CLR Rx</TD><TD>LDI $0,Rx</TD><TD>Clears Rx, leaves flags untouched. This instruction cannot be conditional.</TD></TR> |
<TR><TD valign=top>EXCH.W Rx</TD><TD>ROL $16,Rx</TD><TD valign=top>Exchanges the top and bottom 16'bit words of Rx</TD></TR> |
<TR><TD valign=top>HALT</TD><TD>Or $SLEEP,CC</TD><TD valign=top>Executed while in interrupt mode. In user mode this is simply a wait until interrupt instructioon.</TD></TR> |
<TR><TD valign=top>INT</TD><TD>AND $!GIE,CC</TD><TD>Without setting an |
interrupt flag or trap vector, the O/S might not know what to do with |
this instruction. Therefore the trap version is recommended<TD></TR> |
<TR><TD valign=top>IRET</TD><TD>OR $GIE,CC</TD><TD></TD></TR> </TD></TR> |
<TR><TD valign=top>INT</TD><TD>LDI $0,CC</TD><TD>Since we're using |
the CC register as a trap vector as well, this executes |
TRAP #0.</TD></TR> |
<TR><TD valign=top>IRET</TD><TD>OR $GIE,CC</TD><TD>Also an RTU instruction |
(Return to Userspace)</TD></TR> |
<TR><TD valign=top>JMP R6+$Addr</TD><TD>MOV $Addr(R6),PC</TD><TD> </TD></TR> |
<TR><TD valign=top rowspan=2>JSR PC+$Addr</TD><TD> |
SUB $1,SP<BR> |
418,7 → 410,8
the bus, so it therefore takes more work to do.<P>Note that in |
this example, $Addr is a byte-wise address, where all other addresses |
are 32-bit wordlength addresses. For this reason, we needed to |
drop the bottom two bits.</TD></TR> |
drop the bottom two bits. This also limits the address space |
of character accesses from 16 MB down to 4MB.</TD></TR> |
<TR><TD valign=top>LSL $1,Rx<BR>LSLC $1,Ry</TD> |
<TD>LSL $1,Ry<BR> |
LSL $1,Rx<BR> |
477,7 → 470,9
STO Ry,(Ra)</TD><TD>This CPU and it's bus are <em>not</em> optimized |
for byte-wise operations.<P>Note that in this example, $addr is a |
byte-wise address, whereas in all of our other examples it is a |
32-bit word address. Further, this instruction implies a byte ordering, |
32-bit word address. This also limits the address space |
of character accesses from 16 MB down to 4MB.F |
Further, this instruction implies a byte ordering, |
such as big or little endian.</TD></TR> |
<TR><TD valign=top>SWAP Rx,Ry</TD><TD> |
XOR Ry,Rx<BR> |