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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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    /zipcpu/trunk/rtl/core
    from Rev 69 to Rev 65
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Rev 69 → Rev 65

/idecode.v File deleted
/div.v File deleted
/idecode_deprecated.v File deleted
/pfcache.v File deleted
/cpuops_deprecated.v File deleted
/zipcpu.v
32,42 → 32,8
// to the spec.pdf for accurate and up to date information.)
//
//
// In general, the pipelining is controlled by three pieces of logic
// per stage: _ce, _stall, and _valid. _valid means that the stage
// holds a valid instruction. _ce means that the instruction from the
// previous stage is to move into this one, and _stall means that the
// instruction from the previous stage may not move into this one.
// The difference between these control signals allows individual stages
// to propagate instructions independently. In general, the logic works
// as:
//
//
// assign (n)_ce = (n-1)_valid && (~(n)_stall)
//
//
// always @(posedge i_clk)
// if ((i_rst)||(clear_pipeline))
// (n)_valid = 0
// else if (n)_ce
// (n)_valid = 1
// else if (n+1)_ce
// (n)_valid = 0
//
// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
// || ( (n)_valid && (n+1)_stall );
//
// and ...
//
// always @(posedge i_clk)
// if (n)_ce
// (n)_variable = ... whatever logic for this stage
//
// Note that a stage can stall even if no instruction is loaded into
// it.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
103,13 → 69,11
//
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
`define CPU_TRAP_BIT 9 // User TRAP has taken place
`define CPU_ILL_BIT 8 // Illegal instruction
`define CPU_BUSERR_BIT 10
`define CPU_TRAP_BIT 9
`define CPU_ILL_BIT 8
`define CPU_BREAK_BIT 7
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
`define CPU_STEP_BIT 6
`define CPU_GIE_BIT 5
`define CPU_SLEEP_BIT 4
// Compile time defines
117,6 → 81,11
`include "cpudefs.v"
//
//
//
// `define DEBUG_SCOPE
//
//
//
module zipcpu(i_clk, i_rst, i_interrupt,
// Debug interface
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
135,20 → 104,12
`endif
);
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
LGICACHE=6;
LGICACHE=6, AW=ADDRESS_WIDTH;
`ifdef OPT_MULTIPLY
parameter IMPLEMENT_MPY = 1;
`else
parameter IMPLEMENT_MPY = 0;
`endif
parameter IMPLEMENT_DIVIDE = 1, IMPLEMENT_FPU = 0,
IMPLEMENT_LOCK=1;
`ifdef OPT_EARLY_BRANCHING
parameter EARLY_BRANCHING = 1;
`else
parameter EARLY_BRANCHING = 0;
`endif
parameter AW=ADDRESS_WIDTH;
input i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
input i_halt, i_clear_pf_cache;
194,7 → 155,7
// Condition codes
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
reg [3:0] flags, iflags;
wire [12:0] w_uflags, w_iflags;
wire [10:0] w_uflags, w_iflags;
reg trap, break_en, step, gie, sleep;
`ifdef OPT_ILLEGAL_INSTRUCTION
reg ill_err_u, ill_err_i;
202,9 → 163,6
wire ill_err_u, ill_err_i;
`endif
reg ibus_err_flag, ubus_err_flag;
wire idiv_err_flag, udiv_err_flag;
wire ifpu_err_flag, ufpu_err_flag;
wire ihalt_phase, uhalt_phase;
 
// The master chip enable
wire master_ce;
215,9 → 173,9
// Variable declarations
//
reg [(AW-1):0] pf_pc;
reg new_pc;
reg new_pc, op_break;
wire clear_pipeline;
assign clear_pipeline = new_pc || i_clear_pf_cache;
assign clear_pipeline = new_pc || i_clear_pf_cache; // || op_break;
 
wire dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
234,25 → 192,33
//
//
reg opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
reg opvalid_div, opvalid_fpu;
wire op_stall, dcd_ce, dcd_phase;
wire [3:0] dcdOp;
wire [4:0] dcdA, dcdB, dcdR;
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
wire [3:0] dcdF;
wire dcdR_wr, dcdA_rd, dcdB_rd,
dcdALU, dcdM, dcdDV, dcdFP,
dcdF_wr, dcd_gie, dcd_break, dcd_lock;
reg r_dcdvalid;
wire dcdvalid;
wire [(AW-1):0] dcd_pc;
wire [31:0] dcdI;
wire dcd_zI; // true if dcdI == 0
wire op_stall, dcd_ce;
reg [3:0] dcdOp;
reg [4:0] dcdA, dcdB;
reg dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
reg [3:0] dcdF;
reg dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
dcdM, dcdF_wr, dcd_gie, dcd_break;
reg [(AW-1):0] dcd_pc;
reg [23:0] r_dcdI;
`ifdef OPT_SINGLE_CYCLE
reg dcd_zI; // true if dcdI == 0
`endif
wire dcdA_stall, dcdB_stall, dcdF_stall;
 
wire dcd_illegal;
wire dcd_early_branch;
`ifdef OPT_PRECLEAR_BUS
reg dcd_clear_bus;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
reg dcd_illegal;
`endif
`ifdef OPT_EARLY_BRANCHING
reg dcd_early_branch_stb, dcd_early_branch;
reg [(AW-1):0] dcd_branch_pc;
`else
wire dcd_early_branch_stb, dcd_early_branch;
wire [(AW-1):0] dcd_branch_pc;
`endif
 
 
//
271,21 → 237,22
wire [31:0] w_opA, w_opB;
wire [31:0] opA_nowait, opB_nowait, opA, opB;
reg opR_wr, opR_cc, opF_wr, op_gie;
wire [12:0] opFl;
wire [10:0] opFl;
reg [5:0] r_opF;
wire [7:0] opF;
reg [2:0] opF_cp;
wire op_ce, op_phase;
wire op_ce;
// Some pipeline control wires
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
reg opA_alu, opA_mem;
reg opB_alu, opB_mem;
`endif
`ifdef OPT_PRECLEAR_BUS
reg op_clear_bus;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
reg op_illegal;
`endif
reg op_break;
wire op_lock;
 
 
//
295,8 → 262,7
//
//
reg [(AW-1):0] alu_pc;
reg alu_pc_valid;
wire alu_phase;
reg alu_pc_valid;;
wire alu_ce, alu_stall;
wire [31:0] alu_result;
wire [3:0] alu_flags;
321,23 → 287,8
wire [31:0] mem_data, mem_result;
reg [4:0] mem_last_reg; // Last register result to go in
 
wire div_ce, div_error, div_busy, div_valid;
wire [31:0] div_result;
wire [3:0] div_flags;
 
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(set_cond);
 
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
wire [31:0] fpu_result;
wire [3:0] fpu_flags;
 
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(set_cond);
 
 
//
//
// PIPELINE STAGE #5 :: Write-back
367,68 → 318,37
//
// PIPELINE STAGE #2 :: Instruction Decode
// Calculate stall conditions
`ifdef OPT_PIPELINED
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
`else
assign dcd_ce = 1'b1;
`endif
`ifdef OPT_PIPELINED
assign dcd_stalled = (dcdvalid)&&(op_stall);
`else
// If not pipelined, there will be no opvalid_ anything, and the
// op_stall will be false, dcdX_stall will be false, thus we can simply
// do a ...
assign dcd_stalled = 1'b0;
`endif
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
assign dcd_stalled = (dcdvalid)&&(
(op_stall)
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
||((opvalid_mem)&&(op_wr_pc))
||((opvalid_mem)&&(opR_cc)));
//
// PIPELINE STAGE #3 :: Read Operands
// Calculate stall conditions
wire op_lock_stall;
`ifdef OPT_PIPELINED
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
// Stall if we're stopped, and not allowed to execute
// an instruction
// (~master_ce) // Already captured in alu_stall
//
assign op_stall = ((opvalid)&&(~master_ce))||(
// Stall if going into the ALU and the ALU is stalled
// i.e. if the memory is busy, or we are single
// stepping. This also includes our stalls for
// op_break and op_lock, so we don't need to
// include those as well here.
((opvalid)&&(alu_stall))
// Stall if the divide is busy, since we can't have
// two parallel stages writing back at the same time
||(div_busy)
// Same for the floating point unit
||(fpu_busy)
// stepping
((opvalid_alu)&&(alu_stall))
//
// ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
// Stall if we are going into memory with an operation
// that cannot be pipelined, and the memory is
// already busy
||((opvalid_mem)&&(mem_stalled))
)
||(dcdvalid)&&(
// Stall if we've got a read going with an
// unknown output (known w/in the memory module)
(mem_rdbusy)
// Or if we need to wait for an operand A
// to be ready to read
||(dcdA_stall)
// Likewise for B, also includes logic
// regarding immediate offset (register must
// be in register file if we need to add to
// an immediate)
||(dcdB_stall)
// Or if we need to wait on flags to work on the
// CC register
||(dcdF_stall)
);
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall))&&(~clear_pipeline);
`ifdef OPT_PIPELINED_BUS_ACCESS
||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
//
// Stall if we are going into memory with a pipeable
// operation, but the memory unit declares it is
// not going to accept any more pipeline operations
||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
`else
assign op_stall = (opvalid)&&(~master_ce);
assign op_ce = (dcdvalid);
||((opvalid_mem)&&(mem_busy))
`endif
);
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
//
// PIPELINE STAGE #4 :: ALU / Memory
443,22 → 363,12
// 4. Last case: Stall if we would otherwise move a break instruction
// through the ALU. Break instructions are not allowed through
// the ALU.
`ifdef OPT_PIPELINED
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
// Old case #3--this isn't an ALU stall though ...
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&(wr_write_cc)) // Case 3
||((opvalid)&&(op_lock)&&(op_lock_stall))
||((opvalid)&&(op_break))
||(div_busy)||(fpu_busy);
assign alu_ce = (master_ce)&&(opvalid_alu)
&&(~alu_stall)
&&(~clear_pipeline);
`else
assign alu_stall = ((~master_ce)&&(opvalid_alu))
||((opvalid_alu)&&(op_break));
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall);
`endif
||((opvalid_alu)&&(op_break)); // Case 3
assign alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
//
 
//
465,22 → 375,12
// Note: if you change the conditions for mem_ce, you must also change
// alu_pc_valid.
//
`ifdef OPT_PIPELINED
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
&&(~clear_pipeline)&&(set_cond);
`else
// If we aren't pipelined, then no one will be changing what's in the
// pipeline (i.e. clear_pipeline), while our only instruction goes
// through the ... pipeline.
assign mem_ce = (master_ce)&&(opvalid_mem)
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
&&(set_cond)&&(~mem_stalled);
`endif
`ifdef OPT_PIPELINED_BUS_ACCESS
assign mem_stalled = (~master_ce)||((opvalid_mem)&&(
(mem_pipe_stalled)
||((~op_pipe)&&(mem_busy))
||(div_busy)
||(fpu_busy)
// Stall waiting for flags to be valid
// Or waiting for a write to the PC register
// Or CC register, since that can change the
488,7 → 388,6
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&((wr_write_pc)||(wr_write_cc)))));
`else
`ifdef OPT_PIPELINED
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
(~master_ce)
// Stall waiting for flags to be valid
496,10 → 395,7
// Or CC register, since that can change the
// PC as well
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
`else
assign mem_stalled = (opvalid_mem)&&(~master_ce);
`endif
`endif
 
 
//
510,100 → 406,276
`ifdef OPT_SINGLE_FETCH
wire pf_ce;
 
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
assign pf_ce = (~dcd_stalled);
prefetch #(ADDRESS_WIDTH)
pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
instruction, instruction_pc, instruction_gie,
pf_valid, pf_illegal,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data);
 
initial r_dcdvalid = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_dcdvalid <= 1'b0;
else if (dcd_ce)
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
else if ((op_ce)||(clear_pipeline))
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
 
`else // Pipe fetch
 
`ifdef OPT_TRADITIONAL_PFCACHE
pfcache #(LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
i_clear_pf_cache,
// dcd_pc,
~dcd_stalled,
((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
? dcd_branch_pc:pf_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
pf_illegal);
`else
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
i_clear_pf_cache, ~dcd_stalled,
(new_pc)?pf_pc:dcd_branch_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
//`ifdef OPT_PRECLEAR_BUS
//((dcd_clear_bus)&&(dcdvalid))
//||((op_clear_bus)&&(opvalid))
//||
//`endif
`ifdef OPT_PRECLEAR_BUS
((dcd_clear_bus)&&(dcdvalid))
||((op_clear_bus)&&(opvalid))
||
`endif
(mem_cyc_lcl)||(mem_cyc_gbl),
pf_illegal);
assign instruction_gie = gie;
`endif
assign instruction_gie = gie;
 
initial r_dcdvalid = 1'b0;
initial dcdvalid = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline))
r_dcdvalid <= 1'b0;
if (i_rst)
dcdvalid <= 1'b0;
else if (dcd_ce)
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
else if (op_ce)
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
dcdvalid <= 1'b0;
 
`ifdef OPT_EARLY_BRANCHING
always @(posedge i_clk)
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
begin
dcd_early_branch <= 1'b0;
// First case, a move to PC instruction
if ((instruction[31:28] == 4'h2)
// Offsets of the PC register *only*
&&(instruction[19:16] == `CPU_PC_REG)
&&((instruction_gie)
||((~instruction[20])&&(~instruction[15])))
&&(instruction[23:21]==3'h0)) // Unconditional
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
end else // Next case, an Add Imm -> PC instruction
if ((instruction[31:28] == 4'ha) // Add
&&(~instruction[20]) // Immediate
&&(instruction[23:21]==3'h0)) // Always
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
end else // Next case: load Immediate to PC
if (instruction[31:28] == 4'h3)
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { instruction[23:0] };
end
end else
begin
if (dcd_ce) dcd_early_branch <= 1'b0;
dcd_early_branch_stb <= 1'b0;
end
generate
if (AW == 24)
begin
always @(posedge i_clk)
if (dcd_ce)
begin
if (instruction[31]) // Add
begin
dcd_branch_pc <= instruction_pc
+ { {(AW-20){instruction[19]}}, instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~instruction[28]) // 4'h2 = MOV
dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
else // if (instruction[28]) // 4'h3 = LDI
dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end else begin
always @(posedge i_clk)
if (dcd_ce)
begin
if (instruction[31]) // Add
begin
dcd_branch_pc <= instruction_pc
+ { {(AW-20){instruction[19]}}, instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~instruction[28]) // 4'h2 = MOV
begin
dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
end else // if (instruction[28]) // 4'h3 = LDI
begin
dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end
end endgenerate
`else // OPT_EARLY_BRANCHING
assign dcd_early_branch_stb = 1'b0;
assign dcd_early_branch = 1'b0;
assign dcd_branch_pc = {(AW){1'b0}};
`endif // OPT_EARLY_BRANCHING
 
always @(posedge i_clk)
if (dcd_ce)
begin
dcd_pc <= instruction_pc
+{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
// Record what operation we are doing
dcdOp <= instruction[31:28];
 
// Default values
dcdA[4:0] <= { instruction_gie, instruction[27:24] };
dcdB[4:0] <= { instruction_gie, instruction[19:16] };
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
dcdM <= 1'b0;
`ifdef OPT_CONDITIONAL_FLAGS
// Don't change the flags on conditional instructions,
// UNLESS: the conditional instruction was a CMP
// or TST instruction.
dcdF_wr <= ((instruction[23:21]==3'h0)
||(instruction[31:29] == 3'h0));
`else
dcdF_wr <= 1'b1;
`endif
`ifdef OPT_PRECLEAR_BUS
dcd_clear_bus <= 1'b0;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
dcd_illegal <= pf_illegal;
`endif
 
`ifdef OPT_NEW_INSTRUCTION_SET
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
dcd_ce, dcd_stalled, instruction, instruction_gie,
instruction_pc, pf_valid, pf_illegal, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcdR_cc, dcdR_pc, dcdR },
{ dcdA_cc, dcdA_pc, dcdA },
{ dcdB_cc, dcdB_pc, dcdB },
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcdR_wr,dcdA_rd, dcdB_rd,
dcd_early_branch,
dcd_branch_pc);
// Set the condition under which we do this operation
// The top four bits are a mask, the bottom four the
// value the flags must equal once anded with the mask
dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
casez(instruction[31:28])
4'h2: begin // Move instruction
if (~instruction_gie)
begin
dcdA[4] <= instruction[20];
dcdB[4] <= instruction[15];
end
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b1;
r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[14:0] == 0);
`endif
dcdF_wr <= 1'b0; // Don't write flags
end
4'h3: begin // Load immediate
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b0;
r_dcdI <= { instruction[23:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[23:0] == 0);
`endif
dcdF_wr <= 1'b0; // Don't write flags
dcdF <= 4'h8; // This is unconditional
dcdOp <= 4'h2;
end
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
`ifdef OPT_CONDITIONAL_FLAGS
// Don't write flags except for multiplies
// and then only if they are unconditional
dcdF_wr <= ((instruction[27:25] != 3'h7)
&&(instruction[23:21]==3'h0));
`else
idecode_deprecated
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
dcd_ce, dcd_stalled, instruction, instruction_gie,
instruction_pc, pf_valid, pf_illegal, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcdR_cc, dcdR_pc, dcdR },
{ dcdA_cc, dcdA_pc, dcdA },
{ dcdB_cc, dcdB_pc, dcdB },
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcdR_wr,dcdA_rd, dcdB_rd,
dcd_early_branch,
dcd_branch_pc);
// Don't write flags except for multiplies
dcdF_wr <= (instruction[27:25] != 3'h7);
`endif
r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
if (instruction[27:24] == 4'he)
begin
// NOOP instruction
dcdA_wr <= 1'b0;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b0;
dcdOp <= 4'h2;
// Might also be a break. Big
// instruction set hole here.
`ifdef OPT_ILLEGAL_INSTRUCTION
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
`endif
end else if (instruction[27:24] == 4'hf)
begin // Load partial immediate(s)
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b1;
dcdB_rd <= 1'b0;
dcdA[4:0] <= { instruction_gie, instruction[19:16] };
dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
dcdOp <= { 3'h3, instruction[20] };
end else begin
// Actual multiply instruction
r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
dcdA_rd <= 1'b1;
dcdB_rd <= (instruction[19:16] != 4'hf);
dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
end end
4'b011?: begin // LOD/STO or Load/Store
dcdF_wr <= 1'b0; // Don't write flags
dcdA_wr <= (~instruction[28]); // Write on loads
dcdA_rd <= (instruction[28]); // Read on stores
dcdB_rd <= instruction[20];
if (instruction[20])
begin
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
end else begin
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[19:0] == 0);
`endif
end
dcdM <= 1'b1; // Memory operation
`ifdef OPT_PRECLEAR_BUS
dcd_clear_bus <= (instruction[23:21]==3'h0);
`endif
end
default: begin
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
dcdA_rd <= 1'b1;
dcdB_rd <= instruction[20];
if (instruction[20])
begin
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
end else begin
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[19:0] == 0);
`endif
end end
endcase
 
 
dcd_gie <= instruction_gie;
end
always @(posedge i_clk)
if (dcd_ce)
dcd_break <= (instruction[31:0] == 32'h4e000001);
else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
dcd_break <= 1'b0;
 
`ifdef OPT_PIPELINED_BUS_ACCESS
reg [23:0] r_opI;
reg [4:0] op_B;
623,10 → 695,10
&&(dcdB == op_B) // Same address register
&&((dcdF[2:0] == opF_cp) // Same condition
||(opF_cp == 3'h0)) // or no prev condition
&&((dcdI[23:0] == r_opI)||(dcdI[23:0]==r_opI+24'h1));
&&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
r_opI <= dcdI[23:0];
r_opI <= r_dcdI;
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
op_B <= dcdB;
655,10 → 727,10
else if (dcdA_pc)
r_opA <= w_pcA_v;
else if (dcdA_cc)
r_opA <= { w_opA[31:13], (dcdA[4])?w_uflags:w_iflags };
r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
else
r_opA <= w_opA;
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
end else if (opvalid)
begin // We were going to pick these up when they became valid,
// but for some reason we're stuck here as they became
668,7 → 740,8
`endif
end
 
wire [31:0] w_opBnI, w_pcB_v;
wire [31:0] dcdI, w_opBnI, w_pcB_v;
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
generate
if (AW < 32)
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
679,13 → 752,13
assign w_opBnI = (~dcdB_rd) ? 32'h00
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
: ((dcdB_pc) ? w_pcB_v
: ((dcdB_cc) ? { w_opB[31:13], (dcdB[4])?w_uflags:w_iflags}
: ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
: w_opB)));
 
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
r_opB <= w_opBnI + dcdI;
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
else if ((opvalid)&&(
((opB_alu)&&(alu_wr))
||((opB_mem)&&(mem_valid))))
706,23 → 779,11
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
case(dcdF[2:0])
3'h0: r_opF <= 6'h00; // Always
`ifdef OPT_NEW_INSTRUCTION_SET
// These were remapped as part of the new instruction
// set in order to make certain that the low order
// two bits contained the most commonly used
// conditions: Always, LT, Z, and NZ.
3'h1: r_opF <= 6'h24; // LT
3'h2: r_opF <= 6'h11; // Z
3'h3: r_opF <= 6'h10; // NE
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
3'h5: r_opF <= 6'h20; // GE (!N)
`else
3'h1: r_opF <= 6'h11; // Z
3'h2: r_opF <= 6'h10; // NE
3'h3: r_opF <= 6'h20; // GE (!N)
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
3'h5: r_opF <= 6'h24; // LT
`endif
3'h6: r_opF <= 6'h02; // C
3'h7: r_opF <= 6'h08; // V
endcase
732,8 → 793,6
if (op_ce)
opF_cp[2:0] <= dcdF[2:0];
 
wire w_opvalid;
assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
initial opvalid = 1'b0;
initial opvalid_alu = 1'b0;
initial opvalid_mem = 1'b0;
753,25 → 812,19
// Hence, the test on dcd_stalled here. If we must
// wait until our operands are valid, then we aren't
// valid yet until then.
opvalid<= w_opvalid;
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`ifdef OPT_ILLEGAL_INSTRUCTION
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`else
opvalid_alu <= (dcdALU)&&(w_opvalid);
opvalid_mem <= (dcdM)&&(w_opvalid);
opvalid_div <= (dcdDV)&&(w_opvalid);
opvalid_fpu <= (dcdFP)&&(w_opvalid);
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`endif
end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
end else if ((~op_stall)||(clear_pipeline))
begin
opvalid <= 1'b0;
opvalid_alu <= 1'b0;
opvalid_mem <= 1'b0;
opvalid_div <= 1'b0;
opvalid_fpu <= 1'b0;
end
 
// Here's part of our debug interface. When we recognize a break
790,109 → 843,47
else if ((clear_pipeline)||(~opvalid))
op_break <= 1'b0;
 
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_op_lock, r_op_lock_stall;
 
initial r_op_lock_stall = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_op_lock_stall <= 1'b0;
else
r_op_lock_stall <= (~opvalid)||(~op_lock)
||(~dcdvalid)||(~pf_valid);
 
assign op_lock_stall = r_op_lock_stall;
 
initial r_op_lock = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_op_lock <= 1'b0;
else if ((op_ce)&&(dcd_lock))
r_op_lock <= 1'b1;
else if ((op_ce)||(clear_pipeline))
r_op_lock <= 1'b0;
assign op_lock = r_op_lock;
 
end else begin
assign op_lock_stall = 1'b0;
assign op_lock = 1'b0;
end endgenerate
 
`else
assign op_lock_stall = 1'b0;
assign op_lock = 1'b0;
`endif
 
`ifdef OPT_ILLEGAL_INSTRUCTION
always @(posedge i_clk)
if(op_ce)
`ifdef OPT_PIPELINED
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
`else
op_illegal <= (dcd_illegal)||(dcd_lock);
op_illegal <= dcd_illegal;
`endif
`endif
 
generate
if (EARLY_BRANCHING > 0)
begin
always @(posedge i_clk)
if (op_ce)
begin
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))&&(~dcd_early_branch);
opR_wr <= (dcdR_wr)&&(~dcd_early_branch);
op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
&&(dcdR[4] == dcd_gie))
&&(~dcd_early_branch);
end
end else begin
always @(posedge i_clk)
if (op_ce)
begin
// Will we write the flags/CC Register with
// our result?
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr));
// Will we be writing our results into a
// register?
opR_wr <= dcdR_wr;
op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
&&(dcdR[4] == dcd_gie));
end
end endgenerate
 
always @(posedge i_clk)
if (op_ce)
begin
opn <= dcdOp; // Which ALU operation?
// opM <= dcdM; // Is this a memory operation?
`ifdef OPT_EARLY_BRANCHING
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
`else
// Will we write the flags/CC Register with our result?
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
// Will we be writing our results into a register?
opR_wr <= dcdA_wr;
`endif
// What register will these results be written into?
opR <= dcdR;
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
opR <= dcdA;
opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
// User level (1), vs supervisor (0)/interrupts disabled
op_gie <= dcd_gie;
 
 
//
`ifdef OPT_EARLY_BRANCHING
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
`else
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
`endif
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
// op_pc <= dcd_pc;
 
`ifdef OPT_PRECLEAR_BUS
op_clear_bus <= dcd_clear_bus;
`endif
end
assign opFl = (op_gie)?(w_uflags):(w_iflags);
 
`ifdef OPT_VLIW
reg r_op_phase;
initial r_op_phase = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline))
r_op_phase <= 1'b0;
else if (op_ce)
r_op_phase <= dcd_phase;
assign op_phase = r_op_phase;
`else
assign op_phase = 1'b0;
`endif
 
// This is tricky. First, the PC and Flags registers aren't kept in
// register set but in special registers of their own. So step one
// is to select the right register. Step to is to replace that
905,7 → 896,7
// We'll create a flag here to start our coordination. Once we
// define this flag to something other than just plain zero, then
// the stalls will already be in place.
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
initial opA_alu = 1'b0;
always @(posedge i_clk)
if (op_ce)
925,7 → 916,7
always @(posedge i_clk)
if (mem_ce)
mem_last_reg <= opR;
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
assign opA = ((opA_alu)&&(alu_wr)) ? alu_result
: ( ((opA_mem)&&(mem_valid))?mem_result
: r_opA );
933,15 → 924,20
assign opA = r_opA;
`endif
 
`ifdef OPT_PIPELINED
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
`ifdef OPT_SINGLE_CYCLE
// Skip the requirement on writing back opA
// Stall on memory, since we'll always need to stall for a
// memory access anyway
((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
`else
// There are no pipeline hazards, if we aren't pipelined
assign dcdA_stall = 1'b0;
((opvalid)&&(opR_wr)&&(opR == dcdA))
||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
||((mem_rdbusy)&&(mem_last_reg == dcdA))
);
`endif
 
`ifdef OPT_PIPELINED
`ifdef OPT_SINGLE_CYCLE
always @(posedge i_clk)
if (op_ce)
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
960,8 → 956,8
assign opB = r_opB;
`endif
 
`ifdef OPT_PIPELINED
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
`ifdef OPT_SINGLE_CYCLE
// Stall on memory ops writing to my register
// (i.e. loads), or on any write to my
// register if I have an immediate offset
982,13 → 978,12
// will write to opB
||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
`else
// No stalls without pipelining, 'cause how can you have a pipeline
// hazard without the pipeline?
assign dcdB_stall = 1'b0;
((opvalid)&&(opR_wr)&&(opR == dcdB))
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
||((mem_rdbusy)&&(mem_last_reg == dcdB))
);
`endif
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])
||((dcdA_rd)&&(dcdA_cc))
||((dcdB_rd)&&(dcdB_cc)))
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
&&(opvalid)&&(opR_cc);
//
//
995,52 → 990,10
// PIPELINE STAGE #4 :: Apply Instruction
//
//
`ifdef OPT_NEW_INSTRUCTION_SET
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
(opvalid_alu), opn, opA, opB,
alu_result, alu_flags, alu_valid, alu_illegal_op);
`else
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
(opvalid_alu), opn, opA, opB,
alu_result, alu_flags, alu_valid, alu_illegal_op);
`endif
 
generate
if (IMPLEMENT_DIVIDE != 0)
begin
div thedivide(i_clk, i_rst, div_ce, opn[0],
opA, opB, div_busy, div_valid, div_error, div_result,
div_flags);
end else begin
assign div_error = 1'b1;
assign div_busy = 1'b0;
assign div_valid = 1'b0;
assign div_result= 32'h00;
assign div_flags = 4'h0;
end endgenerate
 
generate
if (IMPLEMENT_FPU != 0)
begin
//
// sfpu thefpu(i_clk, i_rst, fpu_ce,
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
// fpu_flags);
//
assign fpu_error = 1'b1;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end else begin
assign fpu_error = 1'b1;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end endgenerate
 
 
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
initial alF_wr = 1'b0;
initial alu_wr = 1'b0;
1060,26 → 1013,11
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
 
`ifdef OPT_VLIW
reg r_alu_phase;
initial r_alu_phase = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_alu_phase <= 1'b0;
else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
r_alu_phase <= op_phase;
assign alu_phase = r_alu_phase;
`else
assign alu_phase = 1'b0;
`endif
 
always @(posedge i_clk)
if ((alu_ce)||(div_ce)||(fpu_ce))
if (alu_ce)
alu_reg <= opR;
else if ((i_halt)&&(i_dbg_we))
alu_reg <= i_dbg_reg;
 
reg [31:0] dbg_val;
reg dbgv;
always @(posedge i_clk)
1113,30 → 1051,8
alu_pc_valid <= ((alu_ce)
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
 
wire bus_lock;
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_bus_lock;
initial r_bus_lock = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_bus_lock <= 1'b0;
else if ((op_ce)&&(op_lock))
r_bus_lock <= 1'b1;
else if (~opvalid_mem)
r_bus_lock <= 1'b0;
assign bus_lock = r_bus_lock;
end else begin
assign bus_lock = 1'b0;
end endgenerate
`else
assign bus_lock = 1'b0;
`endif
 
`ifdef OPT_PIPELINED_BUS_ACCESS
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
pipemem #(AW) domem(i_clk, i_rst, mem_ce,
(opn[0]), opB, opA, opR,
mem_busy, mem_pipe_stalled,
mem_valid, bus_err, mem_wreg, mem_result,
1146,7 → 1062,7
mem_ack, mem_stall, mem_err, i_wb_data);
`else // PIPELINED_BUS_ACCESS
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
memops #(AW) domem(i_clk, i_rst, mem_ce,
(opn[0]), opB, opA, opR,
mem_busy,
mem_valid, bus_err, mem_wreg, mem_result,
1190,15 → 1106,13
// Further, alu_wr includes (set_cond), so we don't need to
// check for that here either.
`ifdef OPT_ILLEGAL_INSTRUCTION
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
`else
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
`endif
// Which register shall be written?
// COULD SIMPLIFY THIS: by adding three bits to these registers,
// One or PC, one for CC, and one for GIE match
// Note that the alu_reg is the register to write on a divide or
// FPU operation.
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
// Are we writing to the CC register?
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1205,10 → 1119,7
// Are we writing to the PC?
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
// What value to write?
assign wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result)
:((mem_valid) ? mem_result
:((div_valid) ? div_result
:fpu_result));
assign wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
always @(posedge i_clk)
if (wr_reg_ce)
regset[wr_reg_id] <= wr_reg_vl;
1217,11 → 1128,14
// Write back to the condition codes/flags register ...
// When shall we write to our flags register? alF_wr already
// includes the set condition ...
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
assign w_uflags = { ufpu_err_flag, udiv_err_flag, ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ifpu_err_flag, idiv_err_flag, ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
 
 
assign wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
`ifdef OPT_ILLEGAL_INSTRUCTION
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`else
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`endif
// What value to write?
always @(posedge i_clk)
// If explicitly writing the register itself
1229,15 → 1143,13
flags <= wr_reg_vl[3:0];
// Otherwise if we're setting the flags from an ALU operation
else if ((wr_flags_ce)&&(alu_gie))
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
flags <= alu_flags;
 
always @(posedge i_clk)
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
iflags <= wr_reg_vl[3:0];
else if ((wr_flags_ce)&&(~alu_gie))
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
iflags <= alu_flags;
 
// The 'break' enable bit. This bit can only be set from supervisor
// mode. It control what the CPU does upon encountering a break
1263,11 → 1175,8
`ifdef OPT_ILLEGAL_INSTRUCTION
assign o_break = ((break_en)||(~op_gie))&&(op_break)
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
&&(~div_busy)&&(~fpu_busy)
&&(~clear_pipeline)
||((~alu_gie)&&(bus_err))
||((~alu_gie)&&(div_valid)&&(div_error))
||((~alu_gie)&&(fpu_valid)&&(fpu_error))
||((~alu_gie)&&(alu_valid)&&(alu_illegal));
`else
assign o_break = (((break_en)||(~op_gie))&&(op_break)
1284,19 → 1193,12
// set the sleep bit and switch to supervisor mode in the same
// instruction: users are not allowed to halt the CPU.
always @(posedge i_clk)
if ((i_rst)||(w_switch_to_interrupt))
if ((i_rst)||((i_interrupt)&&(gie)))
sleep <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
// In supervisor mode, we have no protections. The
// supervisor can set the sleep bit however he wants.
// Well ... not quite. Switching to user mode and
// sleep mode shouold only be possible if the interrupt
// flag isn't set.
// Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
// don't set the sleep bit
// otherwise however it would o.w. be set
sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
&&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
// In user mode, however, you can only set the sleep
// mode while remaining in user mode. You can't switch
1315,20 → 1217,16
// The GIE register. Only interrupts can disable the interrupt register
assign w_switch_to_interrupt = (gie)&&(
// On interrupt (obviously)
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
(i_interrupt)
// If we are stepping the CPU
||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
||((alu_pc_valid)&&(step))
// If we encounter a break instruction, if the break
// enable isn't set.
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(op_break)&&(~break_en))
||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
`ifdef OPT_ILLEGAL_INSTRUCTION
// On an illegal instruction
||((alu_valid)&&(alu_illegal))
`endif
||((div_valid)&&(div_error))
||((fpu_valid)&&(fpu_error))
||(bus_err)
// If we write to the CC register
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
1350,9 → 1248,12
always @(posedge i_clk)
if (i_rst)
trap <= 1'b0;
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied
else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
trap <= 1'b1;
// else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
// &&(~i_dbg_data[`CPU_GIE_BIT]))
// trap <= i_dbg_data[`CPU_TRAP_BIT];
else if (w_release_from_interrupt)
trap <= 1'b0;
 
1416,103 → 1317,6
else if ((bus_err)&&(alu_gie))
ubus_err_flag <= 1'b1;
 
generate
if (IMPLEMENT_DIVIDE != 0)
begin
reg r_idiv_err_flag, r_udiv_err_flag;
 
// Supervisor/interrupt divide (by zero) error flag -- this will
// crash the CPU if ever set. This bit is thus available for us
// to be able to tell if/why the CPU crashed.
initial r_idiv_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_idiv_err_flag <= 1'b0;
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_reg_vl[`CPU_DIVERR_BIT]))
r_idiv_err_flag <= 1'b0;
else if ((div_error)&&(div_valid)&&(~alu_gie))
r_idiv_err_flag <= 1'b1;
// User divide (by zero) error flag -- if ever set, it will
// cause a sudden switch interrupt to supervisor mode.
initial r_udiv_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_udiv_err_flag <= 1'b0;
else if (w_release_from_interrupt)
r_udiv_err_flag <= 1'b0;
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
&&(~wr_reg_vl[`CPU_DIVERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_udiv_err_flag <= 1'b0;
else if ((div_error)&&(alu_gie)&&(div_valid))
r_udiv_err_flag <= 1'b1;
 
assign idiv_err_flag = r_idiv_err_flag;
assign udiv_err_flag = r_udiv_err_flag;
end else begin
assign idiv_err_flag = 1'b0;
assign udiv_err_flag = 1'b0;
end endgenerate
 
generate
if (IMPLEMENT_FPU !=0)
begin
// Supervisor/interrupt floating point error flag -- this will
// crash the CPU if ever set.
reg r_ifpu_err_flag, r_ufpu_err_flag;
initial r_ifpu_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ifpu_err_flag <= 1'b0;
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_reg_vl[`CPU_FPUERR_BIT]))
r_ifpu_err_flag <= 1'b0;
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
r_ifpu_err_flag <= 1'b1;
// User floating point error flag -- if ever set, it will cause
// a sudden switch interrupt to supervisor mode.
initial r_ufpu_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ufpu_err_flag <= 1'b0;
else if (w_release_from_interrupt)
r_ufpu_err_flag <= 1'b0;
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
&&(~wr_reg_vl[`CPU_FPUERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_ufpu_err_flag <= 1'b0;
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
r_ufpu_err_flag <= 1'b1;
 
assign ifpu_err_flag = r_ifpu_err_flag;
assign ufpu_err_flag = r_ufpu_err_flag;
end else begin
assign ifpu_err_flag = 1'b0;
assign ufpu_err_flag = 1'b0;
end endgenerate
 
`ifdef OPT_VLIW
reg r_ihalt_phase, r_uhalt_phase;
 
initial r_ihalt_phase = 0;
initial r_uhalt_phase = 0;
always @(posedge i_clk)
if (~alu_gie)
r_ihalt_phase <= alu_phase;
always @(posedge i_clk)
if (alu_gie)
r_uhalt_phase <= alu_phase;
else if (w_release_from_interrupt)
r_uhalt_phase <= 1'b0;
 
assign ihalt_phase = r_ihalt_phase;
assign uhalt_phase = r_uhalt_phase;
`else
assign ihalt_phase = 1'b0;
assign uhalt_phase = 1'b0;
`endif
 
//
// Write backs to the PC register, and general increments of it
// We support two: upc and ipc. If the instruction is normal,
1546,15 → 1350,8
pf_pc <= upc;
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
pf_pc <= wr_reg_vl[(AW-1):0];
`ifdef OPT_PIPELINED
else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
pf_pc <= dcd_branch_pc + 1;
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
else if (dcd_ce)
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
else if ((alu_pc_valid)&&(~clear_pipeline))
pf_pc <= alu_pc;
`endif
 
initial new_pc = 1'b1;
always @(posedge i_clk)
1581,7 → 1378,7
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
end
1593,7 → 1390,7
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
end
1621,8 → 1418,7
`ifdef DEBUG_SCOPE
always @(posedge i_clk)
o_debug <= {
/*
pf_pc[3:0], flags,
pf_pc[7:0],
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
op_ce, alu_ce, mem_ce,
//
1636,13 → 1432,6
// opA[23:20], opA[3:0],
gie, sleep,
wr_reg_vl[5:0]
*/
i_rst, master_ce, (new_pc),
((dcd_early_branch)&&(dcdvalid)),
pf_valid, pf_illegal,
op_ce, dcd_ce, dcdvalid, dcd_stalled,
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
pf_pc[7:0], pf_addr[7:0]
};
`endif
/pipemem.v
13,7 → 13,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
35,7 → 35,7
//
///////////////////////////////////////////////////////////////////////////
//
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
module pipemem(i_clk, i_rst, i_pipe_stb,
i_op, i_addr, i_data, i_oreg,
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
42,9 → 42,9
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
parameter ADDRESS_WIDTH = 24, AW=ADDRESS_WIDTH;
input i_clk, i_rst;
input i_pipe_stb, i_lock;
input i_pipe_stb;
// CPU interface
input i_op;
input [31:0] i_addr;
58,10 → 58,8
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl, o_wb_we;
output reg o_wb_cyc_gbl, o_wb_stb_gbl;
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
// Wishbone inputs
68,7 → 66,6
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
 
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
reg [3:0] rdaddr, wraddr;
wire [3:0] nxt_rdaddr;
reg [(5-1):0] fifo_oreg [0:15];
95,13 → 92,13
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
initial cyc = 0;
initial r_wb_cyc_lcl = 0;
initial r_wb_cyc_gbl = 0;
initial o_wb_cyc_lcl = 0;
initial o_wb_cyc_gbl = 0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
cyc <= 1'b0;
119,14 → 116,14
 
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
cyc <= 1'b0;
end
end else if (i_pipe_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_cyc_lcl <= lcl_stb;
o_wb_cyc_gbl <= gbl_stb;
o_wb_stb_lcl <= lcl_stb;
o_wb_stb_gbl <= gbl_stb;
cyc <= 1'b1;
165,26 → 162,4
 
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
 
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
 
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl));
end
 
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
 
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
 
endmodule
/prefetch.v
20,7 → 20,7
// can trap on it if necessary.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
47,18 → 47,18
// mode which this prefetch does not support. In non--pipelined mode, the
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// or 72 clocks to fetch one instruction.
module prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux,
module prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
o_i, o_pc, o_aux, o_valid, o_illegal,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
input i_clk, i_rst, i_ce, i_stalled_n;
input i_clk, i_rst, i_ce;
input [(AW-1):0] i_pc;
input [(AUX_WIDTH-1):0] i_aux;
output reg [31:0] o_i;
output reg [(AW-1):0] o_pc;
output reg [(AUX_WIDTH-1):0] o_aux;
output reg o_valid, o_illegal;
output wire o_valid, o_illegal;
// Wishbone outputs
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
96,7 → 96,7
 
always @(posedge i_clk)
if (i_rst) // Set the address to guarantee the result is invalid
o_wb_addr <= {(AW){1'b1}};
o_wb_addr <= 1'b0;
else if ((i_ce)&&(~o_wb_cyc))
o_wb_addr <= i_pc;
always @(posedge i_clk)
108,17 → 108,8
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
o_pc <= o_wb_addr;
initial o_valid = 1'b0;
initial o_illegal = 1'b0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
begin
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err);
o_illegal <= i_wb_err;
end else if (i_stalled_n)
begin
o_valid <= 1'b0;
o_illegal <= 1'b0;
end
 
assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
assign o_illegal = (o_wb_cyc)&&(i_wb_err);
 
endmodule
/pipefetch.v
26,7 → 26,7
// these exceptions yet.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/cpuops.v
4,13 → 4,10
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This supports the instruction set reordering of operations
// created by the second generation instruction set, as well as
// the new operations of POPC (population count) and BREV (bit reversal).
// Purpose:
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
32,7 → 29,7
//
///////////////////////////////////////////////////////////////////////////
//
module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
o_illegal);
parameter IMPLEMENT_MPY = 1;
input i_clk, i_rst, i_ce;
57,36 → 54,16
assign w_lsr_result = (|i_b[31:5])? 33'h00
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
// Bit reversal pre-logic
wire [31:0] w_brev_result;
genvar k;
generate
for(k=0; k<32; k=k+1)
assign w_brev_result[k] = i_b[31-k];
endgenerate
 
// Popcount pre-logic
wire [31:0] w_popc_result;
assign w_popc_result[5:0]=
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
assign w_popc_result[31:6] = 26'h00;
 
// Prelogic for our flags registers
wire z, n, v;
reg c, pre_sign, set_ovfl;
always @(posedge i_clk)
if (i_ce) // 1 LUT
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
||(i_op == 4'h6) // LSL
||(i_op == 4'h5)); // LSR
if (i_ce)
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
&&(i_a[31] != i_b[31]))
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
||(i_op == 4'hd) // LSL
||(i_op == 4'hf)); // LSR
 
 
// A 4-way multiplexer can be done in one 6-LUT.
103,22 → 80,20
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
4'b0001: o_c <= i_a & i_b; // BTST/And
4'b0010:{c,o_c } <= i_a + i_b; // Add
4'b0011: o_c <= i_a | i_b; // Or
4'b0100: o_c <= i_a ^ i_b; // Xor
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
// 4'h1010: The unimplemented MPYU,
// 4'h1011: and here for the unimplemented MPYS
4'b1100: o_c <= w_brev_result; // BREV
4'b1101: o_c <= w_popc_result; // POPC
4'b1110: o_c <= w_rol_result; // ROL
default: o_c <= i_b; // MOV, LDI
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
// 4'h3: There's a hole here for the unimplemented MPYU,
// 4'h4: and here for the unimplemented MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
endcase
end
end else begin
125,12 → 100,10
//
// Multiply pre-logic
//
wire signed_mpy;
assign signed_mpy = i_op[0];
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
wire signed [33:0] w_mpy_result;
assign w_mpy_a_input ={ ((i_a[15])&&(signed_mpy)), i_a[15:0] };
assign w_mpy_b_input ={ ((i_b[15])&&(signed_mpy)), i_b[15:0] };
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
 
 
143,22 → 116,20
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
4'b0001: o_c <= i_a & i_b; // BTST/And
4'b0010:{c,o_c } <= i_a + i_b; // Add
4'b0011: o_c <= i_a | i_b; // Or
4'b0100: o_c <= i_a ^ i_b; // Xor
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'b1010:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
4'b1011:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
4'b1100: o_c <= w_brev_result; // BREV
4'b1101: o_c <= w_popc_result; // POPC
4'b1110: o_c <= w_rol_result; // ROL
default: o_c <= i_b; // MOV, LDI
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
endcase
end
end endgenerate
/memops.v
15,7 → 15,7
// error signal).
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
37,7 → 37,7
//
///////////////////////////////////////////////////////////////////////////
//
module memops(i_clk, i_rst, i_stb, i_lock,
module memops(i_clk, i_rst, i_stb,
i_op, i_addr, i_data, i_oreg,
o_busy, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
44,9 → 44,9
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
parameter ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
input i_clk, i_rst;
input i_stb, i_lock;
input i_stb;
// CPU interface
input i_op;
input [31:0] i_addr;
59,11 → 59,8
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl;
output reg o_wb_we;
output reg o_wb_cyc_gbl, o_wb_stb_gbl;
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
// Wishbone inputs
70,29 → 67,26
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
 
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
initial r_wb_cyc_gbl = 1'b0;
initial r_wb_cyc_lcl = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
begin
if ((i_wb_ack)||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
end
end else if (i_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_cyc_lcl <= lcl_stb;
o_wb_cyc_gbl <= gbl_stb;
end
always @(posedge i_clk)
if (o_wb_cyc_gbl)
126,25 → 120,4
always @(posedge i_clk)
if (i_wb_ack)
o_result <= i_wb_data;
 
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
 
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
 
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
 
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
endmodule

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