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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/rtl/peripherals
    from Rev 48 to Rev 36
    ↔ Reverse comparison
  •

Rev 48 → Rev 36

/wbdmac.v
113,8 → 113,7
i_dev_ints,
o_interrupt,
i_other_busmaster_requests_bus);
parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,
DW=32, LGDV=5,AW=ADDRESS_WIDTH;
parameter LGMEMLEN = 10, DW=32, LGDV=5;
input i_clk;
// Slave/control wishbone inputs
input i_swb_cyc, i_swb_stb, i_swb_we;
126,8 → 125,7
output reg [(DW-1):0] o_swb_data;
// Master/DMA wishbone control
output reg o_mwb_cyc, o_mwb_stb, o_mwb_we;
output reg [(AW-1):0] o_mwb_addr;
output reg [(DW-1):0] o_mwb_data;
output reg [(DW-1):0] o_mwb_addr, o_mwb_data;
// Master/DMA wishbone responses from the bus
input i_mwb_ack, i_mwb_stall;
input [(DW-1):0] i_mwb_data;
142,7 → 140,7
 
reg cfg_wp; // Write protect
reg cfg_err;
reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len;
reg [(DW-1):0] cfg_waddr, cfg_raddr, cfg_len;
reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one;
reg cfg_incs, cfg_incd;
reg [(LGDV-1):0] cfg_dev_trigger;
153,14 → 151,14
 
reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)];
reg [(LGMEMLEN):0] nread, nwritten, nacks;
wire [(AW-1):0] bus_nacks;
assign bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
wire [(DW-1):0] bus_nacks;
assign bus_nacks = { {(DW-LGMEMLEN-1){1'b0}}, nacks };
 
initial o_interrupt = 1'b0;
initial o_mwb_cyc = 1'b0;
initial cfg_err = 1'b0;
initial cfg_wp = 1'b0;
initial cfg_len = {(AW){1'b0}};
initial cfg_len = 32'h00;
initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
initial cfg_on_dev_trigger = 1'b0;
always @(posedge i_clk)
273,9 → 271,9
cfg_incd <= ~i_swb_data[28];
cfg_err <= 1'b0;
end
2'b01: cfg_len <= i_swb_data[(AW-1):0];
2'b10: cfg_raddr <= i_swb_data[(AW-1):0];
2'b11: cfg_waddr <= i_swb_data[(AW-1):0];
2'b01: cfg_len <= i_swb_data;
2'b10: cfg_raddr <= i_swb_data;
2'b11: cfg_waddr <= i_swb_data;
endcase
end
end
313,9 → 311,9
cfg_on_dev_trigger, cfg_dev_trigger,
cfg_blocklen_sub_one
};
2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len };
2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
2'b01: o_swb_data <= cfg_len;
2'b10: o_swb_data <= cfg_raddr;
2'b11: o_swb_data <= cfg_waddr;
endcase
 
always @(posedge i_clk)
/zipport.v
0,0 → 1,129
///////////////////////////////////////////////////////////////////////////
//
// Filename: zipport.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A communications port for passing data between CPU's in a
// multi-cpu system.
//
// Example: Imagine a signal processing system with many 'CPUs' working
// together. Each communicates its outputs to the next CPU.
// Writes to this port will send values to the next port over,
// and reads from this port will read such values.
//
// These ports are ripe for adding FIFO's too, but the port
// itself doesn't offer a FIFO. Worse, as written, the port
// offers no flags to a FIFO to know when to read the next
// value.
//
// Note: There are other means of message passing, this is just
// one--perhaps not even the best one.
//
// Interface:
// 2-bits of control:
// top bit means valid data that hasn't been read.
// next bit means data has not been read, but instead has been
// lost
// These statuses are cleared upon any read.
// 30-bits of data.
//
// External CPU:
// Can read/write to the port.
// Writes to the port take place by setting i_port_v and strobing i_port_w.
// Writes from this port to other ports take place the same way.
// Reads/writes to/from this port by the CPU take place via the single
// wishbone address.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
module zipport(i_clk,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
i_port_w, i_port_v,
o_port_w, o_port_v,
o_int_full, o_int_ovflw);
parameter BW = 32, DW = (BW-2);
input i_clk;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [(BW-1):0] i_wb_data;
// Wishbone outputs
output reg o_wb_ack;
output wire o_wb_stall;
output wire [(BW-1):0] o_wb_data;
// Port connections
input i_port_w; // Write strobe
input [(DW-1):0] i_port_v; // Value received
output reg o_port_w; // Writing strobe
output reg [(BW-1):0] o_port_v; // Value being sent
// Interrupt line
output wire o_int_full, o_int_ovflw;
 
wire wb_write, wb_read, wb_cycle;
assign wb_write = (i_wb_cyc)&&(i_wb_stb)&&(i_wb_we);
assign wb_read = (i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we);
assign wb_cycle = (i_wb_cyc)&&(i_wb_stb);
 
reg r_valid, r_ovflw;
reg [(DW-1):0] r_data;
 
initial r_valid = 1'b0;
initial r_ovflw = 1'b0;
always @(posedge i_clk)
if (wb_write)
begin
o_port_w <= 1'b1;
o_port_v <= i_wb_data;
end else
o_port_w <= 1'b0;
 
always @(posedge i_clk)
if (i_port_w)
r_valid <= 1'b1;
else if (wb_read)
r_valid <= 1'b0;
 
always @(posedge i_clk)
if (i_port_w)
r_ovflw <= (r_valid);
else if (wb_read)
r_ovflw <= 1'b0;
 
always @(posedge i_clk)
if (i_port_w)
r_data <= i_port_v;
 
assign o_int_full = r_valid;
assign o_int_ovflw= r_ovflw;
 
initial o_wb_ack = 1'b0;
always @(posedge i_clk)
o_wb_ack <= wb_cycle;
assign o_wb_stall = 1'b0;
 
assign o_wb_data = { r_valid, r_ovflw, {(BW-2-DW){1'b0}}, r_data };
 
endmodule

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