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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl
    from Rev 128 to Rev 129
    Reverse comparison

Rev 128 → Rev 129

/core/pfcache.v
74,6 → 74,7
reg [(CW-1):0] rdaddr;
reg [(AW-1):CW] tagval;
wire [(AW-1):PW] lasttag;
reg illegal_valid;
reg [(AW-1):PW] illegal_cache;
 
initial o_i = 32'h76_00_00_00; // A NOOP instruction
95,7 → 96,7
// has been filled, but our prior attempt to do so has lead
// to a race condition, so we keep this logic simple.
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
lastpc <= tags[i_pc[(CW-1):PW]];
tagval <= tags[i_pc[(CW-1):PW]];
else
tagval <= tags[lastpc[(CW-1):PW]];
 
155,7 → 156,9
o_wb_stb <= 1'b0;
end else if (o_wb_cyc)
begin
if ((o_wb_stb)&&(~i_wb_stall))
if (i_wb_err)
o_wb_stb <= 1'b0;
else if ((o_wb_stb)&&(~i_wb_stall))
begin
if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
o_wb_stb <= 1'b0;
166,8 → 169,7
if (i_wb_ack)
begin
rdaddr <= rdaddr + 1;
if (rdaddr[(PW-1):0] == {(PW){1'b1}})
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
end
 
if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
179,7 → 181,7
end else if ((~r_v)&&(delay==0)
&&((tagval != lastpc[(AW-1):CW])
||(~vmask[lastpc[(CW-1):PW]]))
&&(~o_illegal))
&&((~illegal_valid)||(lastpc[(AW-1):PW] != illegal_cache)))
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
204,7 → 206,6
vmask[lastpc[(CW-1):PW]] <= 1'b0;
end
 
reg illegal_valid;
initial illegal_cache = 0;
initial illegal_valid = 0;
always @(posedge i_clk)
214,7 → 215,7
illegal_valid <= 0;
end else if ((o_wb_cyc)&&(i_wb_err))
begin
illegal_cache <= lastpc[(AW-1):PW];
illegal_cache <= o_wb_addr[(AW-1):PW];
illegal_valid <= 1'b1;
end
 
224,7 → 225,6
o_illegal <= 1'b0;
else
o_illegal <= (illegal_valid)
&&(tagval == i_pc[(AW-1):CW])
&&(illegal_cache == i_pc[(AW-1):PW]);
 
endmodule

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