URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl
- from Rev 18 to Rev 15
- ↔ Reverse comparison
Rev 18 → Rev 15
/core/pipefetch.v
37,7 → 37,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
module pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_request); |
44,8 → 44,7
parameter RESET_ADDRESS=32'h0010_0000, |
LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN), |
BUSW=32; |
input i_clk, i_rst, i_new_pc, |
i_clear_cache, i_stall_n; |
input i_clk, i_rst, i_new_pc, i_stall_n; |
input [(BUSW-1):0] i_pc; |
output reg [(BUSW-1):0] o_i; |
output reg [(BUSW-1):0] o_pc; |
97,10 → 96,9
initial r_cache_base = RESET_ADDRESS; |
always @(posedge i_clk) |
begin |
if ((i_rst)||(i_clear_cache)) |
if (i_rst) |
begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
// r_cache_base <= RESET_ADDRESS; |
// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0) |
// &&(i_pc >= r_cache_base) |
166,7 → 164,7
end |
|
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset |
if (i_rst) // Required, so we can reload memoy and then reset |
r_nvalid <= 0; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache))) |
177,29 → 175,21
r_nvalid <= r_nvalid+1; |
|
always @(posedge i_clk) |
if (i_clear_cache) |
r_cache_base <= i_pc; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache))) |
r_cache_base <= (i_new_pc) ? i_pc : r_addr; |
else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2)); |
|
always @(posedge i_clk) |
if (i_clear_cache) |
if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache))) |
r_cache_offset <= 0; |
else if ((~o_wb_cyc)&&( |
(w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
r_cache_offset <= 0; |
else if ((~o_wb_cyc)&&(w_running_out_of_cache)) |
r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2)); |
|
always @(posedge i_clk) |
if (i_clear_cache) |
o_wb_addr <= i_pc; |
else if ((~o_wb_cyc)&&((w_pc_out_of_bounds) |
if ((~o_wb_cyc)&&((w_pc_out_of_bounds) |
||(w_ran_off_end_of_cache))) |
o_wb_addr <= (i_new_pc) ? i_pc : r_addr; |
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)) |
221,7 → 211,7
|
initial r_addr_set = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
if (i_rst) |
r_addr_set <= 1'b0; |
else if (i_new_pc) |
r_addr_set <= 1'b1; |
251,4 → 241,5
if (i_stall_n) |
o_pc <= r_addr; |
|
|
endmodule |
/core/zipcpu.v
114,8 → 114,8
`define CPU_SLEEP_BIT 4 |
module zipcpu(i_clk, i_rst, i_interrupt, |
// Debug interface |
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data, |
o_dbg_stall, o_dbg_reg, o_dbg_cc, |
i_halt, i_dbg_reg, i_dbg_we, i_dbg_data, |
o_dbg_stall, o_dbg_reg, |
o_break, |
// CPU interface to the wishbone bus |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
125,7 → 125,7
parameter RESET_ADDRESS=32'h0100000; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
input i_halt; |
input [4:0] i_dbg_reg; |
input i_dbg_we; |
input [31:0] i_dbg_data; |
132,7 → 132,6
// Debug interface -- outputs |
output reg o_dbg_stall; |
output reg [31:0] o_dbg_reg; |
output reg [3:0] o_dbg_cc; |
output wire o_break; |
// Wishbone interface -- outputs |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
164,8 → 163,6
// |
reg [31:0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc || i_clear_pf_cache; |
|
wire dcd_stalled; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall; |
286,9 → 283,9
// Calculate stall conditions |
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM)) |
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG })); |
assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~clear_pipeline); |
assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc); |
// |
assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond); |
assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond); |
assign mem_stalled = (mem_busy)||((opvalid)&&(opM)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
317,7 → 314,7
pf_ack, pf_stall, i_wb_data); |
`else // Pipe fetch |
pipefetch #(RESET_ADDRESS) |
pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc, |
pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, i_wb_data, |
329,8 → 326,8
if (i_rst) |
dcdvalid <= 1'b0; |
else if (dcd_ce) |
dcdvalid <= (~clear_pipeline); |
else if ((~dcd_stalled)||(clear_pipeline)) |
dcdvalid <= (~new_pc); |
else if ((~dcd_stalled)||(new_pc)) |
dcdvalid <= 1'b0; |
|
always @(posedge i_clk) |
514,8 → 511,8
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
else if ((~op_stall)||(clear_pipeline)) |
opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled); |
else if ((~op_stall)||(new_pc)) |
opvalid <= 1'b0; |
|
// Here's part of our debug interface. When we recognize a break |
531,7 → 528,7
op_break <= 1'b0; |
else if (op_ce) |
op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
else if ((~op_stall)||(clear_pipeline)) |
else if ((~op_stall)||(new_pc)) |
op_break <= 1'b0; |
|
always @(posedge i_clk) |
629,7 → 626,7
alu_pc <= op_pc; |
initial alu_pc_valid = 1'b0; |
always @(posedge i_clk) |
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline) |
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc) |
&&((~opM) |
||(~mem_stalled)); |
|
679,8 → 676,6
always @(posedge i_clk) |
if (wr_reg_ce) |
regset[wr_reg_id] <= wr_reg_vl; |
else if ((i_halt)&&(i_dbg_we)) |
regset[i_dbg_reg] <= i_dbg_data[31:0]; |
|
// |
// Write back to the condition codes/flags register ... |
837,7 → 832,7
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
if (i_rst) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
863,9 → 858,6
((i_dbg_reg[4])?flags:iflags) }; |
end |
always @(posedge i_clk) |
o_dbg_cc <= { break_en, step, gie, sleep }; |
|
always @(posedge i_clk) |
o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy) |
||((~opvalid)&&(~i_rst)) |
||((~dcdvalid)&&(~i_rst)); |
/zipsystem.v
129,8 → 129,6
i_wb_ack, i_wb_stall, i_wb_data, |
// Incoming interrupts |
i_ext_int, |
// Our one outgoing interrupt |
o_ext_int, |
// Wishbone slave interface for debugging purposes |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data); |
144,8 → 142,6
input [31:0] i_wb_data; |
// Incoming interrupts |
input i_ext_int; |
// Outgoing interrupt |
output wire o_ext_int; |
// Wishbone slave |
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr; |
input [31:0] i_dbg_data; |
199,9 → 195,8
// register. |
// |
wire cpu_break, dbg_cmd_write; |
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache; |
reg cmd_reset, cmd_halt, cmd_step; |
reg [5:0] cmd_addr; |
wire [3:0] cpu_dbg_cc; |
assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr); |
// |
initial cmd_reset = 1'b1; |
216,14 → 211,6
cmd_halt <= dbg_idata[10]; |
else if ((cmd_step)||(cpu_break)) |
cmd_halt <= 1'b1; |
|
always @(posedge i_clk) |
if (i_rst) |
cmd_clear_pf_cache <= 1'b0; |
else if (dbg_cmd_write) |
cmd_clear_pf_cache <= dbg_idata[11]; |
else |
cmd_clear_pf_cache <= 1'b0; |
// |
initial cmd_step = 1'b0; |
always @(posedge i_clk) |
240,22 → 227,8
assign cpu_halt = (cmd_halt)&&(~cmd_step); |
wire [31:0] pic_data; |
wire [31:0] cmd_data; |
// Values: |
// 0x0003f -> cmd_addr mask |
// 0x00040 -> reset |
// 0x00080 -> interrrupts enabled |
// 0x00100 -> cmd_step |
// 0x00200 -> cmd_stall |
// 0x00400 -> cmd_halt |
// 0x00800 -> cmd_clear_pf_cache |
// 0x01000 -> cc.sleep |
// 0x02000 -> cc.gie |
// 0x04000 -> cc.step |
// 0x08000 -> cc.break_en |
// 0x10000 -> External interrupt line is high |
assign cmd_data = { 15'h00, i_ext_int, cpu_dbg_cc, |
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0, |
pic_data[15], cpu_reset, cmd_addr }; |
assign cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15], |
cpu_reset, cmd_addr }; |
|
`ifdef USE_TRAP |
// |
478,9 → 451,9
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5]) |
&&(dbg_we)&&(dbg_addr)); |
zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
cpu_halt, cmd_addr[4:0], cpu_dbg_we, |
dbg_idata, cpu_dbg_stall, cpu_dbg_data, |
cpu_dbg_cc, cpu_break, |
cpu_break, |
cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data, |
cpu_ack, cpu_stall, wb_data, |
cpu_op_stall, cpu_pf_stall, cpu_i_count); |
556,7 → 529,4
| wdt_stall | cache_stall |
| cpu_ext_stall); |
assign cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack); |
|
assign o_ext_int = (cmd_halt) && (~cpu_stall); |
|
endmodule |
/Makefile
49,7 → 49,7
VOBJ := obj_dir |
|
$(VOBJ)/Vzipsystem.cpp: $(VSRC) |
verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipsystem.v |
verilator -cc -y $(CORED)/ -y $(PRPHD) -y $(AUXD) zipsystem.v |
|
$(VOBJ)/Vzipsystem__ALL.a: $(VOBJ)/Vzipsystem.cpp $(VOBJ)/Vzipsystem.h |
cd $(VOBJ); make -f Vzipsystem.mk |