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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/sw
    from Rev 59 to Rev 60
    Reverse comparison

Rev 59 → Rev 60

/zasm/test.S
86,6 → 86,7
#define PUSH_TEST
#define PIPELINE_STACK_TEST
#define MEM_PIPELINE_TEST
#define CONDITIONAL_EXECUTION_TEST
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
test:
#ifdef DO_TEST_ASSEMBLER
572,6 → 573,10
JSR(mem_pipeline_test,R0)
#endif // MEM_PIPELINE_TEST
 
#ifdef CONDITIONAL_EXECUTION_TEST
JSR(conditional_execution_test,R0)
#endif // CONDITIONAL_EXECUTION_TEST
 
#ifdef NOWAIT_PIPELINE_TEST
JSR(nowait_pipeline_test,R0)
#endif // NOWAIT_PIPELINE_TEST
698,6 → 703,24
RETN
#endif
 
#ifdef CONDITIONAL_EXECUTION_TEST
conditional_execution_test:
; R0 is corrupt on entry, no need to save it
; SUB 1,SP
; STO R0,1(SP)
 
CLRF R0
ADD.Z 1,R0
TRAP.NZ R11
CMP.Z 0,R0
TRAP.Z R11
 
; LOD 1(SP),R0
; ADD 1,SP
; ; Stall
RETN
#endif
 
;
; Pipeline stalls have been hideous problems for me. The CPU has been modified
; with special logic to keep stages from stalling. For the most part, this
708,34 → 731,92
nowait_pipeline_test:
; Allocate for us some number of registers
;
SUB 5,SP
STO R0,1(SP)
STO R1,2(SP)
STO R2,3(SP)
STO R3,4(SP)
STO R4,5(SP)
SUB 6,SP
; Leave a spot open on the stack for a local variable,
; kept in memory.
STO R0,2(SP)
STO R1,3(SP)
STO R2,4(SP)
STO R3,5(SP)
STO R4,6(SP)
;
; Let's start with ALU-ALU testing
; AA: result->input A
CLR R0
ADD 1,R0
CMP 1,R0
TRAP.NZ R11
 
; AA: result->input B
CLR R0
CLR R1
ADD 1,R0
CMP R0,R1
TRAP.Z R11
 
; AA: result->input A on condition
CLRF R0
ADD.Z 5,R0
CMP 5,R0
TRAP.NZ R11
 
; AA: result->input B on condition
CLR R0
CLRF R1
ADD.Z 5,R0
CMP R0,R1
TRAP.Z R11
 
; AA: result->input B plus offset
CLR R0
CLRF R1
ADD 5,R0
CMP -5(R0),R1
TRAP.NZ R11
 
; AA: result->input B plus offset on condition
CLR R0
CLRF R1
ADD.Z 5,R0
CMP -5(R0),R1
TRAP.NZ R11
 
;
; Then we need to do ALU-Mem input testing
; (not implemented yet)
;
CLR R0
STO R0,1(SP)
LDI 8352,R0
LOD 1(SP),R0
TST -1,R0
TRAP.NZ R11
 
LDI 937,R0 ; Let's try again, this time something that's
STO R0,1(SP) ; not zero
NOOP
LOD 1(SP),R0
CMP 938,R0 ; Let's not compare with self, let's that
TRAP.GE R11 ; masks a problem--compare with a different
CMP 936,R0 ; number instead.
TRAP.LT R11
 
; Mem output->ALU input testing
; (not implemented yet)
; We just did that as partof our last test
; Mem output->MEM input testing
; (not implemented yet)
;
LOD 1(SP),R0
LOD 2(SP),R1
LOD 3(SP),R2
LOD 4(SP),R3
LOD 5(SP),R4
ADD 5,SP
LDI 5328,R2
LOD 1(SP),R2
STO R2,1(SP)
LOD 1(SP),R1
CMP 937,R1
TRAP.NZ R11
;
LOD 2(SP),R0
LOD 3(SP),R1
LOD 4(SP),R2
LOD 5(SP),R3
LOD 6(SP),R4
ADD 6,SP
RETN
#endif // NOWAIT_PIPELINE_TEST
 
/zasm/asmdata.cpp
389,17 → 389,20
return lln;
}break;
case OP_JMP:
if (!fitsin(imm, 16))
yyerror("JMP: Immediate out of range");
else if (m_opb == zp.ZIP_Rnone) {
if (m_opb == zp.ZIP_Rnone) {
if (m_cond != zp.ZIPC_ALWAYS)
yyerror("JMP: Conditions are not allowed for absolute jumps.");
imm &= (1<<24)-1;
if (!fitsin(imm, 24))
yyerror("JMP: Absolute jump address out of range");
zp.op_ldi(imm, zp.ZIP_PC);
}
in = zp.op_mov(m_cond, imm, m_opb, zp.ZIP_PC);
in = zp.op_ldi(imm, zp.ZIP_PC);
} else if (fitsin(imm,16)) {
in = zp.op_mov(m_cond, imm, m_opb, zp.ZIP_PC);
} else if (fitsin(imm,20))
in = zp.op_add(m_cond, imm, m_opb, zp.ZIP_PC);
else
yyerror("JMP: Immediate out of range");
break;
case OP_BRA:
BLD_BRANCH(op_bra,ZIPC_ALWAYS)
break;
433,8 → 436,8
case OP_TRAP:
if((m_opb == zp.ZIP_Rnone)&&(m_cond == zp.ZIPC_ALWAYS))
in = zp.op_ldi(imm, zp.ZIP_CC);
else if((m_opb == zp.ZIP_Rnone)&&((imm&0x0ffff)==imm))
in = zp.op_ldilo(imm, zp.ZIP_CC);
else if((m_opb == zp.ZIP_Rnone)&&((imm&0x0ffdf)==imm))
in = zp.op_ldilo(m_cond, imm & 0x0ffdf, zp.ZIP_CC);
else if((m_opb != zp.ZIP_Rnone)&&(fitsin(imm, 16)))
in = zp.op_mov(m_cond, imm, m_opb, zp.ZIP_CC);
else {
/zasm/sys.i
113,12 → 113,12
#define POP(RG,SP) LOD 1(SP),RG \
ADD 1,SP
#define FJSR(LBL,RG) MOV __here__+2(PC),RG \
JMP LBL
BRA LBL
#define FRET(RG) MOV RG,PC
#define JSR(LBL,RG) SUB 1,SP \
MOV __here__+3(PC),RG \
STO RG,1(SP) \
JMP LBL \
BRA LBL \
ADD 1,SP
#define RET LOD 1(SP),PC
#define SAVE_USER_CONTEXT(DR,AR) \

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