URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 121 to Rev 122
- ↔ Reverse comparison
Rev 121 → Rev 122
/trunk/sw/gcc-zippatch.patch
138,7 → 138,7
+ |
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h |
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400 |
@@ -21,7 +21,7 @@ |
#ifndef GCC_AARCH64_LINUX_H |
150,7 → 150,7
#undef ASAN_CC1_SPEC |
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h |
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -23,8 +23,8 @@ |
#define EXTRA_SPECS \ |
164,7 → 164,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h |
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -68,8 +68,8 @@ |
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */ |
178,7 → 178,7
|
#define GLIBC_DYNAMIC_LINKER \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h |
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400 |
@@ -62,7 +62,7 @@ |
|
190,7 → 190,7
#define LINUX_TARGET_LINK_SPEC "%{h*} \ |
%{static:-Bstatic} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h |
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -45,7 +45,7 @@ |
%{shared:-G -Bdynamic} \ |
202,7 → 202,7
|
#undef TARGET_SUPPORTS_SYNC_CALLS |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h |
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -102,7 +102,7 @@ |
#undef CRIS_DEFAULT_CPU_VERSION |
214,7 → 214,7
#undef CRIS_LINK_SUBTARGET_SPEC |
#define CRIS_LINK_SUBTARGET_SPEC \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h |
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400 |
@@ -129,9 +129,9 @@ |
#endif |
229,7 → 229,7
|
/* NOTE: The freebsd-spec.h header is included also for various |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h |
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -34,7 +34,7 @@ |
#define ENDFILE_SPEC \ |
241,7 → 241,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h |
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,7 +22,7 @@ |
#define GNU_USER_LINK_EMULATION "elf_i386" |
253,7 → 253,7
#undef STARTFILE_SPEC |
#if defined HAVE_LD_PIE |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,6 +22,6 @@ |
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd" |
266,7 → 266,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1" |
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -19,4 +19,4 @@ |
<http://www.gnu.org/licenses/>. */ |
275,7 → 275,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1" |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h |
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -27,6 +27,6 @@ |
#define GNU_USER_LINK_EMULATION64 "elf_x86_64" |
288,7 → 288,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" |
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h |
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -20,4 +20,4 @@ |
<http://www.gnu.org/licenses/>. */ |
297,7 → 297,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2" |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h |
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -55,7 +55,7 @@ |
/* Define this for shared library support because it isn't in the main |
309,7 → 309,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h |
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -32,4 +32,4 @@ |
|
318,7 → 318,7
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1" |
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h |
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -31,5 +31,4 @@ |
while (0) |
328,7 → 328,7
- |
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h |
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -73,10 +73,10 @@ |
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or |
346,7 → 346,7
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker" |
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h |
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -67,7 +67,7 @@ |
%{shared:-shared} \ |
358,7 → 358,7
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS() |
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h |
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -71,7 +71,7 @@ |
When the -shared link option is used a final link is not being |
370,7 → 370,7
#undef LINK_SPEC |
#define LINK_SPEC "-m m68kelf %{shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h |
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-06 17:56:01.475918570 -0400 |
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400 |
@@ -28,7 +28,7 @@ |
#undef TLS_NEEDS_GOT |
382,7 → 382,7
#define SUBTARGET_EXTRA_SPECS \ |
{ "dynamic_linker", DYNAMIC_LINKER } |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h |
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -22,20 +22,20 @@ |
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32" |
412,7 → 412,7
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32" |
#define GNU_USER_DYNAMIC_LINKERN32 \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h |
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-02 11:53:47.213604913 -0400 |
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -32,7 +32,7 @@ |
#undef ASM_SPEC |
424,7 → 424,7
#undef LINK_SPEC |
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h |
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400 |
@@ -37,7 +37,7 @@ |
/* Define this for shared library support because it isn't in the main |
436,7 → 436,7
#undef LINK_SPEC |
#define LINK_SPEC "\ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h |
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400 |
@@ -357,14 +357,14 @@ |
#undef LINK_OS_DEFAULT_SPEC |
459,7 → 459,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h |
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400 |
@@ -757,8 +757,8 @@ |
|
473,7 → 473,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" |
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h |
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400 |
@@ -60,8 +60,8 @@ |
#define MULTILIB_DEFAULTS { "m31" } |
487,7 → 487,7
#undef LINK_SPEC |
#define LINK_SPEC \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h |
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -43,7 +43,7 @@ |
|
499,7 → 499,7
#undef SUBTARGET_LINK_EMUL_SUFFIX |
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux" |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h |
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -84,8 +84,8 @@ |
When the -shared link option is used a final link is not being |
522,7 → 522,7
%{!static: \ |
%{rdynamic:-export-dynamic} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h |
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -83,7 +83,7 @@ |
When the -shared link option is used a final link is not being |
534,7 → 534,7
#undef LINK_SPEC |
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h |
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -41,7 +41,7 @@ |
%{!shared: \ |
546,7 → 546,7
|
#undef WCHAR_TYPE |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h |
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-02 11:53:47.217604879 -0400 |
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-06 17:56:01.479918541 -0400 |
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500 |
@@ -44,7 +44,7 @@ |
%{mlongcalls:--longcalls} \ |
696,8 → 696,8
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c |
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-01 06:26:30.217272207 -0400 |
@@ -0,0 +1,2341 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-06 17:47:47.255349663 -0400 |
@@ -0,0 +1,2099 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip.c |
773,12 → 773,13
+#include "optabs.h" |
+#include "explow.h" |
+#include "emit-rtl.h" |
+#include "ifcvt.h" |
+ |
+// #include "tmp_p.h" |
+#include "target.h" |
+#include "target-def.h" |
+// #include "tm-constrs.h" |
+// #include "tm-preds.h" |
+#include "tm-preds.h" |
+ |
+#include "diagnostic.h" |
+// #include "integrate.h" |
787,9 → 788,7
+// static bool zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool); |
+static bool zip_return_in_memory(const_tree, const_tree); |
+static bool zip_frame_pointer_required(void); |
+// static bool zip_must_pass_in_stack(enum machine_mode, const_tree); |
+ |
+// static void zip_setup_incoming_varargs(CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int); |
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode, |
+ const_tree type, bool named); |
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named); |
800,7 → 799,6
+static tree zip_builtin_decl(unsigned, bool); |
+// static void zip_asm_output_anchor(rtx x); |
+ void zip_asm_output_def(FILE *s, const char *n, const char *v); |
+ void zip_update_cc_notice(rtx exp, rtx_insn *insn); |
+static rtx zip_expand_builtin(tree exp, rtx target, rtx subtarget, |
+ enum machine_mode tmode, int ignore); |
+static bool zip_scalar_mode_supported_p(enum machine_mode mode); |
808,8 → 806,8
+static int zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd); |
+static bool zip_mode_dependent_address_p(const_rtx addr, addr_space_t); |
+static unsigned HOST_WIDE_INT zip_const_anchor = 0x20000; |
+static HOST_WIDE_INT zip_min_opb_imm = -0x200000; |
+static HOST_WIDE_INT zip_max_opb_imm = 0x1fffff; |
+static HOST_WIDE_INT zip_min_opb_imm = -0x20000; |
+static HOST_WIDE_INT zip_max_opb_imm = 0x1ffff; |
+static HOST_WIDE_INT zip_min_anchor_offset = -0x20000; |
+static HOST_WIDE_INT zip_max_anchor_offset = 0x1ffff; |
+static HOST_WIDE_INT zip_min_mov_offset = -0x1000; |
824,6 → 822,12
+static int zip_memory_move_cost(machine_mode, reg_class_t, bool); |
+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode); |
+static bool zip_cannot_modify_jumps_p(void); |
+#ifdef HAVE_cc0 |
+ void zip_update_cc_notice(rtx exp, rtx_insn *insn); |
+#error "We're not supposed to have CC0 anymore" |
+#else |
+static bool zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b); |
+#endif |
+ |
+ |
+#define ALL_DEBUG_OFF false |
1088,27 → 1092,6
+ return true; |
+ return (frame_pointer_needed); |
+/* |
+ fprintf(stderr, "ZIP_FRAME_POINTER_REQUIRED()\n"); |
+ if (frame_pointer_needed) { |
+ fprintf(stderr, "FRAME_POINTER_NEEDED is true\n"); |
+ zip_debug_rtx(frame_pointer_rtx); |
+ if (frame_pointer_rtx == NULL_RTX) |
+ return true; |
+ if (GET_CODE(frame_pointer_rtx)==PLUS) { |
+ if ((REG_P(XEXP(frame_pointer_rtx,0))) |
+ &&(REGNO(XEXP(frame_pointer_rtx, 0))==zip_SP) |
+ &&(CONST_INT_P(XEXP(frame_pointer_rtx,1)))) |
+ return false; |
+ if ((REG_P(XEXP(frame_pointer_rtx,1))) |
+ &&(REGNO(XEXP(frame_pointer_rtx, 1))==zip_SP) |
+ &&(CONST_INT_P(XEXP(frame_pointer_rtx,0)))) |
+ return false; |
+ return true; |
+ } else if ((REG_P(frame_pointer_rtx)) |
+ &&(REGNO(frame_pointer_rtx) == zip_SP)) |
+ return false; |
+ return true; |
+ } else return false; |
+*/ |
+} |
+ |
1189,13 → 1172,6
+ + cfun->machine->saved_reg_size |
+ + args_size; |
+ |
+ /* |
+ if (cfun->machine->fp_needed) |
+ frame_pointer_rtx = gen_rtx_REG(Pmode, zip_FP); |
+ else |
+ frame_pointer_rtx = plus_constant(Pmode, gen_rtx_REG(Pmode, zip_SP), |
+ cfun->machine->sp_fp_offset); |
+ */ |
+} |
+ |
+void |
1382,30 → 1358,7
+ return ret; |
+} |
+ |
+/* Return non-zero if the function argument described by TYPE is to be passed |
+ * by reference. |
+ */ |
+/* |
+static bool |
+zip_pass_by_reference(CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
+ enum machine_mode mode, const_tree type, |
+ bool name ATTRIBUTE_UNUSED) { |
+ unsigned HOST_WIDE_INT size; |
+ |
+ if (type) { |
+ if (AGGREGATE_TYPE_P(type)) { |
+ return TRUE; |
+ } size = int_size_in_bytes(type); |
+ } else |
+ size = GET_MODE_SIZE(mode); |
+ |
+ return (size > GET_MODE_SIZE(SImode)); // > 1 word : is this okay? |
+ // The idea is to pass everything larger than an int by reference (or |
+ // on the stack) |
+} |
+*/ |
+ |
+/* |
+ * Code taken from m68k ... |
+ */ |
+static bool |
1418,18 → 1371,6
+} |
+ |
+/* |
+static bool |
+zip_must_pass_in_stack(enum machine_mode mode, const_tree type) |
+{ |
+ if (mode == BLKmode) { |
+ return true; |
+ } if (type == NULL) { |
+ return false; |
+ } return AGGREGATE_TYPE_P(type); |
+} |
+*/ |
+ |
+/* |
+static void |
+zip_basic_check(void) |
+{ |
1471,30 → 1412,6
+ |
+/* pushed in function prologue */ |
+/* |
+static void |
+zip_setup_incoming_varargs(CUMULATIVE_ARGS *cum, enum machine_mode mode, |
+ tree type, int *pretend_size, int no_rtl) { |
+ if (no_rtl) |
+ return; |
+ |
+ gcc_assert(mode != BLKmode); |
+ |
+ if (*cum < (ZIP_LAST_ARG_REGNO+1)) { |
+ int size = ZIP_FIRST_ARG_REGNO + ZIP_NUM_ARGS_REGS - *cum; |
+ rtx regblock; |
+ int offset = (*cum - ZIP_FIRST_ARG_REGNO) * UNITS_PER_WORD; |
+ regblock = gen_rtx_MEM(BLKmode, |
+ plus_constant(arg_pointer_rtx, offset)); |
+ move_block_from_reg(*cum, regblock, size); |
+ *pretend_size = size * UNITS_PER_WORD; |
+ } |
+ |
+ if (targetm.calls.strict_argument_naming(cum)) |
+ *cum = *cum + zip_num_arg_regs(mode, type); |
+} |
+*/ |
+ |
+/* |
+static int |
+zip_arg_partial_bytes(CUMULATIVE_ARGS *cum, enum machine_mode mode, |
+ tree type, bool name ATTRIBUTE_UNUSED) { |
1548,11 → 1465,13
+ gen_rtx_REG(mode, (*cum)+1); |
+} |
+ |
+#ifdef HAVE_cc0 |
+/* NOTICE_UPDATE_CC sends us here |
+ */ |
+void |
+zip_update_cc_notice(rtx exp, rtx_insn *insn) |
+{ |
+#error "The CC0 code was supposed to be removed" |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ enum attr_ccresult ccr; |
+ enum attr_conditional conditionally_executed; |
1695,8 → 1614,60
+// then delete the compare. |
+// |
+} |
+#else |
+ |
+void zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1, |
+ bool preserve_op0) |
+{ |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ |
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":""); |
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx)); |
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0); |
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1); |
+ |
+ if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) { |
+ rtx tem = *op0; |
+ *op0 = *op1; |
+ *op1 = tem; |
+ *code = (int)swap_condition((enum rtx_code)*code); |
+ } |
+ |
+ if ((*code == LE)||(*code == LEU)||(*code == GTU)) { |
+ int offset = 1; // (*code == GTU) ? 1 : -1; |
+ bool swap = false; |
+ |
+ if (CONST_INT_P(*op1)) { |
+ *op1 = GEN_INT(INTVAL(*op1)+offset); |
+ swap = true; |
+ } else if (REG_P(*op1)) { |
+ *op1 = plus_constant(SImode, *op1, offset, true); |
+ swap = true; |
+ } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){ |
+ *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0), |
+ INTVAL(XEXP(*op1,1))+offset); |
+ swap = true; |
+ } if (swap) { |
+ if (*code == LE) |
+ (*code)= LT; |
+ else if (*code == LEU) |
+ (*code)= LTU; |
+ else // (*code == GTU) |
+ (*code) = GEU; |
+ } |
+ } |
+} |
+ |
+static bool |
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) { |
+ *a = zip_CC; |
+ *b = INVALID_REGNUM; |
+ return true; |
+} |
+ |
+#endif |
+ |
+ |
+/* totally buggy - we can't return pointers to nested functions */ |
+static void |
+zip_asm_trampoline_template(FILE *f) { |
1913,6 → 1884,9
+ case SImode: |
+ fprintf(stderr, "%s:SI\n", str); |
+ break; |
+ case CCmode: |
+ fprintf(stderr, "%s:CC\n", str); |
+ break; |
+ case DImode: |
+ fprintf(stderr, "%s:DI\n", str); |
+ break; |
1933,10 → 1907,21
+ gcc_assert(0 && "Bad RTX Code"); |
+ return; |
+ } switch(GET_CODE(x)) { // rtl.def |
+ case PARALLEL: zip_debug_print(pfx, lvl, "(PARALLEL"); |
+ debug_rtx(x); break; |
+ case PARALLEL: |
+ zip_debug_print(pfx, lvl, "(PARALLEL"); |
+ for(int j=0; j<XVECLEN(x,0);j++) |
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
+ debug_rtx(x); |
+ break; |
+ case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break; |
+ case SEQUENCE: zip_debug_print(pfx, lvl, "(SEQUENCE"); break; |
+ case SEQUENCE: |
+ zip_debug_print(pfx, lvl, "(SEQUENCE"); |
+ for(int j=0; j<XVECLEN(x,0);j++) |
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1); |
+ zip_debug_print(pfx, lvl, ")"); |
+ debug_rtx(x); |
+ break; |
+ case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break; |
+ case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break; |
+ case INSN: |
2007,23 → 1992,24
+ zip_debug_print(pfx, lvl, ")"); |
+ debug_rtx(x); |
+ break; |
+ case REG: |
+ case REG: { |
+ char buf[25]; |
+ if (REGNO(x) == zip_PC) |
+ zip_debug_print(pfx, lvl, "(PC)"); |
+ sprintf(buf, "(PC)"); |
+ else if (REGNO(x) == zip_CC) |
+ zip_debug_print(pfx, lvl, "(CC0)"); |
+ sprintf(buf, "(CC)"); |
+ else if (REGNO(x) == zip_SP) |
+ zip_debug_print(pfx, lvl, "(SP)"); |
+ sprintf(buf, "(SP)"); |
+ else if (REGNO(x) == zip_FP) |
+ zip_debug_print(pfx, lvl, "(REG FP)"); |
+ sprintf(buf, "(REG FP)"); |
+ else if (REGNO(x) == zip_GOT) |
+ zip_debug_print(pfx, lvl, "(REG GBL)"); |
+ sprintf(buf, "(REG GBL)"); |
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x))) |
+ zip_debug_print(pfx, lvl, "(REG RTN-VL)"); |
+ sprintf(buf, "(REG RTN-VL)"); |
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM) |
+ zip_debug_print(pfx, lvl, "(REG RTN-AD)"); |
+ else { char buf[25]; |
+ sprintf(buf, "(REG %d)", REGNO(x)); |
+ sprintf(buf, "(REG RTN-AD)"); |
+ else |
+ sprintf(buf, "(REG %d)", REGNO(x)); |
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x)); |
+ } break; |
+ case IF_THEN_ELSE: // 51 |
2061,7 → 2047,7
+ zip_debug_print(pfx, lvl, buf); |
+ } break; |
+ case LABEL_REF: |
+ { char buf[256], *bp; |
+ { char buf[256]; |
+ sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x))); |
+ zip_debug_print(pfx, lvl, buf); |
+ } |
2241,7 → 2227,7
+ |
+ |
+static bool |
+zip_legitimate_opb(const_rtx x, bool strict) |
+zip_legitimate_opb(rtx x, bool strict) |
+{ |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ |
2250,32 → 2236,32
+ |
+ if (NULL_RTX == x) |
+ return false; |
+ else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) |
+ else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) { |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n"); |
+ return false; |
+ else if (REG_P(x)) { |
+ bool res; |
+ // Only insist the register b a valid register if strict is true |
+ res = (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) != zip_CC)); |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> %s (Reg)\n", |
+ (res)?"YES!":"No"); |
+ return res; |
+ } else if ((!strict)&&(SUBREG_P(x))) { |
+ // Only insist the register b a valid register if strict is true |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Subreg(Reg),recurse)\n"); |
+ return zip_legitimate_opb(XEXP(x,0), strict); |
+ } else if ((strict)&&(REG_P(x))) { |
+ if (REGNO(x)<zip_CC) { |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n"); |
+ return true; |
+ } else return false; |
+ } else if (register_operand(x, GET_MODE(x))) { |
+ // This also handles subregs |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n"); |
+ return true; |
+ } else if ((CONST_INT_P(x)) |
+ &&(INTVAL(x) >= zip_min_opb_imm) |
+ &&(INTVAL(x) <= zip_max_opb_imm)) { |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const)\n"); |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", zip_min_opb_imm, INTVAL(x), zip_max_opb_imm); |
+ return true; |
+ // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) { |
+ // return true; |
+ } else if (GET_CODE(x) == PLUS) { |
+ // Is it a valid register? |
+ if(!REG_P(XEXP(x,0))) { |
+ if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) { |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n", |
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":""); |
+ return false; |
+ } if ((strict)&&((!is_ZIP_REG(REGNO(XEXP(x,0))))||(REGNO(XEXP(x,0)) == zip_CC))) { |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0))); |
+ } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) { |
+ return false; |
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT) |
+ &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset) |
2285,6 → 2271,7
+ // gcc_unreachable(); |
+ return true; |
+ } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF) |
+ ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL) |
+ ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) { |
+ // While we can technically support this, the problem |
+ // is that the symbol address could be anywhere, and we |
2293,18 → 2280,6
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n"); |
+ return false; |
+ } |
+ // if ((GET_CODE(XEXP(x, 1)) == MINUS) |
+ // &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF) |
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT) |
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF)) |
+ // &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF) |
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT) |
+ // ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF)) |
+ // &&((GET_CODE(XEXP(XEXP(x,1),0))) |
+ // == (GET_CODE(XEXP(XEXP(x,1),1))))) { |
+ // if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n"); |
+ // return true; |
+ //} |
+ } |
+ |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n"); |
2319,38 → 2294,19
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n"); |
+ if (dbg) zip_debug_rtx_pfx("VMov?: ", x); |
+ |
+ if (NULL_RTX == x) |
+ if (!zip_legitimate_opb(x, strict)) |
+ return false; |
+ else if (REG_P(x)) { |
+ // Only insist the register b a valid register if strict is true |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (Reg)\n"); |
+ return (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) !=zip_CC)); |
+ } else if (GET_CODE(x) == PLUS) { |
+ // if (GET_CODE(XEXP(x,0))==PLUS) { |
+ // return (zip_legitimate_opb(XEXP(x,0), strict)) |
+ // &&(zip_const_address_operand(XEXP(x,0))); |
+ // } |
+ // Is it a valid register? |
+ if(GET_CODE(XEXP(x,0)) != REG) { |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (No reg in +%s)\n", |
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":""); |
+ else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) { |
+ if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset) |
+ ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) { |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %d\n", INTVAL(XEXP(x,1))); |
+ return false; |
+ } if ((strict)&& |
+ ((!is_ZIP_REG(REGNO(XEXP(x,0)))) |
+ ||(REGNO(XEXP(x,0)) == zip_CC))) { |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0))); |
+ return false; |
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT) |
+ &&(INTVAL(XEXP(x, 1)) <= zip_max_mov_offset) |
+ &&(INTVAL(XEXP(x, 1)) >= zip_min_mov_offset)) { |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (reg+int)\n"); |
+ return true; |
+ } |
+ } |
+ |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No\n"); |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n"); |
+ if (dbg) zip_debug_rtx(x); |
+ return false; |
+ return true; |
+} |
+ |
+int |
2413,7 → 2369,7
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ |
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n"); |
+ return zip_legitimate_opb(op, !can_create_pseudo_p()); |
+ return zip_legitimate_opb(op, false); //, !can_create_pseudo_p()); |
+} |
+ |
+int |
2520,48 → 2476,6
+ fputc('\n', stream); |
+} |
+ |
+/* |
+bool zip_load_address_lod(rtx regrx, rtx memrx) { |
+ fprintf(stderr, "ZIP-LOAD-ADDRESS-LOD\n"); |
+ if (!MEM_P(memrx)) |
+ return false; |
+ if (GET_CODE(regrx) != REG) |
+ return false; |
+ enum rtx_code ic = GET_CODE(memrx); |
+ if ((ic == SYMBOL_REF) |
+ ||(ic == CODE_LABEL) |
+ ||(ic == LABEL_REF)) { |
+ if (can_create_pseudo_p()) { |
+ rtx scratch_reg; |
+ scratch_reg = gen_rtx_SCRATCH(SImode); |
+ emit_insn(gen_movsi_ldi(scratch_reg, XEXP(memrx, 0))); |
+ emit_insn(gen_movsi_lod(regrx, scratch_reg)); |
+ return true; |
+ } else return false; |
+ } else return false; |
+} |
+ |
+bool zip_load_address_sto(rtx memrx, rtx regrx) { |
+ fprintf(stderr, "CHECKING-IN-W/ZIP_LOAD_ADDRESS_STORE\n"); |
+ if (!MEM_P(memrx)) |
+ return false; |
+ if (GET_CODE(regrx) != REG) |
+ return false; |
+ enum rtx_code ic = GET_CODE(memrx); |
+ if ((ic == SYMBOL_REF) |
+ ||(ic == CODE_LABEL) |
+ ||(ic == LABEL_REF)) { |
+ if (can_create_pseudo_p()) { |
+ rtx scratch_reg; |
+ scratch_reg = gen_rtx_SCRATCH(SImode); |
+ emit_insn(gen_movsi_ldi(scratch_reg, XEXP(memrx, 0))); |
+ emit_insn(gen_movsi_sto(scratch_reg, regrx)); |
+ return true; |
+ } else return false; |
+ } return false; |
+} |
+*/ |
+ |
+#define USE_SUBREG |
+#ifdef USE_SUBREG |
+#define SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0)))) |
2571,243 → 2485,6
+#define SMEM_P(RTX) false |
+#endif |
+ |
+bool zip_gen_move_rtl(rtx dst, rtx src) { |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE\n"); |
+ if (dbg) zip_debug_rtx_pfx("FROM: ", src); |
+ if (dbg) zip_debug_rtx_pfx("TO : ", dst); |
+ if (dbg) fprintf(stderr, "PSEUDOs: %s\n", can_create_pseudo_p()?"true":"false"); |
+ if (((REG_P(dst))||(SREG_P(dst))) |
+ &&((REG_P(src))||(SREG_P(src)))) { |
+ // First type of move... register to register |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG -- EMIT\n"); |
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst)); |
+ // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src)); |
+ emit_insn(gen_movsi_reg(dst, src)); |
+ } else if ((MEM_P(dst))&&(MEM_P(XEXP(dst,0)))) { |
+ // An indirect store, (mem (mem (addr .))) = whatever ... |
+ if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(Pmode); |
+ zip_gen_move_rtl(tmp, XEXP(dst,0)); |
+ // mark_reg_pointer(tmp,0); |
+ zip_gen_move_rtl(gen_rtx_MEM(GET_MODE(src), tmp), src); |
+ } else { |
+ fprintf(stderr, "ZIP:Cannot move into mem w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if ((MEM_P(src))&&(MEM_P(XEXP(src,0)))) { |
+ // If this is an indirect load, Rx = (mem (mem (addr))) |
+ if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(Pmode); |
+ zip_gen_move_rtl(tmp, XEXP(src,0)); |
+ // mark_reg_pointer(tmp,0); |
+ zip_gen_move_rtl(dst, gen_rtx_MEM(GET_MODE(src), tmp)); |
+ } else { |
+ fprintf(stderr, "ZIP: Cannot move from mem(mem(ptr)) w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src)==PLUS) |
+ &&(REG_P(XEXP(src,0))) |
+ &&(CONST_INT_P(XEXP(src,1)))) { |
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst)); |
+ // Second type of move... register plus offset to register |
+ if ((INTVAL(XEXP(src, 1)) <= zip_max_mov_offset) |
+ &&(INTVAL(XEXP(src, 1)) >= zip_min_mov_offset)) { |
+ // The offset is within bounds |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG+OFF -- EMIT\n"); |
+ emit_insn(gen_movsi_reg_off(dst, XEXP(src,0),XEXP(src,1))); |
+ } else if (can_create_pseudo_p()) { |
+ // The offset is out of bounds, get a new register and |
+ // generate an add instruction to split this up. |
+ rtx tmp = gen_reg_rtx(GET_MODE(XEXP(src,0))); |
+ |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LDI\n"); |
+ emit_insn(gen_movsi_ldi(tmp, XEXP(src,1))); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/ADD\n"); |
+ emit_insn(gen_addsi3(tmp, tmp, XEXP(src,0))); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/DST\n"); |
+ emit_insn(gen_movsi_reg(dst, tmp)); |
+ } else { |
+ fprintf(stderr, "ZIP: Cannot move a(r),b w/o pseudo for out of bounds a\n"); |
+ return false; |
+ } |
+ } else if ((MEM_P(dst))&&(MEM_P(src))) { |
+ rtx tmp; |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/MEM/MEM\n"); |
+ if (can_create_pseudo_p()) { |
+ tmp = gen_reg_rtx(GET_MODE(src)); |
+ emit_insn(gen_movsi(tmp, src)); |
+ emit_insn(gen_movsi(dst, tmp)); |
+ } else { |
+ fprintf(stderr, "ZIP: Cannot move mem(A) to mem(B) w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(MEM_P(src))) { |
+ // Memory load |
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst)); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD\n"); |
+ if (zip_legitimate_opb(XEXP(src, 0), false)) { |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/SIMPLE-LOD(ADDR)\n"); |
+ if (dbg) zip_debug_rtx_pfx("Smple-Addr: ", src); |
+ emit_insn(gen_movsi_lod(dst, src)); |
+ } else if (zip_const_address_operand(XEXP(src,0))) { |
+ if (can_create_pseudo_p()) { |
+ rtx tmp; |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR)\n"); |
+ tmp = gen_reg_rtx(Pmode); |
+ emit_insn(gen_movsi_ldi(tmp, XEXP(src,0))); |
+ emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),tmp))); |
+ } else { |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR,SELF)\n"); |
+ emit_insn(gen_movsi_ldi(dst, XEXP(src,0))); |
+ emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),dst))); |
+ } |
+ } else { |
+ internal_error("%s", "ZIP/No usable load\n"); |
+ } |
+ } else if ((MEM_P(dst))&&((REG_P(src))||(SREG_P(src)))) { |
+ // Memory store |
+ // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src)); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO\n"); |
+ if (zip_legitimate_opb(XEXP(dst, 0), false)) { |
+ // If it's a legitimate address already, do nothing mor |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Legit Addr)--EMIT\n"); |
+ // if (REG_P(XEXP(dst,0))) |
+ // mark_reg_pointer(XEXP(dst,0),0); |
+ // else if ((GET_CODE(XEXP(dst,0))==PLUS) |
+ // &&(REG_P(XEXP(XEXP(dst,0),0)))) |
+ // mark_reg_pointer(XEXP(XEXP(dst,0),0),0); |
+ emit_insn(gen_movsi_sto(dst, src)); |
+ } else if (zip_const_address_operand(XEXP(dst,0))) { |
+ rtx tmp; |
+ |
+ if (can_create_pseudo_p()) { |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Const Addr,Reg) -- EMIT\n"); |
+ // Otherwise we need to load the memory address |
+ // into a register |
+ tmp = gen_reg_rtx(Pmode); |
+ // mark_reg_pointer(tmp,0); |
+ emit_insn(gen_movsi_ldi(tmp, XEXP(dst,0))); |
+ // |
+ // Then we can do our load |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO -- emit\n"); |
+ emit_insn(gen_movsi_sto(gen_rtx_MEM(GET_MODE(src), tmp), src)); |
+ } else { |
+ fprintf(stderr, "Cannot move src -> mem(dst) w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if (can_create_pseudo_p()) |
+ internal_error("%s", "ZIP/No usable store\n"); |
+ else { |
+ fprintf(stderr, "ZIP/Unanticipated store problem\n"); |
+ return false; |
+ } |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO -- DONE\n"); |
+ } else if ((MEM_P(dst))&&((CONST_INT_P(src))||(GET_CODE(src)==SYMBOL_REF))) { |
+ // Store a constant into memory |
+ rtx tmp; |
+ |
+ if (can_create_pseudo_p()) { |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM\n"); |
+ // Load the source constant into a register first |
+ tmp = gen_reg_rtx((GET_MODE(src)==VOIDmode)?GET_MODE(dst):GET_MODE(src)); |
+ emit_insn(gen_movsi_ldi(tmp,src)); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG->MEM -- RECURSE\n"); |
+ |
+ // Then do a normal move, recursing to handle memory |
+ // properly |
+ zip_gen_move_rtl(dst, tmp); |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM -- DONE\n"); |
+ } else { |
+ fprintf(stderr, "ZIP/Cannot store constant into mem w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(CONST_INT_P(src))) { |
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst)); |
+ // Load a constant into a register |
+ // The assembler really takes care of all of this, since |
+ // the assembler will split the constant if it doesn't fit |
+ // into a single instruction. |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG\n"); |
+ // if ((GET_MODE(dst)==VOIDmode)&&(GET_MODE(src)==VOIDmode)) |
+ // PUT_MODE(dst,SImode); |
+ emit_insn(gen_movsi_ldi(dst, src)); |
+ } else if ((REG_P(dst))&& |
+ ((LABEL_P(src)) |
+ ||(GET_CODE(src)==SYMBOL_REF) |
+ ||(GET_CODE(src)==LABEL_REF))) { |
+ // Load a constant into a register |
+ // The assembler really takes care of all of this, since |
+ // the assembler will split the constant if it doesn't fit |
+ // into a single instruction. |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL->REG\n"); |
+ emit_insn(gen_movsi_ldi(dst, src)); |
+ } else if ((REG_P(dst))&& |
+ ((GET_CODE(src)==PLUS) |
+ &&((GET_CODE(XEXP(src,0))==SYMBOL_REF) |
+ ||(GET_CODE(XEXP(src,0))==LABEL_REF)) |
+ &&(CONST_INT_P(XEXP(src,1))))) { |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL+OFFSET->REG\n"); |
+ if ((INTVAL(XEXP(src,1))>=zip_min_mov_offset) |
+ &&(INTVAL(XEXP(src,1))<=zip_max_mov_offset)) { |
+ emit_insn(gen_movsi_ldi(dst, XEXP(src,1))); |
+ emit_insn(gen_movsi_reg_off(dst, dst, XEXP(src,1))); |
+ } else if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(Pmode); |
+ emit_insn(gen_movsi_ldi(tmp, XEXP(src,1))); |
+ emit_insn(gen_movsi_ldi(dst, src)); |
+ emit_insn(gen_addsi3(dst,dst,tmp)); |
+ return true; |
+ } else { |
+ fprintf(stderr, "Cannot move LABEL+OFFSET -> dst w/o pseudo\n"); |
+ return false; |
+ } |
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src) == CONST)) { |
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst)); |
+ zip_gen_move_rtl(dst, XEXP(src,0)); |
+ } else if (SMEM_P(dst)) { |
+ rtx addr = XEXP(XEXP(dst,0),0); |
+ if (REG_P(addr)) { |
+ zip_gen_move_rtl( |
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addr, |
+ SUBREG_BYTE(dst),false)),src); |
+ } else if ((GET_CODE(addr)==PLUS) |
+ &&(REG_P(XEXP(addr,0))) |
+ &&(CONST_INT_P(XEXP(addr,1)))) { |
+ rtx addreg = XEXP(addr,0); |
+ zip_gen_move_rtl( |
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addreg, |
+ INTVAL(XEXP(addr,1))+SUBREG_BYTE(dst), |
+ false)),src); |
+ } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n"); |
+ } else if (SMEM_P(src)) { |
+ rtx addr = XEXP(XEXP(src,0),0); |
+ if (REG_P(addr)) { |
+ zip_gen_move_rtl(dst, |
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addr, |
+ SUBREG_BYTE(src),false))); |
+ } else if ((GET_CODE(addr)==PLUS) |
+ &&(REG_P(XEXP(addr,0))) |
+ &&(CONST_INT_P(XEXP(addr,1)))) { |
+ rtx addreg = XEXP(addr,0); |
+ zip_gen_move_rtl(dst, |
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addreg, |
+ INTVAL(XEXP(addr,1))+SUBREG_BYTE(src), |
+ false))); |
+ } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n"); |
+ } else { |
+ fprintf(stderr, "ZIP/No usable move\n"); |
+ zip_debug_rtx_pfx("TO : ", dst); |
+ zip_debug_rtx_pfx("FROM: ", src); |
+ debug_rtx(dst); |
+ debug_rtx(src); |
+ return false; |
+ } |
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE -- DONE\n"); |
+ return true; |
+} |
+ |
+const char *zip_set_zero_or_one(rtx condition, rtx dst) { |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n"); |
3032,7 → 2709,6
+} |
+ |
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"? |
+ |
+static bool zip_cannot_modify_jumps_p(void) { |
+ // Let's try their suggested approach, keeping us from modifying jumps |
+ // after reload. This should also allow our peephole2 optimizations |
3039,10 → 2715,92
+ // to adjust things back to what they need to be if necessary. |
+ return (reload_completed || reload_in_progress); |
+} |
+ |
+rtx_insn *zip_ifcvt_info; |
+ |
+void |
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) { |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF); |
+ if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n"); |
+ if (*true_expr) switch(GET_CODE(*true_expr)) { |
+ case LE: |
+ case GTU: |
+ case GEU: |
+ case LEU: |
+ if (dbg) fprintf(stderr, "TRUE, missing expr\n"); |
+ if (dbg) zip_debug_rtx(*true_expr); |
+ *true_expr = NULL_RTX; |
+ break; |
+ default: // LT, GT, GTE, LTU, NE, EQ |
+ break; |
+ } |
+ |
+ if (*false_expr) switch(GET_CODE(*false_expr)) { |
+ case LE: |
+ case GTU: |
+ case GEU: |
+ case LEU: |
+ if (dbg) fprintf(stderr, "FALSE, missing expr\n"); |
+ if (dbg) zip_debug_rtx(*false_expr); |
+ *false_expr = NULL_RTX; |
+ default: |
+ break; |
+ } |
+ if ((dbg)&&((!*true_expr)||(!*false_expr))) |
+ fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n"); |
+} |
+ |
+void |
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) { |
+/* |
+ fprintf(stderr, "IFCVT -- CANCEL\n"); |
+ zip_ifcvt_info = NULL; |
+*/ |
+} |
+ |
+void |
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) { |
+/* |
+rtx_insn *insn; |
+FOR_BB_INSNS(ceinfo->test_bb, insn) |
+ fprintf(stderr, "IFCVT -- FINAL\n"); |
+ zip_debug_rtx_pfx("FINAL-TEST-BB", insn); |
+ zip_ifcvt_info = NULL; |
+*/ |
+} |
+ |
+void |
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) { |
+/* |
+ zip_ifcvt_info = NULL; |
+ rtx_insn *insn, *ifinsn = NULL; |
+ FOR_BB_INSNS(ceinfo->test_bb, insn) { |
+ rtx p; |
+ p = single_set(insn); |
+ if (!p) continue; |
+ if (SET_DEST(p)==pc_rtx) { |
+ ifinsn = insn; |
+ } |
+ if (!REG_P(SET_DEST(p))) |
+ continue; |
+ if (GET_MODE(SET_DEST(p))!=CCmode) |
+ continue; |
+ if (REGNO(SET_DEST(p))!=zip_CC) |
+ continue; |
+ zip_ifcvt_info = insn; |
+ } |
+ |
+ if (zip_ifcvt_info) |
+ zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info); |
+ if (ifinsn) |
+ zip_debug_rtx_pfx("PRIOR-JMP",ifinsn); |
+*/ |
+} |
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h |
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-01 06:33:55.090614401 -0400 |
@@ -0,0 +1,3898 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-04 18:41:58.074920257 -0400 |
@@ -0,0 +1,3983 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: gcc/config/zip/zip.h |
5679,7 → 5437,9
+ * ZipCPU --- We need this, as not all expressions set (cc0). |
+ * |
+ */ |
+#ifdef HAVE_cc0 |
+#define NOTICE_UPDATE_CC(EXP, INSN) zip_update_cc_notice(EXP, INSN) |
+#endif |
+ |
+ |
+/* 17.15.2 Representation of condition codes using registers */ |
5687,7 → 5447,26
+ * this section isn't supposed to apply. |
+ */ |
+ |
+/* SELECT_CC_MODE(op, x, y) |
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be |
+ * produced by other instructions than compares, for example the branch can use |
+ * directyl the condition code set by a subtract instruction. However, on some |
+ * machines when the condition code is set this way some bits (such as the |
+ * overflow bit) are not set in the same way as a test instruction, so that a |
+ * different branch instruction must be used for some conditional branches. |
+ * When this happens, use the machinemode of the condition code register to |
+ * record different formats of the condition code register. Modes can also be |
+ * used to reccord which compare instruction (e.g. a signed or an unsigned |
+ * comparison) produced the condition codes. |
+ * |
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and |
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare. This |
+ * is needed because the modes have to be chosen not only during RTL generation |
+ * but also, for example, by instruction combination. The result of |
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ... |
+ * |
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in |
+ * machine-modes.def and should be fine with it. Hence, this doesn't need |
+ * to be defined. |
+ */ |
+ |
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines |
5717,8 → 5496,68
+ * The only problem is ... this hook appears to only be called on non-CC0 |
+ * machines. Hence, defining it hasn't done anything for us. |
+ */ |
+// #define TARGET_CANONICALIZE_COMPARISON zip_canonicalize_comparison |
+#define TARGET_CANONICALIZE_COMPARISON zip_canonicalize_comparison |
+ |
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is |
+ * always safe to reverse a comparison whose mode is MODE. If SELECT_CC_MODE |
+ * can ever return MODE for a floating-point inequality comparison, than |
+ * REVERSIBLE_CC_MODE(MODE) must be zero. |
+ * |
+ * You need not define this macro if it would always return zero or if the |
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT. For example, |
+ * here ... |
+ * |
+ * ZipCPU -- We'll always return zero, so this need not be defined. |
+ */ |
+ |
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed |
+ * condition code of thecode for comparison done in CC_MODE MODE. This macro |
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ... |
+ * |
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave |
+ * this undefined. |
+ */ |
+ |
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do |
+ * not use (cc0), and which use a hard register rather than a pseudo-register |
+ * to hold condition codes, the regular CSE passes are often not able to |
+ * identify cases in which the hard register is set to a common value. Use this |
+ * hook to enable a small pass which optimizes such cases. This hook should |
+ * return true to enable this pass, and it should set the integers to which its |
+ * arguments point to the hard register numbers used for condition codes. When |
+ * there is only one such register, as is true on most systems, the integer |
+ * pointed to by p2 should be set to INVALID_REGNUM. |
+ * |
+ * The default version of this hook returns false. |
+ * |
+ * ZipCPU --- I like the idea of enabling optimizations. Let's return |
+ * something other than false. |
+ */ |
+#define TARGET_FIXED_CONDITION_CODE_REGS zip_fixed_condition_code_regs |
+ |
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use |
+ * multiple condition code modes in class MODE_CC, it is sometimes the case |
+ * that a comparison can be validly done in more than one mode. On such a |
+ * system, define this target hook to take two mode arguments and to return a |
+ * mode in which both comparisons may be validly done. If there is no such |
+ * mode, return VOIDmode. |
+ * |
+ * The default version of this hook checks whether the modes are the same. If |
+ * they are, it returns that mode. If they are different, it returns VOIDmode. |
+ * |
+ * ZipCPU--Given that we only have the one CCmode, the default definition works |
+ * well enough for us. |
+ */ |
+ |
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags |
+ * register, and it needs to use the post-reload comparison elimination pass, |
+ * then this value should be set appropriately. |
+ * |
+ * ZipCPU---Looks like we can set this easily enough without any problems. |
+ */ |
+#undef TARGET_FLAGS_REGNUM |
+#define TARGET_FLAGS_REGNUM zip_CC |
+ |
+/* 17.16 Relative costs of operations */ |
+ |
+ |
6418,7 → 6257,7
+ * ZipCPU --- I need to set this to properly take advantage of our conditional |
+ * execution and conditional testing capabilities. |
+ */ |
+// #warning "Need to come back to this." |
+#define IFCVT_MODIFY_TESTS(CI,TR,FL) zip_ifcvt_modify_tests(CI,&TR,&FL) |
+ |
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like |
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements |
6431,6 → 6270,7
+ * execution and conditional testing capabilities. |
+ */ |
+// #warning "Need to come back to this." |
+#define IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX |
+ |
+ |
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the |
6455,6 → 6295,7
+ * execution and conditional testing capabilities. |
+ */ |
+// #warning "Need to come back to this." |
+#define IFCVT_MODIFY_FINAL(CEINFO) zip_ifcvt_modify_final(CEINFO) |
+ |
+ |
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine |
6467,6 → 6308,7
+ * execution and conditional testing capabilities. |
+ */ |
+// #warning "Need to come back to this." |
+#define IFCVT_MODIFY_CANCEL(CEINFO) zip_ifcvt_modify_cancel(CEINFO) |
+ |
+ |
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine |
6478,6 → 6320,7
+ * execution and conditional testing capabilities. |
+ */ |
+// #warning "Need to come back to this." |
+#define IFCVT_MACHDEP_INIT(CEINFO) zip_ifcvt_machdep_init(CEINFO) |
+ |
+ |
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a |
6943,8 → 6786,8
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md |
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-01 19:21:20.490611131 -0400 |
@@ -0,0 +1,2122 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-06 17:47:12.387591487 -0400 |
@@ -0,0 +1,2262 @@ |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+;; |
+;; Filename: zip.md |
7055,13 → 6898,19
+}) |
+ |
+(define_predicate "zip_opb_operand_p" |
+ (match_code "reg,plus,const_int") |
+ (match_code "reg,plus,const_int,subreg") |
+{ |
+ return zip_pd_opb_operand(op); |
+}) |
+ |
+(define_predicate "zip_opb_immv_p" |
+ (match_code "const_int") |
+{ |
+ return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13))); |
+}) |
+ |
+(define_predicate "zip_opb_single_operand_p" |
+ (match_code "reg,const_int") |
+ (match_code "reg,subreg,const_int") |
+{ |
+ return zip_pd_opb_operand(op); |
+}) |
7095,6 → 6944,10
+{ |
+ if (MEM_P(op)) // Check for valid store address |
+ return zip_pd_opb_operand(XEXP(op,0)); |
+ else if (SUBREG_P(op)) |
+ return 1; |
+ else if ((REG_P(op))||(SUBREG_P(op))) |
+ return register_operand(op, GET_MODE(op)); |
+ return 1; |
+}) |
+ |
7105,6 → 6958,14
+ return zip_pd_opb_operand(XEXP(op,0)); |
+ else if (GET_CODE(op)==PLUS) |
+ return zip_pd_opb_operand(op); |
+ else if (SUBREG_P(op)) { |
+ //; As far as predicates are concerned, subregs must be valid. |
+ //; The details of them are settled within the constraints. |
+ return 1; |
+ } else if ((REG_P(op))||(SUBREG_P(op))) |
+ return register_operand(op,SImode); |
+ else if (CONST_INT_P(op)) |
+ return 1; |
+ return 1; |
+}) |
+ |
7237,9 → 7098,7
+ if ((MEM_P(operands[1]))&& |
+ //; (!REG_P(XEXP(operands[1],0))) |
+ ((zip_const_address_operand(XEXP(operands[1],0))) |
+ ||(!zip_pd_opb_operand(XEXP(operands[1],0)))) |
+ ) |
+ { |
+ ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) { |
+ //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n"); |
+ if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(Pmode); |
7256,7 → 7115,7
+(define_insn "movsi_raw" |
+ [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r") |
+ (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))] |
+ "(REG_P(operands[0]))||(REG_P(operands[1]))" |
+ "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))" |
+ "@ |
+ MOV\t%1,%0 |
+ STO\t%1,%0 |
7363,14 → 7222,16
+; |
+; |
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0))) |
+ ]) ]) |
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ ] |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (plus:SI (match_operand:SI 1 "register_operand" "0") |
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ADD %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7378,7 → 7239,8
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "const_int_operand" "N"))))] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ADD %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
7386,15 → 7248,15
+; |
+; |
+(define_expand "sub<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ ]) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "sub<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ ] |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "SUB %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7402,8 → 7264,8
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r") |
+ (match_operand:ZI 3 "const_int_operand" "N")))) |
+ ] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "SUB %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
7411,7 → 7273,8
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (mult:ZI (match_operand:ZI 1 "register_operand" "%r") |
+ (match_operand:ZI 2 "register_operand" "r"))) |
+ (clobber (match_scratch:ZI 3 "=r"))] |
+ (clobber (match_scratch:ZI 3 "=r")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)" |
+ "" |
+ "MOV %1,%0 |
7431,14 → 7294,16
+ [(set_attr "ccresult" "unknown")]) |
+ |
+(define_expand "div<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (div:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))] |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])] |
+ "(ZIP_DIVIDE)") |
+(define_insn "div<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (div:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_DIVIDE)" |
+ "DIVS %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7446,19 → 7311,22
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (div:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "const_int_operand" "N"))))] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_DIVIDE)" |
+ "DIVS %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_expand "udiv<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))] |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])] |
+ "(ZIP_DIVIDE)") |
+(define_insn "udiv<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_DIVIDE)" |
+ "DIVU %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7466,7 → 7334,8
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "const_int_operand" "N"))))] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_DIVIDE)" |
+ "DIVU %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
7478,6 → 7347,7
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (umin:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %0,%2 |
7487,6 → 7357,7
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (umax:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %2,%0 |
7496,6 → 7367,7
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (smin:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %2,%0 |
7505,6 → 7377,7
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (smax:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %0,%2 |
7511,13 → 7384,15
+ MOV.LT %2,%0" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+(define_expand "and<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "and<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "rO")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "AND %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7525,20 → 7400,21
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (and:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "const_int_operand" "N")))) |
+ ] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "AND %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_expand "ior<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]) |
+(define_insn "ior<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO"))) |
+ ] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "OR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7546,20 → 7422,22
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "nonmemory_operand" "N")))) |
+ ] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "OR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_expand "xor<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]) |
+ (match_operand:ZI 2 "zip_opb_operand_p" ""))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])] |
+ "") |
+(define_insn "xor<mode>3_reg" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO"))) |
+ ] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "XOR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7567,8 → 7445,8
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "nonmemory_operand" "N")))) |
+ ] |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N")))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "XOR %3+%2,%0" |
+ [(set_attr "ccresult" "set")]) |
7576,7 → 7454,7
+ ;[(set (match_operand:ZI 0 "register_operand" "=r") |
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r") |
+ ;(match_operand:ZI 2 "general_operand" "rO"))) |
+ ;(set (pc) (if_then_else (eq (cc0) (const_int 0)) |
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0)) |
+ ;(label_ref (match_operand 3)) |
+ ;(pc)))] |
+ ;"" |
7603,7 → 7481,8
+(define_insn "ashr<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rR")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ASR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7610,14 → 7489,16
+(define_insn "ashl<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rR")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ASR %2,%0" |
+ "LSL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "lshr<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "register_operand" "rR")))] |
+ (match_operand:ZI 2 "register_operand" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "LSR %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7624,7 → 7505,8
+(define_insn "rotl<mode>3" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0") |
+ (match_operand:ZI 2 "nonmemory_operand" "rR")))] |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "ROL %2,%0" |
+ [(set_attr "ccresult" "set")]) |
7632,7 → 7514,7
+(define_insn "neg<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r"))) |
+ ] |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "NEG %1,%0" |
+ [(set_attr "ccresult" "validzn")]) |
7639,7 → 7521,7
+(define_insn "abs<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0"))) |
+ ] |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "TEST %0 |
+ NEG.LT %0" |
7647,54 → 7529,30
+(define_insn "popcount<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r"))) |
+ ] |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "POPC %1,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_expand "parity<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r"))) |
+ (set (match_dup:ZI 0) (and:ZI (match_dup:ZI 0) (const_int -2))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (parallel [ |
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+(define_insn "one_cmpl<mode>2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (not:ZI (match_operand:ZI 1 "register_operand" "0"))) |
+ ] |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ "XOR -1,%0" |
+ [(set_attr "ccresult" "set")]) |
+; |
+; |
+;(define_extract "ssadsi" |
+; [(set (cc0) (compare (match_operand:SI 1 "register_operand" "+r") |
+; (match_operand:SI 2 "register_operand" "+r"))) |
+; (cond_exec (lt (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2)))) |
+; (cond_exec (lt (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 2) (match_dup:SI 1)))) |
+; (cond_exec (lt (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2)))) |
+; (set (match_dup:SI 2) (subtract (match_dup:SI 1) (match_dup:SI 2))) |
+; (set (match_operand:SI 3 "register_operand" "=r") (add:SI (match_dup:SI 2) (match_dup:SI 3))) |
+; ] |
+; "") |
+;(define_expand "usadsi" |
+; [(set (cc0) (compare (match_operand:SI 1 "register_operand" "+r") |
+; (match_operand:SI 2 "register_operand" "+r"))) |
+; (cond_exec (ltu (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2)))) |
+; (cond_exec (ltu (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 2) (match_dup:SI 1)))) |
+; (cond_exec (ltu (cc0) (const_int 0)) |
+; (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2)))) |
+; (set (match_dup:SI 2) (subtract (match_dup:SI 1) (match_dup:SI 2))) |
+; (set (match_operand:SI 3 "register_operand" "=r") (add:SI (match_dup:SI 2) (match_dup:SI 3))) |
+; ] |
+; "") |
+; |
+; |
+; |
+; |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
+;; |
+;; General arithmetic instructions -- double words |
7708,22 → 7566,22
+ (match_operand:DI 1 "general_operand" ""))]) |
+(define_insn "movdi_lod" |
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "r")))] |
+ (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))] |
+ "" |
+ { |
+ if (REG_P(operands[0])) |
+ if (REG_P(operands[1])) |
+ return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0"; |
+ else if (GET_CODE(operands[0])==PLUS) { |
+ if ((REG_P(XEXP(operands[0],0))) |
+ &&(CONST_INT_P(XEXP(operands[0],1)))) { |
+ else if (GET_CODE(operands[1])==PLUS) { |
+ if ((REG_P(XEXP(operands[1],0))) |
+ &&(CONST_INT_P(XEXP(operands[1],1)))) { |
+ static char buf[64]; |
+ sprintf(buf, |
+ "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0", |
+ INTVAL(XEXP(operands[0],1)), |
+ INTVAL(XEXP(operands[0],1)+1)); |
+ INTVAL(XEXP(operands[1],1)), |
+ INTVAL(XEXP(operands[1],1)+1)); |
+ return buf; |
+ } |
+ } else return "BREAK"; |
+ } return "BREAK"; |
+ } |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+(define_insn "movdi_sto" |
7756,6 → 7614,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (plus:DI (match_operand:DI 1 "register_operand" "0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "ADD %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0" |
7765,6 → 7624,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (minus:DI (match_operand:DI 1 "register_operand" "0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "SUB %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0" |
7774,6 → 7634,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (and:DI (match_operand:DI 1 "register_operand" "%0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "AND %L2,%L0\n\tAND\t%H2,%H0" |
7783,6 → 7644,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (ior:DI (match_operand:DI 1 "register_operand" "%0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "OR %2,%0\n\tOR\t%H2,%H0" |
7792,6 → 7654,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (xor:DI (match_operand:DI 1 "register_operand" "%0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "XOR %2,%0\n\tXOR\t%H2,%H0" |
7799,15 → 7662,19
+; |
+(define_insn "negdi2" |
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (neg:DI (match_operand:DI 1 "register_operand" "0")))] |
+ (neg:DI (match_operand:DI 1 "register_operand" "0"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "XOR -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+; |
+(define_insn "absdi2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0"))) |
+ (clobber (match_scratch:SI 2 "=r"))] |
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (abs:DI (match_operand:DI 1 "register_operand" "0"))) |
+ (clobber (match_scratch:SI 2 "=r")) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CLR %2 |
+ TEST %H0 ; Problem, we can't tell conditions |
7815,11 → 7682,12
+ XOR.LT -1,%L0 |
+ XOR.LT -1,%H0 |
+ ADD %2,%L0 |
+ ADD.C %1,%HI" |
+ ADD.C 1,%H0" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+(define_insn "one_cmpldi2" |
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (not:DI (match_operand:DI 1 "register_operand" "0"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "XOR -1,%L0\n\tXOR\t-1,%H0" |
7828,6 → 7696,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (umin:DI (match_operand:DI 1 "register_operand" "%0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %H0,%H2 |
7839,6 → 7708,7
+ [(set (match_operand:DI 0 "register_operand" "=r") |
+ (umax:DI (match_operand:DI 1 "register_operand" "%0") |
+ (match_operand:DI 2 "register_operand" "r"))) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "CMP %H2,%H0 |
7848,8 → 7718,9
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+(define_insn "popcountdi2" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (popcount (match_operand:DI 1 "register_operand" "r"))) |
+ (popcount:SI (match_operand:DI 1 "register_operand" "r"))) |
+ (clobber (match_scratch:SI 2 "=r")) |
+ (clobber (reg:CC CC_REG)) |
+ ] |
+ "" |
+ "POPC %L1,%0 |
7906,11 → 7777,11
+; |
+; |
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3 |
+ [(set (cc0) (compare (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "nonmemory_operand" "rO"))) |
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r") |
+ (match_operand:ZI 3 "zip_opb_operand_p" "rO"))) |
+ (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI |
+ (match_operator 1 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (const_int 1) (const_int 0)))] |
+ "" |
+ ) |
7917,9 → 7788,10
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3 |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator" |
+ [(compare (match_operand:DI 2 "register_operand" "r") |
+ (match_operand:DI 3 "register_operand" "r"))]) |
+ (const_int 1) (const_int 0)))] |
+ [(match_operand:DI 2 "register_operand" "r") |
+ (match_operand:DI 3 "register_operand" "r")]) |
+ (const_int 1) (const_int 0))) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ { |
+ switch(GET_CODE(operands[1])) { |
7948,32 → 7820,50
+;; This will only work so well, since the direction of the compare is |
+;; important in unsigned compares. |
+;; |
+(define_insn "cmp<mode>" |
+ [(set (cc0) (compare (match_operand:ZI 0 "register_operand" "r") |
+ (match_operand:ZI 1 "nonmemory_operand" "rO")))] |
+(define_expand "cmp<mode>" |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:ZI 0 "register_operand" "r") |
+ (match_operand:ZI 1 "nonmemory_operand" "")))] |
+ "" |
+ { |
+ if (!zip_opb_operand_p(operands[1],SImode)) { |
+ if (can_create_pseudo_p()) { |
+ //; fprintf(stderr, "Generating pseudo register for compare\n"); |
+ rtx tmp = gen_reg_rtx(SImode); |
+ emit_insn(gen_movsi(tmp,operands[1])); |
+ operands[1] = tmp; |
+ } else FAIL; |
+ } |
+ }) |
+(define_insn "cmp<mode>_reg" |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:ZI 0 "register_operand" "r") |
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))] |
+ "" |
+ "CMP\t%1,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "cmp<mode>_off" |
+ [(set (cc0) (compare (match_operand:ZI 0 "register_operand" "r") |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:ZI 0 "register_operand" "r") |
+ (plus (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand 2 "const_int_operand" "N"))))] |
+ (match_operand 2 "zip_opb_immv_p" "N"))))] |
+ "" |
+ "CMP\t%2+%1,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "test<mode>" |
+ [(set (cc0) (compare (and:ZI (match_operand:ZI 0 "register_operand" "r") |
+ (match_operand:ZI 1 "nonmemory_operand" "rO")) |
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r") |
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")) |
+ (const_int 0)))] |
+ "" |
+ "TEST %1,%0" |
+ [(set_attr "ccresult" "set")]) |
+(define_insn "test<mode>_off" |
+ [(set (cc0) (compare (and:ZI (match_operand:ZI 0 "register_operand" "r") |
+ (plus:ZI |
+ (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "const_int_operand" "N"))) |
+ (const_int 0)))] |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (and:ZI (match_operand:ZI 0 "register_operand" "r") |
+ (plus:ZI |
+ (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "zip_opb_immv_p" "N"))) |
+ (const_int 0)))] |
+ "" |
+ "TEST %2+%1,%0" |
+ [(set_attr "ccresult" "set")]) |
7998,32 → 7888,32
+; both methods. |
+; |
+(define_cond_exec |
+ [(ne (cc0) (const_int 0))] |
+ [(ne (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(NZ)" |
+ [(set_attr "conditional" "yes")]) |
+(define_cond_exec |
+ [(lt (cc0) (const_int 0))] |
+ [(lt (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(LT)" |
+ [(set_attr "conditional" "yes")]) |
+(define_cond_exec |
+ [(eq (cc0) (const_int 0))] |
+ [(eq (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(Z)" |
+ [(set_attr "conditional" "yes")]) |
+(define_cond_exec |
+ [(gt (cc0) (const_int 0))] |
+ [(gt (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(GT)" |
+ [(set_attr "conditional" "yes")]) |
+(define_cond_exec |
+ [(ge (cc0) (const_int 0))] |
+ [(ge (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(GE)" |
+ [(set_attr "conditional" "yes")]) |
+(define_cond_exec |
+ [(ltu (cc0) (const_int 0))] |
+ [(ltu (reg:CC CC_REG) (const_int 0))] |
+ "" |
+ "(C)" |
+ [(set_attr "conditional" "yes")]) |
8043,7 → 7933,7
+(define_insn "set_zero_or_one<mode>" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI |
+ (match_operator 1 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (const_int 1) (const_int 0)))] |
+ "" |
+ { return (zip_set_zero_or_one(operands[1], operands[0])); |
8052,7 → 7942,7
+(define_insn "mov<mode>cc" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (match_operand:ZI 2 "general_operand" "rio") |
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))] |
+ "" |
8063,7 → 7953,7
+(define_insn "add<mode>cc" |
+ [(set (match_operand:ZI 0 "register_operand" "=r,r") |
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "0,r") |
+ (match_operand:ZI 3 "nonmemory_operand" "rO,M")) |
+ (match_dup 0)))] |
8077,7 → 7967,7
+;(define_expand "mov<mode>cc" |
+; [(set (match_operand:ZI 0 "general_operand" "=rm,rm,r,r,r" |
+; (if_then_else:ZI (match_operator 1 "ordered_comparison_operator" |
+; [(cc0) (const_int 0)]) |
+; [(reg:CC CC_REG) (const_int 0)]) |
+; (match_operand:ZI 2 "general_operand" "0,r,0,m,rm") |
+; (match_operand:ZI 3 "general_operand" "r,0,m,0,rm"))))] |
+; ) |
8222,10 → 8112,10
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ... |
+;; |
+(define_expand "cbranch<mode>4" |
+ [(set (cc0) (compare (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO"))) |
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "zip_opb_operand_p" "rO"))) |
+ (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (label_ref (match_operand 3 "" "")) |
+ (pc)))] |
+ "" |
8234,29 → 8124,27
+ //; Two branches give us no end of difficulty when implementing. |
+ //; Let's check for these two branch codes, and swap the |
+ //; comparison to simplify them. |
+ // fprintf(stderr, "CBRANCH\n"); |
+ // zip_debug_rtx_pfx("- CMP: ", operands[0]); |
+ // zip_debug_rtx_pfx("- A : ", operands[1]); |
+ // zip_debug_rtx_pfx("- B : ", operands[2]); |
+ // zip_debug_rtx_pfx("- JMP: ", operands[3]); |
+ //; fprintf(stderr, "CBRANCH\n"); |
+ //; zip_debug_rtx_pfx("- CMP: ", operands[0]); |
+ //; zip_debug_rtx_pfx("- A : ", operands[1]); |
+ //; zip_debug_rtx_pfx("- B : ", operands[2]); |
+ //; zip_debug_rtx_pfx("- JMP: ", operands[3]); |
+ //; Can we do better if we reverse some compares? |
+ if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) { |
+ // fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n"); |
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx, |
+ gen_rtx_COMPARE(VOIDmode, operands[2], operands[1]))); |
+ //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n"); |
+ emit_insn(gen_cmpsi(operands[2], operands[1])); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) { |
+ // fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n"); |
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx, |
+ gen_rtx_COMPARE(VOIDmode, operands[2], operands[1]))); |
+ emit_jump_insn(gen_cbranch_jmp_leu(operands[3])); |
+ //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n"); |
+ emit_insn(gen_cmpsi_off(operands[2], operands[1], |
+ GEN_INT(1))); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) { |
+ // fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n"); |
+ //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n"); |
+ //; Swap operands, turn into a GTE compare |
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx, |
+ gen_rtx_COMPARE(VOIDmode, operands[2], operands[1]))); |
+ emit_insn(gen_cmpsi(operands[2], operands[1])); |
+ emit_jump_insn(gen_cbranch_jmp_ge(operands[3])); |
+ DONE; |
+ } // ; Otherwise ... just handle the branch normally |
8266,28 → 8154,62
+ //; would be difficult to explain to users why MIN_INT didn't |
+ //; compare properly. Hence we only adjust constant integers. |
+ //; |
+ if ((GET_CODE(operands[0])==LE) |
+ &&(CONST_INT_P(operands[2])) |
+ if (GET_CODE(operands[0])==LE) { |
+ if ((CONST_INT_P(operands[2])) |
+ &&(INTVAL(operands[2])<(1<<17)-2)) { |
+ // fprintf(stderr, "CBRANCH:(LE,?,#,?)\n"); |
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx, |
+ gen_rtx_COMPARE(VOIDmode, operands[1], |
+ GEN_INT(INTVAL(operands[2])+1)))); |
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3])); |
+ DONE; |
+ } else if ((GET_CODE(operands[0])==LEU) |
+ &&(CONST_INT_P(operands[2])) |
+ //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n"); |
+ emit_insn(gen_cmpsi(operands[1], |
+ GEN_INT(INTVAL(operands[2])+1))); |
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3])); |
+ DONE; |
+ //; Now for the controversial ones--where we add one |
+ //; when it may or may not be permissable. For now, we |
+ //; just do it anyway and postpone the philosophical |
+ //; discussion for later. |
+ } else if (REG_P(operands[2])) { |
+ emit_insn(gen_cmpsi_off(operands[1], |
+ operands[2],GEN_INT(1))); |
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3])); |
+ DONE; |
+ } else if ((GET_CODE(operands[2])==PLUS) |
+ &&(REG_P(XEXP(operands[2],0))) |
+ &&(CONST_INT_P(XEXP(operands[2],1))) |
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) { |
+ emit_insn(gen_cmpsi_off(operands[1], |
+ XEXP(operands[2],0), |
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1))); |
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3])); |
+ DONE; |
+ } |
+ } else if (GET_CODE(operands[0])==LEU) { |
+ if ((CONST_INT_P(operands[2])) |
+ &&(INTVAL(operands[2])<(1<<17)-2)) { |
+ // fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n"); |
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx, |
+ gen_rtx_COMPARE(VOIDmode, operands[1], |
+ GEN_INT(INTVAL(operands[2])+1)))); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n"); |
+ emit_insn(gen_cmpsi(operands[1], |
+ GEN_INT(INTVAL(operands[2])+1))); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ //; Now for the controversial ones--this time having |
+ //; to do with unsigned compares. |
+ } else if (REG_P(operands[2])) { |
+ emit_insn(gen_cmpsi_off(operands[1], |
+ operands[2],GEN_INT(1))); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ } else if ((GET_CODE(operands[2])==PLUS) |
+ &&(REG_P(XEXP(operands[2],0))) |
+ &&(CONST_INT_P(XEXP(operands[2],1))) |
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) { |
+ emit_insn(gen_cmpsi_off(operands[1], |
+ XEXP(operands[2],0), |
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1))); |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3])); |
+ DONE; |
+ } |
+ } |
+ }) |
+(define_insn "cbranch_jmp_eq" |
+ [(set (pc) (if_then_else (eq (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8296,7 → 8218,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_neq" |
+ [(set (pc) (if_then_else (ne (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8305,7 → 8227,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_lt" |
+ [(set (pc) (if_then_else (lt (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8314,7 → 8236,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_le" |
+ [(set (pc) (if_then_else (le (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8324,7 → 8246,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_gt" |
+ [(set (pc) (if_then_else (gt (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8333,7 → 8255,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_ge" |
+ [(set (pc) (if_then_else (ge (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8342,7 → 8264,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_ltu" |
+ [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" |
8351,9 → 8273,11
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_gtu" |
+ [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ (pc))) |
+ ;(clobber (reg:CC CC_REG)) |
+ ] |
+ "" ; Flip the condition, and then we can jump |
+ "XOR\t2,CC |
+ BC\t%0" |
8361,7 → 8285,7
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unknown")]) |
+(define_insn "cbranch_jmp_leu" |
+ [(set (pc) (if_then_else (leu (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ "" ; Need to check for both LTU (i.e. C) and Z |
8371,9 → 8295,11
+ (set_attr "conditional" "yes") |
+ (set_attr "ccresult" "unchanged")]) |
+(define_insn "cbranch_jmp_geu" |
+ [(set (pc) (if_then_else (geu (cc0) (const_int 0)) |
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 0 "" "")) |
+ (pc)))] |
+ (pc))) |
+ ;(clobber (reg:CC CC_REG)) |
+ ] |
+ "" ; Flip the comparison, then check for GEU (once flipped)a |
+ ; Z is naturally checked for, as C would've never been set on Z |
+ ; so by flipping it, it is tantamount to saying Z or GTU. |
8387,10 → 8313,10
+ [(set (pc) (if_then_else |
+ (match_operator 0 "ordered_comparison_operator" |
+ [(match_operand:DI 1 "register_operand" "r") |
+ (match_operand:DI 2 "nonmemory_operand" "rO")]) |
+ (match_operand:DI 2 "register_operand" "r")]) |
+ (label_ref (match_operand 3 "" "")) |
+ (pc))) |
+ (clobber (cc0))] |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ { |
+ switch(GET_CODE(operands[0])) { |
8458,7 → 8384,7
+ // This should always be the case |
+ rtx addr = XEXP(operands[0],0); |
+ if (zip_const_address_operand_p(addr, SImode)) { |
+ // fprintf(stderr, "Generating gen_void_call_const()\n"); |
+ //; fprintf(stderr, "Generating gen_void_call_const()\n"); |
+ emit_call_insn(gen_void_call_const(addr, |
+ operands[1])); |
+ } else if ((MEM_P(addr))&&(zip_address_operand( |
8491,16 → 8417,18
+; recognize as such, but for now we'll use .Lcall# as our label. |
+; |
+(define_insn "void_call_const" |
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" "")) |
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" "")) |
+ (match_operand 1 "const_int_operand" "n")) |
+ (clobber (reg:SI RTN_REG))])] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+(define_insn "void_call_mem" |
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q")) |
+ [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q")) |
+ (match_operand 1 "const_int_operand" "n")) |
+ (clobber (reg:SI RTN_REG))])] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
8507,35 → 8435,37
+; |
+; #warning "This predicate is appropriate for non-moves, but not for JMPs" |
+(define_insn "void_call_var" |
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")) |
+ [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")) |
+ (match_operand 1 "const_int_operand" "n")) |
+ (clobber (reg:SI RTN_REG))])] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+(define_expand "call_value" |
+ [(set (reg:SI RTNV_REG) |
+ [(parallel [(set (reg:SI RTNV_REG) |
+ (call (match_operand:SI 1 "" "") |
+ (match_operand 2 "const_int_operand" "n"))) |
+ (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))] |
+ (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG)) |
+ (clobber (reg:CC CC_REG))])] |
+ "" |
+ { |
+ // extern void zip_debug_rtx(const_rtx); |
+ // fprintf(stderr, "ZIP.MD::CALL-VALUE()\n"); |
+ // zip_debug_rtx(operands[1]); |
+ //; extern void zip_debug_rtx(const_rtx); |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n"); |
+ //; zip_debug_rtx(operands[1]); |
+ if (MEM_P(operands[1])) { |
+ // fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n"); |
+ // zip_debug_rtx(operands[1]); |
+ // This should always be the case |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n"); |
+ //; zip_debug_rtx(operands[1]); |
+ //; This should always be the case |
+ rtx addr = XEXP(operands[1],0); |
+ if (zip_const_address_operand_p(addr, SImode)) { |
+ // fprintf(stderr, "Generating gen_reg_call_const()\n"); |
+ //; fprintf(stderr, "Generating gen_reg_call_const()\n"); |
+ emit_call_insn(gen_reg_call_const(addr, operands[2])); |
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) { |
+ // fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n"); |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n"); |
+ emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2])); |
+ } else { |
+ // fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n"); |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n"); |
+ emit_call_insn(gen_reg_call_var(addr, operands[2])); |
+ } |
+ DONE; |
8542,10 → 8472,11
+ } |
+ }) |
+(define_insn "reg_call_const" |
+ [(parallel [(set (reg:SI RTNV_REG) |
+ [(set (reg:SI RTNV_REG) |
+ (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" "")) |
+ (match_operand 1 "const_int_operand" "n"))) |
+ (clobber (reg:SI RTN_REG))])] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
8553,7 → 8484,8
+ [(set (reg:SI RTNV_REG) |
+ (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q")) |
+ (match_operand 1 "const_int_operand" "n"))) |
+ (clobber (reg:SI RTN_REG))] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
8560,10 → 8492,11
+; |
+; #warning "This predicate is appropriate for non-moves, but not for JMPs" |
+(define_insn "reg_call_var" |
+ [(parallel [(set (reg:SI RTNV_REG) |
+ [(set (reg:SI RTNV_REG) |
+ (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")) |
+ (match_operand 1 "const_int_operand" "n"))) |
+ (clobber (reg:SI RTN_REG))])] |
+ (clobber (reg:SI RTN_REG)) |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "MOV .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
8614,19 → 8547,19
+; |
+(define_insn "zip_rtu" |
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU) |
+ (clobber (cc0))] |
+ (clobber (reg:CC CC_REG))] |
+ "(!ZIP_USER)" |
+ "RTU" |
+ [(set_attr "ccresult" "unknown")]) |
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out |
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT) |
+ (clobber (cc0))] |
+ (clobber (reg:CC CC_REG))] |
+ "(!ZIP_USER)" |
+ "HALT" |
+ [(set_attr "ccresult" "unknown")]) |
+(define_insn "zip_idle" |
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE) |
+ (clobber (cc0))] |
+ (clobber (reg:CC CC_REG))] |
+ "" |
+ "WAIT" |
+ [(set_attr "ccresult" "unknown")]) |
8685,7 → 8618,7
+ STO\t%2,13(%0) |
+ STO\t%3,14(%0) |
+ STO\t%4,15(%0)" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+; |
+; See the comment above about why operand 0, %0, *must* be a "+r" operand, |
+; even though we don't really read (or change) its value throughout this |
8731,7 → 8664,7
+ MOV\t%2,uSP |
+ MOV\t%3,uCC |
+ MOV\t%4,uPC" |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")]) |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) |
+(define_insn "zip_bitrev" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV)) |
8738,7 → 8671,7
+ ] |
+ "" |
+ "BREV\t%1,%0" |
+ [(set_attr "ccresult" "set")]) |
+ [(set_attr "ccresult" "unchanged")]) |
+(define_insn "zip_cc" |
+ [(set (match_operand:SI 0 "register_operand" "=r") |
+ (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))] |
8786,7 → 8719,8
+(define_insn "addsf3" |
+ [(set (match_operand:SF 0 "register_operand" "=r") |
+ (plus:SF (match_operand:SF 1 "register_operand" "0") |
+ (match_operand:SF 2 "register_operand" "r")))] |
+ (match_operand:SF 2 "register_operand" "r"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_FPU)" |
+ "FPADD %2,%0" |
+ [(set_attr "ccresult" "unknown")]) |
8793,7 → 8727,8
+(define_insn "subsf3" |
+ [(set (match_operand:SF 0 "register_operand" "=r") |
+ (minus:SF (match_operand:SF 1 "register_operand" "0") |
+ (match_operand:SF 2 "register_operand" "r")))] |
+ (match_operand:SF 2 "register_operand" "r"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_FPU)" |
+ "FPSUB %2,%0" |
+ [(set_attr "ccresult" "unknown")]) |
8800,7 → 8735,8
+(define_insn "mulsf3" |
+ [(set (match_operand:SF 0 "register_operand" "=r") |
+ (mult:SF (match_operand:SF 1 "register_operand" "0") |
+ (match_operand:SF 2 "register_operand" "r")))] |
+ (match_operand:SF 2 "register_operand" "r"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_FPU)" |
+ "FPMUL %2,%0" |
+ [(set_attr "ccresult" "unknown")]) |
8807,7 → 8743,8
+(define_insn "divsf3" |
+ [(set (match_operand:SF 0 "register_operand" "=r") |
+ (div:SF (match_operand:SF 1 "register_operand" "0") |
+ (match_operand:SF 2 "register_operand" "r")))] |
+ (match_operand:SF 2 "register_operand" "r"))) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(ZIP_FPU)" |
+ "FPDIV %2,%0" |
+ [(set_attr "ccresult" "unknown")]) |
8821,18 → 8758,19
+ if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(SImode); |
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode))); |
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_XOR(SImode, operands[0], tmp))); |
+ emit_insn(gen_xorsi3(operands[0], operands[0], tmp)); |
+ DONE; |
+ } else { |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0])); |
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_IOR(SImode, operands[0],gen_int_mode(1,SImode)))); |
+ emit_insn(gen_iorsi3(operands[0], operands[0], |
+ gen_int_mode(1,SImode))); |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0])); |
+ DONE; |
+ } |
+ }) |
+(define_expand "abssf2" |
+ [(set (match_operand:ZI 0 "register_operand" "=r") |
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0"))) |
+ [(set (match_operand:SF 0 "register_operand" "=r") |
+ (abs:SF (match_operand:SF 1 "register_operand" "0"))) |
+ ] |
+ "" |
+ { |
8840,13 → 8778,12
+ if (can_create_pseudo_p()) { |
+ rtx tmp = gen_reg_rtx(SImode); |
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode))); |
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_AND(SImode, operands[0], tmp))); |
+ emit_insn(gen_andsi3(operands[0], operands[0], tmp)); |
+ DONE; |
+ } else { |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0])); |
+ emit_insn(gen_rtx_SET(SImode, operands[0], |
+ gen_rtx_AND(SImode, operands[0], |
+ gen_int_mode(-2,SImode)))); |
+ emit_insn(gen_andsi3(operands[0], operands[0], |
+ gen_int_mode(-2,SImode))); |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0])); |
+ DONE; |
+ } |
8876,16 → 8813,17
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")]) |
+; |
+(define_expand "ctrap<mode>4" |
+ [(set (cc0) (compare (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "nonmemory_operand" "rO"))) |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:ZI 1 "register_operand" "r") |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO"))) |
+ (trap_if (match_operator 0 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (match_operand 3 "const_int_operand" "O"))] |
+ "" |
+ ) |
+(define_insn "trapif" |
+ [(trap_if (match_operator 0 "ordered_comparison_operator" |
+ [(cc0) (const_int 0)]) |
+ [(reg:CC CC_REG) (const_int 0)]) |
+ (match_operand 1 "const_int_operand" "O"))] |
+ "" |
+ "BREAK\t%1" |
8901,53 → 8839,6
+; |
+; |
+; |
+; The book says that add<mode>3 is used if addptr<mode>3 is undefined. |
+; Hence we leave this as unimplemented. |
+; |
+;(define_insn "addptrsi3" |
+; [(set (match_operand:SI 0 "register_operand" "=r") |
+; (plus:SI (match_operand:SI 1 "register_operand" "r") |
+; (match_operand:SI 2 "general_operand" "M")))] |
+; ; Addptr is not allowed to clobber condition codes, thus we *must* |
+; ; use the mov (A+B),C form of the add. |
+; "" |
+; "MOV %2(%1),%0" |
+; [(set_attr "ccresult" "unchanged")]) |
+; |
+; (define_insn "casesi" |
+; "LDI %4,R0 |
+; SUB %2,%1 |
+; BLT %5 |
+; CMP %3,%1 |
+; BGT %5 |
+; ADD %1,R0 |
+; LOD (R0),pc" |
+; "") |
+; (define_insn "decrement_and_branch_until_zero" |
+ ; [(parallel [ |
+ ; (set (match_operand:SI 0 "regiser_operand" "r") |
+ ; (minus:SI (match_dup 0) (const_int 1))) |
+ ; (set (pc) (if_then_else |
+ ; (ge (minus:SI (match_dup 0) (const_int 1))) |
+ ; (label_ref (match_operand 1 "" "")) |
+ ; (pc)))])] |
+ ; "" |
+; ; SUB 1,%0 |
+; ; BNZ %1 |
+; ; .vice the faster (optimize for speed) |
+ ; "SUB 1,%0 |
+ ; BZ %= |
+ ; BRA %1 |
+ ; %=:" |
+ ; [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) |
+; doloop_end - do not define--would require cost of an unopt register to use |
+; allocate_stack - do not define ... |
+; nonlocal_goto - do not define |
+;(define_insn "ctrapmm4" |
+; CMP %1,%2 |
+; MOV.%0 %3,R0 |
+; LDILO.%0 0,(CC) |
+; |
+;(define_insn "sync_compare_and_swapsi" |
+; [(set ... |
+; )] |
8974,50 → 8865,57
+; "") |
+ |
+(define_peephole2 |
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "register_operand" ""))) |
+ (set (pc) (if_then_else (gtu (cc0) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:SI 0 "register_operand") |
+ (match_operand:SI 1 "register_operand"))) |
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ [(set (cc0) (compare (match_dup 1) (match_dup 0))) |
+ (set (pc) (if_then_else (ltu (cc0) (const_int 0)) |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
+(define_peephole2 |
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "register_operand" ""))) |
+ (set (pc) (if_then_else (geu (cc0) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:SI 0 "register_operand") |
+ (match_operand:SI 1 "register_operand"))) |
+ (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ [(set (cc0) (compare (match_dup 1) (plus (match_dup 0) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (cc0) (const_int 0)) |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_dup 1) (plus (match_dup 0) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
+(define_peephole2 |
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "register_operand" ""))) |
+ (set (pc) (if_then_else (ge (cc0) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:SI 0 "register_operand") |
+ (match_operand:SI 1 "register_operand"))) |
+ (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "")) |
+ (pc)))] |
+ "" |
+ [(set (cc0) (compare (match_dup 1) (match_dup 0))) |
+ (set (pc) (if_then_else (le (cc0) (const_int 0)) |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) |
+ (plus:SI (match_dup 0) (const_int 1)))) |
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
+(define_peephole2 |
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+ [(set (reg:CC CC_REG) (compare:CC |
+ (match_operand:SI 0 "register_operand" "") |
+ (match_operand:SI 1 "register_operand" ""))) |
+ (set (pc) (if_then_else (leu (cc0) (const_int 0)) |
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_operand 2 "" "")) |
+ (pc)))] |
+ "" |
+ [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (cc0) (const_int 0)) |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) |
+ (plus (match_dup 1) (const_int 1)))) |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0)) |
+ (label_ref (match_dup 2)) |
+ (pc)))] |
+ "") |
9027,26 → 8925,26
+; ... doesn't work. |
+; |
+;(define_peephole2 |
+; [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "") |
+; (match_operand:SI 1 "const_int_operand" ""))) |
+; (set (pc) (if_then_else (le (cc0) (const_int 0)) |
+; (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_operand 2 "" "")) |
+; (pc)))] |
+; "(INTVAL(operands[1])<((1<<17)-2))" |
+; [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (cc0) (const_int 0)) |
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_dup 2)) |
+; (pc)))] |
+; "") |
+;(define_peephole2 |
+; [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") |
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "") |
+; (match_operand:SI 1 "const_int_operand" ""))) |
+; (set (pc) (if_then_else (leu (cc0) (const_int 0)) |
+; (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_operand 2 "" "")) |
+; (pc)))] |
+; "(INTVAL(operands[1])<((1<<17)-2))" |
+; [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (cc0) (const_int 0)) |
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1)))) |
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0)) |
+; (label_ref (match_dup 2)) |
+; (pc)))] |
+; "") |
9060,6 → 8958,91
+; "MOV\tlabel,R0 |
+; JMP\tsubroutine" |
+; |
+; and for |
+; BRA target |
+; BRA target ; two branches to the same identical target in a row ... |
+; |
+; |
+; |
+; Match: |
+; MOV A(R1),R3 |
+; CMP R3,R0 |
+; (R3 is dead) |
+; Transform to: |
+; CMP A(R1),R0 |
+; |
+(define_peephole2 |
+ [(set (match_operand:SI 3 "register_operand") |
+ (plus:SI (match_operand:SI 1 "register_operand") |
+ (match_operand:SI 2 "zip_mvimm_operand_p"))) |
+ (set (reg:CC CC_REG) |
+ (compare:CC (match_operand:SI 0 "register_operand") |
+ (match_dup 3)))] |
+ "peep2_regno_dead_p(2, REGNO(operands[3]))" |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) |
+ (plus:SI (match_dup 1) (match_dup 2))))] |
+ "") |
+; |
+; |
+; Match: |
+; ALU OpB,R0 |
+; CMP 0,R0 |
+; Transform to: |
+; ALU OpB,R0 |
+; |
+(define_peephole2 |
+ [(parallel [(set (match_operand 0 "register_operand") |
+ (match_operand 1 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ ]) |
+; |
+; |
+; Match: |
+; ALU OpB,R0 |
+; MOV R1,R2 // Can be LDI, LOD, STO, etc. |
+; CMP 0,R1 |
+; Transform to: |
+; ALU OpB,R0 |
+; MOV R0,R1 |
+; |
+(define_peephole2 |
+ [(parallel [(set (match_operand 0 "register_operand") |
+ (match_operand 1 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand 2 "nonimmediate_operand") (match_operand 3 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] |
+ "(!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG)))" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_dup 2) (match_dup 3)) |
+ ]) |
+; |
+; |
+; Match: |
+; ALU OpB,R0 |
+; MOV R0,R1 |
+; CMP 0,R1 |
+; Transform to: |
+; ALU OpB,R0 |
+; MOV R0,R1 |
+; |
+(define_peephole2 |
+ [(parallel [(set (match_operand 0 "register_operand") |
+ (match_operand 1 "")) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_operand 2 "register_operand") (match_dup 0)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))] |
+ "" |
+ [(parallel [(set (match_dup 0) (match_dup 1)) |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]) |
+ (set (match_dup 2) (match_dup 3)) |
+ ]) |
+ |
+; |
+; STILL MISSING: |
+; SYSCALL(ID) |
+; MOV %ID,R0 |
9096,8 → 9079,8
+// config directory. |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h |
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-03-12 17:39:02.331344108 -0500 |
@@ -0,0 +1,70 @@ |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-04-06 14:25:35.431154171 -0400 |
@@ -0,0 +1,78 @@ |
+//////////////////////////////////////////////////////////////////////////////// |
+// |
+// Filename: zip-protos.h |
9146,12 → 9129,15
+extern int zip_num_arg_regs(enum machine_mode, tree); |
+ |
+extern void zip_asm_output_def(FILE *s, const char *n, const char *v); |
+ |
+#ifdef HAVE_cc0 |
+extern void zip_update_cc_notice(rtx exp, rtx_insn *insn); |
+#else |
+extern void zip_canonicalize_comparison(int *, rtx *, rtx *, bool); |
+#endif |
+extern int zip_address_operand(rtx op); |
+extern int zip_const_address_operand(rtx op); |
+extern bool zip_gen_move_rtl(rtx, rtx); |
+// extern bool zip_load_address_lod(rtx, rtx); |
+// extern bool zip_load_address_sto(rtx, rtx); |
+extern bool zip_use_return_insn(void); |
+extern const char *zip_set_zero_or_one(rtx, rtx); |
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx); |
9166,6 → 9152,11
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx); |
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx); |
+ |
+extern void zip_ifcvt_machdep_init(struct ce_if_block *ceinfo); |
+extern void zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo); |
+extern void zip_ifcvt_modify_final(struct ce_if_block *ceinfo); |
+extern void zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr); |
+ |
+#endif |
+ |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc |
9200,7 → 9191,7
exit 1 |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c |
--- gcc-5.3.0-original/gcc/cse.c 2015-02-03 15:41:38.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/cse.c 2016-03-19 12:28:45.584701098 -0400 |
+++ gcc-5.3.0-zip/gcc/cse.c 2016-04-05 22:26:30.816200542 -0400 |
@@ -634,6 +634,15 @@ |
|
/* Nonzero if X has the form (PLUS frame-pointer integer). */ |
9599,12 → 9590,12
enum expand_modifier modifier, rtx *alt_rtl, |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c |
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/final.c 2016-03-29 08:41:03.919647461 -0400 |
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-06 10:11:34.628479923 -0400 |
@@ -109,6 +109,14 @@ |
#include "wide-int-print.h" |
#include "rtl-iter.h" |
|
+ |
+// #define DO_ZIP_DEBUGS |
+#ifdef DO_ZIP_DEBUGS |
+extern void zip_debug_rtx(const_rtx); |
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0) |
9708,7 → 9699,7
} |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c |
--- gcc-5.3.0-original/gcc/jump.c 2015-01-27 04:19:30.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/jump.c 2016-04-01 06:41:10.724002408 -0400 |
+++ gcc-5.3.0-zip/gcc/jump.c 2016-04-06 14:06:50.207563805 -0400 |
@@ -80,6 +80,14 @@ |
#include "target.h" |
#include "rtl-iter.h" |
9985,7 → 9976,7
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c |
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400 |
+++ gcc-5.3.0-zip/gcc/recog.c 2016-03-29 08:44:33.142234843 -0400 |
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-06 17:45:29.552304498 -0400 |
@@ -68,6 +68,15 @@ |
#include "df.h" |
#include "insn-codes.h" |
10002,7 → 9993,15
#ifndef STACK_PUSH_CODE |
#ifdef STACK_GROWS_DOWNWARD |
#define STACK_PUSH_CODE PRE_DEC |
@@ -3671,7 +3680,6 @@ |
@@ -2283,6 +2292,7 @@ |
recog_data.n_dups = 0; |
recog_data.is_asm = false; |
|
+ZIP_DEBUG_LINE("Extract-insn", insn); |
switch (GET_CODE (body)) |
{ |
case USE: |
@@ -3671,7 +3681,6 @@ |
break; |
|
/* The buffer filled to the current maximum, so try to match. */ |
10010,7 → 10009,7
pos = peep2_buf_position (peep2_current + peep2_current_count); |
peep2_insn_data[pos].insn = PEEP2_EOB; |
COPY_REG_SET (peep2_insn_data[pos].live_before, live); |
@@ -3704,6 +3712,7 @@ |
@@ -3704,6 +3713,7 @@ |
rebuild_jump_labels (get_insns ()); |
if (peep2_do_cleanup_cfg) |
cleanup_cfg (CLEANUP_CFG_CHANGED); |
10020,7 → 10019,7
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c |
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-01 06:34:13.138506735 -0400 |
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-06 17:44:36.240674020 -0400 |
@@ -72,6 +72,14 @@ |
#include "dumpfile.h" |
#include "rtl-iter.h" |
10076,8 → 10075,33
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c |
--- gcc-5.3.0-original/gcc/reload.c 2015-01-15 08:28:42.000000000 -0500 |
+++ gcc-5.3.0-zip/gcc/reload.c 2016-03-19 12:28:30.592811127 -0400 |
@@ -2707,8 +2707,17 @@ |
+++ gcc-5.3.0-zip/gcc/reload.c 2016-04-06 17:49:33.418613170 -0400 |
@@ -136,6 +136,15 @@ |
#include "target.h" |
#include "ira.h" |
|
+// #define DO_ZIP_DEBUGS |
+#ifdef DO_ZIP_DEBUGS |
+extern void zip_debug_rtx(const_rtx); |
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0) |
+#else |
+#define ZIP_DEBUG_LINE(STR,RTX) |
+#endif |
+ |
+ |
/* True if X is a constant that can be forced into the constant pool. |
MODE is the mode of the operand, or VOIDmode if not known. */ |
#define CONST_POOL_OK_P(MODE, X) \ |
@@ -2700,6 +2709,8 @@ |
hard_regs_live_known = live_known; |
static_reload_reg_p = reload_reg_p; |
|
+ZIP_DEBUG_LINE("Find reloads\n", insn); |
+ |
/* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; |
neither are insns that SET cc0. Insns that use CC0 are not allowed |
to have any input reloads. */ |
@@ -2707,8 +2718,17 @@ |
no_output_reloads = 1; |
|
#ifdef HAVE_cc0 |