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Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu
    from Rev 177 to Rev 178
    Reverse comparison

Rev 177 → Rev 178

/trunk/rtl/core/idecode.v
104,7 → 104,7
wire [3:0] w_cond;
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp;
wire w_ljmp, w_ljmp_dly;
wire [31:0] iword;
 
 
148,7 → 148,9
// If the result register is either CC or PC, and this would otherwise
// be a floating point instruction with floating point opcode of 0,
// then this is a NOOP.
assign w_noop = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7);
assign w_noop = (w_op[4:0] == 5'h18)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
||(IMPLEMENT_FPU==0));
 
// 4 LUTs
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
249,9 → 251,10
reg r_phase;
initial r_phase = 1'b0;
always @(posedge i_clk)
if (i_rst) // When no instruction is in the pipe, phase is zero
if ((i_rst) // When no instruction is in the pipe, phase is zero
||(o_early_branch)||(w_ljmp_dly))
r_phase <= 1'b0;
else if (i_ce)
else if ((i_ce)&&(i_pf_valid))
r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
// Phase is '1' on the first instruction of a two-part set
// But, due to the delay in processing, it's '1' when our output is
276,7 → 279,7
`else
o_illegal <= ((i_illegal) || (i_instruction[31]));
`endif
if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)))
o_illegal <= 1'b1;
 
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
357,10 → 360,14
o_M <= w_dcdM;
o_DV <= w_dcdDV;
o_FP <= w_dcdFP;
 
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
o_break <= (w_op[4:0]==5'b11001)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
||(IMPLEMENT_FPU==0));
`ifdef OPT_PIPELINED
r_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
r_lock <= (w_op[4:0]==5'b11010)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
||(IMPLEMENT_FPU==0));
`endif
`ifdef OPT_VLIW
r_nxt_half <= { iword[31], iword[13:5],
426,9 → 433,11
+ {{(AW-1){1'b0}},1'b1};
end
 
assign w_ljmp_dly = r_ljmp;
assign o_early_branch = r_early_branch;
assign o_branch_pc = r_branch_pc;
end else begin
assign w_ljmp_dly = 1'b0;
assign o_early_branch = 1'b0;
assign o_branch_pc = {(AW){1'b0}};
assign o_ljmp = 1'b0;

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