URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 193 to Rev 194
- ↔ Reverse comparison
Rev 193 → Rev 194
/trunk/rtl/core/pfcache.v
13,7 → 13,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
38,8 → 38,12
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, |
o_illegal); |
parameter LGCACHELEN = 8, ADDRESS_WIDTH=24, |
CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH, |
CW=LGCACHELEN, PW=LGCACHELEN-5; |
LGLINES=5; // Log of the number of separate cache lines |
localparam CACHELEN=(1<<LGCACHELEN); // Size of our cache memory |
localparam CW=LGCACHELEN; // Short hand for LGCACHELEN |
localparam PW=LGCACHELEN-LGLINES; // Size of a cache line |
localparam BUSW = 32; // Number of data lines on the bus |
localparam AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH |
input i_clk, i_rst, i_new_pc; |
input i_clear_cache; |
input i_stall_n; |
66,8 → 70,8
|
wire r_v; |
reg [(BUSW-1):0] cache [0:((1<<CW)-1)]; |
reg [(AW-CW-1):0] tags [0:((1<<(CW-PW))-1)]; |
reg [((1<<(CW-PW))-1):0] vmask; |
reg [(AW-CW-1):0] tags [0:((1<<(LGLINES))-1)]; |
reg [((1<<(LGLINES))-1):0] vmask; |
|
reg [(AW-1):0] lastpc; |
reg [(CW-1):0] rdaddr; |
255,7 → 259,7
reg svmask; |
initial vmask = 0; |
initial svmask = 1'b0; |
reg [(CW-PW-1):0] saddr; |
reg [(LGLINES-1):0] saddr; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) |
begin |
/trunk/rtl/core/pipemem.v
42,7 → 42,7
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
/trunk/rtl/zipsystem.v
170,7 → 170,7
, o_cpu_debug |
`endif |
); |
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24, |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1, |
`ifdef OPT_MULTIPLY |
IMPLEMENT_MPY = `OPT_MULTIPLY, |
523,6 → 523,9
wire [31:0] dc_data; |
wire [(AW-1):0] dc_addr; |
wire cpu_gbl_cyc; |
wire [31:0] dmac_int_vec; |
assign dmac_int_vec = { 1'b0, alt_int_vector, 1'b0, |
main_int_vector[14:1], 1'b0 }; |
assign dmac_stb = (sys_stb)&&(sys_addr[4]); |
`ifdef INCLUDE_DMA_CONTROLLER |
wbdmac #(AW) dma_controller(i_clk, cpu_reset, |
533,8 → 536,7
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_ack, dc_stall, ext_idata, dc_err, |
// External device interrupts |
{ 1'b0, alt_int_vector, 1'b0, |
main_int_vector[14:1], 1'b0 }, |
dmac_int_vec, |
// DMAC interrupt, for upon completion |
dmac_int); |
`else |
782,7 → 784,7
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall |
| wdt_stall | ctri_stall | actr_stall |
| pic_stall | dmac_stall); |
| pic_stall | dmac_stall); // Always 1'b0! |
assign cpu_stall = (sys_stall)|(cpu_ext_stall); |
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack); |
assign cpu_ack = (sys_ack)||(cpu_ext_ack); |