URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 200 to Rev 201
- ↔ Reverse comparison
Rev 200 → Rev 201
/zipcpu/trunk/rtl/Makefile
13,7 → 13,7
# |
################################################################################ |
# |
# Copyright (C) 2015-2016, Gisselquist Technology, LLC |
# Copyright (C) 2015-2017, Gisselquist Technology, LLC |
# |
# This program is free software (firmware): you can redistribute it and/or |
# modify it under the terms of the GNU General Public License as published |
32,7 → 32,7
################################################################################ |
# |
.PHONY: all |
all: zipsystem zipbones cpudefs.h div zipmmu cpuops |
all: zipsystem zipbones cpudefs.h div zipmmu cpuops pfcache |
|
CORED:= core |
PRPHD:= peripherals |
57,46 → 57,56
$(CORED)/div.v \ |
$(AUXD)/busdelay.v $(AUXD)/wbdblpriarb.v \ |
$(CORED)/idecode.v $(CORED)/cpuops.v |
|
VOBJ := obj_dir |
SUBMAKE := $(MAKE) --no-print-directory --directory=$(VOBJ) -f |
|
|
VERILATE=verilator --trace -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) |
|
$(VOBJ)/Vzipsystem.cpp: $(VSRC) |
verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipsystem.v |
$(VERILATE) zipsystem.v |
$(VOBJ)/Vzipsystem.h: $(VOBJ)/Vzipsystem.cpp |
|
$(VOBJ)/Vzipbones.cpp: $(VZIP) |
verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipbones.v |
$(VERILATE) zipbones.v |
$(VOBJ)/Vzipbones.h: $(VOBJ)/Vzipbones.cpp |
|
$(VOBJ)/Vdiv.cpp: $(CORED)/div.v |
verilator -cc -y $(CORED) $(CORED)/div.v |
$(VERILATE) $(CORED)/div.v |
$(VOBJ)/Vdiv.h: $(VOBJ)/Vdiv.cpp |
|
$(VOBJ)/Vcpuops.cpp: $(CORED)/cpuops.v cpudefs.v |
verilator -cc -y $(CORED) $(CORED)/cpuops.v |
$(VERILATE) $(CORED)/cpuops.v |
$(VOBJ)/Vcpuops.h: $(VOBJ)/Vcpuops.cpp |
|
$(VOBJ)/Vzipmmu.cpp: $(PRPHD)/zipmmu.v |
verilator -cc -y $(PRPHD) $(PRPHD)/zipmmu.v |
$(VERILATE) $(PRPHD)/zipmmu.v |
$(VOBJ)/Vzipmmu.h: $(VOBJ)/Vzipmmu.cpp |
|
$(VOBJ)/Vpfcache.cpp: $(CORED)/pfcache.v |
$(VERILATE) $(CORED)/pfcache.v |
$(VOBJ)/Vpfcache.h: $(VOBJ)/Vpfcache.cpp |
|
$(VOBJ)/Vzipsystem__ALL.a: $(VOBJ)/Vzipsystem.cpp $(VOBJ)/Vzipsystem.h |
cd $(VOBJ); make --no-print-directory -f Vzipsystem.mk |
$(SUBMAKE) Vzipsystem.mk |
|
$(VOBJ)/Vzipbones__ALL.a: $(VOBJ)/Vzipbones.cpp $(VOBJ)/Vzipbones.h |
cd $(VOBJ); make --no-print-directory -f Vzipbones.mk |
$(SUBMAKE) Vzipbones.mk |
|
$(VOBJ)/Vdiv__ALL.a: $(VOBJ)/Vdiv.cpp $(VOBJ)/Vdiv.h |
cd $(VOBJ); make --no-print-directory -f Vdiv.mk |
$(SUBMAKE) Vdiv.mk |
|
$(VOBJ)/Vcpuops__ALL.a: $(VOBJ)/Vcpuops.cpp $(VOBJ)/Vcpuops.h |
cd $(VOBJ); make --no-print-directory -f Vcpuops.mk |
$(SUBMAKE) Vcpuops.mk |
|
$(VOBJ)/Vzipmmu__ALL.a: $(VOBJ)/Vzipmmu.cpp $(VOBJ)/Vzipmmu.h |
cd $(VOBJ); make --no-print-directory -f Vzipmmu.mk |
$(SUBMAKE) Vzipmmu.mk |
|
$(VOBJ)/Vpfcache__ALL.a: $(VOBJ)/Vpfcache.cpp $(VOBJ)/Vpfcache.h |
$(SUBMAKE) Vpfcache.mk |
|
# $(VOBJ)/V%__ALL.a: $(VOBJ)/V%.cpp $(VOBJ)/V%.h |
# cd $(VOBJ); make --no-print-directory -f V%.mk |
# $(SUBMAKE) V%.mk |
|
cpudefs.h: cpudefs.v |
@echo "Building cpudefs.h" |
121,6 → 131,9
.PHONY: zipmmu |
zipmmu: $(VOBJ)/Vzipmmu__ALL.a |
|
.PHONY: pfcache |
pfcache: $(VOBJ)/Vpfcache__ALL.a |
|
.PHONY: clean |
clean: |
rm -rf $(VOBJ) cpudefs.h |
/zipcpu/trunk/rtl/aux/busdelay.v
37,7 → 37,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
49,6 → 49,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
55,12 → 60,13
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module busdelay(i_clk, |
// The input bus |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, |
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err, |
// The delayed bus |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data, |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel, |
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err); |
parameter AW=32, DW=32, DELAY_STALL = 0; |
input i_clk; |
68,6 → 74,7
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(AW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
input [(DW/8-1):0] i_wb_sel; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
76,6 → 83,7
output reg o_dly_cyc, o_dly_stb, o_dly_we; |
output reg [(AW-1):0] o_dly_addr; |
output reg [(DW-1):0] o_dly_data; |
output reg [(DW/8-1):0] o_dly_sel; |
input i_dly_ack; |
input i_dly_stall; |
input [(DW-1):0] i_dly_data; |
85,8 → 93,9
if (DELAY_STALL != 0) |
begin |
reg r_stb, r_we, r_rtn_stall, r_rtn_err; |
reg [(AW-1):0] r_addr; |
reg [(DW-1):0] r_data; |
reg [(AW-1):0] r_addr; |
reg [(DW/8-1):0] r_sel; |
|
initial o_dly_cyc = 1'b0; |
initial r_rtn_stall= 1'b0; |
100,6 → 109,7
r_we <= i_wb_we; |
r_addr <= i_wb_addr; |
r_data <= i_wb_data; |
r_sel <= i_wb_sel; |
|
if (r_stb) |
begin |
106,6 → 116,7
o_dly_we <= r_we; |
o_dly_addr <= r_addr; |
o_dly_data <= r_data; |
o_dly_sel <= r_sel; |
o_dly_stb <= 1'b1; |
r_rtn_stall <= 1'b0; |
r_stb <= 1'b0; |
113,6 → 124,7
o_dly_we <= i_wb_we; |
o_dly_addr <= i_wb_addr; |
o_dly_data <= i_wb_data; |
o_dly_sel <= i_wb_sel; |
o_dly_stb <= i_wb_stb; |
r_stb <= 1'b0; |
r_rtn_stall <= 1'b0; |
122,6 → 134,7
r_we <= i_wb_we; |
r_addr <= i_wb_addr; |
r_data <= i_wb_data; |
r_sel <= i_wb_sel; |
r_stb <= i_wb_stb; |
|
r_rtn_stall <= i_wb_stb; |
165,6 → 178,9
if (~o_wb_stall) |
o_dly_data <= i_wb_data; |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_sel <= i_wb_sel; |
always @(posedge i_clk) |
o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc); |
always @(posedge i_clk) |
o_wb_data <= i_dly_data; |
/zipcpu/trunk/rtl/aux/wbarbiter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbarbiter.v |
// |
34,9 → 34,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
48,20 → 48,26
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define WBA_ALTERNATING |
module wbarbiter(i_clk, i_rst, |
// Bus A |
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err); |
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err); |
// 18 bits will address one GB, 4 bytes at a time. |
// 19 bits will allow the ability to address things other than just |
// the 1GB of memory we are expecting. |
71,6 → 77,7
input i_clk, i_rst; |
input [(AW-1):0] i_a_adr, i_b_adr; |
input [(DW-1):0] i_a_dat, i_b_dat; |
input [(DW/8-1):0] i_a_sel, i_b_sel; |
input i_a_we, i_a_stb, i_a_cyc; |
input i_b_we, i_b_stb, i_b_cyc; |
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall, |
77,6 → 84,7
o_a_err, o_b_err; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
output wire o_we, o_stb, o_cyc; |
input i_ack, i_stall, i_err; |
|
159,11 → 167,12
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
// irrelevant. (This allows us to get two outputs per Xilinx 6-LUT) |
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb); |
assign o_we = (w_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat; |
assign o_we = (w_a_owner) ? i_a_we : i_b_we; |
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb); |
assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
/zipcpu/trunk/rtl/aux/wbdblpriarb.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdblpriarb.v |
// |
42,9 → 42,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
56,19 → 56,25
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module wbdblpriarb(i_clk, i_rst, |
// |
module wbdblpriarb(i_clk, i_rst, |
// Bus A |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel, |
i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
78,28 → 84,31
input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
input [(DW/8-1):0] i_a_sel; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
input [(DW/8-1):0] i_b_sel; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
// |
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
input i_ack, i_stall, i_err; |
|
// All of our logic is really captured in the 'r_a_owner' register. |
// This register determines who owns the bus. If no one is requesting |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// requesting the bus and A is not, then ownership goes to not A on |
// the next clock. (Sounds simple ...) |
// |
// The CYC logic is here to make certain that, by the time we determine |
// who the bus owner is, we can do so based upon determined criteria. |
assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
109,9 → 118,34
r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1; |
|
|
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
`ifdef ZERO_ON_IDLE |
// |
// ZERO_ON_IDLE uses more logic than the alternative. It should be |
// useful for reducing power, as these circuits tend to drive wires |
// all the way across the design, but it may also slow down the master |
// clock. I've used it as an option when using VERILATOR, 'cause |
// zeroing things on idle can make them stand out all the more when |
// staring at wires and dumps and such. |
// |
wire o_cyc, o_stb; |
assign o_cyc = ((o_cyc_a)||(o_cyc_b)); |
assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b)); |
assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a); |
assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b); |
assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0; |
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; |
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; |
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0; |
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1; |
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0; |
`else |
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on these various lines are |
// irrelevant. |
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; |
119,6 → 153,7
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
137,6 → 172,7
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
`endif |
|
endmodule |
|
/zipcpu/trunk/rtl/aux/wbpriarbiter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbpriarbiter.v |
// |
25,9 → 25,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
39,19 → 39,25
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module wbpriarbiter(i_clk, |
// |
module wbpriarbiter(i_clk, |
// Bus A |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err); |
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// |
input i_clk; |
59,16 → 65,19
input i_a_cyc, i_a_stb, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
input [(DW/8-1):0] i_a_sel; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc, i_b_stb, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
input [(DW/8-1):0] i_b_sel; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
// |
output wire o_cyc, o_stb, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
input i_ack, i_stall, i_err; |
|
// Go high immediately (new cycle) if ... |
89,13 → 98,34
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
`ifdef ZERO_ON_IDLE |
// |
// ZERO_ON_IDLE will use up more logic and may even slow down the master |
// clock if set. However, it may also reduce the power used by the |
// FPGA by preventing things from toggling when the bus isn't in use. |
// The option is here because it also makes it a lot easier to look |
// for when things happen on the bus via VERILATOR when timing and |
// logic counts don't matter. |
// |
assign o_stb = (o_cyc)?((r_a_owner) ? i_a_stb : i_b_stb):0; |
assign o_adr = (o_stb)?((r_a_owner) ? i_a_adr : i_b_adr):0; |
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; |
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; |
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0; |
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1; |
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0; |
`else |
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
108,10 → 138,11
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// |
// |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
`endif |
|
endmodule |
|
/zipcpu/trunk/rtl/core/idecode_deprecated.v
File deleted
/zipcpu/trunk/rtl/core/cpuops_deprecated.v
File deleted
/zipcpu/trunk/rtl/core/cpuops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops.v |
// |
12,9 → 12,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,11 → 26,16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
`include "cpudefs.v" |
// |
45,12 → 50,6
output reg o_valid; |
output wire o_busy; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result, w_lsl_result; |
wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted; |
75,28 → 74,20
assign w_brev_result[k] = i_b[31-k]; |
end endgenerate |
|
// Popcount pre-logic |
wire [31:0] w_popc_result; |
assign w_popc_result[5:0]= |
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]}) |
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]}) |
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]}) |
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]}) |
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]}) |
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]}) |
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]}) |
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]}); |
assign w_popc_result[31:6] = 26'h00; |
|
// Prelogic for our flags registers |
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl; |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'h6) // LSL |
||(i_op == 4'h5)); // LSR |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
keep_sgn_on_ovfl<= |
(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD |
|
wire [63:0] mpy_result; // Where we dump the multiply result |
reg mpyhi; // Return the high half of the multiply |
110,7 → 101,7
// this will cost a minimum of 132 6-LUTs. |
|
wire this_is_a_multiply_op; |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8)); |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc)); |
|
generate |
if (IMPLEMENT_MPY == 0) |
333,13 → 324,11
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= mpy_result[31:0]; // MPY |
4'b1000: o_c <= w_brev_result; // BREV |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= mpy_result[31:0]; // MPY |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else // if (mpydone) |
359,8 → 348,9
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n, c, z }; |
assign o_f = { v, n^vx, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
/zipcpu/trunk/rtl/core/dcache.v
0,0 → 1,507
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: dcache.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: To provide a simple data cache for the ZipCPU. The cache is |
// designed to be a drop in replacement for the pipememm memory |
// unit currently existing within the ZipCPU. The goal of this unit is |
// to achieve single cycle read access to any memory in the last cache line |
// used, or two cycle access to any memory currently in the cache. |
// |
// The cache separates between four types of accesses, one write and three |
// read access types. The read accesses are split between those that are |
// not cacheable, those that are in the cache, and those that are not. |
// |
// 1. Write accesses always create writes to the bus. For these reasons, |
// these may always be considered cache misses. |
// |
// Writes to memory locations within the cache must also update |
// cache memory immediately, to keep the cache in synch. |
// |
// It is our goal to be able to maintain single cycle write |
// accesses for memory bursts. |
// |
// 2. Read access to non-cacheable memory locations will also immediately |
// go to the bus, just as all write accesses go to the bus. |
// |
// 3. Read accesses to cacheable memory locations will immediately read |
// from the appropriate cache line. However, since thee valid |
// line will take a second clock to read, it may take up to two |
// clocks to know if the memory was in cache. For this reason, |
// we bypass the test for the last validly accessed cache line. |
// |
// We shall design these read accesses so that reads to the cache |
// may take place concurrently with other writes to the bus. |
// |
// Errors in cache reads will void the entire cache line. For this reason, |
// cache lines must always be of a smaller in size than any associated |
// virtual page size--lest in the middle of reading a page a TLB miss |
// take place referencing only a part of the cacheable page. |
// |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module dcache(i_clk, i_rst, i_pipe_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg,o_data, |
o_wb_cyc_gbl, o_wb_cyc_lcl, o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter LGCACHELEN = 8, |
ADDRESS_WIDTH=32, |
LGNLINES=5, // Log of the number of separate cache lines |
IMPLEMENT_LOCK=0, |
NAUX=5; // # of aux d-wires to keep aligned w/memops |
localparam SDRAM_BIT = 26; |
localparam FLASH_BIT = 22; |
localparam BLKRAM_BIT= 15; |
localparam AW = ADDRESS_WIDTH; // Just for ease of notation below |
localparam CS = LGCACHELEN; // Number of bits in a cache address |
localparam LS = CS-LGNLINES; // Bits to spec position w/in cline |
localparam LGAUX = 3; // log_2 of the maximum number of piped data |
input i_clk, i_rst; |
// Interface from the CPU |
input i_pipe_stb, i_lock; |
input i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [(NAUX-1):0] i_oreg; // Aux data, such as reg to write to |
// Outputs, going back to the CPU |
output wire o_busy, o_pipe_stalled, o_valid, o_err; |
output reg [(NAUX-1):0] o_wreg; |
output reg [31:0] o_data; |
// Wishbone bus master outputs |
output wire o_wb_cyc_gbl, o_wb_cyc_lcl; |
output reg o_wb_stb_gbl, o_wb_stb_lcl; |
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
// Wishbone bus slave response inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
|
reg cyc, stb, last_ack, end_of_line, last_line_stb; |
|
|
reg [((1<<LGNLINES)-1):0] c_v; // One bit per cache line, is it valid? |
reg [(AW-LS-1):0] c_vtags [0:((1<<LGNLINES)-1)]; |
reg [31:0] c_mem [0:((1<<CS)-1)]; |
// reg [((1<<LGNLINES)-1):0] c_wr; // Is the cache line writable? |
// reg c_wdata; |
// reg c_waddr; |
|
// To simplify writing to the cache, and the job of the synthesizer to |
// recognize that a cache write needs to take place, we'll take an extra |
// clock to get there, and use these c_w... registers to capture the |
// data in the meantime. |
reg c_wr; |
reg [31:0] c_wdata; |
reg [(CS-1):0] c_waddr; |
|
reg [(AW-LS-1):0] last_tag; |
|
|
wire [(LGNLINES-1):0] i_cline; |
wire [(CS-1):0] i_caddr; |
wire [(AW-LS-1):0] i_ctag; |
|
assign i_cline = i_addr[(CS-1):LS]; |
assign i_caddr = i_addr[(CS-1):0]; |
assign i_ctag = i_addr[(AW-1):LS]; |
|
wire cache_miss_inow, w_cachable; |
assign cache_miss_inow = (last_tag != i_addr[31:LS])||(!c_v[i_cline]); |
assign w_cachable = (i_addr[31:30]!=2'b11)&&(!i_lock)&&( |
((SDRAM_BIT>0)&&(i_addr[SDRAM_BIT])) |
||((FLASH_BIT>0)&&(i_addr[FLASH_BIT])) |
||((BLKRAM_BIT>0)&&(i_addr[BLKRAM_BIT]))); |
|
reg r_cachable, r_svalid, r_dvalid, r_rd, r_cache_miss, r_rvalid; |
reg [(AW-1):0] r_addr; |
reg [31:0] r_idata, r_ddata, r_rdata; |
wire [(LGNLINES-1):0] r_cline; |
wire [(CS-1):0] r_caddr; |
wire [(AW-LS-1):0] r_ctag; |
|
assign r_cline = r_addr[(CS-1):LS]; |
assign r_caddr = r_addr[(CS-1):0]; |
assign r_ctag = r_addr[(AW-1):LS]; |
|
|
reg wr_cstb, r_iv, pipeable_op, non_pipeable_op, in_cache; |
reg [(AW-LS-1):0] r_itag; |
|
// |
// The one-clock delayed read values from the cache. |
// |
initial r_rd = 1'b0; |
initial r_cachable = 1'b0; |
initial r_svalid = 1'b0; |
initial r_dvalid = 1'b0; |
always @(posedge i_clk) |
begin |
// The single clock path |
r_idata <= c_mem[i_addr[(CS-1):0]]; |
// The valid for the single clock path |
// Only ... we need to wait if we are currently writing |
// to our cache. |
r_svalid<= (!i_op)&&(!cache_miss_inow)&&(w_cachable) |
&&(i_pipe_stb)&&(!c_wr)&&(!wr_cstb); |
|
// |
// The two clock in-cache path |
// |
// Some preliminaries that needed to be calculated on the first |
// clock |
if (!o_busy) |
begin |
r_iv <= c_v[i_cline]; |
r_itag <= c_vtags[i_cline]; |
r_addr <= i_addr; |
r_cachable <= (!i_op)&&(w_cachable)&&(i_pipe_stb); |
end else begin |
r_iv <= c_v[r_cline]; |
r_itag <= c_vtags[r_cline]; |
end |
// r_idata still contains the right answer |
r_rd <= (i_pipe_stb)&&(!i_op); |
r_ddata <= r_idata; |
// r_itag contains the tag we didn't have available to us on the |
// last clock, r_ctag is a bit select from r_addr containing a |
// one clock delayed address. |
r_dvalid <= (r_itag == r_ctag)&&(r_iv)&&(r_cachable); |
if ((r_itag == r_ctag)&&(r_iv)&&(r_cachable)) |
last_tag <= r_ctag; |
|
// r_cache miss takes a clock cycle. It is only ever true for |
// something that should be cachable, but isn't in the cache. |
// A cache miss is only true _if_ |
// 1. A read was requested |
// 2. It is for a cachable address, AND |
// 3. It isn't in the cache on the first read |
// or the second read |
// 4. The read hasn't yet started to get this address |
r_cache_miss <= ((!cyc)||(o_wb_we))&&(r_cachable) |
// One clock path -- miss |
&&(!r_svalid) |
// Two clock path -- misses as well |
&&(r_rd)&&(!r_svalid) |
&&((r_itag != r_ctag)||(!r_iv)); |
|
r_rdata <= c_mem[r_addr[(CS-1):0]]; |
r_rvalid<= ((i_wb_ack)&&(last_ack)); |
end |
|
`define DC_IDLE 2'b00 |
`define DC_WRITE 2'b01 |
`define DC_READS 2'b10 |
`define DC_READC 2'b11 |
reg [1:0] state; |
|
reg [(AW-LS-1):0] wr_wtag, wr_vtag; |
reg [31:0] wr_data; |
reg [(CS-1):0] wr_addr; |
always @(posedge i_clk) |
begin |
// By default, update the cache from the write 1-clock ago |
c_wr <= (wr_cstb)&&(wr_wtag == wr_vtag); |
c_wdata <= wr_data; |
c_waddr <= wr_addr[(CS-1):0]; |
|
wr_cstb <= 1'b0; |
wr_vtag <= c_vtags[o_wb_addr[(CS-LS-1):0]]; |
wr_wtag <= o_wb_addr[(AW-LS-1):0]; |
wr_data <= o_wb_data; |
wr_addr <= o_wb_addr[(CS-1):0]; |
|
|
if (LS <= 1) |
end_of_line <= 1'b1; |
else |
end_of_line<=(cyc)&&((c_waddr[(LS-1):1]=={(LS-1){1'b1}}) |
||((i_wb_ack) |
&&(c_waddr[(LS-1):0]=={{(LS-2){1'b1}},2'b01}))); |
|
if (LS <= 1) |
last_line_stb <= 1'b1; |
else |
last_line_stb <= (stb)&& |
((o_wb_addr[(LS-1):1]=={(LS-1){1'b1}}) |
||((!i_wb_stall) |
&&(o_wb_addr[(LS-1):0] |
=={{(LS-2){1'b1}},2'b01}))); |
|
// |
if (state == `DC_IDLE) |
pipeable_op <= 1'b0; |
if (state == `DC_IDLE) |
non_pipeable_op <= 1'b0; |
|
|
if (state == `DC_IDLE) |
begin |
o_wb_we <= 1'b0; |
o_wb_data <= i_data; |
pipeable_op <= 1'b0; |
non_pipeable_op <= 1'b1; |
|
cyc <= 1'b0; |
stb <= 1'b0; |
|
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
o_wb_stb_gbl <= 1'b0; |
o_wb_stb_lcl <= 1'b0; |
|
in_cache <= (i_op)&&(w_cachable); |
if ((i_pipe_stb)&&(i_op)) |
begin // Write operation |
state <= `DC_WRITE; |
o_wb_addr <= i_addr; |
o_wb_we <= 1'b1; |
pipeable_op <= 1'b1; |
|
cyc <= 1'b1; |
stb <= 1'b1; |
|
r_wb_cyc_gbl <= (i_addr[31:30]!=2'b11); |
r_wb_cyc_lcl <= (i_addr[31:30]==2'b11); |
o_wb_stb_gbl <= (i_addr[31:30]!=2'b11); |
o_wb_stb_lcl <= (i_addr[31:30]==2'b11); |
|
end else if (r_cache_miss) |
begin |
state <= `DC_READC; |
o_wb_addr <= { i_ctag, {(LS){1'b0}} }; |
non_pipeable_op <= 1'b1; |
|
cyc <= 1'b1; |
stb <= 1'b1; |
r_wb_cyc_gbl <= 1'b1; |
o_wb_stb_gbl <= 1'b1; |
end else if ((i_pipe_stb)&&(!w_cachable)) |
begin // Read non-cachable memory area |
state <= `DC_READS; |
o_wb_addr <= i_addr; |
pipeable_op <= 1'b1; |
|
cyc <= 1'b1; |
stb <= 1'b1; |
r_wb_cyc_gbl <= (i_addr[31:30]!=2'b11); |
r_wb_cyc_lcl <= (i_addr[31:30]==2'b11); |
o_wb_stb_gbl <= (i_addr[31:30]!=2'b11); |
o_wb_stb_lcl <= (i_addr[31:30]==2'b11); |
end // else we stay idle |
|
end else if (state == `DC_READC) |
begin |
// We enter here once we have committed to reading |
// data into a cache line. |
if ((stb)&&(!i_wb_stall)) |
begin |
stb <= (!last_line_stb); |
o_wb_stb_gbl <= (!last_line_stb); |
o_wb_addr[(LS-1):0] <= o_wb_addr[(LS-1):0]+1'b1; |
end |
|
if(stb) |
c_v[o_wb_addr[(CS-LS-1):0]] <= 1'b0; |
|
c_wr <= (i_wb_ack); |
c_wdata <= o_wb_data; |
c_waddr <= ((c_wr)?(c_waddr+1'b1):c_waddr); |
|
c_vtags[o_wb_addr[(CS-LS-1):0]]<= o_wb_addr[(AW-LS-1):0]; |
|
if (((i_wb_ack)&&(end_of_line))||(i_wb_err)) |
begin |
state <= `DC_IDLE; |
non_pipeable_op <= 1'b0; |
cyc <= 1'b0; |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
// |
c_v[o_wb_addr[(CS-LS-1):0]] <= i_wb_ack; |
end |
end else if (state == `DC_READS) |
begin |
// We enter here once we have committed to reading |
// data that cannot go into a cache line |
if ((!i_wb_stall)&&(!i_pipe_stb)) |
begin |
stb <= 1'b0; |
o_wb_stb_gbl <= 1'b0; |
o_wb_stb_lcl <= 1'b0; |
pipeable_op <= 1'b0; |
end |
|
if ((!i_wb_stall)&&(i_pipe_stb)) |
o_wb_addr <= i_data; |
|
c_wr <= 1'b0; |
|
if (((i_wb_ack)&&(last_ack))||(i_wb_err)) |
begin |
state <= `DC_IDLE; |
cyc <= 1'b0; |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
end |
end else if (state == `DC_WRITE) |
begin |
// c_wr <= (c_v[])&&(c_tag[])&&(in_cache)&&(stb); |
c_wdata <= o_wb_data; |
c_waddr <= (state == `DC_IDLE)?i_caddr |
: ((c_wr)?(c_waddr+1'b1):c_waddr); |
|
if ((!i_wb_stall)&&(!i_pipe_stb)) |
begin |
stb <= 1'b0; |
o_wb_stb_gbl <= 1'b0; |
o_wb_stb_lcl <= 1'b0; |
pipeable_op <= 1'b0; |
end |
|
wr_cstb <= (stb)&&(!i_wb_stall)&&(in_cache); |
|
if ((stb)&&(!i_wb_stall)&&(i_pipe_stb)) |
o_wb_addr <= i_addr; |
if ((stb)&&(!i_wb_stall)&&(i_pipe_stb)) |
o_wb_data <= i_data; |
|
if (((i_wb_ack)&&(last_ack))||(i_wb_err)) |
begin |
state <= `DC_IDLE; |
cyc <= 1'b0; |
r_wb_cyc_gbl <= 1'b0; |
r_wb_cyc_lcl <= 1'b0; |
end |
end |
end |
|
// |
// Writes to the cache |
// |
// These have been made as simple as possible. Note that the c_wr |
// line has already been determined, as have the write value and address |
// on the last clock. Further, this structure is defined to match the |
// block RAM design of as many architectures as possible. |
// |
always @(posedge i_clk) |
if (c_wr) |
c_mem[c_waddr] <= c_wdata; |
|
// |
// Reads from the cache |
// |
// Some architectures require that all reads be registered. We |
// accomplish that here. Whether or not the result of this read is |
// going to be our output will need to be determined with combinatorial |
// logic on the output. |
// |
reg [31:0] cached_idata, cached_rdata; |
always @(posedge i_clk) |
cached_idata <= c_mem[i_caddr]; |
|
always @(posedge i_clk) |
cached_rdata <= c_mem[r_caddr]; |
|
// o_data can come from one of three places: |
// 1. The cache, assuming the data was in the last cache line |
// 2. The cache, second clock, assuming the data was in the cache at all |
// 3. The cache, after filling the cache |
// 4. The wishbone state machine, upon reading the value desired. |
always @(posedge i_clk) |
if (r_svalid) |
o_data <= cached_idata; |
else if ((i_wb_ack)&&(pipeable_op)) |
o_data <= i_wb_data; |
else |
o_data <= cached_rdata; |
always @(posedge i_clk) |
o_valid <= (r_svalid)||((i_wb_ack)&&(pipeable_op)) |
||(r_dvalid)||(r_rvalid); |
always @(posedge i_clk) |
o_err <= (cyc)&&(i_wb_err); |
|
assign o_busy = (state != `DC_IDLE); |
|
|
// |
// Handle our auxilliary data lines. |
// |
// These just go into a FIFO upon request, and then get fed back out |
// upon completion of an OP. |
// |
// These are currently designed for handling bursts of writes or |
// non-cachable reads. |
// |
// A very similar structure will be used once we switch to using an |
// MMU, in order to make certain memory operations are synchronous |
// enough to deal with bus errors. |
// |
reg [(LGAUX-1):0] aux_head, aux_tail; |
reg [(NAUX-1):0] aux_fifo [0:((1<<LGAUX)-1)]; |
initial aux_head = 0; |
initial aux_tail = 0; |
always @(posedge i_clk) |
begin |
if ((i_rst)||(i_wb_err)) |
aux_head <= 0; |
else if ((i_pipe_stb)&&(!o_busy)) |
aux_head <= aux_head + 1'b1; |
aux_fifo[aux_head] <= i_oreg; |
end |
always @(posedge i_clk) |
begin |
if ((i_rst)||(i_wb_err)) |
aux_tail <= 0; |
else if (o_valid) // ||(aux_tail[WBIT])&&(no-mmu-error) |
aux_tail <= aux_tail + 1'b1; |
o_wreg <= aux_fifo[aux_tail]; |
end |
|
// |
// We can use our FIFO addresses to pre-calculate when an ACK is going |
// to be the last_noncachable_ack. |
|
|
assign o_pipe_stalled=((pipeable_op)&&(i_wb_stall))||(non_pipeable_op); |
// pipeable_op must become zero when stb goes low |
|
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl); |
endmodule |
/zipcpu/trunk/rtl/core/div.v
1,18 → 1,77
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: div.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Provide an Integer divide capability to the Zip CPU. |
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides |
// for both signed and unsigned divide. |
// |
// Steps: |
// i_rst The DIVide unit starts in idle. It can also be placed into an |
// idle by asserting the reset input. |
// |
// i_wr When i_rst is asserted, a divide begins. On the next clock: |
// |
// o_busy is set high so everyone else knows we are at work and they can |
// wait for us to complete. |
// |
// pre_sign is set to true if we need to do a signed divide. In this |
// case, we take a clock cycle to turn the divide into an unsigned |
// divide. |
// |
// o_quotient, a place to store our result, is initialized to all zeros. |
// |
// r_dividend is set to the numerator |
// |
// r_divisor is set to 2^31 * the denominator (shift left by 31, or add |
// 31 zeros to the right of the number. |
// |
// pre_sign When true (clock cycle after i_wr), a clock cycle is used |
// to take the absolute value of the various arguments (r_dividend |
// and r_divisor), and to calculate what sign the output result |
// should be. |
// |
// |
// At this point, the divide is has started. The divide works by walking |
// through every shift of the |
// |
// DIVIDEND over the |
// DIVISOR |
// |
// If the DIVISOR is bigger than the dividend, the divisor is shifted |
// right, and nothing is done to the output quotient. |
// |
// DIVIDEND |
// DIVISOR |
// |
// This repeats, until DIVISOR is less than or equal to the divident, as in |
// |
// DIVIDEND |
// DIVISOR |
// |
// At this point, if the DIVISOR is less than the dividend, the |
// divisor is subtracted from the dividend, and the DIVISOR is again |
// shifted to the right. Further, a '1' bit gets set in the output |
// quotient. |
// |
// Once we've done this for 32 clocks, we've accumulated our answer into |
// the output quotient, and we can proceed to the next step. If the |
// result will be signed, the next step negates the quotient, otherwise |
// it returns the result. |
// |
// On the clock when we are done, o_busy is set to false, and o_valid set |
// to true. (It is a violation of the ZipCPU internal protocol for both |
// busy and valid to ever be true on the same clock. It is also a |
// violation for busy to be false with valid true thereafter.) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
24,12 → 83,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// `include "cpudefs.v" |
// |
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator, |
/zipcpu/trunk/rtl/core/idecode.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,14 → 31,20
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define CPU_SP_REG 4'hd |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
56,7 → 62,8
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, o_ljmp, |
o_pipe |
o_pipe, |
o_sim, o_sim_immv |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH; |
67,7 → 74,7
input i_pf_valid, i_illegal; |
output wire o_phase; |
output reg o_illegal; |
output reg [(AW-1):0] o_pc; |
output reg [AW:0] o_pc; |
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
82,6 → 89,8
output wire [(AW-1):0] o_branch_pc; |
output wire o_ljmp; |
output wire o_pipe; |
output reg o_sim /* verilator public_flat */; |
output reg [22:0] o_sim_immv /* verilator public_flat */; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
102,18 → 111,18
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wF, w_mem, w_sto, w_lod, w_div, w_fpu; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp, w_ljmp_dly; |
wire w_ljmp, w_ljmp_dly, w_cis_ljmp; |
wire [31:0] iword; |
|
|
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
`ifdef OPT_CIS |
reg [15:0] r_nxt_half; |
assign iword = (o_phase) |
// set second half as a NOOP ... but really |
// set second half as a NOOP ... but really |
// shouldn't matter |
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 } |
? { r_nxt_half[15:0], i_instruction[15:0] } |
: i_instruction; |
`else |
assign iword = { 1'b0, i_instruction[30:0] }; |
121,27 → 130,87
|
generate |
if (EARLY_BRANCHING != 0) |
begin |
`ifdef OPT_CIS |
reg r_pre_ljmp; |
always @(posedge i_clk) |
if ((i_rst)||(o_early_branch)) |
r_pre_ljmp <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_pre_ljmp <= (!o_phase)&&(i_instruction[31]) |
&&(i_instruction[14:0] == 15'h7cf8); |
else if (i_ce) |
r_pre_ljmp <= 1'b0; |
|
assign w_cis_ljmp = r_pre_ljmp; |
`else |
assign w_cis_ljmp = 1'b0; |
`endif |
// 0.1111.10010.000.1.1111.000000000... |
// 0111.1100.1000.0111.11000.... |
assign w_ljmp = (iword == 32'h7c87c000); |
else |
end else begin |
assign w_cis_ljmp = 1'b0; |
assign w_ljmp = 1'b0; |
end |
endgenerate |
|
`ifdef OPT_CIS |
`ifdef VERILATOR |
wire [4:0] w_cis_op; |
always @(iword) |
if (!iword[31]) |
w_cis_op = w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op = 5'h00; |
3'h1: w_cis_op = 5'h01; |
3'h2: w_cis_op = 5'h02; |
3'h3: w_cis_op = 5'h10; |
3'h4: w_cis_op = 5'h12; |
3'h5: w_cis_op = 5'h13; |
3'h6: w_cis_op = 5'h18; |
3'h7: w_cis_op = 5'h0d; |
endcase |
`else |
reg [4:0] w_cis_op; |
always @(iword,w_op) |
if (!iword[31]) |
w_cis_op <= w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op <= 5'h00; |
3'h1: w_cis_op <= 5'h01; |
3'h2: w_cis_op <= 5'h02; |
3'h3: w_cis_op <= 5'h10; |
3'h4: w_cis_op <= 5'h12; |
3'h5: w_cis_op <= 5'h13; |
3'h6: w_cis_op <= 5'h18; |
3'h7: w_cis_op <= 5'h0d; |
endcase |
`endif |
`else |
wire [4:0] w_cis_op; |
assign w_cis_op = w_op; |
`endif |
|
assign w_op= iword[26:22]; |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_ALU = (~w_op[4]); |
assign w_mov = (w_cis_op == 5'h0d); |
assign w_ldi = (w_cis_op[4:1] == 4'hc); |
assign w_brev = (w_cis_op == 5'h8); |
assign w_cmptst = (w_cis_op[4:1] == 4'h8); |
assign w_ldilo = (w_cis_op[4:0] == 5'h9); |
assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ... |
&&(w_cis_op[3:1] != 3'h7); // not the divide |
|
// 4 LUTs |
|
// w_dcdR (4 LUTs) |
// |
// What register will we be placing results into (if at all)? |
// |
// Two parts to the result register: the register set, given for |
// moves in i_word[18] but only for the supervisor, and the other |
// moves in iword[18] but only for the supervisor, and the other |
// four bits encoded in the instruction. |
// |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
assign w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
// 2 LUTs |
// |
148,16 → 217,20
// If the result register is either CC or PC, and this would otherwise |
// be a floating point instruction with floating point opcode of 0, |
// then this is a NOOP. |
assign w_noop = (w_op[4:0] == 5'h18)&&( |
assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7)) |
||(IMPLEMENT_FPU==0)); |
|
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
// dcdB - What register is used in the opB? |
// |
assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie; |
assign w_dcdB[3:0]= (iword[31]) |
? (((!iword[23])&&(iword[26:25]==2'b10)) |
? `CPU_SP_REG : iword[22:19]) |
: iword[17:14]; |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; |
assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
165,8 → 238,8
assign w_dcdA_pc = w_dcdR_pc; |
assign w_dcdA_cc = w_dcdR_cc; |
// 2 LUTs, 1 delays each |
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG); |
assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG); |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
173,46 → 246,55
// is completely unconditional. |
// |
// 3+4 LUTs |
assign w_cond = (w_ldi) ? 4'h8 : |
(iword[31])?{(iword[20:19]==2'b00), |
1'b0,iword[20:19]} |
: { (iword[21:19]==3'h0), iword[21:19] }; |
assign w_cond = ((w_ldi)||(iword[31])) ? 4'h8 : |
{ (iword[21:19]==3'h0), iword[21:19] }; |
|
// 1 LUT |
assign w_dcdM = (w_op[4:1] == 4'h9); |
assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00); |
assign w_sto = (w_mem)&&( w_cis_op[0]); |
assign w_lod = (w_mem)&&(!w_cis_op[0]); |
// 1 LUT |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7); |
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before) |
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV |
assign w_rA = (w_dcdFP) |
// Divide's read A |
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
||(w_op[4:1]== 4'h8); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7); |
// 2 LUTs |
assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11) |
&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00); |
// |
// rA - do we need to read register A? |
assign w_rA = // Floating point reads reg A |
((w_fpu)&&(w_cis_op[4:1] != 4'hf)) |
// Divide's read A |
||(w_div) |
// ALU ops read A, |
// except for MOV's and BREV's which don't |
||((w_ALU)&&(!w_brev)&&(!w_mov)) |
// STO's read A |
||(w_sto) |
// Test/compares |
||(w_cmptst); |
// rB -- do we read a register for operand B? Specifically, do we |
// add the registers value to the immediate to create opB? |
assign w_rB = (w_mov) |
||((!iword[31])&&(iword[18])&&(!w_ldi)) |
||(( iword[31])&&(iword[23])&&(!w_ldi)) |
// If using compressed instruction sets, |
// we *always* read on memory operands. |
||(( iword[31])&&(w_mem)); |
// wR -- will we be writing our result back? |
// wR_n = !wR |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
assign w_wR_n = (w_sto) |
||((!iword[31])&&(w_cis_op[4:3]==2'b11) |
&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR = ~w_wR_n; |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
// and writes to the PC/CC register(s). |
// wF -- do we write flags when we are done? |
// |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev) |
&&(iword[30:28] != 3'h7)))); |
||((w_cond[3])&&((w_fpu)||(w_div) |
||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev) |
&&(w_dcdR[3:1] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
224,16 → 306,23
wire w_Iz; |
|
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move |
// MOVE immediates have one less bit |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } |
// Normal Op-B immediate ... 18 or 14 bits |
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] } |
: { {(23-14){iword[13]}}, iword[13:0] } |
)); |
|
`ifdef OPT_VLIW |
wire [5:0] w_halfI; |
assign w_halfI = (w_ldi) ? iword[5:0] |
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]}); |
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI; |
`ifdef OPT_CIS |
wire [7:0] w_halfbits; |
assign w_halfbits = iword[23:16]; |
|
wire [7:0] w_halfI; |
assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0] |
:(w_halfbits[7])? |
{ {(6){w_halfbits[2]}}, w_halfbits[1:0]} |
:{ w_halfbits[6], w_halfbits[6:0] }; |
assign w_I = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI; |
`else |
assign w_I = w_fullI; |
`endif |
240,12 → 329,12
assign w_Iz = (w_I == 0); |
|
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
// |
// The o_phase parameter is special. It needs to let the software |
// following know that it cannot break/interrupt on an o_phase asserted |
// instruction, lest the break take place between the first and second |
// half of a VLIW instruction. To do this, o_phase must be asserted |
// half of a CIS instruction. To do this, o_phase must be asserted |
// when the first instruction half is valid, but not asserted on either |
// a 32-bit instruction or the second half of a 2x16-bit instruction. |
reg r_phase; |
255,7 → 344,10
||(o_early_branch)||(w_ljmp_dly)) |
r_phase <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_phase <= (o_phase)? 1'b0:(i_instruction[31]); |
r_phase <= (o_phase)? 1'b0 |
: ((i_instruction[31])&&(i_pf_valid)); |
else if (i_ce) |
r_phase <= 1'b0; |
// Phase is '1' on the first instruction of a two-part set |
// But, due to the delay in processing, it's '1' when our output is |
// valid for that first part, but that'll be the same time we |
274,32 → 366,32
o_illegal <= 1'b0; |
else if (i_ce) |
begin |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
o_illegal <= (i_illegal); |
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08))) |
if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c))) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
if ((IMPLEMENT_DIVIDE==0)&&(w_div)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7)) |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
|
|
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7)) |
if ((IMPLEMENT_FPU==0)&&(w_fpu)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP)) |
o_illegal <= 1'b1; |
|
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_op[2:0] != 3'h1) // BREAK |
(w_cis_op[2:0] != 3'h4) // BREAK |
`ifdef OPT_PIPELINED |
&&(w_op[2:0] != 3'h2) // LOCK |
&&(w_cis_op[2:0] != 3'h5) // LOCK |
`endif |
&&(w_op[2:0] != 3'h0))) // NOOP |
// SIM instructions are always illegal |
&&(w_cis_op[2:0] != 3'h7))) // NOOP |
o_illegal <= 1'b1; |
end |
|
307,16 → 399,19
always @(posedge i_clk) |
if (i_ce) |
begin |
`ifdef OPT_VLIW |
if (~o_phase) |
begin |
`ifdef OPT_CIS |
if (!o_phase) |
o_gie<= i_gie; |
// i.e. dcd_pc+1 |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
end |
|
if ((iword[31])&&(!o_phase)) |
o_pc <= { i_pc, 1'b1 }; |
else if ((iword[31])&&(i_pf_valid)) |
o_pc <= { i_pc, 1'b0 }; |
else |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
`else |
o_gie<= i_gie; |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
`endif |
|
// Under what condition will we execute this |
334,12 → 429,12
// the ALU. Likewise, the two compare instructions |
// CMP and TST becomes SUB and AND here as well. |
// We keep only the bottom four bits, since we've |
// already done the rest of the decode necessary to |
// already done the rest of the decode necessary to |
// settle between the other instructions. For example, |
// o_FP plus these four bits uniquely defines the FP |
// instruction, o_DV plus the bottom of these defines |
// the divide, etc. |
o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0]; |
o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0]; |
|
// Default values |
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; |
351,29 → 446,36
r_I <= w_I; |
o_zI <= w_Iz; |
|
// Turn a NOOP into an ALU operation--subtract in |
// Turn a NOOP into an ALU operation--subtract in |
// particular, although it doesn't really matter as long |
// as it doesn't take longer than one clock. Note |
// also that this depends upon not setting any registers |
// or flags, which should already be true. |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT |
o_M <= w_dcdM; |
o_DV <= w_dcdDV; |
o_FP <= w_dcdFP; |
|
o_break <= (w_op[4:0]==5'b11001)&&( |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); |
o_M <= w_mem; |
o_DV <= w_div; |
o_FP <= w_fpu; |
|
o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`ifdef OPT_PIPELINED |
r_lock <= (w_op[4:0]==5'b11010)&&( |
r_lock <= (!iword[31])&&(w_op[4:0]==5'h1d)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`endif |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
iword[4:0] }; |
`ifdef OPT_CIS |
r_nxt_half <= { iword[31], iword[14:0] }; |
`endif |
|
`ifdef VERILATOR |
// Support the SIM instruction(s) |
o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf) |
&&(w_dcdR[3:1] == 3'h7); |
`else |
o_sim <= 1'b0; |
`endif |
o_sim_immv <= iword[22:0]; |
end |
|
`ifdef OPT_PIPELINED |
392,6 → 494,10
always @(posedge i_clk) |
if (i_rst) |
r_ljmp <= 1'b0; |
`ifdef OPT_CIS |
else if ((i_ce)&&(o_phase)) |
r_ljmp <= w_cis_ljmp; |
`endif |
else if ((i_ce)&&(i_pf_valid)) |
r_ljmp <= (w_ljmp); |
assign o_ljmp = r_ljmp; |
404,17 → 510,14
if (r_ljmp) |
// LOD (PC),PC |
r_early_branch <= 1'b1; |
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG) |
&&(w_cond[3])) |
begin |
if (w_op[4:1] == 4'hb) // LDI to PC |
// LDI x,PC |
r_early_branch <= 1'b1; |
else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
if ((w_op[4:0]==5'h02)&&(!iword[18])) |
// Add x,PC |
r_early_branch <= 1'b1; |
else begin |
else |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end else if (i_ce) |
424,12 → 527,10
if (i_ce) |
begin |
if (r_ljmp) |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_op[4:1] == 4'hb) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
r_branch_pc <= iword[(AW+1):2]; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-17){iword[17]}},iword[16:0]} |
+ {{(AW-15){iword[17]}},iword[16:2]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
459,15 → 560,26
initial r_pipe = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_instruction[17:14] != o_dcdA[3:0]) |
r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase)) |
// Both must be memory operations |
&&(w_mem)&&(o_M) |
// Both must be writes, or both stores |
&&(o_op[0] == w_cis_op[0]) |
// Both must be register ops |
&&(w_rB) |
// Both must use the same register for B |
&&(w_dcdB[3:0] == o_dcdB[3:0]) |
// But ... the result can never be B |
&&((o_op[0]) |
||(w_dcdB[3:0] != o_dcdA[3:0])) |
// Needs to be to the mode, supervisor or user |
&&(i_gie == o_gie) |
// Same condition, or no condition before |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
// Same immediate |
&&((w_I[13:2]==r_I[13:2]) |
||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1))); |
assign o_pipe = r_pipe; |
`else |
assign o_pipe = 1'b0; |
482,8 → 594,8
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
|
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |
|
endmodule |
/zipcpu/trunk/rtl/core/memops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memops.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,24 → 31,31
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module memops(i_clk, i_rst, i_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0, WITH_LOCAL_BUS=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
input i_op; |
input [2:0] i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
66,6 → 73,7
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
72,8 → 80,8
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff)); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
104,13 → 112,54
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
|
reg [3:0] r_op; |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_we <= i_op[0]; |
casez({ i_op[2:1], i_addr[1:0] }) |
`ifdef ZERO_ON_IDLE |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
`else |
4'b10??: o_wb_data <= { (2){ i_data[15:0] } }; |
4'b11??: o_wb_data <= { (4){ i_data[7:0] } }; |
`endif |
default: o_wb_data <= i_data; |
endcase |
|
o_wb_addr <= i_addr[(AW+1):2]; |
`ifdef SET_SEL_ON_READ |
if (i_op[0] == 1'b0) |
o_wb_sel <= 4'hf; |
else |
`endif |
casez({ i_op[2:1], i_addr[1:0] }) |
4'b01??: o_wb_sel <= 4'b1111; |
4'b100?: o_wb_sel <= 4'b1100; |
4'b101?: o_wb_sel <= 4'b0011; |
4'b1100: o_wb_sel <= 4'b1000; |
4'b1101: o_wb_sel <= 4'b0100; |
4'b1110: o_wb_sel <= 4'b0010; |
4'b1111: o_wb_sel <= 4'b0001; |
default: o_wb_sel <= 4'b1111; |
endcase |
r_op <= { i_op[2:1] , i_addr[1:0] }; |
end |
`ifdef ZERO_ON_IDLE |
else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl)) |
begin |
o_wb_we <= 1'b0; |
o_wb_addr <= 0; |
o_wb_data <= 32'h0; |
o_wb_sel <= 4'h0; |
end |
`endif |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
124,8 → 173,21
if (i_stb) |
o_wreg <= i_oreg; |
always @(posedge i_clk) |
if (i_wb_ack) |
o_result <= i_wb_data; |
`ifdef ZERO_ON_IDLE |
if (!i_wb_ack) |
o_result <= 32'h0; |
else |
`endif |
casez(r_op) |
4'b01??: o_result <= i_wb_data; |
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] }; |
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; |
default: o_result <= i_wb_data; |
endcase |
|
generate |
if (IMPLEMENT_LOCK != 0) |
/zipcpu/trunk/rtl/core/pfcache.v
13,7 → 13,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
25,6 → 25,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
31,6 → 36,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache, |
// i_early_branch, i_from_addr, |
i_stall_n, i_pc, o_i, o_pc, o_v, |
/zipcpu/trunk/rtl/core/pipefetch.v
30,7 → 30,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
42,6 → 42,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
48,6 → 53,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
/zipcpu/trunk/rtl/core/pipemem.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pipemem.v |
// |
15,9 → 15,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
29,24 → 29,31
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
input i_op; |
input [2:0] i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
64,6 → 71,7
output reg o_wb_stb_lcl, o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
72,25 → 80,27
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
reg [3:0] rdaddr, wraddr; |
wire [3:0] nxt_rdaddr; |
reg [(5-1):0] fifo_oreg [0:15]; |
reg [(4+5-1):0] fifo_oreg [0:15]; |
initial rdaddr = 0; |
initial wraddr = 0; |
|
always @(posedge i_clk) |
fifo_oreg[wraddr] <= i_oreg; |
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] }; |
|
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
wraddr <= 0; |
else if (i_pipe_stb) |
wraddr <= wraddr + 4'h1; |
wraddr <= wraddr + 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
rdaddr <= 0; |
else if ((i_wb_ack)&&(cyc)) |
rdaddr <= rdaddr + 4'h1; |
assign nxt_rdaddr = rdaddr + 4'h1; |
rdaddr <= rdaddr + 1'b1; |
assign nxt_rdaddr = rdaddr + 1'b1; |
|
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign lcl_stb = (i_addr[31:24]==8'hff); |
assign gbl_stb = (~lcl_stb); |
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
135,19 → 145,36
// o_wb_we <= i_op |
end |
always @(posedge i_clk) |
if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall)) |
if ((!cyc)||(!i_wb_stall)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end else if ((~cyc)&&(i_pipe_stb)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW+1):2]; |
if (!i_op[0]) // Always select everything on reads |
o_wb_sel <= 4'b1111; // Op is even |
else casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_sel <= 4'b1100; // Op = 5 |
4'b101?: o_wb_sel <= 4'b0011; // Op = 5 |
4'b1100: o_wb_sel <= 4'b1000; // Op = 5 |
4'b1101: o_wb_sel <= 4'b0100; // Op = 7 |
4'b1110: o_wb_sel <= 4'b0010; // Op = 7 |
4'b1111: o_wb_sel <= 4'b0001; // Op = 7 |
default: o_wb_sel <= 4'b1111; // Op = 7 |
endcase |
|
casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
default: o_wb_data <= i_data; |
endcase |
|
end |
|
|
always @(posedge i_clk) |
if ((i_pipe_stb)&&(~cyc)) |
o_wb_we <= i_op; |
o_wb_we <= i_op[0]; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
157,12 → 184,20
o_err <= (cyc)&&(i_wb_err); |
assign o_busy = cyc; |
|
wire [8:0] w_wreg; |
assign w_wreg = fifo_oreg[rdaddr]; |
always @(posedge i_clk) |
o_wreg <= fifo_oreg[rdaddr]; |
o_wreg <= w_wreg[8:4]; |
always @(posedge i_clk) |
// if (i_wb_ack) isn't necessary, since o_valid won't be true |
// then either. |
o_result <= i_wb_data; |
casez(w_wreg[3:0]) |
4'b1100: o_result = { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result = { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result = { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result = { 24'h00, i_wb_data[ 7: 0] }; |
4'b100?: o_result = { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result = { 16'h00, i_wb_data[15: 0] }; |
default: o_result = i_wb_data[31:0]; |
endcase |
|
assign o_pipe_stalled = (cyc) |
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl))); |
177,7 → 212,7
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
/zipcpu/trunk/rtl/core/prefetch.v
24,7 → 24,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
36,6 → 36,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
42,6 → 47,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Flash requires a minimum of 4 clocks per byte to read, so that would be |
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline |
// mode which this prefetch does not support. In non--pipelined mode, the |
114,7 → 120,7
if ((o_wb_cyc)&&(i_wb_ack)) |
begin |
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err); |
o_illegal <= i_wb_err; |
o_illegal <= (i_wb_err)&&(i_pc == o_wb_addr); |
end else if (i_stalled_n) |
begin |
o_valid <= 1'b0; |
/zipcpu/trunk/rtl/core/zipcpu.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcpu.v |
// |
18,7 → 18,7
// |
// The Zip CPU is fully pipelined with the following pipeline stages: |
// |
// 1. Prefetch, returns the instruction from memory. |
// 1. Prefetch, returns the instruction from memory. |
// |
// 2. Instruction Decode |
// |
72,9 → 72,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
86,28 → 86,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a VLIW |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS |
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error |
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero |
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error |
114,7 → 109,7
`define CPU_TRAP_BIT 9 // User TRAP has taken place |
`define CPU_ILL_BIT 8 // Illegal instruction |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions |
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
130,7 → 125,7
// CPU interface to the wishbone bus |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
139,7 → 134,8
, o_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
parameter [31:0] RESET_ADDRESS=32'h0100000; |
parameter ADDRESS_WIDTH=30, |
LGICACHE=8; |
`ifdef OPT_MULTIPLY |
parameter IMPLEMENT_MPY = `OPT_MULTIPLY; |
162,7 → 158,9
`else |
parameter EARLY_BRANCHING = 0; |
`endif |
parameter WITH_LOCAL_BUS = 1; |
localparam AW=ADDRESS_WIDTH; |
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2]; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
179,6 → 177,7
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
203,22 → 202,22
// that logic. |
// |
(* ram_style = "distributed" *) |
`ifdef OPT_NO_USERMODE |
reg [31:0] regset [0:15]; |
`else |
reg [31:0] regset [0:31]; |
`endif |
|
// Condition codes |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
reg [3:0] flags, iflags; |
wire [14:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep, r_halted; |
wire break_pending; |
wire w_clear_icache; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_u, ill_err_i; |
`else |
wire ill_err_u, ill_err_i; |
`endif |
reg ubreak; |
reg ibus_err_flag, ubus_err_flag; |
reg break_en, step, sleep, r_halted; |
wire break_pending, trap, gie, ubreak; |
wire w_clear_icache, ill_err_u; |
reg ill_err_i; |
reg ibus_err_flag; |
wire ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
wire ifpu_err_flag, ufpu_err_flag; |
wire ihalt_phase, uhalt_phase; |
231,7 → 230,7
// PIPELINE STAGE #1 :: Prefetch |
// Variable declarations |
// |
reg [(AW-1):0] pf_pc; |
reg [(AW+1):0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc; |
240,9 → 239,9
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [(AW-1):0] pf_addr; |
wire [31:0] pf_data; |
wire [31:0] instruction; |
wire [(AW-1):0] instruction_pc; |
wire pf_valid, instruction_gie, pf_illegal; |
wire [31:0] pf_instruction; |
wire [(AW-1):0] pf_instruction_pc; |
wire pf_valid, pf_gie, pf_illegal; |
|
// |
// |
250,29 → 249,33
// Variable declarations |
// |
// |
reg opvalid, opvalid_mem, opvalid_alu; |
reg opvalid_div, opvalid_fpu; |
reg op_valid /* verilator public_flat */, |
op_valid_mem, op_valid_alu; |
reg op_valid_div, op_valid_fpu; |
wire op_stall, dcd_ce, dcd_phase; |
wire [3:0] dcdOp; |
wire [4:0] dcdA, dcdB, dcdR; |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc; |
wire [3:0] dcdF; |
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
wire [3:0] dcd_opn; |
wire [4:0] dcd_A, dcd_B, dcd_R; |
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; |
wire [3:0] dcd_F; |
wire dcd_wR, dcd_rA, dcd_rB, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, |
dcd_wF, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe, dcd_ljmp; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
wire [31:0] dcdI; |
wire dcd_zI; // true if dcdI == 0 |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
reg r_dcd_valid; |
wire dcd_valid; |
wire [AW:0] dcd_pc /* verilator public_flat */; |
wire [31:0] dcd_I; |
wire dcd_zI; // true if dcd_I == 0 |
wire dcd_A_stall, dcd_B_stall, dcd_F_stall; |
|
wire dcd_illegal; |
wire dcd_early_branch; |
wire [(AW-1):0] dcd_branch_pc; |
|
wire dcd_sim; |
wire [22:0] dcd_sim_immv; |
|
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands |
282,33 → 285,33
// |
// Now, let's read our operands |
reg [4:0] alu_reg; |
wire [3:0] opn; |
wire [4:0] opR; |
reg [31:0] r_opA, r_opB; |
wire [3:0] op_opn; |
wire [4:0] op_R; |
reg [31:0] r_op_Av, r_op_Bv; |
reg [(AW-1):0] op_pc; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opF_wr; |
wire op_gie, opR_cc; |
wire [14:0] opFl; |
reg [5:0] r_opF; |
wire [7:0] opF; |
wire [31:0] w_op_Av, w_op_Bv; |
wire [31:0] op_A_nowait, op_B_nowait, op_Av, op_Bv; |
reg op_wR, op_wF; |
wire op_gie, op_Rcc; |
wire [14:0] op_Fl; |
reg [6:0] r_op_F; |
wire [7:0] op_F; |
wire op_ce, op_phase, op_pipe, op_change_data_ce; |
// Some pipeline control wires |
`ifdef OPT_PIPELINED |
reg opA_alu, opA_mem; |
reg opB_alu, opB_mem; |
reg op_A_alu, op_A_mem; |
reg op_B_alu, op_B_mem; |
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`else |
wire op_illegal; |
assign op_illegal = 1'b0; |
`endif |
wire op_break; |
wire op_lock; |
|
`ifdef VERILATOR |
reg op_sim /* verilator public_flat */; |
reg [22:0] op_sim_immv /* verilator public_flat */; |
`endif |
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
319,20 → 322,18
reg r_alu_pc_valid, mem_pc_valid; |
wire alu_pc_valid; |
wire alu_phase; |
wire alu_ce, alu_stall; |
wire alu_ce /* verilator public_flat */, alu_stall; |
wire [31:0] alu_result; |
wire [3:0] alu_flags; |
wire alu_valid, alu_busy; |
wire set_cond; |
reg alu_wr, alF_wr; |
reg alu_wR, alu_wF; |
wire alu_gie, alu_illegal; |
|
|
|
wire mem_ce, mem_stalled; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
wire mem_pipe_stalled; |
`endif |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
340,12 → 341,13
wire mem_busy, mem_rdbusy; |
wire [(AW-1):0] mem_addr; |
wire [31:0] mem_data, mem_result; |
wire [3:0] mem_sel; |
|
wire div_ce, div_error, div_busy, div_valid; |
wire [31:0] div_result; |
wire [3:0] div_flags; |
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div) |
assign div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
353,7 → 355,7
wire [31:0] fpu_result; |
wire [3:0] fpu_flags; |
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu) |
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
369,7 → 371,8
wire [4:0] wr_reg_id; |
wire [31:0] wr_gpreg_vl, wr_spreg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW-1):0] upc, ipc; |
reg [(AW+1):0] ipc; |
wire [(AW+1):0] upc; |
|
|
|
376,7 → 379,7
// |
// MASTER: clock enable. |
// |
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep); |
assign master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep); |
|
|
// |
389,13 → 392,13
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline); |
|
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
assign dcd_stalled = (dcd_valid)&&(op_stall); |
`else |
// If not pipelined, there will be no opvalid_ anything, and the |
// op_stall will be false, dcdX_stall will be false, thus we can simply |
// If not pipelined, there will be no op_valid_ anything, and the |
// op_stall will be false, dcd_X_stall will be false, thus we can simply |
// do a ... |
assign dcd_stalled = 1'b0; |
`endif |
402,17 → 405,17
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
wire op_lock_stall; |
wire prelock_stall; |
`ifdef OPT_PIPELINED |
reg cc_invalid_for_dcd; |
always @(posedge i_clk) |
cc_invalid_for_dcd <= (wr_flags_ce) |
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG) |
||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG))) |
||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG))) |
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(mem_busy)||(div_busy)||(fpu_busy); |
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins |
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins |
// Stall if we're stopped, and not allowed to execute |
// an instruction |
// (~master_ce) // Already captured in alu_stall |
425,27 → 428,29
// This also includes whether or not the divide or |
// floating point units are busy. |
(alu_stall) |
||(((op_valid_div)||(op_valid_fpu)) |
&&(!adf_ce_unconditional)) |
// |
// Stall if we are going into memory with an operation |
// that cannot be pipelined, and the memory is |
// already busy |
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled |
||(opR_cc) |
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled |
||(op_Rcc) |
) |
||(dcdvalid)&&( |
||(dcd_valid)&&( |
// Stall if we need to wait for an operand A |
// to be ready to read |
(dcdA_stall) |
(dcd_A_stall) |
// Likewise for B, also includes logic |
// regarding immediate offset (register must |
// be in register file if we need to add to |
// an immediate) |
||(dcdB_stall) |
||(dcd_B_stall) |
// Or if we need to wait on flags to work on the |
// CC register |
||(dcdF_stall) |
||(dcd_F_stall) |
); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); |
|
|
// BUT ... op_ce is too complex for many of the data operations. So |
452,11 → 457,11
// let's make their circuit enable code simpler. In particular, if |
// op_ doesn't need to be preserved, we can change it all we want |
// ... right? The clear_pipeline code, for example, really only needs |
// to determine whether opvalid is true. |
// to determine whether op_valid is true. |
assign op_change_data_ce = (~op_stall); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline); |
assign op_stall = (op_valid)&&(~master_ce); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline); |
assign op_change_data_ce = 1'b1; |
`endif |
|
465,7 → 470,7
// Calculate stall conditions |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Stall if someone on the other end is writing the CC register, |
474,16 → 479,16
// through the ALU. Break instructions are not allowed through |
// the ALU. |
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) // || op_illegal |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2 |
||(prelock_stall) |
||((op_valid)&&(op_break)) |
||(wr_reg_ce)&&(wr_write_cc) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall) |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall) |
&&(~clear_pipeline); |
`else |
assign alu_stall = (opvalid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline); |
assign alu_stall = (op_valid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline); |
`endif |
// |
|
492,7 → 497,7
// alu_pc_valid. |
// |
`ifdef OPT_PIPELINED |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`else |
// If we aren't pipelined, then no one will be changing what's in the |
503,12 → 508,13
// something gets in the pipeline and then (due to interrupt or some |
// such) needs to be voided? Thus we avoid simplification and keep |
// what worked here. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
assign mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&( |
(mem_pipe_stalled) |
||(prelock_stall) |
||((~op_pipe)&&(mem_busy)) |
||(div_busy) |
||(fpu_busy) |
520,7 → 526,7
&&((wr_write_pc)||(wr_write_cc))))); |
`else |
`ifdef OPT_PIPELINED |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
assign mem_stalled = (mem_busy)||((op_valid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
528,14 → 534,14
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
`else |
assign mem_stalled = (opvalid_mem)&&(~master_ce); |
assign mem_stalled = (op_valid_mem)&&(~master_ce); |
`endif |
`endif |
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid) |
&&(~opvalid_mem)&&(~mem_rdbusy) |
&&((~opvalid_alu)||(~alu_stall))&&(~op_break) |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid) |
&&(~op_valid_mem)&&(~mem_rdbusy) |
&&((~op_valid_alu)||(~alu_stall))&&(~op_break) |
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline); |
|
// |
546,110 → 552,94
`ifdef OPT_SINGLE_FETCH |
wire pf_ce; |
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
assign pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie, |
pf_instruction, pf_instruction_pc, pf_gie, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
|
initial r_dcdvalid = 1'b0; |
initial r_dcd_valid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
if (clear_pipeline) |
r_dcd_valid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)||(pf_illegal); |
r_dcd_valid <= (pf_valid)||(pf_illegal); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
|
`else // Pipe fetch |
|
wire pf_stalled; |
assign pf_stalled = (dcd_stalled)||(dcd_phase); |
`ifdef OPT_TRADITIONAL_PFCACHE |
wire [(AW-1):0] pf_request_address; |
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline)) |
? dcd_branch_pc:pf_pc[(AW+1):2]; |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
w_clear_icache, |
// dcd_pc, |
~dcd_stalled, |
((dcd_early_branch)&&(~clear_pipeline)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
`else |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch), |
w_clear_icache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
w_clear_icache, (!pf_stalled), |
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
//`ifdef OPT_PRECLEAR_BUS |
//((dcd_clear_bus)&&(dcdvalid)) |
//||((op_clear_bus)&&(opvalid)) |
//|| |
//`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
assign instruction_gie = gie; |
`ifdef OPT_NO_USERMODE |
assign pf_gie = 1'b0; |
`else |
assign pf_gie = gie; |
`endif |
|
initial r_dcdvalid = 1'b0; |
initial r_dcd_valid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)||(w_clear_icache)) |
r_dcdvalid <= 1'b0; |
if ((clear_pipeline)||(w_clear_icache)) |
r_dcd_valid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch); |
r_dcd_valid <= ((dcd_phase)||(pf_valid)) |
&&(~dcd_ljmp)&&(~dcd_early_branch); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
`endif |
|
`ifdef OPT_NEW_INSTRUCTION_SET |
|
// If not pipelined, there will be no opvalid_ anything, and the |
// If not pipelined, there will be no op_valid_ anything, and the |
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
(~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
instruction_decoder(i_clk, (clear_pipeline), |
(~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie, |
pf_instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcd_Rcc, dcd_Rpc, dcd_R }, |
{ dcd_Acc, dcd_Apc, dcd_A }, |
{ dcd_Bcc, dcd_Bpc, dcd_B }, |
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock, |
dcd_wR,dcd_rA, dcd_rB, |
dcd_early_branch, |
dcd_branch_pc, dcd_ljmp, |
dcd_pipe); |
`else |
idecode_deprecated |
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
assign dcd_ljmp = 1'b0; |
`endif |
dcd_pipe, |
dcd_sim, dcd_sim_immv); |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg r_op_pipe; |
|
initial r_op_pipe = 1'b0; |
// To be a pipeable operation, there must be |
// To be a pipeable operation, there must be |
// two valid adjacent instructions |
// Both must be memory instructions |
// Both must be writes, or both must be reads |
659,7 → 649,9
// However ... we need to know this before this clock, hence this is |
// calculated in the instruction decoder. |
always @(posedge i_clk) |
if (op_ce) |
if (clear_pipeline) |
r_op_pipe <= 1'b0; |
else if (op_ce) |
r_op_pipe <= dcd_pipe; |
else if (mem_ce) // Clear us any time an op_ is clocked in |
r_op_pipe <= 1'b0; |
673,31 → 665,20
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
`ifdef OPT_NO_USERMODE |
assign w_op_Av = regset[dcd_A[3:0]]; |
assign w_op_Bv = regset[dcd_B[3:0]]; |
`else |
assign w_op_Av = regset[dcd_A]; |
assign w_op_Bv = regset[dcd_B]; |
`endif |
|
wire [8:0] w_cpu_info; |
assign w_cpu_info = { |
`ifdef OPT_ILLEGAL_INSTRUCTION |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_MULTIPLY |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_DIVIDE |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
1'b1, |
`else |
1'b0, |
`endif |
(IMPLEMENT_MPY >0)? 1'b1:1'b0, |
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0, |
(IMPLEMENT_FPU >0)? 1'b1:1'b0, |
`ifdef OPT_PIPELINED |
1'b1, |
`else |
718,7 → 699,7
`else |
1'b0, |
`endif |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
1'b1 |
`else |
1'b0 |
726,79 → 707,85
}; |
|
wire [31:0] w_pcA_v; |
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcA_v[31:(AW+2)] = 0; |
endgenerate |
|
`ifdef OPT_PIPELINED |
reg [4:0] opA_id, opB_id; |
reg opA_rd, opB_rd; |
reg [4:0] op_Aid, op_Bid; |
reg op_rA, op_rB; |
always @(posedge i_clk) |
if (op_ce) |
begin |
opA_id <= dcdA; |
opB_id <= dcdB; |
opA_rd <= dcdA_rd; |
opB_rd <= dcdB_rd; |
op_Aid <= dcd_A; |
op_Bid <= dcd_B; |
op_rA <= dcd_rA; |
op_rB <= dcd_rB; |
end |
`endif |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_change_data_ce) |
if (op_ce) |
`endif |
begin |
`ifdef OPT_PIPELINED |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == dcd_A)) |
r_op_Av <= wr_gpreg_vl; |
else |
`endif |
if (dcdA_pc) |
r_opA <= w_pcA_v; |
else if (dcdA_cc) |
r_opA <= { w_cpu_info, w_opA[22:16], 1'b0, (dcdA[4])?w_uflags:w_iflags }; |
if (dcd_Apc) |
r_op_Av <= w_pcA_v; |
else if (dcd_Acc) |
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags }; |
else |
r_opA <= w_opA; |
r_op_Av <= w_op_Av; |
`ifdef OPT_PIPELINED |
end else |
begin // We were going to pick these up when they became valid, |
// but for some reason we're stuck here as they became |
// valid. Pick them up now anyway |
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid))) |
// r_opA <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd)) |
r_opA <= wr_gpreg_vl; |
// if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid))) |
// r_op_Av <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA)) |
r_op_Av <= wr_gpreg_vl; |
`endif |
end |
|
wire [31:0] w_opBnI, w_pcB_v; |
wire [31:0] w_op_BnI, w_pcB_v; |
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcB_v[31:(AW+2)] = 0; |
endgenerate |
|
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
assign w_op_BnI = (!dcd_rB) ? 32'h00 |
`ifdef OPT_PIPELINED |
: ((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl |
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl |
`endif |
: ((dcdB_pc) ? w_pcB_v |
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:16], // w_opB[31:14], |
1'b0, (dcdB[4])?w_uflags:w_iflags} |
: w_opB)); |
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14], |
1'b0, (dcd_B[4])?w_uflags:w_iflags} |
: w_op_Bv); |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_change_data_ce) |
r_opB <= w_opBnI + dcdI; |
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd)) |
r_opB <= wr_gpreg_vl; |
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else if (op_ce) |
r_op_Bv <= w_op_BnI + dcd_I; |
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB)) |
r_op_Bv <= wr_gpreg_vl; |
`else |
r_opB <= w_opBnI + dcdI; |
if ((dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else |
r_op_Bv <= w_op_BnI + dcd_I; |
`endif |
|
// The logic here has become more complex than it should be, no thanks |
809,54 → 796,42
// conditions checking those bits. Therefore, Vivado complains that |
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// opF. |
// op_F. |
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_ce) // Cannot do op_change_data_ce here since opF depends |
if (op_ce) // Cannot do op_change_data_ce here since op_F depends |
// upon being either correct for a valid op, or correct |
// for the last valid op |
`endif |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcdF[2:0]) |
3'h0: r_opF <= 6'h00; // Always |
`ifdef OPT_NEW_INSTRUCTION_SET |
// These were remapped as part of the new instruction |
// set in order to make certain that the low order |
// two bits contained the most commonly used |
// conditions: Always, LT, Z, and NZ. |
3'h1: r_opF <= 6'h24; // LT |
3'h2: r_opF <= 6'h11; // Z |
3'h3: r_opF <= 6'h10; // NE |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h20; // GE (!N) |
`else |
3'h1: r_opF <= 6'h11; // Z |
3'h2: r_opF <= 6'h10; // NE |
3'h3: r_opF <= 6'h20; // GE (!N) |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h24; // LT |
`endif |
3'h6: r_opF <= 6'h02; // C |
3'h7: r_opF <= 6'h08; // V |
case(dcd_F[2:0]) |
3'h0: r_op_F <= 7'h00; // Always |
3'h1: r_op_F <= 7'h11; // Z |
3'h2: r_op_F <= 7'h44; // LT |
3'h3: r_op_F <= 7'h22; // C |
3'h4: r_op_F <= 7'h08; // V |
3'h5: r_op_F <= 7'h10; // NE |
3'h6: r_op_F <= 7'h40; // GE (!N) |
3'h7: r_op_F <= 7'h20; // NC |
endcase |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
assign op_F = { r_op_F[3], r_op_F[6:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
initial opvalid_div = 1'b0; |
initial opvalid_fpu = 1'b0; |
wire w_op_valid; |
assign w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch); |
initial op_valid = 1'b0; |
initial op_valid_alu = 1'b0; |
initial op_valid_mem = 1'b0; |
initial op_valid_div = 1'b0; |
initial op_valid_fpu = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
867,25 → 842,19
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid); |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal)); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch); |
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal) |
||(dcd_early_branch)); |
op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid); |
end else if ((adf_ce_unconditional)||(mem_ce)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
896,16 → 865,17
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001); |
`ifdef OPT_PIPELINED |
reg r_op_break; |
|
initial r_op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) r_op_break <= 1'b0; |
else if (op_ce) r_op_break <= (dcd_break); //||dcd_illegal &&(dcdvalid) |
else if ((clear_pipeline)||(~opvalid)) |
r_op_break <= 1'b0; |
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0; |
else if (op_ce) |
r_op_break <= (dcd_break); |
else if (!op_valid) |
r_op_break <= 1'b0; |
assign op_break = r_op_break; |
`else |
assign op_break = dcd_break; |
915,33 → 885,21
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_op_lock, r_op_lock_stall; |
reg r_op_lock; |
|
initial r_op_lock_stall = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock_stall <= 1'b0; |
else |
r_op_lock_stall <= (~opvalid)||(~op_lock) |
||(~dcdvalid)||(~pf_valid); |
|
assign op_lock_stall = r_op_lock_stall; |
|
initial r_op_lock = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_op_lock <= 1'b0; |
else if (op_ce) |
r_op_lock <= (dcd_lock)&&(~clear_pipeline); |
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline); |
assign op_lock = r_op_lock; |
|
end else begin |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
end endgenerate |
|
`else |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
`endif |
|
948,13 → 906,13
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial op_illegal = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
op_illegal <= 1'b0; |
else if(op_ce) |
`ifdef OPT_PIPELINED |
op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
`else |
op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock)); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock)); |
`endif |
else if(alu_ce) |
op_illegal <= 1'b0; |
967,61 → 925,87
always @(posedge i_clk) |
if (op_ce) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`else |
always @(posedge i_clk) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`endif |
|
`ifdef VERILATOR |
`ifdef OPT_PIPELINED |
reg [3:0] r_opn; |
reg [4:0] r_opR; |
reg r_opR_cc; |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
op_sim <= dcd_sim; |
op_sim_immv <= dcd_sim_immv; |
end |
`else |
always @(*) |
begin |
op_sim = dcd_sim; |
op_sim_immv = dcd_sim_immv; |
end |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [3:0] r_op_opn; |
reg [4:0] r_op_R; |
reg r_op_Rcc; |
reg r_op_gie; |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
r_opn <= dcdOp; // Which ALU operation? |
// opM <= dcdM; // Is this a memory operation? |
// Which ALU operation? Early branches are |
// unimplemented moves |
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn; |
// opM <= dcd_M; // Is this a memory operation? |
// What register will these results be written into? |
r_opR <= dcdR; |
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie); |
r_op_R <= dcd_R; |
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); |
// User level (1), vs supervisor (0)/interrupts disabled |
r_op_gie <= dcd_gie; |
|
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
end |
assign opn = r_opn; |
assign opR = r_opR; |
assign op_opn = r_op_opn; |
assign op_R = r_op_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = r_op_gie; |
assign opR_cc = r_opR_cc; |
`endif |
assign op_Rcc = r_op_Rcc; |
`else |
assign opn = dcdOp; |
assign opR = dcdR; |
assign op_opn = dcd_opn; |
assign op_R = dcd_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = dcd_gie; |
`endif |
// With no pipelining, there is no early branching. We keep it |
always @(posedge i_clk) |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
`endif |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
assign op_Fl = (op_gie)?(w_uflags):(w_iflags); |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_op_phase; |
initial r_op_phase = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_op_phase <= 1'b0; |
else if (op_change_data_ce) |
r_op_phase <= dcd_phase; |
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc)); |
assign op_phase = r_op_phase; |
`else |
assign op_phase = 1'b0; |
1040,10 → 1024,10
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`ifdef OPT_PIPELINED |
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd)) |
? wr_gpreg_vl : r_opA; |
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA)) |
? wr_gpreg_vl : r_op_Av; |
`else |
assign opA = r_opA; |
assign op_Av = r_op_Av; |
`endif |
|
`ifdef OPT_PIPELINED |
1053,21 → 1037,21
// The operation might set flags, and we wish to read the |
// CC register |
// OR ... (No other conditions) |
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere |
&&((opvalid)||(mem_rdbusy) |
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc)) |
||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd)); |
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc)) |
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd)); |
`else |
// There are no pipeline hazards, if we aren't pipelined |
assign dcdA_stall = 1'b0; |
assign dcd_A_stall = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd)) |
? wr_gpreg_vl: r_opB; |
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB)) |
? wr_gpreg_vl: r_op_Bv; |
`else |
assign opB = r_opB; |
assign op_Bv = r_op_Bv; |
`endif |
|
`ifdef OPT_PIPELINED |
1078,12 → 1062,12
// CC register |
// OR the operation might set register B, and we still need |
// a clock to add the offset to it |
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere |
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere |
// If the op stage isn't valid, yet something |
// is running, then it must have been valid. |
// We'll use the last values from that stage |
// (opR_wr, opF_wr, opR) in our logic below. |
&&((opvalid)||(mem_rdbusy) |
// (op_wR, op_wF, op_R) in our logic below. |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)||(alu_busy)) |
&&( |
// Okay, what happens if the result register |
1090,13 → 1074,13
// from instruction 1 becomes the input for |
// instruction two, *and* there's an immediate |
// offset in instruction two? In that case, we |
// need an extra clock between the two |
// instructions to calculate the base plus |
// need an extra clock between the two |
// instructions to calculate the base plus |
// offset. |
// |
// What if instruction 1 (or before) is in a |
// memory pipeline? We may no longer know what |
// the register was! We will then need to |
// the register was! We will then need to |
// blindly wait. We'll temper this only waiting |
// if we're not piping this new instruction. |
// If we were piping, the pipe logic in the |
1104,28 → 1088,28
// is clear, so we're okay then. |
// |
((~dcd_zI)&&( |
((opR == dcdB)&&(opR_wr)) |
((op_R == dcd_B)&&(op_wR)) |
||((mem_rdbusy)&&(~dcd_pipe)) |
)) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for opB. |
||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc)) |
// flags (CC) register for op_B. |
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc)) |
// Stall on any ongoing memory operation that |
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
// will write to op_B -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI)) |
) |
||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd)); |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd)); |
assign dcd_F_stall = ((~dcd_F[3]) |
||((dcd_rA)&&(dcd_Acc)) |
||((dcd_rB)&&(dcd_Bcc))) |
&&(op_valid)&&(op_Rcc); |
// &&(dcd_valid) is checked for elsewhere |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcdB_stall = 1'b0; |
assign dcdF_stall = 1'b0; |
assign dcd_B_stall = 1'b0; |
assign dcd_F_stall = 1'b0; |
`endif |
// |
// |
1132,15 → 1116,15
// PIPELINE STAGE #4 :: Apply Instruction |
// |
// |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (i_rst)||(clear_pipeline), |
alu_ce, opn, opA, opB, |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline), |
alu_ce, op_opn, op_Av, op_Bv, |
alu_result, alu_flags, alu_valid, alu_busy); |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0], |
opA, opB, div_busy, div_valid, div_error, div_result, |
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0], |
op_Av, op_Bv, div_busy, div_valid, div_error, div_result, |
div_flags); |
end else begin |
assign div_error = 1'b0; // Can't be high unless div_valid |
1155,7 → 1139,7
begin |
// |
// sfpu thefpu(i_clk, i_rst, fpu_ce, |
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// fpu_flags); |
// |
assign fpu_error = 1'b0; // Must only be true if fpu_valid |
1172,27 → 1156,27
end endgenerate |
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
initial alF_wr = 1'b0; |
initial alu_wr = 1'b0; |
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]); |
initial alu_wF = 1'b0; |
initial alu_wR = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
alu_wR <= 1'b0; |
alu_wF <= 1'b0; |
end else if (alu_ce) |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
// alu_reg <= op_R; |
alu_wR <= (op_wR)&&(set_cond); |
alu_wF <= (op_wF)&&(set_cond); |
end else if (~alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
alu_wR <= (i_halt)&&(i_dbg_we); |
alu_wF <= 1'b0; |
end |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_alu_phase; |
initial r_alu_phase = 1'b0; |
always @(posedge i_clk) |
1208,7 → 1192,7
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (adf_ce_unconditional) |
alu_reg <= opR; |
alu_reg <= op_R; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
`else |
1216,7 → 1200,7
if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
else |
alu_reg <= opR; |
alu_reg <= op_R; |
`endif |
|
// |
1229,6 → 1213,9
reg [31:0] dbg_val; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
`ifdef OPT_NO_USERMODE |
assign alu_gie = 1'b0; |
`else |
`ifdef OPT_PIPELINED |
reg r_alu_gie; |
|
1236,24 → 1223,27
if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_gie <= op_gie; |
assign alu_gie = r_alu_gie; |
`else |
assign alu_gie = op_gie; |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [(AW-1):0] r_alu_pc; |
always @(posedge i_clk) |
if ((adf_ce_unconditional) |
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
||((master_ce)&&(op_valid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
r_alu_pc <= op_pc; |
assign alu_pc = r_alu_pc; |
`else |
assign alu_gie = op_gie; |
assign alu_pc = op_pc; |
`endif |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_alu_illegal <= 1'b0; |
else if (alu_ce) |
r_alu_illegal <= op_illegal; |
1260,16 → 1250,13
else |
r_alu_illegal <= 1'b0; |
assign alu_illegal = (r_alu_illegal); |
`else |
assign alu_illegal = 1'b0; |
`endif |
|
initial r_alu_pc_valid = 1'b0; |
initial mem_pc_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_alu_pc_valid <= 1'b0; |
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline) |
else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline) |
r_alu_pc_valid <= 1'b1; |
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |
1285,17 → 1272,43
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_prelock_stall; |
|
initial r_prelock_stall = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_stall <= 1'b0; |
else if ((op_valid)&&(op_lock)&&(op_ce)) |
r_prelock_stall <= 1'b1; |
else if ((op_valid)&&(dcd_valid)&&(pf_valid)) |
r_prelock_stall <= 1'b0; |
|
assign prelock_stall = r_prelock_stall; |
|
reg r_prelock_primed; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_primed <= 1'b0; |
else if (r_prelock_stall) |
r_prelock_primed <= 1'b1; |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_prelock_primed <= 1'b0; |
|
reg [1:0] r_bus_lock; |
initial r_bus_lock = 2'b00; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_bus_lock <= 2'b00; |
else if ((op_ce)&&(op_lock)) |
r_bus_lock <= 2'b11; |
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce))) |
r_bus_lock <= r_bus_lock + 2'b11; |
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce))) |
begin |
if (r_prelock_primed) |
r_bus_lock <= 2'b10; |
else if (r_bus_lock != 2'h0) |
r_bus_lock <= r_bus_lock + 2'b11; |
end |
assign bus_lock = |r_bus_lock; |
end else begin |
assign prelock_stall = 1'b0; |
assign bus_lock = 1'b0; |
end endgenerate |
`else |
1304,38 → 1317,49
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, mem_pipe_stalled, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
|
|
`else // PIPELINED_BUS_ACCESS |
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_pipe_stalled = 1'b0; |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbdblpriarb #(32,AW) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
// |
// At a first glance, we might want something like: |
// |
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf, |
// |
// However, we know that the prefetch will not generate any |
// writes. Therefore, the write specific lines (mem_data and |
// mem_sel) can be shared with the memory in order to ease |
// timing and LUT usage. |
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
|
1362,25 → 1386,25
// When shall we write back? On one of two conditions |
// Note that the flags needed to be checked before issuing the |
// bus instruction, so they don't need to be checked here. |
// Further, alu_wr includes (set_cond), so we don't need to |
// Further, alu_wR includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wr)&&(alu_valid)) |
&&(((alu_wR)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`else |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`endif |
// Which register shall be written? |
// COULD SIMPLIFY THIS: by adding three bits to these registers, |
// One or PC, one for CC, and one for GIE match |
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`ifdef OPT_NO_USERMODE |
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid) |
? alu_reg[3:0]:mem_wreg[3:0]; |
assign wr_reg_id[4] = 1'b0; |
`else |
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`endif |
|
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}); |
1397,13 → 1421,17
:((dbgv) ? dbg_val : alu_result)); |
always @(posedge i_clk) |
if (wr_reg_ce) |
regset[wr_reg_id] <= wr_gpreg_vl; |
`ifdef OPT_NO_USERMODE |
regset[wr_reg_id[3:0]] <= wr_gpreg_vl; |
`else |
regset[wr_reg_id] <= wr_gpreg_vl; |
`endif |
|
// |
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alF_wr already |
// When shall we write to our flags register? alu_wF already |
// includes the set condition ... |
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag, |
udiv_err_flag, ubus_err_flag, trap, ill_err_u, |
ubreak, step, 1'b1, sleep, |
1437,7 → 1465,7
// |
// The goal, upon encountering a break is that the CPU should stop and |
// not execute the break instruction, choosing instead to enter into |
// either interrupt mode or halt first. |
// either interrupt mode or halt first. |
// if ((break_en) AND (break_instruction)) // user mode or not |
// HALT CPU |
// else if (break_instruction) // only in user mode |
1458,7 → 1486,7
|
initial r_break_pending = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)||(~opvalid)) |
if ((clear_pipeline)||(~op_valid)) |
r_break_pending <= 1'b0; |
else if (op_break) |
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce); |
1481,9 → 1509,31
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
initial sleep = 1'b0; |
`ifdef OPT_NO_USERMODE |
reg r_sleep_is_halt; |
initial r_sleep_is_halt = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_sleep_is_halt <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&(~wr_spreg_vl[`CPU_GIE_BIT])) |
r_sleep_is_halt <= 1'b1; |
|
// Trying to switch to user mode, either via a WAIT or an RTU |
// instruction will cause the CPU to sleep until an interrupt, in |
// the NO-USERMODE build. |
always @(posedge i_clk) |
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt))) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_GIE_BIT])) |
sleep <= 1'b1; |
`else |
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
1503,6 → 1553,7
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT]; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
1511,6 → 1562,10
step <= wr_spreg_vl[`CPU_STEP_BIT]; |
|
// The GIE register. Only interrupts can disable the interrupt register |
`ifdef OPT_NO_USERMODE |
assign w_switch_to_interrupt = 1'b0; |
assign w_release_from_interrupt = 1'b0; |
`else |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
1519,10 → 1574,8
// If we encounter a break instruction, if the break |
// enable isn't set. |
||((master_ce)&&(break_pending)&&(~break_en)) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
// On an illegal instruction |
||((alu_illegal)&&(!clear_pipeline)) |
`endif |
// On division by zero. If the divide isn't |
// implemented, div_valid and div_error will be short |
// circuited and that logic will be bypassed |
1531,7 → 1584,7
// fpu_error must *never* be set unless fpu_valid is |
// also set as well, else this will fail. |
||(fpu_error) |
// |
// |
||(bus_err) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
1542,34 → 1595,56
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_scc)) |
); |
`endif |
|
`ifdef OPT_NO_USERMODE |
assign gie = 1'b0; |
`else |
reg r_gie; |
|
initial r_gie = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_switch_to_interrupt) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_release_from_interrupt) |
gie <= 1'b1; |
r_gie <= 1'b1; |
assign gie = r_gie; |
`endif |
|
initial trap = 1'b0; |
`ifdef OPT_NO_USERMODE |
assign trap = 1'b0; |
assign ubreak = 1'b0; |
`else |
reg r_trap; |
|
initial r_trap = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
trap <= 1'b0; |
r_trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied |
trap <= 1'b1; |
r_trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie)) |
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
|
initial ubreak = 1'b0; |
reg r_ubreak; |
|
initial r_ubreak = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
ubreak <= 1'b0; |
r_ubreak <= 1'b0; |
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt)) |
ubreak <= 1'b1; |
r_ubreak <= 1'b1; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
|
assign trap = r_trap; |
assign ubreak = r_ubreak; |
`endif |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial ill_err_i = 1'b0; |
always @(posedge i_clk) |
1580,18 → 1655,27
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]); |
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline)) |
ill_err_i <= 1'b1; |
initial ill_err_u = 1'b0; |
|
`ifdef OPT_NO_USERMODE |
assign ill_err_u = 1'b0; |
`else |
reg r_ill_err_u; |
|
initial r_ill_err_u = 1'b0; |
always @(posedge i_clk) |
// The bit is automatically cleared on release from interrupt |
// or reset |
if ((i_rst)||(w_release_from_interrupt)) |
ill_err_u <= 1'b0; |
r_ill_err_u <= 1'b0; |
// If the supervisor (or debugger) writes to this register, |
// clearing the bit, then clear it |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline)) |
ill_err_u <= 1'b1; |
r_ill_err_u <= 1'b1; |
|
assign ill_err_u = r_ill_err_u; |
`endif |
`else |
assign ill_err_u = 1'b0; |
assign ill_err_i = 1'b0; |
1607,16 → 1691,24
else if ((bus_err)&&(~alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
initial ubus_err_flag = 1'b0; |
// supervisor mode. |
`ifdef OPT_NO_USERMODE |
assign ubus_err_flag = 1'b0; |
`else |
reg r_ubus_err_flag; |
|
initial r_ubus_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
ubus_err_flag <= 1'b0; |
r_ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(alu_gie)) |
ubus_err_flag <= 1'b1; |
r_ubus_err_flag <= 1'b1; |
|
assign ubus_err_flag = r_ubus_err_flag; |
`endif |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
1633,8 → 1725,13
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(~alu_gie)) |
r_idiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
`ifdef OPT_NO_USERMODE |
assign udiv_err_flag = 1'b0; |
`else |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
1645,8 → 1742,8
else if ((div_error)&&(alu_gie)) |
r_udiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
assign udiv_err_flag = r_udiv_err_flag; |
`endif |
end else begin |
assign idiv_err_flag = 1'b0; |
assign udiv_err_flag = 1'b0; |
1667,7 → 1764,7
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie)) |
r_ifpu_err_flag <= 1'b1; |
// User floating point error flag -- if ever set, it will cause |
// a sudden switch interrupt to supervisor mode. |
// a sudden switch interrupt to supervisor mode. |
initial r_ufpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)&&(w_release_from_interrupt)) |
1685,16 → 1782,24
assign ufpu_err_flag = 1'b0; |
end endgenerate |
|
`ifdef OPT_VLIW |
reg r_ihalt_phase, r_uhalt_phase; |
`ifdef OPT_CIS |
reg r_ihalt_phase; |
|
initial r_ihalt_phase = 0; |
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (i_rst) |
r_ihalt_phase <= 1'b0; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
r_ihalt_phase <= alu_phase; |
|
assign ihalt_phase = r_ihalt_phase; |
|
`ifdef OPT_NO_USERMODE |
assign uhalt_phase = 1'b0; |
`else |
reg r_uhalt_phase; |
|
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_uhalt_phase <= 1'b0; |
1703,8 → 1808,8
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT]; |
|
assign ihalt_phase = r_ihalt_phase; |
assign uhalt_phase = r_uhalt_phase; |
`endif |
`else |
assign ihalt_phase = 1'b0; |
assign uhalt_phase = 1'b0; |
1720,58 → 1825,52
// What happens when the pipeline has gie and ~gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
`ifdef OPT_NO_USERMODE |
assign upc = {(AW+2){1'b0}}; |
`else |
reg [(AW+1):0] r_upc; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
upc <= wr_spreg_vl[(AW-1):0]; |
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
upc <= alu_pc; |
r_upc <= { alu_pc, 2'b00 }; |
assign upc = r_upc; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
ipc <= RESET_ADDRESS; |
ipc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_spreg_vl[(AW-1):0]; |
else if ((~alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)) |
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((!alu_gie)&&(!alu_phase)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
ipc <= alu_pc; |
ipc <= { alu_pc, 2'b00 }; |
|
always @(posedge i_clk) |
if (i_rst) |
pf_pc <= RESET_ADDRESS; |
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache))) |
pf_pc <= ipc; |
pf_pc <= { ipc[(AW+1):2], 2'b00 }; |
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache))) |
pf_pc <= upc; |
pf_pc <= { upc[(AW+1):2], 2'b00 }; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_spreg_vl[(AW-1):0]; |
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
`ifdef OPT_PIPELINED |
else if ((dcd_early_branch)&&(~clear_pipeline)) |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 }; |
else if ((new_pc)||((!pf_stalled)&&(pf_valid))) |
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 }; |
`else |
else if ((alu_gie==gie)&&( |
((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
pf_pc <= alu_pc; |
pf_pc <= { alu_pc[(AW-1):0], 2'b00 }; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
`ifdef OPT_PIPELINED |
reg r_clear_icache; |
initial r_clear_icache = 1'b1; |
1784,42 → 1883,63
r_clear_icache <= 1'b0; |
assign w_clear_icache = r_clear_icache; |
`else |
assign w_clear_icache = 1'b0; |
assign w_clear_icache = i_clear_pf_cache; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(w_clear_icache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
// |
// The debug interface |
wire [31:0] w_debug_pc; |
`ifdef OPT_NO_USERMODE |
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 }; |
`else |
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4]) |
? { upc[(AW+1):2], uhalt_phase, 1'b0 } |
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } }; |
`endif |
generate |
if (AW<32) |
if (AW<30) |
assign w_debug_pc[31:(AW+2)] = 0; |
endgenerate |
|
always @(posedge i_clk) |
begin |
always @(posedge i_clk) |
`ifdef OPT_NO_USERMODE |
o_dbg_reg <= regset[i_dbg_reg[3:0]]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end else begin |
always @(posedge i_clk) |
`else |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end endgenerate |
`endif |
end |
|
always @(posedge i_clk) |
o_dbg_cc <= { o_break, bus_err, gie, sleep }; |
1832,12 → 1952,12
(~pf_cyc)&&(~mem_busy)&&(~alu_busy) |
&&(~div_busy)&&(~fpu_busy) |
// Operations must either be valid, or illegal |
&&((opvalid)||(i_rst)||(dcd_illegal)) |
&&((op_valid)||(i_rst)||(dcd_illegal)) |
// Decode stage must be either valid, in reset, or ill |
&&((dcdvalid)||(i_rst)||(pf_illegal))); |
&&((dcd_valid)||(i_rst)||(pf_illegal))); |
`else |
always @(posedge i_clk) |
r_halted <= (i_halt)&&((opvalid)||(i_rst)); |
r_halted <= (i_halt)&&((op_valid)||(i_rst)); |
`endif |
assign o_dbg_stall = ~r_halted; |
|
1857,24 → 1977,24
/* |
o_break, i_wb_err, pf_pc[1:0], |
flags, |
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid, |
pf_valid, dcd_valid, op_valid, alu_valid, mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, opvalid_alu, opvalid_mem, |
master_ce, op_valid_alu, op_valid_mem, |
// |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_we, |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
// ((op_valid_alu)&&(alu_stall)) |
// ||((op_valid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// op_Av[23:20], op_Av[3:0], |
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0] |
*/ |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcdvalid)), |
((dcd_early_branch)&&(dcd_valid)), |
pf_valid, pf_illegal, |
op_ce, dcd_ce, dcdvalid, dcd_stalled, |
op_ce, dcd_ce, dcd_valid, dcd_stalled, |
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err, |
pf_pc[7:0], pf_addr[7:0] |
*/ |
1884,20 → 2004,20
mem_busy, |
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we, |
o_wb_addr[8:0] } |
: { instruction[31:21] }, |
: { pf_instruction[31:21] }, |
pf_valid, (pf_valid) ? alu_pc[14:0] |
:{ pf_cyc, pf_stb, pf_pc[12:0] } |
:{ pf_cyc, pf_stb, pf_pc[14:2] } |
|
/* |
i_wb_err, gie, new_pc, dcd_early_branch, // 4 |
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4 |
instruction[30:27], // 4 |
pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4 |
pf_instruction[30:27], // 4 |
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4 |
dcdvalid, |
dcd_valid, |
((dcd_early_branch)&&(~clear_pipeline)) // 15 |
? dcd_branch_pc[14:0]:pf_pc[14:0] |
*/ |
}; |
`endif |
|
|
endmodule |
/zipcpu/trunk/rtl/cpudefs.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpudefs.v |
// |
26,7 → 26,7
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
40,11 → 40,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`ifndef CPUDEFS_H |
`define CPUDEFS_H |
// |
101,7 → 108,7
// |
// |
// OPT_IMPLEMENT_FPU will (one day) control whether or not the floating point |
// unit (once I have one) is built and included into the ZipCPU by default. |
// unit (once I have one) is built and included into the ZipCPU by default. |
// At that time, if this option is set then a parameter will be set that |
// causes the floating point unit to be included. (This parameter may |
// still be overridden, as with any parameter ...) If the floating point unit |
114,32 → 121,12
// |
// |
// |
// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set |
// is in use. The new instruction set contains space for floating point |
// operations, signed and unsigned divide instructions, as well as bit reversal |
// and ... at least two other operations yet to be defined. The decoder alone |
// uses about 70 fewer LUTs, although in practice this works out to 12 fewer |
// when all works out in the wash. Further, floating point and divide |
// instructions will cause an illegal instruction exception if they are not |
// implemented--so software capability can be built to use these instructions |
// immediately, even if the hardware is not yet ready. |
// |
// This option is likely to go away in the future, obsoleting the previous |
// instruction set, so I recommend setting this option and switching to the |
// new instruction set as soon as possible. |
// |
`define OPT_NEW_INSTRUCTION_SET |
// |
// |
// |
// |
// |
// |
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and |
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and |
// whether or not it can issue one instruction per clock. When set, the |
// prefetch has no cache, and only one instruction is fetched at a time. |
// This effectively sets the CPU so that only one instruction is ever |
// in the pipeline at once, and hence you may think of this as a "kill |
// This effectively sets the CPU so that only one instruction is ever |
// in the pipeline at once, and hence you may think of this as a "kill |
// pipeline" option. However, since the pipelined fetch component uses so |
// much area on the FPGA, this is an important option to use in trimming down |
// used area if necessary. Hence, it needs to be maintained for that purpose. |
148,7 → 135,7
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
173,9 → 160,9
// |
// |
// |
// OPT_PIPELINED is the natural result and opposite of using the single |
// OPT_PIPELINED is the natural result and opposite of using the single |
// instruction fetch unit. If you are not using that unit, the ZipCPU will |
// be pipelined. The option is defined here more for readability than |
// be pipelined. The option is defined here more for readability than |
// anything else, since OPT_PIPELINED makes more sense than OPT_SINGLE_FETCH, |
// well ... that and it does a better job of explaining what is going on. |
// |
229,36 → 216,30
// |
// |
// |
`ifdef OPT_NEW_INSTRUCTION_SET |
// |
// |
// The instruction set defines an optional compressed instruction set (CIS) |
// complement. These were at one time erroneously called Very Long Instruction |
// Words. They are more appropriately referred to as compressed instructions. |
// The compressed instruction format allows two instructions to be packed into |
// the same instruction word. Some instructions can be compressed, not all. |
// Compressed instructions take the same time to complete. Set OPT_CIS to |
// include these double instructions as part of the instruction set. These |
// instructions are designed to get more code density from the instruction set, |
// and to hopefully take some pain off of the performance of the pre-fetch and |
// instruction cache. |
// |
// The new instruction set also defines a set of very long instruction words. |
// Well, calling them "very long" instruction words is probably a misnomer, |
// although we're going to do it. They're really 2x16-bit instructions--- |
// instruction words that pack two instructions into one word. (2x14 bit |
// really--'cause you need a bit to note the instruction is a 2x instruction, |
// and then 3-bits for the condition codes ...) Set OPT_VLIW to include these |
// double instructions as part of the new instruction set. These allow a single |
// instruction to contain two instructions within. These instructions are |
// designed to get more code density from the instruction set, and to hopefully |
// take some pain off of the performance of the pre-fetch and instruction cache. |
// |
// These new instructions, however, also necessitate a change in the Zip |
// CPU--the Zip CPU can no longer execute instructions atomically. It must |
// now execute non-VLIW instructions, or VLIW instruction pairs, atomically. |
// now execute non-CIS instructions, or CIS instruction pairs, atomically. |
// This logic has been added into the ZipCPU, but it has not (yet) been |
// tested thoroughly. |
// |
// Oh, and the assembler, the debugger, and the object file dumper, and the |
// simulator all need to be updated as well .... |
// |
`define OPT_VLIW |
`define OPT_CIS |
// |
// |
`endif // OPT_NEW_INSTRUCTION_SET |
// |
// |
`endif // OPT_SINGLE_FETCH |
// |
// |
/zipcpu/trunk/rtl/peripherals/flashcache.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: flashcache.v |
// |
41,9 → 41,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
55,12 → 55,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module flashcache(i_clk, |
// Wishbone contrl interface |
i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we, i_wb_addr, i_wb_data, |
/zipcpu/trunk/rtl/peripherals/icontrol.v
52,7 → 52,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
64,6 → 64,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
70,6 → 75,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus, |
i_brd_ints, o_interrupt); |
parameter IUSED = 15; |
/zipcpu/trunk/rtl/peripherals/wbdmac.v
1,6 → 1,5
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: wbdmac.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
78,12 → 77,12
// buffer by reading from bits 25..16 of this control/status |
// register. |
// |
// Creator: Dan Gisselquist |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
95,11 → 94,16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define DMA_IDLE 3'b000 |
168,7 → 172,7
|
reg last_read_request, last_read_ack, |
last_write_request, last_write_ack; |
reg trigger, abort; |
reg trigger, abort, user_halt; |
|
initial dma_state = `DMA_IDLE; |
initial o_interrupt = 1'b0; |
193,7 → 197,7
begin |
case(i_swb_addr) |
2'b00: begin |
if ((i_swb_data[27:16] == 12'hfed) |
if ((i_swb_data[31:16] == 16'h0fed) |
&&(cfg_len_nonzero)) |
dma_state <= `DMA_WAIT; |
cfg_blocklen_sub_one |
221,6 → 225,8
nread <= 0; |
if (abort) |
dma_state <= `DMA_IDLE; |
else if (user_halt) |
dma_state <= `DMA_IDLE; |
else if (trigger) |
dma_state <= `DMA_READ_REQ; |
end |
240,11 → 246,14
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
if (user_halt) |
dma_state <= `DMA_READ_ACK; |
if (i_mwb_err) |
begin |
cfg_len <= 0; |
dma_state <= `DMA_IDLE; |
end |
|
if (abort) |
dma_state <= `DMA_IDLE; |
if (i_mwb_ack) |
266,6 → 275,8
nread <= nread+1; |
if (last_read_ack) // (nread+1 == nracks) |
dma_state <= `DMA_PRE_WRITE; |
if (user_halt) |
dma_state <= `DMA_IDLE; |
if (cfg_incs) |
cfg_raddr <= cfg_raddr |
+ {{(AW-1){1'b0}},1'b1}; |
303,6 → 314,8
nwacks <= nwacks+1; |
cfg_len <= cfg_len +{(AW){1'b1}}; // -1 |
end |
if (user_halt) |
dma_state <= `DMA_WRITE_ACK; |
if (abort) |
dma_state <= `DMA_IDLE; |
end |
332,9 → 345,10
|
initial o_interrupt = 1'b0; |
always @(posedge i_clk) |
o_interrupt <= (dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack) |
&&(last_write_ack) |
&&(cfg_len == {{(AW-1){1'b0}},1'b1}); |
o_interrupt <= ((dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack) |
&&(last_write_ack) |
&&(cfg_len == {{(AW-1){1'b0}},1'b1})) |
||((dma_state != `DMA_IDLE)&&(i_mwb_err)); |
|
initial cfg_err = 1'b0; |
always @(posedge i_clk) |
466,5 → 480,12
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hffed0000)); |
|
initial user_halt = 1'b0; |
always @(posedge i_clk) |
user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE)) |
||((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE) |
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hafed0000)); |
|
endmodule |
|
/zipcpu/trunk/rtl/peripherals/wbwatchdog.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbwatchdog.v |
// |
29,9 → 29,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
43,12 → 43,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbwatchdog(i_clk, i_rst, i_ce, i_timeout, o_int); |
parameter BW = 32; |
input i_clk, i_rst, i_ce; |
/zipcpu/trunk/rtl/peripherals/zipcounter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcounter.v |
// |
25,9 → 25,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
39,12 → 39,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module zipcounter(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
/zipcpu/trunk/rtl/peripherals/zipjiffies.v
45,7 → 45,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
57,6 → 57,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
63,6 → 68,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module zipjiffies(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
/zipcpu/trunk/rtl/peripherals/zipmmu.v
0,0 → 1,554
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipmmu.v |
// |
// Project: Zip CPU backend for the GNU Compiler Collection |
// |
// Purpose: To provide a "bump-in-the-line" wishbone memory management |
// unit, that is configured from one wishbone bus and modifies a |
// separate wishbone bus. Both busses will not be active at the same time. |
// |
// The idea is that the CPU can use one portion of its peripheral |
// system memory space to configure the MMU, and another portion of its |
// memory space to access the MMU. Even more, configuring the MMU is to |
// be done when the CPU is in supervisor mode. This means that all |
// high-memory, system-peripheral accesses will be enabled *only* when |
// the CPU is in supervisor mode. |
// |
// There is a very specific reason for this design choice: by designing |
// the MMU in this fashion, the MMU may then be inluded (or not) at the |
// discretion of the individual assembling the ZipSystem (or equivalent) |
// module. |
// |
// Design Goals: |
// |
// Since we're trying to design this for disadvantaged, limited CPUs, |
// we should be able to offer such CPUs only as much MMU as they want. |
// Therefore, it should be possible to scale the MMU up and/or down in |
// LUT space. |
// |
// Memory space: |
// 1. On access via the memory bus, the MMU should provide for a speed |
// going through it such that any access is delayed by only one |
// clock cycle. Further, multiple accesses to the same page |
// should not take any longer than the one cycle delay. Accesses |
// to other pages should take a minimum number of clocks. |
// Accesses from one page to the next, such as from one page to |
// the next subsequent one, should cost no delays. |
// |
// 2. One independent control word to set the current context |
// |
// - When context = 0, virtual page = physical page, page table is an |
// unused pass through. |
// - When context != 0, MMU translation is active anytime the GIE is |
// set. Pages must match context, as well as virtual address. |
// |
// - Contains 4 RdOnly bits indicating the log address size for the |
// machine, offset by 17. Thus, the build will have an address |
// bus of width (lgpage+17), or a memory space of (2^(lgpage+17)). |
// Under this formula, the number of valid address bits can range |
// from 17 to 32. |
// - Contains 4 RdOnly bits indicating log_2 TLB table size. |
// Size is given by (2^(lgsize)). I'm considering sizes of 6,7&8 |
// - Contains 4 RdOnly bits indicating the log page size, offset by |
// eight. Page sizes are therefore given by (2^(lgpage+8)), and |
// the smallest page size is 256 words. |
// - Contains 4 RdOnly bits indicating the log context size, offset by 1. |
// The number of bits in the context word therefore run from 1 to |
// (lgcontext+1)-1, supporting between (2^1)-1=3 and |
// (2^16)-1 = 65535 contexts. (The zero context is not being |
// counted here, as it is special.) |
// |
// +------+------+------+------+--------------------+ |
// | | | | | | |
// | 4b | 4b | 4b | 4b | 16-bit | |
// | LGADR| LGTBL|LGPGSZ|LGCTXT| Context word | |
// | | | | | | |
// +------+------+------+------+--------------------+ |
// |
// Supervisor *cannot* have page table entries, since there are no |
// interrupts (page faults) allowed in supervisor context. |
// |
// To be valid, |
// Context Size (1..16), NFlags ( 4) < Page Size (8-23 bits) |
// Page size (8-23 bits) > NFlags bits (4) |
// |
// Small page sizes, then, mean fewer contexts are possible |
// |
// 3. One status word, which contains the address that failed and some |
// flags: |
// |
// Top Virtual address bits indicate which page ... caused a problem. |
// These will be the top N bits of the word, where N is the size |
// of the virtual address bits. (Bits are cleared upon any write.) |
// |
// Flags: (Up to 12 bits, all zeros means no fault. Bits are cleared upon |
// write) |
// - 4: Multiple page table matches |
// - 2: Attempt to write a read-only page |
// - 1: Page not found |
// |
// 3. Two words per active page table entry, accessed through two bus |
// addresses. This word contains: |
// |
// 16-bits Page context |
// 20-bits Virtual address |
// 20-bits Physical address |
// A physical address of all ones means that the |
// page does not exist, and any attempt to access |
// the virtual address associated with this page |
// should fault. |
// |
// Flags: |
// 1-bit Read-only / ~written (user set/read/written) |
// If set, this page will cause a fault on any |
// attempt to write this memory. |
// 1-bit Accessed |
// This an be used to implement a least-recently |
// used measure. The hardware will set this value |
// when the page is accessed. The user can also |
// set or clear this at will. |
// 1-bit Cacheable |
// This is not a hardware page, but a memory page. |
// Therefore, the values within this page may be |
// cached. |
// 1-bit This context |
// This is a read-only bit, indicating that the |
// context register of this address matches the |
// context register in the control word. |
// |
// (Loaded flag Not necessary, just map the physical page to 0) |
// |
// We could equivalently do a 16-bit V&P addresses, for a 28-bit total |
// address space, if we didn't want to support the entire 32-bit space. |
// |
// |
// 4. Can read/write this word in two parts: |
// |
// (20-bit Virtual )(8-bits lower context)(4-bit flags), and |
// (20-bit Physical)(8-bits upper context)(4-bit flags) |
// |
// Actual bit lengths will vary as the MMU configuration changes, |
// however the flags will always be the low order four bits, |
// and the virtual/physical address flags will always consume |
// 32 bits minus the page table size. The context bits will |
// always be split into upper and lower context bits. If there |
// are more context bits than can fit in the space, then the |
// upper bits of the context field will be filled with zeros. |
// |
// On any write, the context bits will be set from the context |
// bits in the control register. |
// |
// +----+----+-----+----+----+----+----+--+--+--+--+ |
// | | Lower 8b| R| A| C| T| |
// | 20-bit Virtual page ID | Context | O| C| C| H| |
// |(top 20 bits of the addr)| ID | n| C| H| S| |
// | | | W| S| E| P| |
// +----+----+-----+----+----+----+----+--+--+--+--+ |
// |
// +----+----+-----+----+----+----+----+--+--+--+--+ |
// | | Upper 8b| R| A| C| T| |
// | 20-bit Physical pg ID | Context | O| C| C| H| |
// |(top 20 bits of the | ID | n| C| H| S| |
// | physical address | | W| S| E| P| |
// +----+----+-----+----+----+----+----+--+--+--+--+ |
// |
// 5. PF Cache--handles words in both physical and virtual |
// - On any pf-read, the MMU returns the current pagetable/TBL mapping |
// This consists of [Context,Va,Pa]. |
// - The PF cache stores this with the address tag. (If the PF is reading, |
// the VP should match, only the physical page ID needs to be |
// sored ...) |
// - At the end of any cache line read, the page table/TBL mapping address |
// will have long been available, the "Valid" bit will be turned |
// on and associated with the physical mapping. |
// - On any data-write (pf doesn't write), MMU sends [Context,Va,Pa] |
// TLB mapping to the pf-cache. |
// - If the write matches any physical PF-cache addresses (???), the |
// pfcache declares that address line invalid, and just plain |
// clears the valid bit for that page. |
// |
// Since the cache lines sizes are smaller than the page table sizes, |
// failure to match the address means ... what? |
// |
// |
// 6. Normal operation and timing: |
// - One clock lost if still on the same page as last time, or in the |
// supervisor (physical pages only) context ... |
// - Two clocks (1-more delay) if opening a new page. |
// (1-clock to look up the entry--comparing against all entries, |
// 1-clock to read it, next clock the access goes forward.) |
// - No more than two stalls for any access, pipelineable. Thus, once |
// you've stalled by both clocks, you'll not stall again during |
// any pipeline operation. |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2016-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
module zipmmu(i_clk, i_reset, i_ctrl_cyc_stb, i_wbm_cyc, i_wbm_stb, i_wb_we, |
i_wb_addr, i_wb_data, |
o_cyc, o_stb, o_we, o_addr, o_data, |
i_stall, i_ack, i_err, i_data, |
o_rtn_stall, o_rtn_ack, o_rtn_err, |
o_rtn_miss, o_rtn_data, |
pf_return_stb, pf_return_we, |
pf_return_p, pf_return_v, |
pf_return_cachable); |
parameter ADDRESS_WIDTH=28, LGTBL=6, PLGPGSZ=12, PLGCTXT=16, DW=32; |
localparam // And for our derived parameters (don't set these ...) |
// AW is just shorthand for the name ADDRESS_WIDTH |
AW = ADDRESS_WIDTH, |
// Page sizes must allow for a minimum of one context |
// bit per page, plus four flag bits, hence the minimum |
// number of bits for an address within a page is 5 |
LGPGSZ=(PLGPGSZ < 5)? 5:PLGPGSZ, |
// The number of context bits is twice the number of |
// bits left over from DW after removing the LGPGSZ |
// and flags bits. |
LGCTXT=(((DW-LGPGSZ-4)<<1)<PLGCTXT)? |
((DW-LGPGSZ-4)<<1):PLGCTXT, |
// LGLCTX is the number of context bits in the low word |
LGLCTX=((LGPGSZ-4)<LGCTXT)?(LGPGSZ-4):LGCTXT, |
// LGHCTX is the number of context bits in the high word |
LGHCTX= (LGCTXT-LGLCTX), |
VAW=(DW-LGPGSZ), // Virtual address width |
PAW=(AW-LGPGSZ), // Physical address width |
TBL_BITS = LGTBL, // Bits necessary to addr tbl |
TBL_SIZE=(1<<TBL_BITS);// Number of table entries |
input i_clk, i_reset; |
// |
input i_ctrl_cyc_stb; |
// |
input i_wbm_cyc, i_wbm_stb; |
// |
input i_wb_we; |
input [(DW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
// |
// Here's where we drive the slave side of the bus |
output reg o_cyc; |
output wire o_stb, o_we; |
output reg [(AW-1):0] o_addr; |
output reg [(DW-1):0] o_data; |
// and get our return information from driving the slave ... |
input i_stall, i_ack, i_err; |
input [(DW-1):0] i_data; |
// |
// Here's where we return information on either our slave/control bus |
// or the memory bus we are controlled from. Note that we share these |
// wires ... |
output wire o_rtn_stall; |
output reg o_rtn_ack; |
output wire o_rtn_err, o_rtn_miss; |
output [(DW-1):0] o_rtn_data; |
// Finally, to allow the prefetch to snoop on the MMU conversion ... |
output wire pf_return_stb, // snoop data is valid |
pf_return_we; // snoop data is chnging |
output wire [(PAW-1):0] pf_return_p; |
output wire [(VAW-1):0] pf_return_v; |
output wire pf_return_cachable; |
// |
// |
|
// |
// |
// |
reg [3:1] tlb_flags [0:(TBL_SIZE-1)]; |
reg [(LGCTXT-1):0] tlb_cdata [0:(TBL_SIZE-1)]; |
reg [(DW-LGPGSZ-1):0] tlb_vdata [0:(TBL_SIZE-1)]; |
reg [(AW-LGPGSZ-1):0] tlb_pdata [0:(TBL_SIZE-1)]; |
|
wire adr_control, adr_status, adr_vtable, adr_ptable; |
wire wr_control, wr_status, wr_vtable, wr_ptable; |
wire [(LGTBL-1):0] wr_tlb_addr; |
assign wr_tlb_addr= i_wb_addr[(LGTBL):1]; // Leave bottom for V/P |
assign adr_control= (i_ctrl_cyc_stb)&&(~i_wb_addr[(LGTBL+1)])&&(~i_wb_addr[0]); |
assign adr_status = (i_ctrl_cyc_stb)&&(~i_wb_addr[(LGTBL+1)])&&( i_wb_addr[0]); |
assign adr_vtable = (i_ctrl_cyc_stb)&&( i_wb_addr[(LGTBL+1)])&&(~i_wb_addr[0]); |
assign adr_ptable = (i_ctrl_cyc_stb)&&( i_wb_addr[(LGTBL+1)])&&( i_wb_addr[0]); |
assign wr_control = (adr_control)&&(i_wb_we); |
assign wr_status = (adr_status )&&(i_wb_we); |
assign wr_vtable = (adr_vtable )&&(i_wb_we); |
assign wr_ptable = (adr_ptable )&&(i_wb_we); |
|
reg setup_ack, z_context, setup_this_page_flag; |
reg [(DW-1):0] setup_data; |
reg [(LGCTXT-1):0] r_context_word, setup_page; |
// |
wire [31:0] w_control_data,w_vtable_reg,w_ptable_reg; |
wire [(LGCTXT-1):0] w_ctable_reg; |
reg [31:0] status_word; |
// |
reg rf_miss, rf_ropage, rf_table_err; |
wire [31:0] control_word; |
wire [3:0] lgaddr_bits, lgtblsz_bits, lgpagesz_bits, |
lgcontext_bits; |
|
reg [(AW-(LGPGSZ)):0] r_mmu_err_vaddr; |
wire [(DW-LGPGSZ):0] w_mmu_err_vaddr; |
// |
reg r_pending, r_we, last_page_valid, last_ro, r_valid; |
reg [(DW-1):0] r_addr; |
reg [(DW-1):0] r_data; |
reg [(PAW-1):0] last_ppage; |
reg [(VAW-1):0] last_vpage; |
// |
wire [(TBL_SIZE-1):0] r_tlb_match; |
reg [(LGTBL-1):0] s_tlb_addr; |
reg s_tlb_miss, s_tlb_hit, s_pending; |
// |
wire ro_flag, simple_miss, ro_miss, table_err, cachable; |
reg p_tlb_miss,p_tlb_err, pf_stb, pf_cachable; |
// |
reg rtn_err; |
|
|
////////////////////////////////////////// |
// |
// |
// Step one -- handle the control bus--i_ctrl_cyc_stb |
// |
// |
////////////////////////////////////////// |
always @(posedge i_clk) |
begin |
// Write to the Translation lookaside buffer |
if (wr_vtable) |
tlb_vdata[wr_tlb_addr]<=i_wb_data[(DW-1):LGPGSZ]; |
if (wr_ptable) |
tlb_pdata[wr_tlb_addr]<=i_wb_data[(AW-1):LGPGSZ]; |
// Set the context register for the page |
if ((wr_vtable)||(wr_ptable)) |
tlb_flags[wr_tlb_addr] <= i_wb_data[3:1]; |
// Otherwise, keep track of the accessed bit if we ever access this page |
else if ((!z_context)&&(r_pending)&&(s_tlb_hit)&&((!r_we)||(!ro_flag))) |
tlb_flags[s_tlb_addr][2] <= 1'b1; |
if (wr_vtable) |
tlb_cdata[wr_tlb_addr][((LGCTXT>=8)? 7:(LGCTXT-1)):0] |
<= i_wb_data[((LGCTXT>=8)? 11:(4+LGCTXT-1)):4]; |
if ((wr_ptable)&&(LGCTXT > 8)) |
tlb_cdata[wr_tlb_addr][(LGCTXT-1):8] |
<= i_wb_data[(4+LGCTXT-8-1):4]; |
setup_ack <= (i_ctrl_cyc_stb)&&(!i_reset); |
end |
// Writing to the control word |
initial z_context = 1'b1; |
initial r_context_word = 0; |
always @(posedge i_clk) |
if (wr_control) |
begin |
r_context_word <= i_wb_data[(LGCTXT-1):0]; |
z_context <= (i_wb_data[(LGCTXT-1):0] == {(LGCTXT){1'b0}}); |
end |
// Status words cannot be written to |
|
/* verilator lint_off WIDTH */ |
assign w_control_data[31:28] = AW-17; |
assign w_control_data[27:24] = LGTBL; |
assign w_control_data[23:20] = LGPGSZ-8; |
assign w_control_data[19:16] = LGCTXT-1; |
/* verilator lint_on WIDTH */ |
assign w_control_data[15: 0] = {{(16-LGCTXT){1'b0}}, r_context_word}; |
// |
assign w_vtable_reg[(DW-1):LGPGSZ] = tlb_vdata[wr_tlb_addr]; |
assign w_vtable_reg[(LGPGSZ-1):(LGLCTX+4-1)] = 0; |
assign w_vtable_reg[(LGLCTX+4-1):4] = { tlb_cdata[wr_tlb_addr][(LGLCTX-1):0] }; |
assign w_vtable_reg[ 3:0] = { tlb_flags[wr_tlb_addr], 1'b0 }; |
// |
assign w_ptable_reg[(DW-1):LGPGSZ] = { {(DW-AW){1'b0}}, |
tlb_pdata[wr_tlb_addr] }; |
assign w_ptable_reg[LGPGSZ:(4+LGHCTX)] = 0; |
assign w_ptable_reg[ 3:0] = { tlb_flags[wr_tlb_addr], 1'b0 }; |
assign w_ctable_reg = tlb_cdata[wr_tlb_addr]; |
// |
generate |
if (4+LGHCTX-1>4) |
assign w_ptable_reg[(4+LGHCTX-1):4] = { |
tlb_cdata[wr_tlb_addr][(LGCTXT-1):LGLCTX] }; |
endgenerate |
|
// Now, reading from the bus |
always @(posedge i_clk) |
setup_page <= w_ctable_reg; |
always @(posedge i_clk) |
setup_this_page_flag <= (i_ctrl_cyc_stb)&&(i_wb_addr[LGTBL+1]); |
always @(posedge i_clk) |
case({i_wb_addr[LGTBL+1],i_wb_addr[0]}) |
2'b00: setup_data <= w_control_data; |
2'b01: setup_data <= status_word; |
2'b10: setup_data <= w_vtable_reg; |
2'b11: setup_data <= w_ptable_reg; |
endcase |
|
|
|
////////////////////////////////////////// |
// |
// |
// Step two -- handle the page lookup on the master bus |
// |
// |
////////////////////////////////////////// |
assign w_mmu_err_vaddr = { {(DW-AW){1'b0}}, r_mmu_err_vaddr }; |
|
// |
// |
// First clock, and the r_ register, copies the bus data from the bus. |
// While this increases the bus latency, it also gives us a moment to |
// work. |
// |
// |
initial r_pending = 1'b0; |
initial r_valid = 1'b0; |
always @(posedge i_clk) |
begin |
if (!o_rtn_stall) |
begin |
r_pending <= i_wbm_stb; |
r_we <= i_wb_we; |
r_addr <= i_wb_addr; |
r_data <= i_wb_data; |
r_valid <= (i_wbm_stb)&&((z_context)||((last_page_valid) |
&&(i_wb_addr[(DW-1):LGPGSZ] == last_vpage) |
&&((!last_ro)||(!i_wb_we)))); |
s_pending <= 1'b0; |
end else begin |
r_valid <= (r_valid)||((last_page_valid) |
&&(r_addr[(DW-1):LGPGSZ] == last_vpage) |
&&((!last_ro)||(!r_we))); |
r_pending<= (r_pending)&&(i_wbm_cyc); |
s_pending <= r_pending; |
end |
|
if (i_reset) |
r_pending <= 1'b0; |
end |
// Second clock: know which buffer entry this belong in. |
// If we don't already know, then the pipeline must be stalled for a |
// while ... |
genvar k, s; |
generate |
for(k=0; k<TBL_BITS; k = k + 1) |
assign r_tlb_match[k] = |
// Virtual address must match |
((tlb_vdata[k] == r_addr[(DW-1):LGPGSZ]) |
// Context must match as well |
&&(tlb_cdata[k] == r_context_word)); |
endgenerate |
|
initial s_tlb_miss = 1'b0; |
initial s_tlb_hit = 1'b0; |
generate |
always @(posedge i_clk) |
begin // valid when s_ becomes valid |
s_tlb_addr <= {(LGTBL){1'b0}}; |
for(k=0; k<TBL_SIZE; k=k+1) |
for(s=0; s<LGTBL; s=s+1) |
if (((k&(1<<s))!=0)&&(r_tlb_match[k])) |
s_tlb_addr[s] <= 1'b1; |
s_tlb_miss <= (r_pending)&&(r_tlb_match[(TBL_BITS-1):0] == 0); |
s_tlb_hit <= 1'b0; |
for(k=0; k<TBL_SIZE; k=k+1) |
if (r_tlb_match == (1<<k)) |
s_tlb_hit <= (r_pending); |
end endgenerate |
|
|
// Third clock: Read from the address the virtual table offset, |
// whether read-only, etc. |
assign ro_flag = tlb_flags[s_tlb_addr][3]; |
assign simple_miss = (s_pending)&&(s_tlb_miss); |
assign ro_miss = (s_pending)&&(s_tlb_hit)&&(r_we)&&(ro_flag); |
assign table_err = (s_pending)&&(!s_tlb_miss)&&(!s_tlb_hit); |
assign cachable = tlb_flags[s_tlb_addr][1]; |
// assign tlb_access_flag = tlb_flags[s_tlb_addr][2]; |
initial pf_stb = 1'b0; |
initial p_tlb_err = 1'b0; |
initial p_tlb_miss = 1'b0; |
always @(posedge i_clk) |
begin |
p_tlb_miss <= (simple_miss)||(ro_miss); |
p_tlb_err <= (s_pending)&&((!s_tlb_miss)&&(!s_tlb_hit)); |
|
pf_cachable <= cachable; |
if ((!z_context)&&(r_pending)) |
begin |
last_ppage <= tlb_pdata[s_tlb_addr]; |
last_vpage <= tlb_vdata[s_tlb_addr]; |
last_ro <= ro_flag; |
pf_stb <= 1'b1; |
end else |
pf_stb <= 1'b0; |
if ((table_err)||(ro_miss)||(simple_miss)) |
status_word <= { r_addr[(DW-1):LGPGSZ], |
{(LGPGSZ-3){1'b0}}, |
(table_err), (ro_miss), (simple_miss) }; |
|
if (wr_control) |
last_page_valid <= (last_page_valid) |
&&(r_context_word == i_wb_data[(LGCTXT-1):0]); |
else if ((r_pending)&&(!z_context)) |
last_page_valid <= (s_tlb_hit)&&(!ro_miss); |
|
if (i_reset) |
last_page_valid <= 1'b0; |
end |
|
initial rtn_err = 1'b0; |
always @(posedge i_clk) |
begin |
o_cyc <= (!i_reset)&&(i_wbm_cyc); |
|
o_rtn_ack <= (!i_reset)&&((setup_ack)||(i_wbm_cyc)&&(i_ack)); |
o_rtn_data <= (setup_ack) ? setup_data : i_data; |
if (setup_this_page_flag) |
o_rtn_data[0] <= ((setup_page == r_context_word)? 1'b1:1'b0); |
rtn_err <= (!i_reset)&&(i_wbm_cyc)&&(i_err); |
end |
assign o_stb = (r_valid); |
assign o_we = (r_we); |
assign o_rtn_stall = (i_wbm_cyc)&&(((r_pending)&&(!r_valid))||(i_stall)); |
assign o_rtn_miss = p_tlb_miss; |
assign o_rtn_err = (rtn_err)||(p_tlb_err); |
|
assign o_addr[(AW-1):0] = {(z_context)? |
r_addr[(AW-1):LGPGSZ] : last_ppage, |
r_addr[(LGPGSZ-1):0]}; |
assign o_data = r_data; |
|
// |
// Bus snooping returns ... |
// |
assign pf_return_stb = pf_stb; |
assign pf_return_we = r_we; |
assign pf_return_p = last_ppage; |
assign pf_return_v = last_vpage; |
assign pf_return_cachable = pf_cachable; |
|
endmodule |
/zipcpu/trunk/rtl/peripherals/ziptimer.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: ziptimer.v |
// |
43,9 → 43,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
57,12 → 57,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module ziptimer(i_clk, i_rst, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
zipcpu/trunk/rtl/peripherals
Property changes :
Added: svn:ignore
## -0,0 +1,7 ##
+bitrev.v
+flashcache.v
+oldtimer.v
+popcount.v
+wbcordic.v
+zipport.v
+ziptrap.v
Index: zipcpu/trunk/rtl/zipbones.v
===================================================================
--- zipcpu/trunk/rtl/zipbones.v (revision 200)
+++ zipcpu/trunk/rtl/zipbones.v (revision 201)
@@ -1,4 +1,4 @@
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipbones.v
//
@@ -11,9 +11,9 @@
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
-// Copyright (C) 2015, Gisselquist Technology, LLC
+// Copyright (C) 2015, 2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
@@ -25,17 +25,23 @@
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
+// target there if the PDF file isn't present.) If not, see
+// for a copy.
+//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
+//
`include "cpudefs.v"
//
module zipbones(i_clk, i_rst,
// Wishbone master interface from the CPU
- o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
+ o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
// Incoming interrupts
i_ext_int,
@@ -48,14 +54,15 @@
, o_zip_debug
`endif
);
- parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
- LGICACHE=8, START_HALTED=0,
- AW=ADDRESS_WIDTH;
+ parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
+ LGICACHE=8, START_HALTED=0;
+ localparam AW=ADDRESS_WIDTH;
input i_clk, i_rst;
// Wishbone master
output wire o_wb_cyc, o_wb_stb, o_wb_we;
output wire [(AW-1):0] o_wb_addr;
output wire [31:0] o_wb_data;
+ output wire [3:0] o_wb_sel;
input i_wb_ack, i_wb_stall;
input [31:0] i_wb_data;
input i_wb_err;
@@ -167,7 +174,10 @@
wire [31:0] cpu_dbg_data;
assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
&&(i_dbg_we)&&(i_dbg_addr));
- zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
+ zipcpu #(.RESET_ADDRESS(RESET_ADDRESS),
+ .ADDRESS_WIDTH(ADDRESS_WIDTH),
+ .LGICACHE(LGICACHE),
+ .WITH_LOCAL_BUS(0))
thecpu(i_clk, cpu_reset, i_ext_int,
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
@@ -174,9 +184,9 @@
cpu_dbg_cc, cpu_break,
o_wb_cyc, o_wb_stb,
cpu_lcl_cyc, cpu_lcl_stb,
- o_wb_we, o_wb_addr, o_wb_data,
+ o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data,
- (i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
+ (i_wb_err)||(cpu_lcl_cyc),
cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef DEBUG_SCOPE
, o_zip_debug
Index: zipcpu/trunk/rtl/zipsystem.v
===================================================================
--- zipcpu/trunk/rtl/zipsystem.v (revision 200)
+++ zipcpu/trunk/rtl/zipsystem.v (revision 201)
@@ -1,4 +1,4 @@
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
// Filename: zipsystem.v
//
@@ -62,9 +62,9 @@
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
-// Copyright (C) 2015-2016, Gisselquist Technology, LLC
+// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
@@ -76,12 +76,18 @@
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// for a copy.
+//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
-///////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
//
+//
`include "cpudefs.v"
//
// While I hate adding delays to any bus access, this next delay is required
@@ -157,7 +163,7 @@
//
module zipsystem(i_clk, i_rst,
// Wishbone master interface from the CPU
- o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
+ o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
// Incoming interrupts
i_ext_int,
@@ -170,7 +176,7 @@
, o_cpu_debug
`endif
);
- parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
+ parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
`ifdef OPT_MULTIPLY
IMPLEMENT_MPY = `OPT_MULTIPLY,
@@ -187,8 +193,8 @@
`else
IMPLEMENT_FPU=0,
`endif
- IMPLEMENT_LOCK=1,
- // Derived parameters
+ IMPLEMENT_LOCK=1;
+ localparam // Derived parameters
AW=ADDRESS_WIDTH;
input i_clk, i_rst;
// Wishbone master
@@ -195,6 +201,7 @@
output wire o_wb_cyc, o_wb_stb, o_wb_we;
output wire [(AW-1):0] o_wb_addr;
output wire [31:0] o_wb_data;
+ output wire [3:0] o_wb_sel;
input i_wb_ack, i_wb_stall;
input [31:0] i_wb_data;
input i_wb_err;
@@ -220,16 +227,16 @@
wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
wire mtc_int, moc_int, mpc_int, mic_int,
utc_int, uoc_int, upc_int, uic_int;
+
+ assign main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int,
+ jif_int, dmac_int };
+
generate
if (EXTERNAL_INTERRUPTS < 9)
- assign main_int_vector = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
- i_ext_int, ctri_int,
- tma_int, tmb_int, tmc_int,
- jif_int, dmac_int };
+ assign main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
+ i_ext_int };
else
- assign main_int_vector = { i_ext_int[8:0], ctri_int,
- tma_int, tmb_int, tmc_int,
- jif_int, dmac_int };
+ assign main_int_vector[14:6] = i_ext_int[8:0];
endgenerate
generate
if (EXTERNAL_INTERRUPTS <= 9)
@@ -251,8 +258,8 @@
i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
`endif
endgenerate
-
+
// Delay the debug port by one clock, to meet timing requirements
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
wire [31:0] dbg_idata, dbg_odata;
@@ -259,11 +266,12 @@
reg dbg_ack;
`ifdef DELAY_DBG_BUS
wire dbg_err, no_dbg_err;
+ wire [3:0] dbg_sel;
assign dbg_err = 1'b0;
busdelay #(1,32) wbdelay(i_clk,
- i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
+ i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
- dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
+ dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
dbg_ack, dbg_stall, dbg_odata, dbg_err);
`else
assign dbg_cyc = i_dbg_cyc;
@@ -671,6 +679,7 @@
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
cpu_we, cpu_dbg_we;
wire [31:0] cpu_data, wb_data;
+ wire [3:0] cpu_sel;
wire cpu_ack, cpu_stall, cpu_err;
wire [31:0] cpu_dbg_data;
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
@@ -690,7 +699,7 @@
cpu_dbg_cc, cpu_break,
cpu_gbl_cyc, cpu_gbl_stb,
cpu_lcl_cyc, cpu_lcl_stb,
- cpu_we, cpu_addr, cpu_data,
+ cpu_we, cpu_addr, cpu_data, cpu_sel,
cpu_ack, cpu_stall, wb_data,
cpu_err,
cpu_op_stall, cpu_pf_stall, cpu_i_count
@@ -744,12 +753,13 @@
cpu_ext_err;
wire [(AW-1):0] ext_addr;
wire [31:0] ext_odata;
+ wire [3:0] ext_sel;
wbpriarbiter #(32,AW) dmacvcpu(i_clk,
- cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
+ cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, cpu_sel,
cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
- dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
+ dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
dc_ack, dc_stall, dc_err,
- ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
+ ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
ext_ack, ext_stall, ext_err);
`ifdef DELAY_EXT_BUS
@@ -756,18 +766,19 @@
busdelay #(AW,32) extbus(i_clk,
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
ext_ack, ext_stall, ext_idata, ext_err,
- o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
+ o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
`else
- assign o_wb_cyc = ext_cyc;
- assign o_wb_stb = ext_stb;
- assign o_wb_we = ext_we;
- assign o_wb_addr = ext_addr;
- assign o_wb_data = ext_odata;
- assign ext_ack = i_wb_ack;
- assign ext_stall = i_wb_stall;
- assign ext_idata = i_wb_data;
- assign ext_err = (i_wb_err)||(wdbus_int);
+ assign o_wb_cyc = ext_cyc;
+ assign o_wb_stb = ext_stb;
+ assign o_wb_we = ext_we;
+ assign o_wb_addr = ext_addr;
+ assign o_wb_data = ext_odata;
+ assign o_wb_sel = ext_sel;
+ assign ext_ack = i_wb_ack;
+ assign ext_stall = i_wb_stall;
+ assign ext_idata = i_wb_data;
+ assign ext_err = (i_wb_err)||(wdbus_int);
`endif
wire tmr_ack;
zipcpu/trunk/rtl
Property changes :
Added: svn:ignore
## -0,0 +1,3 ##
+.gitignore
+obj_dir
+cpudefs.h