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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/bench/cpp
    from Rev 34 to Rev 36
    ↔ Reverse comparison
  •

Rev 34 → Rev 36

/zippy_tb.cpp
55,12 → 55,13
#define CMD_DATA 1
#define CMD_HALT (1<<10)
#define CMD_STALL (1<<9)
#define CMD_STEP (1<<8)
#define CMD_INT (1<<7)
#define CMD_RESET (1<<6)
#define CMD_STEP ((1<<8)|CMD_HALT)
 
#define KEY_ESCAPE 27
#define KEY_RETURN 10
#define CTRL(X) ((X)&0x01f)
 
// No particular "parameters" need definition or redefinition here.
class ZIPPY_TB : public TESTB<Vzipsystem> {
73,9 → 74,13
int m_cursor;
 
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
// dbg_fp = fopen("dbg.txt", "w");
dbg_fp = NULL;
dbg_flag = false;
if (true) {
dbg_fp = fopen("dbg.txt", "w");
dbg_flag = true;
} else {
dbg_fp = NULL;
dbg_flag = false;
}
bomb = false;
m_cursor = 0;
}
179,7 → 184,20
int ln= 0;
 
mvprintw(ln,0, "Peripherals-SS"); ln++;
printw(" %s",
// (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":" ",
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" "
);
/*
printw(" %s%s%s",
(m_core->v__DOT__thecpu__DOT__ill_err)?"IL":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
);
*/
/*
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
mvprintw(ln, 17, "%s%s",
((m_core->v__DOT__sys_cyc)
189,7 → 207,7
*/
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
 
ln++;
237,11 → 255,13
 
showreg(ln, 0, "sR12", 12, (m_cursor==24));
showreg(ln,20, "sSP ", 13, (m_cursor==25));
mvprintw(ln,40, "sCC :%s%s%s%s%s%s%s%s",
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ",
(m_core->v__DOT__thecpu__DOT__break_en)?"BK":" ",
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ",
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
285,13 → 305,16
attroff(A_BOLD);
ln+=1;
 
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
ln++;
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
300,20 → 323,23
(m_core->v__DOT__thecpu__DOT__pf_addr),
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
(m_core->v__DOT__cpu_stall)?"STL":" ",
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
(m_core->v__DOT__wb_data)); ln++;
 
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":" ",
(m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":" ",
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
:((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":" "),
(m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
:((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":" "),
(m_core->v__DOT__thecpu__DOT__mem_we )?"WE":" ",
(m_core->v__DOT__thecpu__DOT__mem_addr),
(m_core->v__DOT__thecpu__DOT__mem_data),
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ",
(m_core->v__DOT__cpu_stall)?"STL":" ",
(m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":" ",
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
 
mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
(m_core->o_wb_cyc)?"CYC":" ",
(m_core->o_wb_stb)?"STB":" ",
(m_core->o_wb_we )?"WE":" ",
329,8 → 355,8
//m_core->v__DOT__thecpu__DOT__instruction_gie,
m_core->v__DOT__thecpu__DOT__gie,
0,
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
showins(ln, "Dc",
m_core->v__DOT__thecpu__DOT__dcd_ce,
454,7 → 480,7
} ln++;
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
// showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
ln++;
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
499,9 → 525,10
dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
 
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s",
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(cc & 0x100)?"TP":" ",
(cc & 0x200)?"TP":" ",
(cc & 0x080)?"BK":" ",
(cc & 0x040)?"ST":" ",
(cc & 0x020)?"IE":" ",
(cc & 0x010)?"SL":" ",
536,7 → 563,7
dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
cc = cmd_read(30);
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
(m_cursor == 42)?">":" ",
(m_cursor == 42)?'>':' ',
(cc&0x100)?"TP":" ",
(cc&0x040)?"ST":" ",
(cc&0x020)?"IE":" ",
592,14 → 619,11
int stb = m_core->o_wb_stb;
if ((m_core->o_wb_addr & (-1<<20))!=1)
stb = 0;
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
m_core->i_wb_ack = 1;
 
if ((dbg_flag)&&(dbg_fp)) {
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
(m_core->i_dbg_cyc)?"CYC":" ",
(m_core->i_dbg_stb)?"STB":
((m_core->v__DOT__dbg_stb)?"DBG":" "),
614,7 → 638,8
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":" ",
(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":" ",
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
(m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
(m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
672,9 → 697,19
m_core->v__DOT__thecpu__DOT__mem_valid,
m_core->v__DOT__thecpu__DOT__w_iflags,
m_core->v__DOT__thecpu__DOT__w_uflags);
fprintf(dbg_fp, "\tbrk=%d,%d\n",
fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
(m_core->v__DOT__thecpu__DOT__master_ce)?"CE":" ",
m_core->v__DOT__thecpu__DOT__break_en,
m_core->v__DOT__thecpu__DOT__op_break);
} else if ((dbg_fp)&&
((m_core->v__DOT__thecpu__DOT__op_break)
||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
(m_core->v__DOT__thecpu__DOT__master_ce)?"CE":" ",
m_core->v__DOT__thecpu__DOT__break_en,
m_core->v__DOT__thecpu__DOT__dcd_break,
m_core->v__DOT__thecpu__DOT__op_break);
}
 
if (dbg_fp) {
684,7 → 719,26
fprintf(dbg_fp, "\tNew PC\n");
}
 
TESTB<Vzipsystem>::tick();
if (dbg_fp)
fprintf(dbg_fp, "----------- TICK ----------\n");
if (false) {
m_core->i_clk = 1;
m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
eval();
m_core->i_clk = 0;
m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
eval();
m_tickcount++;
} else {
m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
TESTB<Vzipsystem>::tick();
}
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
(gie)?"User":"Supervisor",
716,10 → 770,12
bool test_failure(void) {
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
== 0x2f0f7fff));
== 0x2f0f7fff)
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
}
 
void wb_write(unsigned a, unsigned int v) {
int errcount = 0;
mvprintw(0,35, "%40s", "");
mvprintw(0,40, "wb_write(%d,%x)", a, v);
m_core->i_dbg_cyc = 1;
729,11 → 785,11
m_core->i_dbg_data = v;
 
tick();
while(m_core->o_dbg_stall)
while((errcount++ < 100)&&(m_core->o_dbg_stall))
tick();
 
m_core->i_dbg_stb = 0;
while(!m_core->o_dbg_ack)
while((errcount++ < 100)&&(!m_core->o_dbg_ack))
tick();
 
// Release the bus
742,10 → 798,15
tick();
mvprintw(0,35, "%40s", "");
mvprintw(0,40, "wb_write -- complete");
 
 
if (errcount >= 100)
bomb = true;
}
 
unsigned long wb_read(unsigned a) {
unsigned int v;
int errcount = 0;
mvprintw(0,35, "%40s", "");
mvprintw(0,40, "wb_read(0x%08x)", a);
m_core->i_dbg_cyc = 1;
754,11 → 815,11
m_core->i_dbg_addr = a & 1;
 
tick();
while(m_core->o_dbg_stall)
while((errcount++<100)&&(m_core->o_dbg_stall))
tick();
 
m_core->i_dbg_stb = 0;
while(!m_core->o_dbg_ack)
while((errcount++<100)&&(!m_core->o_dbg_ack))
tick();
v = m_core->o_dbg_data;
 
770,6 → 831,8
mvprintw(0,35, "%40s", "");
mvprintw(0,40, "wb_read = 0x%08x", v);
 
if (errcount >= 100)
bomb = true;
return v;
}
 
824,6 → 887,7
case KEY_LEFT: case KEY_BACKSPACE:
if (pos > 0) pos--;
break;
case CTRL('L'): redrawwin(stdscr); break;
case KEY_CLEAR:
pos = 0;
break;
889,7 → 953,7
break;
case 32: tb->m_core->v__DOT__pic_data = v; break;
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
931,7 → 995,7
int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
ZIPPY_TB *tb = new ZIPPY_TB();
bool autorun = false, exit_on_done = false;
bool autorun = false, exit_on_done = false, autostep=false;
 
// mem[0x00000] = 0xbe000010; // Halt instruction
unsigned int mptr = 0;
953,6 → 1017,9
usage();
exit(0);
break;
case 's':
autostep = true;
break;
default:
usage();
exit(-1);
994,6 → 1061,15
 
done = (tb->test_success())||(tb->test_failure());
}
} else if (autostep) {
bool done = false;
 
printf("Running in non-interactive mode, via step commands\n");
tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
while(!done) {
tb->wb_write(CMD_REG, CMD_STEP);
done = (tb->test_success())||(tb->test_failure());
}
} else { // Interactive
initscr();
raw();
1034,7 → 1110,10
done = true;
break;
case 'r': case 'R':
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
if (manual)
tb->reset();
else
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
halted = true;
erase();
break;
1062,6 → 1141,7
case KEY_DOWN: tb->cursor_down(); break;
case KEY_LEFT: tb->cursor_left(); break;
case KEY_RIGHT: tb->cursor_right(); break;
case CTRL('L'): redrawwin(stdscr); break;
case ERR: case KEY_CLEAR:
default:
if (!manual)
1113,12 → 1193,18
printf("Instructions / Clock: %.2f\n",
(double)tb->m_core->v__DOT__mic_data
/ (double)tb->m_core->v__DOT__mtc_data);
if (tb->test_success())
 
int rcode = 0;
if (tb->bomb) {
printf("TEST BOMBED\n");
rcode = -1;
} else if (tb->test_success()) {
printf("SUCCESS!\n");
else if (tb->test_failure())
} else if (tb->test_failure()) {
rcode = -2;
printf("TEST FAILED!\n");
else
} else
printf("User quit\n");
exit(0);
exit(rcode);
}
 
/testb.h
50,10 → 50,10
}
 
virtual void tick(void) {
m_core->i_clk = 1;
eval();
m_core->i_clk = 0;
eval();
m_core->i_clk = 1;
eval();
 
m_tickcount++;
}
63,7 → 63,7
tick();
m_core->i_rst = 0;
m_tickcount = 0l;
printf("RESET\n");
// printf("RESET\n");
}
};
 
/memsim.cpp
79,11 → 79,11
m_mem[nr] = 0l;
}
 
void MEMSIM::apply(const unsigned char wb_cyc,
void MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc,
const unsigned char wb_stb, const unsigned char wb_we,
const BUSW wb_addr, const BUSW wb_data,
unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
if ((wb_cyc)&&(wb_stb)) {
if ((wb_cyc)&&(wb_stb)&&(clk)) {
if (wb_we)
m_mem[wb_addr & m_mask] = wb_data;
o_ack = 1;
95,7 → 95,7
(wb_we)?"WRITE":"READ",
wb_addr, o_data);
*/
} else {
} else if (clk) {
o_ack = 0;
o_stall = 0;
}
/Makefile
45,11 → 45,21
LIBS := $(RAWLIB) -lncurses
TESTF := ../../sw/zasm/z.out
 
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h
$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@
 
.PHONY: stest
stest: zippy_tb
./zippy_tb -s $(TESTF)
 
.PHONY: itest
itest: zippy_tb
./zippy_tb $(TESTF)
 
test: zippy_tb
.PHONY: test
test: zippy_tb stest
./zippy_tb -a $(TESTF)
 
.PHONY: clean
clean:
rm ./zippy_tb
/memsim.h
51,13 → 51,14
MEMSIM(const unsigned int nwords);
~MEMSIM(void);
void load(const char *fname);
void apply(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
void apply(const unsigned clk, const uchar wb_cyc, const uchar wb_stb,
const uchar wb_we,
const BUSW wb_addr, const BUSW wb_data,
uchar &o_ack, uchar &o_stall, BUSW &o_data);
void operator()(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
void operator()(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, const uchar wb_we,
const BUSW wb_addr, const BUSW wb_data,
uchar &o_ack, uchar &o_stall, BUSW &o_data) {
apply(wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data);
apply(clk, wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data);
}
BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; }
};

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