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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/rtl/core
    from Rev 15 to Rev 18
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  •

Rev 15 → Rev 18

/pipefetch.v
37,7 → 37,7
//
////////////////////////////////////////////////////////////////////////////////
//
module pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
o_i, o_pc, o_v,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
44,7 → 44,8
parameter RESET_ADDRESS=32'h0010_0000,
LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
BUSW=32;
input i_clk, i_rst, i_new_pc, i_stall_n;
input i_clk, i_rst, i_new_pc,
i_clear_cache, i_stall_n;
input [(BUSW-1):0] i_pc;
output reg [(BUSW-1):0] o_i;
output reg [(BUSW-1):0] o_pc;
96,9 → 97,10
initial r_cache_base = RESET_ADDRESS;
always @(posedge i_clk)
begin
if (i_rst)
if ((i_rst)||(i_clear_cache))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
// r_cache_base <= RESET_ADDRESS;
// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
// &&(i_pc >= r_cache_base)
164,7 → 166,7
end
 
always @(posedge i_clk)
if (i_rst) // Required, so we can reload memoy and then reset
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
r_nvalid <= 0;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
175,21 → 177,29
r_nvalid <= r_nvalid+1;
 
always @(posedge i_clk)
if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
if (i_clear_cache)
r_cache_base <= i_pc;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
r_cache_base <= (i_new_pc) ? i_pc : r_addr;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
 
always @(posedge i_clk)
if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
if (i_clear_cache)
r_cache_offset <= 0;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
r_cache_offset <= 0;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
always @(posedge i_clk)
if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
if (i_clear_cache)
o_wb_addr <= i_pc;
else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
211,7 → 221,7
 
initial r_addr_set = 1'b0;
always @(posedge i_clk)
if (i_rst)
if ((i_rst)||(i_clear_cache))
r_addr_set <= 1'b0;
else if (i_new_pc)
r_addr_set <= 1'b1;
241,5 → 251,4
if (i_stall_n)
o_pc <= r_addr;
 
endmodule
/zipcpu.v
114,8 → 114,8
`define CPU_SLEEP_BIT 4
module zipcpu(i_clk, i_rst, i_interrupt,
// Debug interface
i_halt, i_dbg_reg, i_dbg_we, i_dbg_data,
o_dbg_stall, o_dbg_reg,
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
o_dbg_stall, o_dbg_reg, o_dbg_cc,
o_break,
// CPU interface to the wishbone bus
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
125,7 → 125,7
parameter RESET_ADDRESS=32'h0100000;
input i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
input i_halt;
input i_halt, i_clear_pf_cache;
input [4:0] i_dbg_reg;
input i_dbg_we;
input [31:0] i_dbg_data;
132,6 → 132,7
// Debug interface -- outputs
output reg o_dbg_stall;
output reg [31:0] o_dbg_reg;
output reg [3:0] o_dbg_cc;
output wire o_break;
// Wishbone interface -- outputs
output wire o_wb_cyc, o_wb_stb, o_wb_we;
163,6 → 164,8
//
reg [31:0] pf_pc;
reg new_pc;
wire clear_pipeline;
assign clear_pipeline = new_pc || i_clear_pf_cache;
 
wire dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
283,9 → 286,9
// Calculate stall conditions
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc);
assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~clear_pipeline);
//
assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond);
assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
assign mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
(~master_ce)
// Stall waiting for flags to be valid
314,7 → 317,7
pf_ack, pf_stall, i_wb_data);
`else // Pipe fetch
pipefetch #(RESET_ADDRESS)
pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, i_wb_data,
326,8 → 329,8
if (i_rst)
dcdvalid <= 1'b0;
else if (dcd_ce)
dcdvalid <= (~new_pc);
else if ((~dcd_stalled)||(new_pc))
dcdvalid <= (~clear_pipeline);
else if ((~dcd_stalled)||(clear_pipeline))
dcdvalid <= 1'b0;
 
always @(posedge i_clk)
511,8 → 514,8
// Hence, the test on dcd_stalled here. If we must
// wait until our operands are valid, then we aren't
// valid yet until then.
opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled);
else if ((~op_stall)||(new_pc))
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
else if ((~op_stall)||(clear_pipeline))
opvalid <= 1'b0;
 
// Here's part of our debug interface. When we recognize a break
528,7 → 531,7
op_break <= 1'b0;
else if (op_ce)
op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
else if ((~op_stall)||(new_pc))
else if ((~op_stall)||(clear_pipeline))
op_break <= 1'b0;
 
always @(posedge i_clk)
626,7 → 629,7
alu_pc <= op_pc;
initial alu_pc_valid = 1'b0;
always @(posedge i_clk)
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc)
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
&&((~opM)
||(~mem_stalled));
 
676,6 → 679,8
always @(posedge i_clk)
if (wr_reg_ce)
regset[wr_reg_id] <= wr_reg_vl;
else if ((i_halt)&&(i_dbg_we))
regset[i_dbg_reg] <= i_dbg_data[31:0];
 
//
// Write back to the condition codes/flags register ...
832,7 → 837,7
 
initial new_pc = 1'b1;
always @(posedge i_clk)
if (i_rst)
if ((i_rst)||(i_clear_pf_cache))
new_pc <= 1'b1;
else if (w_switch_to_interrupt)
new_pc <= 1'b1;
858,6 → 863,9
((i_dbg_reg[4])?flags:iflags) };
end
always @(posedge i_clk)
o_dbg_cc <= { break_en, step, gie, sleep };
 
always @(posedge i_clk)
o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
||((~opvalid)&&(~i_rst))
||((~dcdvalid)&&(~i_rst));

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