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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/rtl/peripherals
    from Rev 56 to Rev 69
    ↔ Reverse comparison
  •

Rev 56 → Rev 69

/wbdmac.v
79,7 → 79,7
// register.
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
// Copyright: 2015
//
111,8 → 111,7
o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
i_dev_ints,
o_interrupt,
i_other_busmaster_requests_bus);
o_interrupt);
parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,
DW=32, LGDV=5,AW=ADDRESS_WIDTH;
input i_clk;
137,7 → 136,13
// An interrupt to be set upon completion
output reg o_interrupt;
// Need to release the bus for a higher priority user
input i_other_busmaster_requests_bus;
// This logic had lots of problems, so it is being
// removed. If you want to make sure the bus is available
// for a higher priority user, adjust the transfer length
// accordingly.
//
// input i_other_busmaster_requests_bus;
//
 
 
reg cfg_wp; // Write protect
169,8 → 174,7
if ((o_mwb_stb)&&(~i_mwb_stall))
begin
nwritten <= nwritten+1;
if ((nwritten == nread-1)
||(i_other_busmaster_requests_bus))
if (nwritten == nread-1)
// Wishbone interruptus
o_mwb_stb <= 1'b0;
else if (cfg_incd) begin
205,8 → 209,7
begin
nacks <= nacks+1;
if ((nacks == {1'b0, cfg_blocklen_sub_one})
||(bus_nacks <= cfg_len-1)
||(i_other_busmaster_requests_bus))
||(bus_nacks <= cfg_len-1))
// Wishbone interruptus
o_mwb_stb <= 1'b0;
else if (cfg_incs) begin
/flashcache.v
10,6 → 10,10
// some amount of flash to be copied into this on-chip RAM,
// and then access it with nearly zero latency.
//
// Status: This file is no longer being used as an active file within
// the ZipCPU project. It's an older file from an idea that
// never really caught traction.
//
// Interface:
// FlashCache sits on the Wishbone bus as both a slave and a master.
// Slave requests for memory will get mapped to a local RAM, from which
35,7 → 39,7
// less than the copy address.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/zipcounter.v
23,7 → 23,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/zipjiffies.v
41,7 → 41,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/ziptimer.v
41,7 → 41,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/icontrol.v
48,7 → 48,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
71,7 → 71,7
////////////////////////////////////////////////////////////////////////////////
//
module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
i_brd_ints, o_interrupt_strobe);
i_brd_ints, o_interrupt);
parameter IUSED = 15;
input i_clk, i_reset;
input i_wr;
78,7 → 78,7
input [31:0] i_proc_bus;
output wire [31:0] o_proc_bus;
input [(IUSED-1):0] i_brd_ints;
output reg o_interrupt_strobe;
output wire o_interrupt;
 
reg [(IUSED-1):0] r_int_state;
reg [(IUSED-1):0] r_int_enable;
127,6 → 127,7
assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
end endgenerate
 
/*
reg int_condition;
initial int_condition = 1'b0;
initial o_interrupt_strobe = 1'b0;
145,5 → 146,8
o_interrupt_strobe <= 1'b1;
end else
o_interrupt_strobe <= 1'b0;
*/
 
assign o_interrupt = r_interrupt;
 
endmodule
/ziptrap.v
49,7 → 49,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/wbwatchdog.v
0,0 → 1,76
///////////////////////////////////////////////////////////////////////////
//
// Filename: wbwatchdog.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A Zip timer, redesigned to be a bus watchdog
//
// This is a **really** stripped down Zip Timer. All options for external
// control have been removed. This timer may be reset, and ... that's
// about it. The goal is that this stripped down timer be used as a bus
// watchdog element. Even at that, it's not really fully featured. The
// rest of the important features can be found in the zipsystem module.
//
// As a historical note, the wishbone watchdog timer began as a normal
// timer, with some fixed inputs. This makes sense, if you think about it:
// if the goal is to interrupt a stalled wishbone transaction by inserting
// a bus error, then you can't use the bus to set it up or configure it
// simply because the bus in question is ... well, unreliable. You're
// trying to make it reliable.
//
// The problem with using the ziptimer in a stripped down implementation
// was that the fixed inputs caused the synthesis tool to complain about
// the use of registers values would never change. This solves that
// problem by explicitly removing the cruft that would otherwise
// just create synthesis warnings and errors.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
module wbwatchdog(i_clk, i_rst, i_ce, i_timeout, o_int);
parameter BW = 32;
input i_clk, i_rst, i_ce;
// Inputs (these were at one time wishbone controlled ...)
input [(BW-1):0] i_timeout;
// Interrupt line
output reg o_int;
 
reg [(BW-1):0] r_value;
initial r_value = 0;
always @(posedge i_clk)
if (i_rst)
r_value <= i_timeout[(BW-1):0];
else if ((i_ce)&&(~o_int))
r_value <= r_value + {(BW){1'b1}}; // r_value - 1;
 
// Set the interrupt on our last tick.
initial o_int = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(~i_ce))
o_int <= 1'b0;
else
o_int <= (r_value == { {(BW-1){1'b0}}, 1'b1 });
 
endmodule

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