URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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- This comparison shows the changes necessary to convert path
/zipcpu/trunk/sw/lib
- from Rev 59 to Rev 69
- ↔ Reverse comparison
Rev 59 → Rev 69
/mpy32u.S
8,7 → 8,7
; multiply.. |
; |
; Creator: Dan Gisselquist, Ph.D. |
; Gisselquist Tecnology, LLC |
; Gisselquist Technology, LLC |
; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
33,19 → 33,21
; |
; |
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1, R2 = rtn addr (on stack) |
SUB 2,SP |
SUB 3,SP |
STO R2,(SP) |
STO R3,1(SP) |
STO R4,2(SP) |
; |
MOV R0,R2 |
MULU R1,R2 ; R2 = Low order bits, low(R0) * low(R1) |
MPYU R1,R2 ; R2 = Low order bits, low(R0) * low(R1) |
MOV R0,R3 |
LSR 16,R3 ; Put high order bits in lower half of R3 |
MULU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1) |
MPYU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1) |
LSR 16,R1 ; R1 = High order bits of R1, being done w/ low order |
MOV R1,R4 ; |
MUL R0,R4 ; R4 = Mid order bits, low(R0) * high(R1) |
MPYU R0,R4 ; R4 = Mid order bits, low(R0) * high(R1) |
LSR 16,R0 |
MULU R1,R0 ; R0 = High order bits, high(R0) * high(R1) |
MPYU R1,R0 ; R0 = High order bits, high(R0) * high(R1) |
ADD R3,R4 ; R4 = sum of mid order bits |
ADD.C 0x010000,R0 ; Add in the carry (if it happened) |
MOV R4,R3 |
55,9 → 57,10
ADD R4,R2 ; R2 = low order bits plus low order mid-bits |
ADD.C 1,R0 ; Add in the carry to R0 (if it happened) |
MOV R2,R1 ; Place low order bits into R1 |
; |
; |
LOD (SP),R2 |
LOD 1(SP),R3 |
LOD 2(SP),R4 |
LOD 3(SP),R2 |
ADD 2,SP |
ADD 3,SP |
JMP R2 |
|
/divs.S
14,9 → 14,9
; |
; |
; |
divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1 |
lib_divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1 |
SUB 2,SP |
; (stall) |
STO R2,(SP) |
STO R3,2(SP) |
; |
CLR R3 ; Keep track of resulting sign in R2 |
29,8 → 29,7
XOR.LT 1,R3 ; If so, result will be opposite sign of before |
NEG.LT R1 ; Now we get R1=ABS(R1) |
MOV.LT divu_divs_return(PC),R2 |
STO R2,1(SP) |
BRA divu ; Do our unsigned multiply |
BRA lib_divu ; Do our unsigned multiply |
; JSR divu ; Do our unsigned multiply |
divu_divs_return: |
TST 1,R3 ; Check resulting sign |
38,8 → 37,8
TST 2,R3 ; Now, if R1 was originally negative |
NEG.NE R1 ; Then negate R1 |
ret_div32s: |
LOD (SP),R2 |
LOD 2(SP),R3 |
LOD 3(SP),R2 |
ADD 2,SP |
JMP R2 |
|
/divu.S
8,7 → 8,7
; This routine is also called by the signed divide. |
; |
; Creator: Dan Gisselquist, Ph.D. |
; Gisselquist Tecnology, LLC |
; Gisselquist Technology, LLC |
; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
32,13 → 32,14
; |
; |
; |
divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 |
lib_divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 |
TST -1,R1 |
; BNZ divu_valid_divide |
CLR.Z R0 ; Should be a divide by zero error / trap |
RETN.Z |
JMP.Z R2 |
divu_valid_divide: |
SUB 1,SP |
SUB 2,SP |
STO R2,(SP) |
STO R3,1(SP) |
; |
LDI 1,R2 ; Here's where we record the bit we are working on |
122,8 → 123,8
divu_record_result: |
MOV R0,R1 |
MOV R3,R0 |
LOD (SP),R2 |
LOD 1(SP),R3 |
LOD 2(SP),R2 |
ADD 1,SP |
ADD 2,SP |
JMP R2 |
|
/mpy32s.S
9,7 → 9,7
; unsigned multiply. |
; |
; Creator: Dan Gisselquist, Ph.D. |
; Gisselquist Tecnology, LLC |
; Gisselquist Technology, LLC |
; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
41,22 → 41,22
; R3 - used as scratch internally |
mpy32s: |
ADD 2,SP |
STO R2,(SP) |
STO R3,2(SP) |
; |
CLR R3 ; Keep track of resulting sign in R2 |
TST R0 ; Is R0 negative? |
XOR.LT #1,R3 ; If so, resulting sign will be negative, and |
TST -1,R0 ; Is R0 negative? |
XOR.LT 1,R3 ; If so, resulting sign will be negative, and |
NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0)) |
TST R1 ; Is R1 negative? |
XOR.LT #1,R3 ; If so, result will be opposite sign of before |
TST -1,R1 ; Is R1 negative? |
XOR.LT 1,R3 ; If so, result will be opposite sign of before |
NEG.LT R1 ; Now we get R1=ABS(R1) |
|
; JSR mpy32u |
MOV __HERE__+2,R2 ; Do our unsigned multiply |
STO R2,1(SP) |
MOV __HERE__+2(PC),R2 ; Do our unsigned multiply |
BRA mpy32u |
; |
TST 0,R3 ; Check resulting sign |
TST -1,R3 ; Check resulting sign |
BZ ret_mul32s ; If positive, do nothing more |
NOT R0 ; If negative, negate the result |
NOT R1 |
63,8 → 63,8
ADD $1,R1 |
ADD.C $1,R0 |
ret_mul32s: |
LOD (SP),R2 |
LOD 2(SP),R3 |
LOD 3(SP),R2 |
ADD 2,SP |
JMP R2 |
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