URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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- This comparison shows the changes necessary to convert path
/zipcpu/trunk
- from Rev 89 to Rev 90
- ↔ Reverse comparison
Rev 89 → Rev 90
/rtl/core/idecode.v
127,7 → 127,7
// 0 LUTs |
assign w_dcdA = w_dcdR; |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
// assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
// 0 LUTs |
assign w_dcdA_pc = w_dcdR_pc; |
172,12 → 172,15
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR = ~w_wR_n; |
// 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits) |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
// and writes to the PC/CC register(s). |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldixx)))); |
||((w_ALU)&&(~w_mov)&&(~w_ldixx) |
&&(iword[30:28] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
334,32 → 337,31
reg r_early_branch; |
reg [(AW-1):0] r_branch_pc; |
always @(posedge i_clk) |
if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3])) |
if (i_ce) |
begin |
if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
begin |
if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc)) |
begin // Move (X+PC) to PC |
r_early_branch <= 1'b1; |
end else if (w_op[4:1] == 4'hb) // LDI to PC |
if (w_op[4:1] == 4'hb) // LDI to PC |
begin // LDI x,PC |
r_early_branch <= 1'b1; |
end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc)) |
end else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
begin // Add x,PC |
r_early_branch <= 1'b1; |
end else begin |
r_early_branch <= 1'b0; |
end |
end else begin |
if (i_ce) |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end |
always @(posedge i_clk) |
if (i_ce) |
begin |
if (w_op[4:1] == 4'hb) |
r_branch_pc <= {{(AW-23){w_I[22]}},w_I}; |
else |
r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I} |
+{{(AW-1){1'b0}},1'b1}; |
if (w_op[4:1] == 4'hb) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-18){iword[17]}},iword[16:0]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
assign o_early_branch = r_early_branch; |