Subversion Repositories zpu
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Index
-
+
- Introduction +
- Download +
- Creating a patch +
- Getting help - mailing list
- Getting started - FPGA
- Getting started - software
- Architecture introduction @@ -24,6 +28,105 @@
The worlds smallest 32 bit CPU with GCC toolchain +
+This CPU is finding a new home at www.opencores.org, please +contact me if you are willing and able to help in shaping up the +www.opencores.org pages. +
+The HDL, GCC toolchain and eCos HAL are actually done. Mainly I +could need a hand with writing up docs/web pages/examples/bug +reports.
+The ZPU has a BSD license for the HDL and GPL for the rest(source +files are sadly out of date here, patches gladly accepted!). This +allows deployments to implement any version of the ZPU they want +without running into commercial problems, but if improvements are +done to the architecture as such, then they need to be contributed +back. +
+One strength of the ZPU is that it is tiny and therefore easy to +implement from scratch to suit specialized needs and optimizations.
+Currently there exists some pages at http://www.zylin.com/zpu.htm +that explains about the ZPU. According to OpenCores policy this +information should be moved to www.opencores.org. Patches gratefully +accepted to do so!
+Per Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin +is free to decide that the ZPU shall have a BSD license for HDL + GPL +for the rest.
+Sincerley,
+Øyvind Harboe
Zylin AS
+
Features +
+-
+
Small size: 442 LUT @ 95 MHz after + P&R w/32 bit datapath Xilinx XC3S400 +
+Wishbone +
+Code size 80% of ARM Thumb +
+GCC toolchain(GDB, newlib, + libstdc+) +
+eCos embedded operating system support
+
Survey +
+Please take the time to fill in this short survey so we can gather +information about where the ZPU can be the most useful:
+http://www.zylin.com/zpusurvey.html
+Status +
+-
+
HDL works +
+GCC toolchain works +
+eCos HAL works, but could be less + RAM hungry +
+The main problem at this point is + not usage of the CPU, but that the documentation/CVS layout needs + attention +
+Needs GDB stub support in eCos +
+Could do with a Verilog implementation(ca. 600 lines to + translate)
+
Simulator +
+The ZPU simulator is integrated into the Zylin Embedded CDT plugin +to ease debugging of ZPU applications:
+http://www.zylin.com/embeddedcdt.html
+The ZPU simulator has many features besides debugging an +application:
+-
+
taking output from simulation(e.g. + ModelSim) and matching that against the Java simulator, thus making + it much easier to debug HDL implementations and also getting real + world timing information +
+can generate gprof output +
+generate various statistics +
+
The plugin is still pretty rough around the edges, and needs to +get GUI support for enabling the ModelSim trace input feature.
+
Compiling
+ZPU application
Setting
+up the simulator
Choosing
+ZPU executable
Debug
+session
+
Getting started - FPGA
The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART @@ -1740,6 +1843,23 @@ with stripped down ARM7 type systems. + +Download source code
+ +The simplest way to get the ZPU HDL source and tools is to check +it out from CVS:
+cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous co +zpu/zpu
+Start by reading zpu/zpu/hdl/index.html
+ +Creating a patch
+
If you have an changes, modify the files locally, create a
+patch and email it to zylin-zpu mailing list. Attach it
+as an uncompressed .txt file:
cd zpu
cvs diff -upN . > mypatch.txt