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Zealot: Implementing in FPGAs
Optimizing for code size
Installing eCos build tools
+ SPI flash controller
Next generation ZPU
@@ -1618,6 +1619,83 @@
zpu-elf-size hello.elf
+ + + +Fast-READ only implementation.
+ 32-bit only access
+ Fast sequential read access - Uses low-clock approach
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SPI flash controller (read-only)
+This is a simple read-only SPI flash controller, with the following characteristics: + +-
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Version
+The current version is 1.2. This is also the first public version available. + +Timing overview
+ +Simple timing overview, with one nonsequential access to address 0x0, followed by a sequential access to address 0x4. +This simulation was done with Xilinx tools, after post-routing, and using a ZPU to access the SPI
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+On Image 2, you can see the clock almost perfectly centered on data, when we write to the SPI flash.
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+Image 1: Timing overview
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+As you can see from Image 3, I assume the worst-case read delay from SPI (which is 15ns, as you can see from the marker).
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+Image 2: Issuing commands to the SPI
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+Image 3: Reading from the SPI
+Usage
+ +Simple description of SPI controller interface: + +| Symbol | +Direction | +Bit width | +Purpose | +
|---|---|---|---|
| adr | Input | 24 | Address where to read from SPI |
| dat_o | Output | 32 | Data read from SPI |
| clk | Input | 1 | Input clock. Used for both interface and SPI |
| ce | Input | 1 | Chip Enable |
| rst | Input | 1 | Asynchronous reset |
| ack | Output | 1 | Data valid ACK |
| SPI_CLK | Output | 1 | SPI output clock |
| SPI_MOSI | Output | 1 | SPI output data from controller to chip |
| SPI_MISO | Input | 1 | SPI input data from chip to controller |
| SPI_SELN | Output | 1 | SPI nSEL (deselect, active low) signal |