OpenCores
URL https://opencores.org/ocsvn/zpu/zpu/trunk

Subversion Repositories zpu

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /zpu/trunk
    from Rev 92 to Rev 93
    ↔ Reverse comparison
  •

Rev 92 → Rev 93

/zpu/zpu4/test/hello/hello.ram
0,0 → 1,3055
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2830 => x"00002c30",
2831 => x"00002c30",
2832 => x"00002c38",
2833 => x"00002c38",
2834 => x"00002c40",
2835 => x"00002c40",
2836 => x"00002c48",
2837 => x"00002c48",
2838 => x"00002c50",
2839 => x"00002c50",
2840 => x"00002c58",
2841 => x"00002c58",
2842 => x"00002c60",
2843 => x"00002c60",
2844 => x"00002c68",
2845 => x"00002c68",
2846 => x"00002c70",
2847 => x"00002c70",
2848 => x"00002c78",
2849 => x"00002c78",
2850 => x"00002c80",
2851 => x"00002c80",
2852 => x"00002c88",
2853 => x"00002c88",
2854 => x"00002c90",
2855 => x"00002c90",
2856 => x"00002c98",
2857 => x"00002c98",
2858 => x"00002ca0",
2859 => x"00002ca0",
2860 => x"00002ca8",
2861 => x"00002ca8",
2862 => x"00002cb0",
2863 => x"00002cb0",
2864 => x"00002cb8",
2865 => x"00002cb8",
2866 => x"00002cc0",
2867 => x"00002cc0",
2868 => x"00002cc8",
2869 => x"00002cc8",
2870 => x"00002cd0",
2871 => x"00002cd0",
2872 => x"00002cd8",
2873 => x"00002cd8",
2874 => x"00002ce0",
2875 => x"00002ce0",
2876 => x"00002ce8",
2877 => x"00002ce8",
2878 => x"00002cf0",
2879 => x"00002cf0",
2880 => x"00002cf8",
2881 => x"00002cf8",
2882 => x"00002d00",
2883 => x"00002d00",
2884 => x"00002d08",
2885 => x"00002d08",
2886 => x"00002d10",
2887 => x"00002d10",
2888 => x"00002d18",
2889 => x"00002d18",
2890 => x"00002d20",
2891 => x"00002d20",
2892 => x"00002d28",
2893 => x"00002d28",
2894 => x"00002d30",
2895 => x"00002d30",
2896 => x"00002d38",
2897 => x"00002d38",
2898 => x"00002d40",
2899 => x"00002d40",
2900 => x"00002d48",
2901 => x"00002d48",
2902 => x"00002d50",
2903 => x"00002d50",
2904 => x"00002d58",
2905 => x"00002d58",
2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002e48",
2965 => x"00002e48",
2966 => x"00002e50",
2967 => x"00002e50",
2968 => x"00002e58",
2969 => x"00002e58",
2970 => x"00002e60",
2971 => x"00002e60",
2972 => x"00002e68",
2973 => x"00002e68",
2974 => x"00002e70",
2975 => x"00002e70",
2976 => x"00002e78",
2977 => x"00002e78",
2978 => x"00002e80",
2979 => x"00002e80",
2980 => x"00002e88",
2981 => x"00002e88",
2982 => x"00002e90",
2983 => x"00002e90",
2984 => x"00002e98",
2985 => x"00002e98",
2986 => x"00002ea0",
2987 => x"00002ea0",
2988 => x"00002ea8",
2989 => x"00002ea8",
2990 => x"00002eb0",
2991 => x"00002eb0",
2992 => x"00002eb8",
2993 => x"00002eb8",
2994 => x"00002ec0",
2995 => x"00002ec0",
2996 => x"00002ec8",
2997 => x"00002ec8",
2998 => x"00002ed0",
2999 => x"00002ed0",
3000 => x"00002ed8",
3001 => x"00002ed8",
3002 => x"00002ee0",
3003 => x"00002ee0",
3004 => x"00002ee8",
3005 => x"00002ee8",
3006 => x"00002ef0",
3007 => x"00002ef0",
3008 => x"00002ef8",
3009 => x"00002ef8",
3010 => x"00002f00",
3011 => x"00002f00",
3012 => x"00002f08",
3013 => x"00002f08",
3014 => x"00002f10",
3015 => x"00002f10",
3016 => x"00002f18",
3017 => x"00002f18",
3018 => x"00002f20",
3019 => x"00002f20",
3020 => x"00002f28",
3021 => x"00002f28",
3022 => x"00002f30",
3023 => x"00002f30",
3024 => x"00002f38",
3025 => x"00002f38",
3026 => x"00002f40",
3027 => x"00002f40",
3028 => x"00002f48",
3029 => x"00002f48",
3030 => x"00002f50",
3031 => x"00002f50",
3032 => x"00002f58",
3033 => x"00002f58",
3034 => x"00002f60",
3035 => x"00002f60",
3036 => x"00002f68",
3037 => x"00002f68",
3038 => x"00002f70",
3039 => x"00002f70",
3040 => x"00002f78",
3041 => x"00002f78",
3042 => x"00002f80",
3043 => x"00002f80",
3044 => x"00002f88",
3045 => x"00002f88",
3046 => x"00002f90",
3047 => x"00002f90",
3048 => x"00002f98",
3049 => x"00002f98",
3050 => x"000027b8",
3051 => x"ffffffff",
3052 => x"00000000",
3053 => x"ffffffff",
3054 => x"00000000",
/zpu/zpu4/test/hello/hello.c
0,0 → 1,47
/*
* Small hello world example, does not use printf()
*/
#include <stdio.h>
 
int j;
int k;
 
int main(int argc, char **argv)
{
int i;
for (i=0; i< 10; i++)
{
puts("Hello world 1\n");
puts("Hello world 2\n");
j=-4;
if ((j>>1)!=-2)
{
abort();
}
k=10;
if (k*j!=-40)
{
abort();
}
j=10;
k=10000000;
if (k*j!=100000000)
{
abort();
}
j=0x80000000;
k=0xffffffff;
if (j>k)
{
abort();
}
}
if (i!=10)
{
abort();
}
}
/zpu/zpu4/test/hello/build.sh
0,0 → 1,4
zpu-elf-gcc -O3 -phi `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g
zpu-elf-objdump --disassemble-all >hello.dis hello.elf
zpu-elf-objcopy -O binary hello.elf hello.bin
java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.ram
/zpu/zpu4/test/hello/hello.elf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/zpu/zpu4/test/hello/hello.elf
zpu/zpu4/test/hello/hello.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/hello/hello.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zpu/zpu4/test/hello/hello.bin =================================================================== --- zpu/zpu4/test/hello/hello.bin (nonexistent) +++ zpu/zpu4/test/hello/hello.bin (revision 93)
zpu/zpu4/test/hello/hello.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/dmips/dmips.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zpu/zpu4/test/dmips/dmips.elf =================================================================== --- zpu/zpu4/test/dmips/dmips.elf (nonexistent) +++ zpu/zpu4/test/dmips/dmips.elf (revision 93)
zpu/zpu4/test/dmips/dmips.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/dmips/dmips.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zpu/zpu4/test/dmips/dmips.bin =================================================================== --- zpu/zpu4/test/dmips/dmips.bin (nonexistent) +++ zpu/zpu4/test/dmips/dmips.bin (revision 93)
zpu/zpu4/test/dmips/dmips.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/dmips/build.sh =================================================================== --- zpu/zpu4/test/dmips/build.sh (nonexistent) +++ zpu/zpu4/test/dmips/build.sh (revision 93) @@ -0,0 +1,4 @@ +zpu-elf-gcc -DTIME ../../../../../../roadshow/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -phi -o dmips.elf +zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf +zpu-elf-objcopy -O binary dmips.elf dmips.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram Index: zpu/zpu4/test/dmips/dmips.ram =================================================================== --- zpu/zpu4/test/dmips/dmips.ram (nonexistent) +++ zpu/zpu4/test/dmips/dmips.ram (revision 93) @@ -0,0 +1,3256 @@ +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80d5f40c", +3 => x"3a0b0b80", +4 => x"c4fb0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c5c22d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c3040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a6", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d5", +162 => x"e0738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88a90400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0bad", +171 => x"aa2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0bad", +179 => x"ee2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d5f00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82fd3fbf", +257 => x"a03f0410", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", +287 => x"833d0d04", +288 => x"80d5f008", +289 => x"802ea438", +290 => x"80d5f408", +291 => x"822ebd38", +292 => x"8380800b", +293 => x"0b0b80e5", +294 => x"e40c82a0", +295 => x"800b80e5", +296 => x"e80c8290", +297 => x"800b80e5", +298 => x"ec0c04f8", +299 => x"808080a4", +300 => x"0b0b0b80", +301 => x"e5e40cf8", +302 => x"80808280", +303 => x"0b80e5e8", +304 => x"0cf88080", +305 => x"84800b80", +306 => x"e5ec0c04", +307 => x"80c0a880", +308 => x"8c0b0b0b", +309 => x"80e5e40c", +310 => x"80c0a880", +311 => x"940b80e5", +312 => x"e80c0b0b", +313 => x"80c7d00b", +314 => x"80e5ec0c", +315 => x"04f23d0d", +316 => x"6080e5e8", +317 => x"08565d82", +318 => x"750c8059", +319 => x"805a800b", +320 => x"8f3d5d5b", +321 => x"7a101015", +322 => x"70087108", +323 => x"719f2c7e", +324 => x"852b5855", +325 => x"557d5359", +326 => x"5799993f", +327 => x"7d7f7a72", +328 => x"077c7207", +329 => x"71716081", +330 => x"05415f5d", +331 => x"5b595755", +332 => x"817b278f", +333 => x"38767d0c", +334 => x"77841e0c", +335 => x"7c800c90", +336 => x"3d0d0480", +337 => x"e5e80855", +338 => x"ffba3970", +339 => x"7080e5f0", +340 => x"335170a7", +341 => x"3880d5fc", +342 => x"08700852", +343 => x"5270802e", +344 => x"94388412", +345 => x"80d5fc0c", +346 => x"702d80d5", +347 => x"fc087008", +348 => x"525270ee", +349 => x"38810b80", +350 => x"e5f03450", +351 => x"50040470", +352 => x"0b0b80e5", +353 => x"e008802e", +354 => x"8e380b0b", +355 => x"0b0b800b", +356 => x"802e0981", +357 => x"06833850", +358 => x"040b0b80", +359 => x"e5e0510b", +360 => x"0b0bf4dc", +361 => x"3f500404", +362 => x"ff3d0d02", +363 => x"8f053352", +364 => x"718a2e8a", +365 => x"387151fd", +366 => x"a63f833d", +367 => x"0d048d51", +368 => x"fd9d3f71", +369 => x"51fd983f", +370 => x"833d0d04", +371 => x"ce3d0db5", +372 => x"3d707084", +373 => x"0552088b", +374 => x"a85c56a5", +375 => x"3d5e5c80", +376 => x"75708105", +377 => x"5733765b", +378 => x"55587378", +379 => x"2e80c138", +380 => x"8e3d5b73", +381 => x"a52e0981", +382 => x"0680c538", +383 => x"78708105", +384 => x"5a335473", +385 => x"80e42e81", +386 => x"b6387380", +387 => x"e42480c6", +388 => x"387380e3", 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zpu/zpu4/test/interrupt/int.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zpu/zpu4/test/interrupt/int.elf =================================================================== --- zpu/zpu4/test/interrupt/int.elf (nonexistent) +++ zpu/zpu4/test/interrupt/int.elf (revision 93)
zpu/zpu4/test/interrupt/int.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/interrupt/int.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zpu/zpu4/test/interrupt/int.bin =================================================================== --- zpu/zpu4/test/interrupt/int.bin (nonexistent) +++ zpu/zpu4/test/interrupt/int.bin (revision 93)
zpu/zpu4/test/interrupt/int.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zpu/zpu4/test/interrupt/build.sh =================================================================== --- zpu/zpu4/test/interrupt/build.sh (nonexistent) +++ zpu/zpu4/test/interrupt/build.sh (revision 93) @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/int.c -o int.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >int.dis int.elf +zpu-elf-objcopy -O binary int.elf int.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam int.bin >int.ram Index: zpu/zpu4/test/interrupt/int.ram =================================================================== --- zpu/zpu4/test/interrupt/int.ram (nonexistent) +++ zpu/zpu4/test/interrupt/int.ram (revision 93) @@ -0,0 +1,3057 @@ +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e00400", +5 => x"00000000", +6 => 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x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", Index: zpu/zpu4/test/interrupt/int.c =================================================================== --- zpu/zpu4/test/interrupt/int.c (nonexistent) +++ zpu/zpu4/test/interrupt/int.c (revision 93) @@ -0,0 +1,40 @@ +/* + * Shows usage of interrupts. Goes along with zpu_core_small_wip.vhd. + */ +#include + + +volatile int counter; + +/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is + * held high for enough cycles to guarantee that it will be noticed, i.e. longer than + * any io access + 4 cycles roughly. + * + * Any non-trivial interrupt controller would have support for + * acknowledging interrupts(i.e. keep interrupts asserted until + * software acknowledges them via memory mapped IO). + */ +void _zpu_interrupt(void) +{ + /* interrupts are enabled so we need to finish up quickly, + * lest we will get infinite recursion!*/ + counter++; +} + +int main(int argc, char **argv) +{ + int t; + t=counter; + for (;;) + { + if (t==counter) + { + puts("No interrupt\n"); + } else + { + puts("Got interrupt\n"); + t=counter; + } + } + +} Index: zpu/zpu4/src/timer.vhd =================================================================== --- zpu/zpu4/src/timer.vhd (nonexistent) +++ zpu/zpu4/src/timer.vhd (revision 93) @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : unsigned(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + Index: zpu/zpu4/src/zpuio.vhd =================================================================== --- zpu/zpu4/src/zpuio.vhd (nonexistent) +++ zpu/zpu4/src/zpuio.vhd (revision 93) @@ -0,0 +1,232 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + +signal dram_read : std_logic; + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + +ram_imp: dram port map ( + clk => cpu_clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"2028003" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else +-- report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"2028003" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else +-- report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + if mem_addr(ioBit)='0' and mem_readEnable='1' then + dram_read <= '1'; + end if; + if dram_read='1' and dram_mem_busy='0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; Index: zpu/zpu4/src/io.vhd =================================================================== --- zpu/zpu4/src/io.vhd (nonexistent) +++ zpu/zpu4/src/io.vhd (revision 93) @@ -0,0 +1,112 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +signal serving : std_logic; + +file l_file : TEXT open write_mode is log_file; +constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); +constant tx_full: std_logic := '0'; +constant rx_empty: std_logic := '1'; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write(7 downto 0), + adr => addr(4 downto 2), + dout => timer_read); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); + begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + + if (areset = '1') then +-- timer_we <= '0'; + elsif (clk'event and clk = '1') then +-- timer_we <= '0'; + if writeEnable = '1' then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Write to UART[0]" & " :0x" & hstr(write); + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(to_integer(unsigned(write)))); + elsif addr(12)='1' then + report "Write to TIMER" & " :0x" & hstr(write); +-- report "xxx" severity failure; +-- timer_we <= '1'; + else + print(l_file, character'val(to_integer(unsigned(write)))); + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; + end if; + + end if; + read <= (others => '0'); + if (readEnable = '1') then + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Read UART[0]"; + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty + elsif ("1" & addr & lowAddrBits)=x"80a0010" then + report "Read UART[1]"; + read(8) <= not rx_empty; -- receiver not empty + read(7 downto 0) <= (others => '0'); + elsif addr(12)='1' then + report "Read TIMER"; + read(7 downto 0) <= timer_read; + elsif addr(11)='1' then + report "Read ZPU Freq"; + read(7 downto 0) <= ZPU_Frequency; + else + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; + end if; + end if; + end if; + end process; + + +end behave; + Index: zpu/zpu4/src/txt_util.vhd =================================================================== --- zpu/zpu4/src/txt_util.vhd (nonexistent) +++ zpu/zpu4/src/txt_util.vhd (revision 93) @@ -0,0 +1,621 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: zpu/zpu4/src/.cvsignore =================================================================== --- zpu/zpu4/src/.cvsignore (nonexistent) +++ zpu/zpu4/src/.cvsignore (revision 93) @@ -0,0 +1,5 @@ +work +vsim.wlf +xilinx_device_details.xml +tcl_stacktrace.txt +vish_stacktrace.vstf Index: zpu/zpu4/src/clocks.vhd =================================================================== --- zpu/zpu4/src/clocks.vhd (nonexistent) +++ zpu/zpu4/src/clocks.vhd (revision 93) @@ -0,0 +1,246 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); +end clocks; + +architecture behave of clocks is + +signal low : std_logic; + +signal cpu_clk_in : std_logic; +signal sdr_clk_fb_in : std_logic; + +signal dcm_cpu1 : std_logic; +signal dcm_cpu2 : std_logic; +signal dcm_cpu2_dum : std_logic; +signal dcm_cpu4 : std_logic; +signal dcm_ddr2 : std_logic; +signal dcm_ddr2_2x : std_logic; + +signal cpu_clk_int : std_logic; +signal cpu_clk_2x_int : std_logic; +signal cpu_clk_2x_dum_int : std_logic; +signal cpu_clk_4x_int : std_logic; +signal ddr_in_clk_int : std_logic; +signal ddr_in_clk_2x_int : std_logic; + +signal dcm1_locked_del : std_logic; +signal dcm2_locked_del : std_logic; +signal dcm2_reset : std_logic; +signal dcm3_reset : std_logic; + +signal locked_int : std_logic_vector(2 downto 0); +signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + CPU_IBUFG: + IBUFG port map ( + O => cpu_clk_in, + I => cpu_clk_p); + + SDR_FB_IBUFG: + IBUFG port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p); + + dcm2_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0)); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1)); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 15.625, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu2, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(0), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_int, -- DCM clock feedback + CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => areset); -- DCM asynchronous reset input + + cpu2_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu4, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(1), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback + CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm2_reset); -- DCM asynchronous reset input + + ddr_read_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE +-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 +-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(2), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => ddr_in_clk_int, -- DCM clock feedback + CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm3_reset); -- DCM asynchronous reset input + + cpu1: + BUFG port map ( + I => dcm_cpu1, + O => cpu_clk_int); + + cpu2: + BUFG port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int); + + cpu2_dum: + BUFG port map ( + I => dcm_cpu2_dum, + O => cpu_clk_2x_dum_int); + + cpu4: + BUFG port map ( + I => dcm_cpu4, + O => cpu_clk_4x_int); + + ddr_clk: + BUFG port map ( + I => dcm_ddr2, + O => ddr_in_clk_int); + + ddr_clk_2x: + BUFG port map ( + I => dcm_ddr2_2x, + O => ddr_in_clk_2x_int); + +end behave; \ No newline at end of file Index: zpu/zpu4/src/trace.vhd =================================================================== --- zpu/zpu4/src/trace.vhd (nonexistent) +++ zpu/zpu4/src/trace.vhd (revision 93) @@ -0,0 +1,117 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : unsigned(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + Index: zpu/zpu4/core/zpupkg.vhd =================================================================== --- zpu/zpu4/core/zpupkg.vhd (nonexistent) +++ zpu/zpu4/core/zpupkg.vhd (revision 93) @@ -0,0 +1,204 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; Index: zpu/zpu4/core/zpu_config.vhd =================================================================== --- zpu/zpu4/core/zpu_config.vhd (nonexistent) +++ zpu/zpu4/core/zpu_config.vhd (revision 93) @@ -0,0 +1,57 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitBRAM : integer := 14; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); +end zpu_config; Index: zpu/zpu4/core/zpu_core.vhd =================================================================== --- zpu/zpu4/core/zpu_core.vhd (nonexistent) +++ zpu/zpu4/core/zpu_core.vhd (revision 93) @@ -0,0 +1,957 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle, +State_Interrupt +); + + +signal pc : unsigned(maxAddrBitIncIO downto 0); +signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal stackA : unsigned(wordSize-1 downto 0); +signal binaryOpResult : unsigned(wordSize-1 downto 0); +signal binaryOpResult2 : unsigned(wordSize-1 downto 0); +signal multResult2 : unsigned(wordSize-1 downto 0); +signal multResult3 : unsigned(wordSize-1 downto 0); +signal multResult : unsigned(wordSize-1 downto 0); +signal multA : unsigned(wordSize-1 downto 0); +signal multB : unsigned(wordSize-1 downto 0); +signal stackB : unsigned(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal inInterrupt: std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + inInterrupt <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + if (interrupt='0') then + -- Interrupt ended, we can serve ISR again + inInterrupt <= '0'; + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBitIncIO+1); + state <= State_Interrupt; + end if; + end if; + when State_Interrupt => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; Index: zpu/zpu4/core/histogram.perl =================================================================== --- zpu/zpu4/core/histogram.perl (nonexistent) +++ zpu/zpu4/core/histogram.perl (revision 93) @@ -0,0 +1,218 @@ +#!/usr/bin/perl +############################################################################## +# +# Copyright (c) 2008 Salvador E. Tropea +# Copyright (c) 2008 Instituto Nacional de Tecnología Industrial +# +############################################################################## +# +# Target: Any +# Language: Perl +# Interpreter used: v5.6.1/v5.8.4 +# Text editor: SETEdit 0.5.5 +# +############################################################################## +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA +# +############################################################################## +# +# Description: Takes a ZPU trace and does some raw stats about opcodes +# frequency and speed. +# +############################################################################## +# +# TODO +# +# A lot ... +# + + +# 0x40-0x460 +# div y mod son especiales +@used=(); +@clks=(); + +$line=1; +$startLine=1; +#$endLine=10000; +$endLine=-1; +$lastClk=0; +$lastOpcode=-1; +while (<>) + { + if ($_=~/^(\S+) (\S+) (\S+) (\S+) (\S+) (\S+) (\S+)/) + { + $clk=hex($7); + #print "$line\n"; + if ($line>=$startLine) + { + #print $_; + $addr=hex($1); + $opcode=hex($2); + $sp=hex($3); + $a=hex($4); + $b=hex($5); + if ($addr>=0x40 and $addr<0x460) + { + @used[$opcode+0x100]++; + @clks[$lastOpcodeEmu]+=$clk-$lastClkEmu unless lastOpcodeEmu==-1; + $lastOpcodeEmu=$opcode+0x100; + $lastClkEmu=$clk; + } + else + { + @used[$opcode]++; + @clks[$lastOpcode]+=$clk-$lastClk unless $lastOpcode==-1; + #printf "%d+=%d\n",$lastOpcode,$clk-$lastClk; + $lastOpcode=$opcode; + $lastClk=$clk; + $lastOpcodeEmu=-1; + $lastClkEmu=$clk; + } + } + else + { + $lastClk=$clk; + } + last if $line==$endLine; + $line++; + } + } +@used[$lastOpcode]--; + +$id=0; +# Cluster them +AddSimple('breakpoint',0); +# 1=shiftleft, invalid +AddSimple('pushsp',2); +# 3=pushint, invalid +AddSimple('poppc',4); +AddSimple('add',5); +AddSimple('and',6); +AddSimple('or',7); +AddSimple('load',8); +AddSimple('not',9); +AddSimple('flip',10); +AddSimple('nop',11); +AddSimple('store',12); +AddSimple('popsp',13); +# 14=compare, invalid +# 15=popint, invalid +AddSimpleRange('addsp',16,31); +# 32-63 emulate +AddSimpleRange('storesp',64,95); +AddSimpleRange('loadsp',96,127); +AddSimpleRange('im',128,255); + +# 32 is the reset entry point +# 33 is the interrupt entry point +AddEmulate('loadh',34); +AddEmulate('storeh',35); +AddEmulate('lessthan',36); +AddEmulate('lessthanorequal',37); +AddEmulate('ulessthan',38); +AddEmulate('ulessthanorequal',39); +AddEmulate('swap',40); # unimplemented +AddEmulate('mult',41); +AddEmulate('lshiftright',42); +AddEmulate('ashiftleft',43); +AddEmulate('ashiftright',44); +AddEmulate('call',45); +AddEmulate('eq',46); +AddEmulate('neq',47); +AddEmulate('neg',48); +AddEmulate('sub',49); +AddEmulate('xor',50); +AddEmulate('loadb',51); +AddEmulate('storeb',52); +AddEmulate('div',53); +AddEmulate('mod',54); +AddEmulate('eqbranch',55); +AddEmulate('neqbranch',56); +AddEmulate('poppcrel',57); +AddEmulate('config',58); +AddEmulate('pushpc',59); +AddEmulate('syscall_emulate',60); # unimplemented +AddEmulate('pushspadd',61); +AddEmulate('halfmult',62); # unimplemented +AddEmulate('callpcrel',63); + +$maxID=$id; +print "Total clocks: $lastClk\n"; +print "Unsorted:\n\n"; +for ($i=0; $i<$maxID; $i++) + { + $used=@used_noemu[$i]; + $clkm=0; + $clkm=@clks_noemu[$i]/$used if $used; + printf "%-20s %8d %6.2f\n",$names[$i],$used,$clkm; + $by_times{$i}=$used; + $by_clks{$i}=@clks_noemu[$i]; + } +print "Sorted by consumed clocks:\n\n"; +foreach $key (sort { $by_clks{$b} <=> $by_clks{$a} } keys %by_clks) + { + printf "%5.2f %-20s %8d\n",$by_clks{$key}/$lastClk*100,$names[$key],$by_clks{$key}; + } + + +sub AddSimple +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]+@used[$opcode+0x100]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]+@clks[$opcode+0x100]; + $id++; +} + +sub AddEmulate +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]; + $id++; +} + +sub AddSimpleRange +{ + my ($name, $opStart, $opLast)=@_; + my $i; + + $names[$id]=$name; + for ($i=$opStart; $i<=$opLast; $i++) + { + @used_noemu[$id]+=@used[$i]; + @used_emu[$id]+=@used[$i+0x100]; + @used_both[$id]+=@used[$i]+@used[$i+0x100]; + @clks_noemu[$id]+=@clks[$i]; + @clks_emu[$id]+=@clks[$i+0x100]; + @clks_both[$id]+=@clks[$i]+@clks[$i+0x100]; + } + $id++; +} + + Index: zpu/zpu4/core/zpu_core_small.vhd =================================================================== --- zpu/zpu4/core/zpu_core_small.vhd (nonexistent) +++ zpu/zpu4/core/zpu_core_small.vhd (revision 93) @@ -0,0 +1,572 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + -- asynchronous reset signal + areset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt : in std_logic; + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +-- this signal is set upon executing an IM instruction +-- the subsequence IM instruction will then behave differently. +-- all other instructions will clear the idim_flag. +-- this yields highly compact immediate instructions. +signal idim_flag : std_logic; + +signal busy : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync, +State_Interrupt + +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP, +Decoded_Interrupt +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +subtype index is integer range 0 to 3; + +signal tOpcode_sel : index; + + +signal inInterrupt : std_logic; + + + +begin + + -- generate a trace file. + -- + -- This is only used in simulation to see what instructions are + -- executed. + -- + -- a quick & dirty regression test is then to commit trace files + -- to CVS and compare the latest trace file against the last known + -- good trace file + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + + -- mem_writeMask is not used in this design, tie it to 1 + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + + + -- dualport_ram must be defined by the application. + -- + -- How this can be implemented is highly dependent on the FPGA + -- and synthesis technology used. + -- + -- sometimes it can be instantiated as in the + -- zpu/example/helloworld.vhd, using inference, + -- but oftentimes it must be instantiated directly + -- portmapping to part specific FPGA resources + -- + -- + -- DANGER!!!!!! If inference fails, then synthesis will try + -- to implement the memory using basic logic resources. This + -- will almost certainly cause the compiler to get "stuck" + -- since synthesising such a huge number of basic logic resources + -- will take more or less forever. + -- + -- So: if your compiler gets "stuck" then inference is not + -- the way to go. + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + -- move out calculation of the opcode to a seperate process + -- to make things a bit easier to read + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; Index: zpu/.project =================================================================== --- zpu/.project (nonexistent) +++ zpu/.project (revision 93) @@ -0,0 +1,11 @@ + + + oczpu + + + + + + + + Index: zpu/COPYING =================================================================== --- zpu/COPYING (nonexistent) +++ zpu/COPYING (revision 93) @@ -0,0 +1,16 @@ +About ZPU licensing: + +The license for HDL implementations is FreeBSD to be +friendly towards commercial projects and other open source +projects, however the architecture, documentation and tools will be GPL. + +This means that all updates to the architecture must be shared, but actual +implementations(which are small and can be very project speific) can +be friendly towards commercial considerations. + +Patches to update files w/correct licensing info will be most appreciated! + +The ZPU and all the files are per 1/1-2008 Copyright Zylin AS, i.e. +Zylin is free to decide upon the BSD license for HDL implementation +and GPL for architecture, tools and documentation. + \ No newline at end of file Index: zpu/example/log.txt =================================================================== --- zpu/example/log.txt (nonexistent) +++ zpu/example/log.txt (revision 93) @@ -0,0 +1,55 @@ +N +o + +i +n +t +e +r +r +u +p +t + + + + + + +G +o +t + +i +n +t +e +r +r +u +p +t + + + + + + +N +o + +i +n +t +e +r +r +u +p +t + + + + + + Index: zpu/example/sim_small_fpga_top.vhd =================================================================== --- zpu/example/sim_small_fpga_top.vhd (nonexistent) +++ zpu/example/sim_small_fpga_top.vhd (revision 93) @@ -0,0 +1,207 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project.-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic := '1'; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; +signal interruptcounter : unsigned(15 downto 0); +signal interrupt : std_logic; + + + +signal break : std_logic; + +begin + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => interrupt, + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + + interruptcounter <= to_unsigned(0, 16); + interrupt <= '0'; + + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + -- keep interrupt signal high for 16 cycles + interruptcounter <= interruptcounter + 1; + if (interruptcounter < 16) then + report "Interrupt asserted!" severity note; + interrupt <='1'; + else + interrupt <='0'; + end if; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end PROCESS clock; + + +end behave; Index: zpu/example/simzpu_small.do =================================================================== --- zpu/example/simzpu_small.do (nonexistent) +++ zpu/example/simzpu_small.do (revision 93) @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_small.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_small_fpga_top_noint.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd +vcom -93 -explicit helloworld.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms Index: zpu/example/zpu_config.vhd =================================================================== --- zpu/example/zpu_config.vhd (nonexistent) +++ zpu/example/zpu_config.vhd (revision 93) @@ -0,0 +1,56 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +package zpu_config is + -- generate trace output + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitBRAM : integer := 16; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); +end zpu_config; Index: zpu/example/simzpu_dmips.do =================================================================== --- zpu/example/simzpu_dmips.do (nonexistent) +++ zpu/example/simzpu_dmips.do (revision 93) @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_dmips.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_small_fpga_top_noint.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms Index: zpu/example/simzpu_interrupt.do =================================================================== --- zpu/example/simzpu_interrupt.do (nonexistent) +++ zpu/example/simzpu_interrupt.do (revision 93) @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_interrupt.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_small_fpga_top.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd +vcom -93 -explicit interrupt.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms Index: zpu/example/sim_small_fpga_top_noint.vhd =================================================================== --- zpu/example/sim_small_fpga_top_noint.vhd (nonexistent) +++ zpu/example/sim_small_fpga_top_noint.vhd (revision 93) @@ -0,0 +1,193 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic := '1'; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + + +signal break : std_logic; + +begin + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end PROCESS clock; + + +end behave; Index: zpu/example/helloworld.vhd =================================================================== --- zpu/example/helloworld.vhd (nonexistent) +++ zpu/example/helloworld.vhd (revision 93) @@ -0,0 +1,3154 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfd80c", +3 => x"3a0b0b80", +4 => x"c6d00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7972d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"c4738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"9f2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"e32d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfd40c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6d93f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc0", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c0085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"d408802e", +299 => x"a43880cf", +300 => x"d808822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc00c", +304 => x"82a0800b", +305 => x"80dfc40c", +306 => x"8290800b", +307 => x"80dfc80c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc0", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfc40cf8", +314 => x"80808480", +315 => x"0b80dfc8", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c00c80c0", +320 => x"a880940b", +321 => x"80dfc40c", +322 => x"0b0b80cf", +323 => x"8c0b80df", +324 => x"c80c0470", +325 => x"7080dfcc", +326 => x"335170a7", +327 => x"3880cfe0", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe00c", +332 => x"702d80cf", +333 => x"e0087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfcc3450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"bc08802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfbc510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"fe3d0d89", +349 => x"5380cf90", +350 => x"5182c13f", +351 => x"80cfa051", +352 => x"82ba3f81", +353 => x"0a0b80df", +354 => x"d80cff0b", +355 => x"80dfdc0c", +356 => x"ff135372", +357 => x"8025de38", +358 => x"72800c84", +359 => x"3d0d04fb", +360 => x"3d0d7779", +361 => x"55558056", +362 => x"757524ab", +363 => x"38807424", +364 => x"9d388053", +365 => x"73527451", +366 => x"80e13f80", +367 => x"08547580", +368 => x"2e853880", +369 => x"08305473", +370 => x"800c873d", +371 => x"0d047330", +372 => x"76813257", +373 => x"54dc3974", +374 => x"30558156", +375 => x"738025d2", +376 => x"38ec39fa", +377 => x"3d0d787a", +378 => x"57558057", +379 => x"767524a4", +380 => x"38759f2c", +381 => x"54815375", +382 => x"74327431", +383 => x"5274519b", +384 => x"3f800854", +385 => x"76802e85", +386 => x"38800830", +387 => x"5473800c", +388 => x"883d0d04", +389 => x"74305581", +390 => x"57d739fc", +391 => x"3d0d7678", +392 => x"53548153", +393 => x"80747326", +394 => x"52557280", +395 => x"2e983870", +396 => x"802eab38", +397 => x"807224a6", +398 => x"38711073", +399 => x"10757226", +400 => x"53545272", +401 => x"ea387351", +402 => x"78833874", +403 => x"5170800c", +404 => x"863d0d04", +405 => x"720a100a", +406 => x"720a100a", +407 => x"53537280", +408 => x"2ee43871", +409 => x"7426ed38", +410 => x"73723175", +411 => x"7407740a", +412 => x"100a740a", +413 => x"100a5555", +414 => x"5654e339", +415 => x"f73d0d7c", +416 => x"70525380", +417 => x"f93f7254", +418 => x"80085580", +419 => x"cfb05681", +420 => x"57800881", +421 => x"055a8b3d", +422 => x"e4115953", +423 => x"8259f413", +424 => x"527b8811", +425 => x"08525381", +426 => x"b23f8008", +427 => x"30708008", +428 => x"079f2c8a", +429 => x"07800c53", +430 => x"8b3d0d04", +431 => x"f63d0d7c", +432 => x"80cfe408", +433 => x"71535553", +434 => x"b53f7255", +435 => x"80085680", +436 => x"cfb05781", +437 => x"58800881", +438 => x"055b8c3d", +439 => x"e4115a53", +440 => x"825af413", +441 => x"52881408", +442 => x"5180f03f", +443 => x"80083070", +444 => x"8008079f", +445 => x"2c8a0780", +446 => x"0c548c3d", +447 => x"0d047070", +448 => x"70707570", +449 => x"71830653", +450 => x"555270b4", +451 => x"38717008", +452 => x"7009f7fb", +453 => x"fdff1206", +454 => x"f8848281", +455 => x"80065452", +456 => x"53719b38", +457 => x"84137008", +458 => x"7009f7fb", +459 => x"fdff1206", +460 => x"f8848281", +461 => x"80065452", +462 => x"5371802e", +463 => x"e7387252", +464 => x"71335372", +465 => x"802e8a38", +466 => x"81127033", +467 => x"545272f8", +468 => x"38717431", +469 => x"800c5050", +470 => x"505004f2", +471 => x"3d0d6062", +472 => x"88110870", +473 => x"58565f5a", +474 => x"73802e81", +475 => x"8c388c1a", +476 => x"2270832a", +477 => x"81328106", +478 => x"56587486", +479 => x"38901a08", +480 => x"91387951", +481 => x"90b73fff", +482 => x"55800880", +483 => x"ec388c1a", +484 => x"22587d08", +485 => x"55807883", +486 => x"ffff0670", +487 => x"0a100a81", +488 => x"06415c57", +489 => x"7e772e80", +490 => x"d7387690", +491 => x"38740884", +492 => x"16088817", +493 => x"57585676", +494 => x"802ef238", +495 => x"76548880", +496 => x"77278438", +497 => x"88805473", +498 => x"5375529c", +499 => x"1a0851a4", +500 => x"1a085877", +501 => x"2d800b80", +502 => x"082582e0", +503 => x"38800816", +504 => x"77800831", +505 => x"7f880508", +506 => x"80083170", +507 => x"6188050c", +508 => x"5b585678", +509 => x"ffb43880", +510 => x"5574800c", +511 => x"903d0d04", +512 => x"7a813281", +513 => x"06774056", +514 => x"75802e81", +515 => x"bd387690", +516 => x"38740884", +517 => x"16088817", +518 => x"57585976", +519 => x"802ef238", +520 => x"881a0878", +521 => x"83ffff06", +522 => x"70892a81", +523 => x"06565956", +524 => x"73802e82", +525 => x"f8387577", +526 => x"278b3877", +527 => x"872a8106", +528 => x"5c7b82b5", +529 => x"38767627", +530 => x"83387656", +531 => x"75537852", +532 => x"79085185", +533 => x"833f881a", +534 => x"08763188", +535 => x"1b0c7908", +536 => x"167a0c76", +537 => x"56751977", +538 => x"77317f88", +539 => x"05087831", +540 => x"70618805", +541 => x"0c415859", +542 => x"7e802efe", +543 => x"fa388c1a", +544 => x"2258ff8a", +545 => x"39787954", +546 => x"7c537b52", +547 => x"5684c93f", +548 => x"881a0879", +549 => x"31881b0c", +550 => x"7908197a", +551 => x"0c7c7631", +552 => x"5d7c8e38", +553 => x"79518ff2", +554 => x"3f800881", +555 => x"8f388008", +556 => x"5f751c77", +557 => x"77317f88", +558 => x"05087831", +559 => x"70618805", +560 => x"0c5d585c", +561 => x"7a802efe", +562 => x"ae387681", +563 => x"83387408", +564 => x"84160888", +565 => x"1757585c", +566 => x"76802ef2", +567 => x"3876538a", +568 => x"527b5182", +569 => x"d33f8008", +570 => x"7c318105", +571 => x"5d800884", +572 => x"3881175d", +573 => x"815f7c59", +574 => x"767d2783", +575 => x"38765994", +576 => x"1a08881b", +577 => x"08115758", +578 => x"807a085c", +579 => x"54901a08", +580 => x"7b278338", +581 => x"81547579", +582 => x"25843873", +583 => x"ba387779", +584 => x"24fee238", +585 => x"77537b52", +586 => x"9c1a0851", +587 => x"a41a0859", +588 => x"782d8008", +589 => x"56800880", +590 => x"24fee238", +591 => x"8c1a2280", +592 => x"c0075e7d", +593 => x"8c1b23ff", +594 => x"5574800c", +595 => x"903d0d04", +596 => x"7effa338", +597 => x"ff873975", +598 => x"537b527a", +599 => x"5182f93f", +600 => x"7908167a", +601 => x"0c79518e", +602 => x"b13f8008", +603 => x"cf387c76", +604 => x"315d7cfe", +605 => x"bc38feac", +606 => x"39901a08", +607 => x"7a087131", +608 => x"78117056", +609 => x"5a575280", +610 => x"cfe40851", +611 => x"84943f80", +612 => x"08802eff", +613 => x"a7388008", +614 => x"901b0c80", +615 => x"08167a0c", +616 => x"77941b0c", +617 => x"76881b0c", +618 => x"7656fd99", +619 => x"39790858", +620 => x"901a0878", +621 => x"27833881", +622 => x"54757727", +623 => x"843873b3", +624 => x"38941a08", +625 => x"54737726", +626 => x"80d33873", +627 => x"5378529c", +628 => x"1a0851a4", +629 => x"1a085877", +630 => x"2d800856", +631 => x"80088024", +632 => x"fd83388c", +633 => x"1a2280c0", +634 => x"075e7d8c", +635 => x"1b23ff55", +636 => x"fed73975", +637 => x"53785277", +638 => x"5181dd3f", +639 => x"7908167a", +640 => x"0c79518d", +641 => x"953f8008", +642 => x"802efcd9", +643 => x"388c1a22", +644 => x"80c0075e", +645 => x"7d8c1b23", +646 => x"ff55fead", +647 => x"39767754", +648 => x"79537852", +649 => x"5681b13f", +650 => x"881a0877", +651 => x"31881b0c", +652 => x"7908177a", +653 => x"0cfcae39", +654 => x"fa3d0d7a", +655 => x"79028805", +656 => x"a7053355", +657 => x"53548374", +658 => x"2780df38", +659 => x"71830651", +660 => x"7080d738", +661 => x"71715755", +662 => x"83517582", +663 => x"802913ff", +664 => x"12525670", +665 => x"8025f338", +666 => x"837427bc", +667 => x"38740876", +668 => x"327009f7", +669 => x"fbfdff12", +670 => x"06f88482", +671 => x"81800651", +672 => x"5170802e", +673 => x"98387451", +674 => x"80527033", +675 => x"5772772e", +676 => x"b9388111", +677 => x"81135351", +678 => x"837227ee", +679 => x"38fc1484", +680 => x"16565473", +681 => x"8326c638", +682 => x"7452ff14", +683 => x"5170ff2e", +684 => x"97387133", +685 => x"5472742e", +686 => x"98388112", +687 => x"ff125252", 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x"00000000", +2730 => x"00000000", +2731 => x"00000000", +2732 => x"00000000", +2733 => x"00000000", +2734 => x"00000000", +2735 => x"00000000", +2736 => x"00000000", +2737 => x"00000000", +2738 => x"00000000", +2739 => x"00000000", +2740 => x"00000000", +2741 => x"00000000", +2742 => x"00000000", +2743 => x"00000000", +2744 => x"00000000", +2745 => x"00000000", +2746 => x"00000000", +2747 => x"00000000", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"00000000", +2752 => x"00000000", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"00000000", +2767 => x"00000000", +2768 => x"00000000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00000000", +2772 => x"00000000", +2773 => x"00000000", +2774 => x"00000000", +2775 => x"00000000", +2776 => x"00000000", +2777 => x"00000000", +2778 => x"00000000", +2779 => x"00000000", +2780 => x"00000000", +2781 => x"00000000", +2782 => x"00000000", +2783 => x"00000000", +2784 => x"00000000", +2785 => x"00000000", +2786 => x"00000000", +2787 => x"00000000", +2788 => x"00000000", +2789 => x"ffffffff", +2790 => x"00000000", +2791 => x"00020000", +2792 => x"00000000", +2793 => x"00000000", +2794 => x"00002ba0", +2795 => x"00002ba0", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; Index: zpu/example/interrupt.vhd =================================================================== --- zpu/example/interrupt.vhd (nonexistent) +++ zpu/example/interrupt.vhd (revision 93) @@ -0,0 +1,3156 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0b8af02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"ab2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"ef2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfdc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", 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x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; Index: zpu/example/.cvsignore =================================================================== --- zpu/example/.cvsignore (nonexistent) +++ zpu/example/.cvsignore (revision 93) @@ -0,0 +1,3 @@ +work +vsim.wlf +install Index: zpu/example/bram_dmips.vhd =================================================================== --- zpu/example/bram_dmips.vhd (nonexistent) +++ zpu/example/bram_dmips.vhd (revision 93) @@ -0,0 +1,3356 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80d5f40c", + 3 => x"3a0b0b80", + 4 => x"c4fb0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5c22d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c3040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a6", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80d5", + 162 => x"e0738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88a90400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0bad", + 171 => x"aa2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b0bad", + 179 => x"ee2d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80d5f00c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"82fd3fbf", + 257 => x"a03f0410", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10105351", + 266 => x"047381ff", + 267 => x"06738306", + 268 => x"09810583", + 269 => x"05101010", + 270 => x"2b0772fc", + 271 => x"060c5151", + 272 => x"043c0472", + 273 => x"72807281", + 274 => x"06ff0509", + 275 => x"72060571", + 276 => x"1052720a", + 277 => x"100a5372", + 278 => x"ed385151", + 279 => x"535104ff", + 280 => x"3d0d0b0b", + 281 => x"80e5e408", + 282 => x"52710870", + 283 => x"882a8132", + 284 => x"70810651", + 285 => x"515170f1", + 286 => x"3873720c", + 287 => x"833d0d04", + 288 => x"80d5f008", + 289 => x"802ea438", + 290 => x"80d5f408", + 291 => x"822ebd38", + 292 => x"8380800b", + 293 => x"0b0b80e5", + 294 => x"e40c82a0", + 295 => x"800b80e5", + 296 => x"e80c8290", + 297 => x"800b80e5", + 298 => x"ec0c04f8", + 299 => x"808080a4", + 300 => x"0b0b0b80", + 301 => x"e5e40cf8", + 302 => x"80808280", + 303 => x"0b80e5e8", + 304 => x"0cf88080", + 305 => x"84800b80", + 306 => x"e5ec0c04", + 307 => x"80c0a880", + 308 => x"8c0b0b0b", + 309 => x"80e5e40c", + 310 => x"80c0a880", + 311 => x"940b80e5", + 312 => x"e80c0b0b", + 313 => x"80c7d00b", + 314 => x"80e5ec0c", + 315 => x"04f23d0d", + 316 => x"6080e5e8", + 317 => x"08565d82", + 318 => x"750c8059", + 319 => x"805a800b", + 320 => x"8f3d5d5b", + 321 => x"7a101015", + 322 => x"70087108", + 323 => x"719f2c7e", + 324 => x"852b5855", + 325 => x"557d5359", + 326 => x"5799993f", + 327 => x"7d7f7a72", + 328 => x"077c7207", + 329 => x"71716081", + 330 => x"05415f5d", + 331 => x"5b595755", + 332 => x"817b278f", + 333 => x"38767d0c", + 334 => x"77841e0c", + 335 => x"7c800c90", + 336 => x"3d0d0480", + 337 => x"e5e80855", + 338 => x"ffba3970", + 339 => x"7080e5f0", + 340 => x"335170a7", + 341 => x"3880d5fc", + 342 => x"08700852", + 343 => x"5270802e", + 344 => x"94388412", + 345 => x"80d5fc0c", + 346 => x"702d80d5", + 347 => x"fc087008", + 348 => x"525270ee", + 349 => x"38810b80", + 350 => x"e5f03450", + 351 => x"50040470", + 352 => x"0b0b80e5", + 353 => x"e008802e", + 354 => x"8e380b0b", + 355 => x"0b0b800b", + 356 => x"802e0981", + 357 => x"06833850", + 358 => x"040b0b80", + 359 => x"e5e0510b", + 360 => x"0b0bf4dc", + 361 => x"3f500404", + 362 => x"ff3d0d02", + 363 => x"8f053352", + 364 => x"718a2e8a", + 365 => x"387151fd", + 366 => x"a63f833d", + 367 => x"0d048d51", + 368 => x"fd9d3f71", + 369 => x"51fd983f", + 370 => x"833d0d04", + 371 => x"ce3d0db5", + 372 => x"3d707084", + 373 => x"0552088b", + 374 => x"a85c56a5", + 375 => x"3d5e5c80", + 376 => x"75708105", + 377 => x"5733765b", + 378 => x"55587378", + 379 => x"2e80c138", + 380 => x"8e3d5b73", + 381 => x"a52e0981", + 382 => x"0680c538", + 383 => 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x"00002eb4", + 2992 => x"00002eb4", + 2993 => x"00002ebc", + 2994 => x"00002ebc", + 2995 => x"00002ec4", + 2996 => x"00002ec4", + 2997 => x"00002ecc", + 2998 => x"00002ecc", + 2999 => x"00002ed4", + 3000 => x"00002ed4", + 3001 => x"00002edc", + 3002 => x"00002edc", + 3003 => x"00002ee4", + 3004 => x"00002ee4", + 3005 => x"00002eec", + 3006 => x"00002eec", + 3007 => x"00002ef4", + 3008 => x"00002ef4", + 3009 => x"00002efc", + 3010 => x"00002efc", + 3011 => x"00002f04", + 3012 => x"00002f04", + 3013 => x"00002f0c", + 3014 => x"00002f0c", + 3015 => x"00002f14", + 3016 => x"00002f14", + 3017 => x"00002f1c", + 3018 => x"00002f1c", + 3019 => x"00002f24", + 3020 => x"00002f24", + 3021 => x"00002f2c", + 3022 => x"00002f2c", + 3023 => x"00002f34", + 3024 => x"00002f34", + 3025 => x"00002f3c", + 3026 => x"00002f3c", + 3027 => x"00002f50", + 3028 => x"00000000", + 3029 => x"000031b8", + 3030 => x"00003214", + 3031 => x"00003270", + 3032 => x"00000000", + 3033 => x"00000000", + 3034 => x"00000000", + 3035 => x"00000000", + 3036 => x"00000000", + 3037 => x"00000000", + 3038 => x"00000000", + 3039 => x"00000000", + 3040 => x"00000000", + 3041 => x"00002ad0", + 3042 => x"00000000", + 3043 => x"00000000", + 3044 => x"00000000", + 3045 => x"00000000", + 3046 => x"00000000", + 3047 => x"00000000", + 3048 => x"00000000", + 3049 => x"00000000", + 3050 => x"00000000", + 3051 => x"00000000", + 3052 => x"00000000", + 3053 => x"00000000", + 3054 => x"00000000", + 3055 => x"00000000", + 3056 => x"00000000", + 3057 => x"00000000", + 3058 => x"00000000", + 3059 => x"00000000", + 3060 => x"00000000", + 3061 => x"00000000", + 3062 => x"00000000", + 3063 => x"00000000", + 3064 => x"00000000", + 3065 => x"00000000", + 3066 => x"00000000", + 3067 => x"00000000", + 3068 => x"00000000", + 3069 => x"00000000", + 3070 => x"00000001", + 3071 => x"330eabcd", + 3072 => x"1234e66d", + 3073 => x"deec0005", + 3074 => x"000b0000", + 3075 => x"00000000", + 3076 => x"00000000", + 3077 => x"00000000", + 3078 => x"00000000", + 3079 => x"00000000", + 3080 => x"00000000", + 3081 => x"00000000", + 3082 => x"00000000", + 3083 => x"00000000", + 3084 => x"00000000", + 3085 => x"00000000", + 3086 => x"00000000", + 3087 => x"00000000", + 3088 => x"00000000", + 3089 => x"00000000", + 3090 => x"00000000", + 3091 => x"00000000", + 3092 => x"00000000", + 3093 => x"00000000", + 3094 => x"00000000", + 3095 => x"00000000", + 3096 => x"00000000", + 3097 => x"00000000", + 3098 => x"00000000", + 3099 => x"00000000", + 3100 => x"00000000", + 3101 => x"00000000", + 3102 => x"00000000", + 3103 => x"00000000", + 3104 => x"00000000", + 3105 => x"00000000", + 3106 => x"00000000", + 3107 => x"00000000", + 3108 => x"00000000", + 3109 => x"00000000", + 3110 => x"00000000", + 3111 => x"00000000", + 3112 => x"00000000", + 3113 => x"00000000", + 3114 => x"00000000", + 3115 => x"00000000", + 3116 => x"00000000", + 3117 => x"00000000", + 3118 => x"00000000", + 3119 => x"00000000", + 3120 => x"00000000", + 3121 => x"00000000", + 3122 => x"00000000", + 3123 => x"00000000", + 3124 => x"00000000", + 3125 => x"00000000", + 3126 => x"00000000", + 3127 => x"00000000", + 3128 => x"00000000", + 3129 => x"00000000", + 3130 => x"00000000", + 3131 => x"00000000", + 3132 => x"00000000", + 3133 => x"00000000", + 3134 => x"00000000", + 3135 => x"00000000", + 3136 => x"00000000", + 3137 => x"00000000", + 3138 => x"00000000", + 3139 => x"00000000", + 3140 => x"00000000", + 3141 => x"00000000", + 3142 => x"00000000", + 3143 => x"00000000", + 3144 => x"00000000", + 3145 => x"00000000", + 3146 => x"00000000", + 3147 => x"00000000", + 3148 => x"00000000", + 3149 => x"00000000", + 3150 => x"00000000", + 3151 => x"00000000", + 3152 => x"00000000", + 3153 => x"00000000", + 3154 => x"00000000", + 3155 => x"00000000", + 3156 => x"00000000", + 3157 => x"00000000", + 3158 => x"00000000", + 3159 => x"00000000", + 3160 => x"00000000", + 3161 => x"00000000", + 3162 => x"00000000", + 3163 => x"00000000", + 3164 => x"00000000", + 3165 => x"00000000", + 3166 => x"00000000", + 3167 => x"00000000", + 3168 => x"00000000", + 3169 => x"00000000", + 3170 => x"00000000", + 3171 => x"00000000", + 3172 => x"00000000", + 3173 => x"00000000", + 3174 => x"00000000", + 3175 => x"00000000", + 3176 => x"00000000", + 3177 => x"00000000", + 3178 => x"00000000", + 3179 => x"00000000", + 3180 => x"00000000", + 3181 => x"00000000", + 3182 => x"00000000", + 3183 => x"00000000", + 3184 => x"00000000", + 3185 => x"00000000", + 3186 => x"00000000", + 3187 => x"00000000", + 3188 => x"00000000", + 3189 => x"00000000", + 3190 => x"00000000", + 3191 => x"00000000", + 3192 => x"00000000", + 3193 => x"00000000", + 3194 => x"00000000", + 3195 => x"00000000", + 3196 => x"00000000", + 3197 => x"00000000", + 3198 => x"00000000", + 3199 => x"00000000", + 3200 => x"00000000", + 3201 => x"00000000", + 3202 => x"00000000", + 3203 => x"00000000", + 3204 => x"00000000", + 3205 => x"00000000", + 3206 => x"00000000", + 3207 => x"00000000", + 3208 => x"00000000", + 3209 => x"00000000", + 3210 => x"00000000", + 3211 => x"00000000", + 3212 => x"00000000", + 3213 => x"00000000", + 3214 => x"00000000", + 3215 => x"00000000", + 3216 => x"00000000", + 3217 => x"00000000", + 3218 => x"00000000", + 3219 => x"00000000", + 3220 => x"00000000", + 3221 => x"00000000", + 3222 => x"00000000", + 3223 => x"00000000", + 3224 => x"00000000", + 3225 => x"00000000", + 3226 => x"00000000", + 3227 => x"00000000", + 3228 => x"00000000", + 3229 => x"00000000", + 3230 => x"00000000", + 3231 => x"00000000", + 3232 => x"00000000", + 3233 => x"00000000", + 3234 => x"00000000", + 3235 => x"00000000", + 3236 => x"00000000", + 3237 => x"00000000", + 3238 => x"00000000", + 3239 => x"00000000", + 3240 => x"00000000", + 3241 => x"00000000", + 3242 => x"00000000", + 3243 => x"00000000", + 3244 => x"00000000", + 3245 => x"00000000", + 3246 => x"00000000", + 3247 => x"00000000", + 3248 => x"00000000", + 3249 => x"00000000", + 3250 => x"00000000", + 3251 => x"00002ad4", + 3252 => x"ffffffff", + 3253 => x"00000000", + 3254 => x"ffffffff", + 3255 => x"00000000", + 3256 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; Index: zpu/readme.txt =================================================================== --- zpu/readme.txt (nonexistent) +++ zpu/readme.txt (revision 93) @@ -0,0 +1,11 @@ +In example folder you'll find a simple hello world example +of the ZPU that you can run in ModelSim. + +Read "example/simzpu_small.do" for more information on +how to run the simulation. + +The ZPU and it's tools are under git version control, +which opencores.org does not yet support. + +See http://opensource.zylin.com/zpu.htm for details +on how to get the full source.

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