URL
https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
Subversion Repositories zx_ula
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- from Rev 14 to Rev 15
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Rev 14 → Rev 15
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/zx_spectrum_48k.xise
0,0 → 1,394
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="tld_spartan3_sp48k_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="tld_spartan3_sp48k_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/test_ram_controller" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_ram_controller" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="6700 ns" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test_ram_controller" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|test_ram_controller" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="zx_spectrum_48k" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-24T12:50:54" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="44419C92BD2D457E847B96D98538FAD4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
<file xil_pn:name="mapa_es.inc" xil_pn:type="FILE_VERILOG"/> |
</autoManagedFiles> |
|
</project> |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/sp48k_for_spartan3_starter_kit.ucf
0,0 → 1,80
NET "clk50" LOC = "T9" | IOSTANDARD = LVCMOS33; |
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle) |
# NET "clk50" PERIOD = 20.0ns HIGH 40%; |
|
NET "reset" LOC = "L14" | IOSTANDARD = LVCMOS33; |
|
# I/O |
NET "r" LOC = "E7" | IOSTANDARD = LVCMOS33; |
NET "g" LOC = "D6" | IOSTANDARD = LVCMOS33; |
NET "b" LOC = "D5" | IOSTANDARD = LVCMOS33; |
NET "i" LOC = "D7" | IOSTANDARD = LVCMOS33; |
|
NET "csync" LOC = "D8" | IOSTANDARD = LVCMOS33; |
NET "audio_out" LOC = "D10" | IOSTANDARD = LVCMOS33; |
NET "ear" LOC = "T13" | IOSTANDARD = LVCMOS33; |
|
# Debug LED's |
NET "ledclk" LOC = "P11" | IOSTANDARD = LVCMOS33; |
NET "ledaux<3>" LOC = "P12" | IOSTANDARD = LVCMOS33; |
NET "ledaux<2>" LOC = "N12" | IOSTANDARD = LVCMOS33; |
NET "ledaux<1>" LOC = "P13" | IOSTANDARD = LVCMOS33; |
NET "ledaux<0>" LOC = "N14" | IOSTANDARD = LVCMOS33; |
|
# Keyboard connections |
NET "clkps2" LOC = "M16" | IOSTANDARD = LVTTL | PULLUP; |
#NET "clkps2" CLOCK_DEDICATED_ROUTE = FALSE; |
NET "dataps2" LOC = "M15" | IOSTANDARD = LVTTL | PULLUP; |
|
# 7-segment display connections and LED's (optional, for PS2 keyboard module) |
NET "dispanodes<0>" LOC = "D14" | IOSTANDARD = LVCMOS33; |
NET "dispanodes<1>" LOC = "G14" | IOSTANDARD = LVCMOS33; |
NET "dispanodes<2>" LOC = "F14" | IOSTANDARD = LVCMOS33; |
NET "dispanodes<3>" LOC = "E13" | IOSTANDARD = LVCMOS33; |
|
NET "dispcathodes<6>" LOC = "E14" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<5>" LOC = "G13" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<4>" LOC = "N16" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<3>" LOC = "F13" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<2>" LOC = "N15" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<1>" LOC = "P15" | IOSTANDARD = LVCMOS33; |
NET "dispcathodes<0>" LOC = "R16" | IOSTANDARD = LVCMOS33; |
|
NET "ledextended" LOC = "P14" | IOSTANDARD = LVCMOS33; |
NET "ledreleased" LOC = "K12" | IOSTANDARD = LVCMOS33; |
NET "ledshift" LOC = "L12" | IOSTANDARD = LVCMOS33; |
|
# External SRAM |
NET "sa<17>" LOC = "L3" | IOSTANDARD = LVCMOS33; |
NET "sa<16>" LOC = "K5" | IOSTANDARD = LVCMOS33; |
NET "sa<15>" LOC = "K3" | IOSTANDARD = LVCMOS33; |
NET "sa<14>" LOC = "J3" | IOSTANDARD = LVCMOS33; |
NET "sa<13>" LOC = "J4" | IOSTANDARD = LVCMOS33; |
NET "sa<12>" LOC = "H4" | IOSTANDARD = LVCMOS33; |
NET "sa<11>" LOC = "H3" | IOSTANDARD = LVCMOS33; |
NET "sa<10>" LOC = "G5" | IOSTANDARD = LVCMOS33; |
NET "sa<9>" LOC = "E4" | IOSTANDARD = LVCMOS33; |
NET "sa<8>" LOC = "E3" | IOSTANDARD = LVCMOS33; |
NET "sa<7>" LOC = "F4" | IOSTANDARD = LVCMOS33; |
NET "sa<6>" LOC = "F3" | IOSTANDARD = LVCMOS33; |
NET "sa<5>" LOC = "G4" | IOSTANDARD = LVCMOS33; |
NET "sa<4>" LOC = "L4" | IOSTANDARD = LVCMOS33; |
NET "sa<3>" LOC = "M3" | IOSTANDARD = LVCMOS33; |
NET "sa<2>" LOC = "M4" | IOSTANDARD = LVCMOS33; |
NET "sa<1>" LOC = "N3" | IOSTANDARD = LVCMOS33; |
NET "sa<0>" LOC = "L5" | IOSTANDARD = LVCMOS33; |
|
NET "sd1<7>" LOC = "B1" | IOSTANDARD = LVCMOS33; |
NET "sd1<6>" LOC = "C1" | IOSTANDARD = LVCMOS33; |
NET "sd1<5>" LOC = "C2" | IOSTANDARD = LVCMOS33; |
NET "sd1<4>" LOC = "R5" | IOSTANDARD = LVCMOS33; |
NET "sd1<3>" LOC = "T5" | IOSTANDARD = LVCMOS33; |
NET "sd1<2>" LOC = "R6" | IOSTANDARD = LVCMOS33; |
NET "sd1<1>" LOC = "T8" | IOSTANDARD = LVCMOS33; |
NET "sd1<0>" LOC = "N7" | IOSTANDARD = LVCMOS33; |
|
NET "sramce1" LOC = "P7" | IOSTANDARD = LVCMOS33; |
NET "sramub1" LOC = "T4" | IOSTANDARD = LVCMOS33; |
NET "sramlb1" LOC = "P6" | IOSTANDARD = LVCMOS33; |
NET "sramwe" LOC = "G3" | IOSTANDARD = LVCMOS33; |
NET "sramoe" LOC = "K4" | IOSTANDARD = LVCMOS33; |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ram.v
0,0 → 1,207
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Dept. Architecture and Computing Technology. University of Seville |
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es |
// |
// Create Date: 19:13:39 4-Apr-2012 |
// Design Name: ZX Spectrum |
// Module Name: ram32k |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 1.00 - File Created |
// Additional Comments: GPL License policies apply to the contents of this file. |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
/* |
This module generates a high level on "isfalling" when "a" changes from high to low. |
*/ |
module getfedge ( |
input clk, |
input a, |
output isfalling |
); |
|
reg sh = 1'b1; |
assign isfalling = sh & ~a; |
always @(posedge clk) |
sh <= a; |
endmodule |
|
|
/* |
This module implements a shared RAM controller. The Spartan 3 Starter Kit has two 256Kx16 SRAM chips. |
It uses half the size of one of these chips (8 bit data bus instead of 16). |
As the ZX Spectrum needs two independent memory banks, and bus cycles may happen to both at the same |
time, it's necessary to emulate those two banks with one chip. |
|
I tried a simple round-robin multiplexing, but didn't work as expected. This module is a bit more complicated |
as it implements a first-come-first-serve approach, with fixed priority scheme when several petitions happen |
at the same time. |
|
Each bank can be up to 64Kx8, so implementing a 128K memory scheme is very easy (I hope so) using this module |
and the external SRAM on board. |
|
This may be my first 100% synchronous implementation for a FPGA (that is, only one clock and all the ff's are |
activated at the same edge) |
|
*/ |
module ram_controller ( |
input clk, |
// Bank 1 (VRAM) |
input [15:0] a1, |
input cs1_n, |
input oe1_n, |
input we1_n, |
input [7:0] din1, |
output [7:0] dout1, |
// Bank 2 (upper RAM) |
input [15:0] a2, |
input cs2_n, |
input oe2_n, |
input we2_n, |
input [7:0] din2, |
output [7:0] dout2, |
// Outputs to actual SRAM on board |
output [17:0] sa, |
inout [7:0] sd, |
output sramce, |
output sramub, |
output sramlb, |
output sramoe, |
output sramwe |
); |
|
// Permanently enable SRAM and set it to use only LSB |
assign sramub = 1; |
assign sramlb = 0; |
assign sramce = 0; |
assign sramoe = 0; |
|
reg rsramwe = 1; |
assign sramwe = rsramwe; |
|
reg [17:0] rsa; |
reg [7:0] rsd; |
assign sa = rsa; |
assign sd = rsd; |
|
// set when there has been a high to low transition in the corresponding signal |
wire bank1read, bank1write, bank2read, bank2write; |
getfedge detectbank1read (clk, cs1_n | oe1_n, bank1read); |
getfedge detectbank2read (clk, cs2_n | oe2_n, bank2read); |
getfedge detectbank1write (clk, cs1_n | we1_n, bank1write); |
getfedge detectbank2write (clk, cs2_n | we2_n, bank2write); |
|
reg [15:0] ra1; |
reg [15:0] ra2; |
reg [7:0] rdin1; |
reg [7:0] rdin2; |
|
reg [7:0] rdout1; |
assign dout1 = rdout1; |
reg [7:0] rdout2; |
assign dout2 = rdout2; |
|
// ff's to store pending memory requests |
reg pendingreadb1 = 0; |
reg pendingwriteb1 = 0; |
reg pendingreadb2 = 0; |
reg pendingwriteb2 = 0; |
|
// ff's to store current memory requests |
reg reqreadb1 = 0; |
reg reqreadb2 = 0; |
reg reqwriteb1 = 0; |
reg reqwriteb2 = 0; |
|
reg state = 1; |
always @(posedge clk) begin |
// get requests from the two banks |
if (bank1read) begin |
ra1 <= a1; |
pendingreadb1 <= 1; |
pendingwriteb1 <= 0; |
end |
else if (bank1write) begin |
ra1 <= a1; |
rdin1 <= din1; |
pendingwriteb1 <= 1; |
pendingreadb1 <= 0; |
end |
if (bank2read) begin |
ra2 <= a2; |
pendingreadb2 <= 1; |
pendingwriteb2 <= 0; |
end |
else if (bank2write) begin |
ra2 <= a2; |
rdin2 <= din2; |
pendingwriteb2 <= 1; |
pendingreadb2 <= 0; |
end |
|
// reads from bank1 have the higher priority, then writes to bank1, |
// the reads from bank2, then writes from bank2. |
// Reads and writes to bank2 are mutually exclusive, though, as only the CPU |
// performs those operations. So they are with respect to bank1. |
case (state) |
0 : begin |
if (reqreadb1 || reqwriteb1) begin |
rsa <= {2'b00,ra1}; // operation to bank1 accepted. We put the memory address on the SRAM address bus |
if (reqwriteb1) begin // if this is a write operation... |
pendingwriteb1 <= 0; // accept it, and mark pending operation as cleared |
rsd <= rdin1; // put the data to be written in the SRAM data bus |
rsramwe <= 0; // pulse /WE in SRAM to begin write |
end |
else begin |
pendingreadb1 <= 0; // else, this is a read operation... |
rsd <= 8'bzzzzzzzz; // disconnect the output bus from the data register to the SRAM data bus, so |
rsramwe <= 1; // we can read from the SRAM data bus itself. Deassert /WE to enable data output bus |
end |
state <= 1; // if either request has been accepted, proceed to next phase. |
end |
else if (reqreadb2 || reqwriteb2) begin // do the same with requests to bank 2... |
rsa <= {2'b01,ra2}; |
if (reqwriteb2) begin |
pendingwriteb2 <= 0; |
rsd <= rdin2; |
rsramwe <= 0; |
end |
else begin |
pendingreadb2 <= 0; |
rsd <= 8'bzzzzzzzz; |
rsramwe <= 1; |
end |
state <= 1; |
end |
end |
1 : begin |
if (reqreadb1) begin // for read requests, read the SRAM data bus and store into the corresponding data output register |
rdout1 <= sd; |
end |
else if (reqreadb2) begin |
rdout2 <= sd; |
end |
if (reqwriteb1) begin // for write requests, deassert /WE, as writting has already been happened. |
rsramwe <= 1; |
end |
else if (reqwriteb2) begin |
rsramwe <= 1; |
end |
reqreadb1 <= pendingreadb1; // current request has finished, so update current requests with pending requests to serve the next one |
reqreadb2 <= pendingreadb2; |
reqwriteb1 <= pendingwriteb1; |
reqwriteb2 <= pendingwriteb2; |
if (pendingreadb1 || pendingreadb2 || pendingwriteb1 || pendingwriteb2) |
state <= 0; |
end |
endcase |
end |
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tv80n.v
0,0 → 1,182
// |
// TV80 8-Bit Microprocessor Core |
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
// |
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
// |
// Permission is hereby granted, free of charge, to any person obtaining a |
// copy of this software and associated documentation files (the "Software"), |
// to deal in the Software without restriction, including without limitation |
// the rights to use, copy, modify, merge, publish, distribute, sublicense, |
// and/or sell copies of the Software, and to permit persons to whom the |
// Software is furnished to do so, subject to the following conditions: |
// |
// The above copyright notice and this permission notice shall be included |
// in all copies or substantial portions of the Software. |
// |
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
// Negative-edge based wrapper allows memory wait_n signal to work |
// correctly without resorting to asynchronous logic. |
|
module tv80n (/*AUTOARG*/ |
// Outputs |
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, |
// Inputs |
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di |
); |
|
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB |
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2 |
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle |
|
|
input reset_n; |
input clk; |
input wait_n; |
input int_n; |
input nmi_n; |
input busrq_n; |
output m1_n; |
output mreq_n; |
output iorq_n; |
output rd_n; |
output wr_n; |
output rfsh_n; |
output halt_n; |
output busak_n; |
output [15:0] A; |
input [7:0] di; |
output [7:0] dout; |
|
reg mreq_n; |
reg iorq_n; |
reg rd_n; |
reg wr_n; |
reg nxt_mreq_n; |
reg nxt_iorq_n; |
reg nxt_rd_n; |
reg nxt_wr_n; |
|
wire cen; |
wire intcycle_n; |
wire no_read; |
wire write; |
wire iorq; |
reg [7:0] di_reg; |
wire [6:0] mcycle; |
wire [6:0] tstate; |
|
assign cen = 1; |
|
tv80_core #(Mode, IOWait) i_tv80_core |
( |
.cen (cen), |
.m1_n (m1_n), |
.iorq (iorq), |
.no_read (no_read), |
.write (write), |
.rfsh_n (rfsh_n), |
.halt_n (halt_n), |
.wait_n (wait_n), |
.int_n (int_n), |
.nmi_n (nmi_n), |
.reset_n (reset_n), |
.busrq_n (busrq_n), |
.busak_n (busak_n), |
.clk (clk), |
.IntE (), |
.stop (), |
.A (A), |
.dinst (di), |
.di (di_reg), |
.dout (dout), |
.mc (mcycle), |
.ts (tstate), |
.intcycle_n (intcycle_n) |
); |
|
always @* |
begin |
nxt_mreq_n = 1; |
nxt_rd_n = 1; |
nxt_iorq_n = 1; |
nxt_wr_n = 1; |
|
if (mcycle[0]) |
begin |
if (tstate[1] || tstate[2]) |
begin |
nxt_rd_n = ~ intcycle_n; |
nxt_mreq_n = ~ intcycle_n; |
nxt_iorq_n = intcycle_n; |
end |
end // if (mcycle[0]) |
else |
begin |
if ((tstate[1] || tstate[2]) && !no_read && !write) |
begin |
nxt_rd_n = 1'b0; |
nxt_iorq_n = ~ iorq; |
nxt_mreq_n = iorq; |
end |
if (T2Write == 0) |
begin |
if (tstate[2] && write) |
begin |
nxt_wr_n = 1'b0; |
nxt_iorq_n = ~ iorq; |
nxt_mreq_n = iorq; |
end |
end |
else |
begin |
if ((tstate[1] || (tstate[2] && !wait_n)) && write) |
begin |
nxt_wr_n = 1'b0; |
nxt_iorq_n = ~ iorq; |
nxt_mreq_n = iorq; |
end |
end // else: !if(T2write == 0) |
end // else: !if(mcycle[0]) |
end // always @ * |
|
always @(negedge clk) |
begin |
if (!reset_n) |
begin |
rd_n <= #1 1'b1; |
wr_n <= #1 1'b1; |
iorq_n <= #1 1'b1; |
mreq_n <= #1 1'b1; |
end |
else |
begin |
rd_n <= #1 nxt_rd_n; |
wr_n <= #1 nxt_wr_n; |
iorq_n <= #1 nxt_iorq_n; |
mreq_n <= #1 nxt_mreq_n; |
end // else: !if(!reset_n) |
end // always @ (posedge clk or negedge reset_n) |
|
always @(posedge clk) |
begin |
if (!reset_n) |
begin |
di_reg <= #1 0; |
end |
else |
begin |
if (tstate[2] && wait_n == 1'b1) |
di_reg <= #1 di; |
end // else: !if(!reset_n) |
end // always @ (posedge clk) |
|
endmodule // t80n |
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ula.v
0,0 → 1,394
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Dept. Architecture and Computing Technology. University of Seville |
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es |
// |
// Create Date: 19:13:39 4-Apr-2012 |
// Design Name: ZX Spectrum |
// Module Name: ula |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 1.00 - File Created |
// Additional Comments: GPL License policies apply to the contents of this file. |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
`define cyclestart(a,b) ((a)==(b)) |
`define cycleend(a,b) ((a)==(b+1)) |
|
module ula( |
input clk14, // 14MHz master clock |
input reset, // to reset the ULA to normal color mode. |
// CPU interfacing |
input [15:0] a, // Address bus from CPU (not all lines are used) |
input [7:0] din, // Input data bus from CPU |
output [7:0] dout, // Output data bus to CPU |
input mreq_n, // MREQ from CPU |
input iorq_n, // IORQ from CPU |
input rd_n, // RD from CPU |
input wr_n, // WR from CPU |
input rfsh_n, // RFSH from CPU |
output clkcpu, // CLK to CPU |
output msk_int_n, // Vertical retrace interrupt, to CPU |
// VRAM interfacing |
output [13:0] va, // Address bus to VRAM (16K) |
input [7:0] vramdout,// Data from VRAM to ULA/CPU |
output [7:0] vramdin,// Data from CPU to VRAM |
output vramoe, // |
output vramcs, // Control signals for VRAM |
output vramwe, // |
// ULA I/O |
input ear, // |
output mic, // I/O ports |
output spk, // |
output [7:0] kbrows, // Keyboard rows |
input [4:0] kbcolumns, // Keyboard columns |
// Video output |
output r, // |
output g, // RGB TTL signal |
output b, // with separate bright |
output i, // and composite sync |
output csync // |
); |
|
reg [2:0] BorderColor = 3'b100; |
reg TimexHiColorMode = 0; |
|
reg ULAPlusConfig = 0; |
reg [7:0] ULAPlusAddrReg = 0; |
wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh |
wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh |
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); |
reg [5:0] paletteaddr; |
wire [7:0] palettedout; |
reg palettewe; |
|
ram64bytes palette ( |
.clk(clk14), |
.a(paletteaddr), |
.din(din), |
.dout(palettedout), |
.we(palettewe) |
); |
|
// Pixel clock |
reg clk7 = 0; |
always @(posedge clk14) |
clk7 <= !clk7; |
|
// Horizontal counter |
reg [8:0] hc = 0; |
always @(posedge clk7) begin |
if (hc==447) |
hc <= 0; |
else |
hc <= hc + 1; |
end |
|
// Vertical counter |
reg [8:0] vc = 0; |
always @(posedge clk7) begin |
if (hc==447) begin |
if (vc == 311) |
vc <= 0; |
else |
vc <= vc + 1; |
end |
end |
|
// HBlank generation |
reg HBlank_n = 1; |
always @(negedge clk7) begin |
if (`cyclestart(hc,320)) |
HBlank_n <= 0; |
else if (`cycleend(hc,415)) |
HBlank_n <= 1; |
end |
|
// HSync generation (6C ULA version) |
reg HSync_n = 1; |
always @(negedge clk7) begin |
if (`cyclestart(hc,344)) |
HSync_n <= 0; |
else if (`cycleend(hc,375)) |
HSync_n <= 1; |
end |
|
// VBlank generation |
reg VBlank_n = 1; |
always @(negedge clk7) begin |
if (`cyclestart(vc,248)) |
VBlank_n <= 0; |
else if (`cycleend(vc,255)) |
VBlank_n <= 1; |
end |
|
// VSync generation (PAL) |
reg VSync_n = 1; |
always @(negedge clk7) begin |
if (`cyclestart(vc,248)) |
VSync_n <= 0; |
else if (`cycleend(vc,251)) |
VSync_n <= 1; |
end |
|
// INT generation |
reg INT_n = 1; |
assign msk_int_n = INT_n; |
always @(negedge clk7) begin |
if (`cyclestart(vc,248) && `cyclestart(hc,0)) |
INT_n <= 0; |
else if (`cyclestart(vc,248) && `cycleend(hc,31)) |
INT_n <= 1; |
end |
|
// Border control signal (=0 when we're not displaying paper/ink pixels) |
reg Border_n = 1; |
always @(negedge clk7) begin |
if ( (vc[7] & vc[6]) | vc[8] | hc[8]) |
Border_n <= 0; |
else |
Border_n <= 1; |
end |
|
// VidEN generation (delaying Border 8 clocks) |
reg VidEN_n = 1; |
always @(negedge clk7) begin |
if (hc[3]) |
VidEN_n <= !Border_n; |
end |
|
// DataLatch generation (posedge to capture data from memory) |
reg DataLatch_n = 1; |
always @(negedge clk7) begin |
if (hc[0] & hc[1] & Border_n & hc[3]) |
DataLatch_n <= 0; |
else |
DataLatch_n <= 1; |
end |
|
// AttrLatch generation (posedge to capture data from memory) |
reg AttrLatch_n = 1; |
always @(negedge clk7) begin |
if (hc[0] & !hc[1] & Border_n & hc[3]) |
AttrLatch_n <= 0; |
else |
AttrLatch_n <= 1; |
end |
|
// SLoad generation (negedge to load shift register) |
reg SLoad = 0; |
always @(negedge clk7) begin |
if (!hc[0] & !hc[1] & hc[2] & !VidEN_n) |
SLoad <= 1; |
else |
SLoad <= 0; |
end |
|
// AOLatch generation (negedge to update attr output latch) |
reg AOLatch_n = 1; |
always @(negedge clk7) begin |
if (hc[0] & !hc[1] & hc[2]) |
AOLatch_n <= 0; |
else |
AOLatch_n <= 1; |
end |
|
// First buffer for bitmap |
reg [7:0] BitmapReg = 0; |
always @(negedge DataLatch_n) begin |
BitmapReg <= vramdout; |
end |
|
// Shift register (second bitmap register) |
reg [7:0] SRegister = 0; |
always @(negedge clk7) begin |
if (SLoad) |
SRegister <= BitmapReg; |
else |
SRegister <= {SRegister[6:0],1'b0}; |
end |
|
// First buffer for attribute |
reg [7:0] AttrReg = 0; |
always @(negedge AttrLatch_n) begin |
AttrReg <= vramdout; |
end |
|
// Second buffer for attribute |
reg [7:0] AttrOut = 0; |
always @(negedge AOLatch_n) begin |
if (!VidEN_n) |
AttrOut <= AttrReg; |
else |
AttrOut <= {2'b00,BorderColor,BorderColor}; |
end |
|
// Flash counter and pixel generation |
reg [4:0] FlashCnt = 0; |
always @(negedge VSync_n) begin |
FlashCnt <= FlashCnt + 1; |
end |
wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]); |
|
// RGB generation |
reg rI,rG,rR,rB; |
assign r = rR; |
assign g = rG; |
assign b = rB; |
assign i = rI; |
always @(*) begin |
if (HBlank_n && VBlank_n) |
{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]}; |
else |
{rI,rG,rR,rB} = 4'b0000; |
end |
|
//CSync generation |
assign csync = HSync_n & VSync_n; |
|
// VRAM address and control line generation |
reg [13:0] rVA = 0; |
reg rVCS = 0; |
reg rVOE = 0; |
reg rVWE = 0; |
assign va = rVA; |
assign vramcs = rVCS; |
assign vramoe = rVOE; |
assign vramwe = rVWE; |
// Latches to hold delayed versions of V and H counters |
reg [8:0] v = 0; |
reg [8:0] c = 0; |
// Address and control line multiplexor ULA/CPU |
always @(negedge clk7) begin |
if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC |
c <= hc; |
v <= vc; |
end |
end |
// Address and control line multiplexor ULA/CPU |
always @(*) begin |
if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present attribute address to VRAM |
rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte). |
{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected |
rVCS = 1; |
rVOE = !hc[0]; |
rVWE = 0; |
end |
else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present display address to VRAM |
rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte) |
rVCS = 1; |
rVOE = !hc[0]; |
rVWE = 0; |
end |
else if (Border_n && hc[3:0]==4'b0000) begin |
rVA = a[13:0]; |
rVCS = 0; |
rVOE = 0; |
rVWE = 0; |
end |
else begin // when VRAM is not in use by ULA, give it to CPU |
rVA = a[13:0]; |
rVCS = !a[15] & a[14] & !mreq_n; |
rVOE = !rd_n; |
rVWE = !wr_n; |
end |
end |
|
// Palette addr and control bus multiplexing |
always @(*) begin |
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM |
palettewe = 0; |
paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] }; |
end |
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15)) begin // present address of ink to palette RAM |
palettewe = 0; |
paletteaddr = { AttrReg[7:6],1'b0,AttrReg[2:0] }; |
end |
else if (dataportsel) begin // if CPU requests access, give it palette control |
paletteaddr = ULAPlusAddrReg[5:0]; |
palettewe = cpu_writes_palette; |
end |
else begin |
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM... |
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address |
end |
end |
|
// CPU contention |
reg CPUClk = 0; |
assign clkcpu = CPUClk; |
reg ioreqtw3 = 0; |
reg mreqt23 = 0; |
wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel; |
wire Nor1 = (~(a[14] | ~ioreq_n)) | |
(~(~a[15] | ~ioreq_n)) | |
(~(hc[2] | hc[3])) | |
(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23); |
wire Nor2 = (~(hc[2] | hc[3])) | |
~Border_n | |
~CPUClk | |
ioreq_n | |
~ioreqtw3; |
wire CLKContention = ~Nor1 | ~Nor2; |
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation |
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low |
CPUClk <= 0; |
else |
CPUClk <= 1; |
end |
always @(posedge CPUClk) begin |
ioreqtw3 <= ioreq_n; |
mreqt23 <= mreq_n; |
end |
|
// ULA+ palette management |
always @(posedge clk7 or posedge reset) begin |
if (reset) |
ULAPlusConfig <= 0; |
else begin |
if (addrportsel && !wr_n) |
ULAPlusAddrReg <= din; |
else if (dataportsel && !wr_n && ULAPlusAddrReg[7:6]==2'b01) |
ULAPlusConfig <= din[0]; |
end |
end |
|
// ULA-CPU interface |
assign dout = (!a[15] && a[14] && !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly |
(!iorq_n && !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state |
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported. |
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register |
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} : |
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout : |
(Border_n)? AttrReg : // to emulate |
8'hFF; // port FF (well, cannot be actually FF anymore) |
assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA |
assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between |
a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then |
a[9]? 1'bz : 1'b0, // there's no need to do this. |
a[12]? 1'bz : 1'b0, |
a[13]? 1'bz : 1'b0, |
a[8]? 1'bz : 1'b0, |
a[14]? 1'bz : 1'b0, |
a[15]? 1'bz : 1'b0 }; |
reg rMic = 0; |
reg rSpk = 0; |
assign mic = rMic; |
assign spk = rSpk; |
always @(negedge clk7 or posedge reset) begin |
if (reset) |
TimexHiColorMode <= 0; |
else if (!iorq_n && a[7:0]==8'hFF && !wr_n) |
TimexHiColorMode <= din[1]; |
else if (!iorq_n & !a[0] & !wr_n) |
{rSpk,rMic,BorderColor} <= din[5:0]; |
end |
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ULAPLUS_NO_YET_FINISHED.TXT
--- zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/zx_spectrum_48k.gise (nonexistent)
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/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/spectrum48k_tld.v
0,0 → 1,271
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Dept. Architecture and Computing Technology. University of Seville |
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es |
// |
// Create Date: 19:13:39 4-Apr-2012 |
// Design Name: ZX Spectrum |
// Module Name: tld_spartan3_sp48k |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 1.00 - File Created |
// Additional Comments: GPL License policies apply to the contents of this file. |
// |
////////////////////////////////////////////////////////////////////////////////// |
module tld_spartan3_sp48k ( |
input clk50, |
input reset, |
output r, |
output g, |
output b, |
output i, |
output csync, |
// ULA I/O |
input ear, |
output audio_out, |
// PS/2 keyboard |
input clkps2, |
input dataps2, |
// diagnostics |
output [6:0] dispcathodes, |
output [3:0] dispanodes, |
output ledreleased, |
output ledextended, |
output ledshift, |
output ledclk, |
output [3:0] ledaux, |
// SRAM memory |
output [17:0] sa, |
inout [7:0] sd1, |
output sramce1, |
output sramub1, |
output sramlb1, |
output sramoe, |
output sramwe |
); |
|
// CPU signals |
wire [15:0] a; |
wire [7:0] cpudout; |
wire [7:0] cpudin; |
wire clkcpu; |
wire mreq_n; |
wire iorq_n; |
wire wr_n; |
wire rd_n; |
wire rfsh_n; |
wire int_n; |
|
// VRAM signals |
wire [13:0] va; |
wire [7:0] vramdin; |
wire [7:0] vramdout; |
wire vramoe; |
wire vramcs; |
wire vramwe; |
|
// I/O |
wire mic; |
wire spk; |
wire [4:0] kbd_columns; |
|
// ULA data bus |
wire [7:0] uladout; |
wire [7:0] uladin; |
|
// SRAM data bus |
wire [7:0] sramdout; |
wire [7:0] sramdin; |
|
// ROM data bus |
wire [7:0] romdout; |
|
wire sram_cs = a[15] & !mreq_n; |
wire ula_cs = !a[0] & !iorq_n; |
wire vram_cs = !a[15] & a[14] & !mreq_n; |
wire port255_cs = !iorq_n && a[7:0]==8'hFF && !rd_n; |
wire ulaplusaddr_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh |
wire ulaplusdata_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11); // port FF3Bh |
wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n; |
|
///////////////////////////////////// |
// Master clock (14MHz) generation |
///////////////////////////////////// |
wire clk28mhz; |
master_clock clock28mhz ( |
.CLKIN_IN(clk50), |
.CLKFX_OUT(clk28mhz), |
.CLKIN_IBUFG_OUT(), |
.CLK0_OUT() |
); |
reg clk14 = 0; |
always @(posedge clk28mhz) begin |
clk14 = !clk14; |
end |
wire clkula = clk14; |
wire clkmem = clk28mhz; |
wire clkaudio = clk14; |
wire clkkbd = clk14; |
|
///////////////////////////////////// |
// ROM |
///////////////////////////////////// |
rom the_rom ( |
.clka(clkmem), |
.ena(rom_cs), |
.addra(a[13:0]), |
.douta(romdout) |
); |
|
///////////////////////////////////// |
// VRAM and upper RAM banks |
///////////////////////////////////// |
ram_controller vram_and_upper_ram ( |
.clk(clkmem), |
// Bank 1 (VRAM) |
.a1({2'b00,va}), |
.cs1_n(!vramcs), |
.oe1_n(!vramoe), |
.we1_n(!vramwe), |
.din1(vramdin), |
.dout1(vramdout), |
// Bank 2 (upper RAM) |
.a2({1'b0,a[14:0]}), |
.cs2_n(!sram_cs), |
.oe2_n(rd_n), |
.we2_n(wr_n), |
.din2(sramdin), |
.dout2(sramdout), |
// Outputs to actual SRAM on board |
.sa(sa), |
.sd(sd1), |
.sramce(sramce1), |
.sramub(sramub1), |
.sramlb(sramlb1), |
.sramoe(sramoe), |
.sramwe(sramwe) |
); |
|
///////////////////////////////////// |
// The ULA |
///////////////////////////////////// |
ula the_ula ( |
.clk14(clkula), |
.reset(reset), |
.a(a), |
.din(uladin), |
.dout(uladout), |
.mreq_n(mreq_n), |
.iorq_n(iorq_n), |
.rd_n(rd_n), |
.wr_n(wr_n), |
.rfsh_n(rfsh_n), |
.clkcpu(clkcpu), |
.msk_int_n(int_n), |
.va(va), |
.vramdout(vramdout), |
.vramdin(vramdin), |
.vramoe(vramoe), |
.vramcs(vramcs), |
.vramwe(vramwe), |
.ear(ear), |
.mic(mic), |
.spk(spk), |
.kbrows(), |
.kbcolumns(kbd_columns), |
.r(r), |
.g(g), |
.b(b), |
.i(i), |
.csync(csync) |
); |
|
///////////////////////////////////// |
// The CPU Z80A |
///////////////////////////////////// |
tv80n cpu ( |
// Outputs |
.m1_n(), |
.mreq_n(mreq_n), |
.iorq_n(iorq_n), |
.rd_n(rd_n), |
.wr_n(wr_n), |
.rfsh_n(rfsh_n), |
.halt_n(), |
.busak_n(), |
.A(a), |
.dout(cpudout), |
// Inputs |
.reset_n(!reset), |
.clk(clkcpu), |
.wait_n(1'b1), |
.int_n(int_n), |
.nmi_n(1'b1), |
.busrq_n(1'b1), |
.di(cpudin) |
); |
|
///////////////////////////////////// |
// CPU data bus |
///////////////////////////////////// |
assign sramdin = cpudout; |
assign uladin = cpudout; |
assign cpudin = (rom_cs)? romdout : |
(ula_cs | vram_cs | port255_cs | ulaplusaddr_cs | ulaplusdata_cs)? uladout : |
(sram_cs)? sramdout : |
8'hFF; |
|
///////////////////////////////////// |
// Audio mixer |
///////////////////////////////////// |
mixer audio_mix ( |
.clkdac(clkaudio), |
.reset(reset), |
.ear(ear), |
.mic(mic), |
.spk(spk), |
.audio(audio_out) |
); |
|
///////////////////////////////////// |
// PS2 Keyboard |
///////////////////////////////////// |
wire [7:0] kbdscancode; |
|
ps2kbd keyboard ( |
.clk(clkkbd), |
.reset(reset), |
.clkps2(clkps2), |
.dataps2(dataps2), |
.ledextended(ledextended), |
.ledreleased(ledreleased), |
.ledmayus(ledshift), |
.scancode(kbdscancode), |
.semifila(a[15:8]), |
.columna(kbd_columns) |
); |
|
///////////////////////////////////// |
// Diagnostics |
///////////////////////////////////// |
display numeric_display ( |
.clk(clkkbd), |
.load(int_n), |
.valor({8'h00,kbdscancode}), |
.an(dispanodes), |
.seg(dispcathodes) |
); |
|
reg [19:0] divclkcpu = 0; |
assign ledclk = divclkcpu[19]; // a simple "hearbeat" blink to let us know that the CPU is running. |
always @(posedge clkcpu) |
divclkcpu <= divclkcpu + 1; |
assign ledaux = 4'b0000; |
|
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/audio_management.v
0,0 → 1,81
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 04:04:00 04/01/2012 |
// Design Name: |
// Module Name: sigma_delta_dac |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
`define MSBI 7 // Most significant Bit of DAC input |
|
//This is a Delta-Sigma Digital to Analog Converter |
module dac (DACout, DACin, Clk, Reset); |
output DACout; // This is the average output that feeds low pass filter |
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI) |
input Clk; |
input Reset; |
|
reg DACout; // for optimum performance, ensure that this ff is in IOB |
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder |
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder |
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder |
reg [`MSBI+2:0] DeltaB; // B input of Delta adder |
|
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1); |
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB; |
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch; |
always @(posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
SigmaLatch <= #1 1'b1 << (`MSBI+1); |
DACout <= #1 1'b0; |
end |
else |
begin |
SigmaLatch <= #1 SigmaAdder; |
DACout <= #1 SigmaLatch[`MSBI+2]; |
end |
end |
endmodule |
|
module mixer ( |
input clkdac, |
input reset, |
input ear, |
input mic, |
input spk, |
output audio |
); |
|
reg [7:0] mix = 0; |
|
always @(posedge clkdac) |
mix <= ({ear,spk,mic}==3'b000)? 17 : |
({ear,spk,mic}==3'b001)? 36 : |
({ear,spk,mic}==3'b010)? 184 : |
({ear,spk,mic}==3'b011)? 192 : |
({ear,spk,mic}==3'b100)? 22 : |
({ear,spk,mic}==3'b101)? 48 : |
({ear,spk,mic}==3'b110)? 244 : 255; |
|
dac audio_dac ( |
.DACout(audio), |
.DACin(mix), |
.Clk(clkdac), |
.Reset(reset) |
); |
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/rom.v
0,0 → 1,158
/******************************************************************************* |
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * |
* * |
* This file contains confidential and proprietary information * |
* of Xilinx, Inc. and is protected under U.S. and * |
* international copyright and other intellectual property * |
* laws. * |
* * |
* DISCLAIMER * |
* This disclaimer is not a license and does not grant any * |
* rights to the materials distributed herewith. Except as * |
* otherwise provided in a valid license issued to you by * |
* Xilinx, and to the maximum extent permitted by applicable * |
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * |
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * |
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * |
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * |
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * |
* (2) Xilinx shall not be liable (whether in contract or tort, * |
* including negligence, or under any other theory of * |
* liability) for any loss or damage of any kind or nature * |
* related to, arising under or in connection with these * |
* materials, including for any direct, or any indirect, * |
* special, incidental, or consequential loss or damage * |
* (including loss of data, profits, goodwill, or any type of * |
* loss or damage suffered as a result of any action brought * |
* by a third party) even if such damage or loss was * |
* reasonably foreseeable or Xilinx had been advised of the * |
* possibility of the same. * |
* * |
* CRITICAL APPLICATIONS * |
* Xilinx products are not designed or intended to be fail- * |
* safe, or for use in any application requiring fail-safe * |
* performance, such as life-support or safety devices or * |
* systems, Class III medical devices, nuclear facilities, * |
* applications related to the deployment of airbags, or any * |
* other applications that could lead to death, personal * |
* injury, or severe property or environmental damage * |
* (individually and collectively, "Critical * |
* Applications"). Customer assumes the sole risk and * |
* liability of any use of Xilinx products in Critical * |
* Applications, subject only to applicable laws and * |
* regulations governing limitations on product liability. * |
* * |
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * |
* PART OF THIS FILE AT ALL TIMES. * |
*******************************************************************************/ |
// The synthesis directives "translate_off/translate_on" specified below are |
// supported by Xilinx, Mentor Graphics and Synplicity synthesis |
// tools. Ensure they are correct for your synthesis tool(s). |
|
// You must compile the wrapper file rom.v when simulating |
// the core, rom. When compiling the wrapper file, be sure to |
// reference the XilinxCoreLib Verilog simulation library. For detailed |
// instructions, please refer to the "CORE Generator Help". |
|
`timescale 1ns/1ps |
|
module rom( |
clka, |
ena, |
addra, |
douta); |
|
|
input clka; |
input ena; |
input [13 : 0] addra; |
output [7 : 0] douta; |
|
// synthesis translate_off |
|
BLK_MEM_GEN_V4_3 #( |
.C_ADDRA_WIDTH(14), |
.C_ADDRB_WIDTH(14), |
.C_ALGORITHM(1), |
.C_BYTE_SIZE(9), |
.C_COMMON_CLK(0), |
.C_DEFAULT_DATA("0"), |
.C_DISABLE_WARN_BHV_COLL(0), |
.C_DISABLE_WARN_BHV_RANGE(0), |
.C_FAMILY("spartan3"), |
.C_HAS_ENA(1), |
.C_HAS_ENB(0), |
.C_HAS_INJECTERR(0), |
.C_HAS_MEM_OUTPUT_REGS_A(0), |
.C_HAS_MEM_OUTPUT_REGS_B(0), |
.C_HAS_MUX_OUTPUT_REGS_A(0), |
.C_HAS_MUX_OUTPUT_REGS_B(0), |
.C_HAS_REGCEA(0), |
.C_HAS_REGCEB(0), |
.C_HAS_RSTA(0), |
.C_HAS_RSTB(0), |
.C_HAS_SOFTECC_INPUT_REGS_A(0), |
.C_HAS_SOFTECC_OUTPUT_REGS_B(0), |
.C_INITA_VAL("0"), |
.C_INITB_VAL("0"), |
.C_INIT_FILE_NAME("rom.mif"), |
.C_LOAD_INIT_FILE(1), |
.C_MEM_TYPE(3), |
.C_MUX_PIPELINE_STAGES(0), |
.C_PRIM_TYPE(1), |
.C_READ_DEPTH_A(16384), |
.C_READ_DEPTH_B(16384), |
.C_READ_WIDTH_A(8), |
.C_READ_WIDTH_B(8), |
.C_RSTRAM_A(0), |
.C_RSTRAM_B(0), |
.C_RST_PRIORITY_A("CE"), |
.C_RST_PRIORITY_B("CE"), |
.C_RST_TYPE("SYNC"), |
.C_SIM_COLLISION_CHECK("ALL"), |
.C_USE_BYTE_WEA(0), |
.C_USE_BYTE_WEB(0), |
.C_USE_DEFAULT_DATA(0), |
.C_USE_ECC(0), |
.C_USE_SOFTECC(0), |
.C_WEA_WIDTH(1), |
.C_WEB_WIDTH(1), |
.C_WRITE_DEPTH_A(16384), |
.C_WRITE_DEPTH_B(16384), |
.C_WRITE_MODE_A("WRITE_FIRST"), |
.C_WRITE_MODE_B("WRITE_FIRST"), |
.C_WRITE_WIDTH_A(8), |
.C_WRITE_WIDTH_B(8), |
.C_XDEVICEFAMILY("spartan3")) |
inst ( |
.CLKA(clka), |
.ENA(ena), |
.ADDRA(addra), |
.DOUTA(douta), |
.RSTA(), |
.REGCEA(), |
.WEA(), |
.DINA(), |
.CLKB(), |
.RSTB(), |
.ENB(), |
.REGCEB(), |
.WEB(), |
.ADDRB(), |
.DINB(), |
.DOUTB(), |
.INJECTSBITERR(), |
.INJECTDBITERR(), |
.SBITERR(), |
.DBITERR(), |
.RDADDRECC()); |
|
|
// synthesis translate_on |
|
// XST black box declaration |
// box_type "black_box" |
// synthesis attribute box_type of rom is "black_box" |
|
endmodule |
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tv80_reg.v
0,0 → 1,77
// |
// TV80 8-Bit Microprocessor Core |
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
// |
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
// |
// Permission is hereby granted, free of charge, to any person obtaining a |
// copy of this software and associated documentation files (the "Software"), |
// to deal in the Software without restriction, including without limitation |
// the rights to use, copy, modify, merge, publish, distribute, sublicense, |
// and/or sell copies of the Software, and to permit persons to whom the |
// Software is furnished to do so, subject to the following conditions: |
// |
// The above copyright notice and this permission notice shall be included |
// in all copies or substantial portions of the Software. |
// |
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
module tv80_reg (/*AUTOARG*/ |
// Outputs |
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, |
// Inputs |
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL |
); |
input [2:0] AddrC; |
output [7:0] DOBH; |
input [2:0] AddrA; |
input [2:0] AddrB; |
input [7:0] DIH; |
output [7:0] DOAL; |
output [7:0] DOCL; |
input [7:0] DIL; |
output [7:0] DOBL; |
output [7:0] DOCH; |
output [7:0] DOAH; |
input clk, CEN, WEH, WEL; |
|
reg [7:0] RegsH [0:7]; |
reg [7:0] RegsL [0:7]; |
|
always @(posedge clk) |
begin |
if (CEN) |
begin |
if (WEH) RegsH[AddrA] <= DIH; |
if (WEL) RegsL[AddrA] <= DIL; |
end |
end |
|
assign DOAH = RegsH[AddrA]; |
assign DOAL = RegsL[AddrA]; |
assign DOBH = RegsH[AddrB]; |
assign DOBL = RegsL[AddrB]; |
assign DOCH = RegsH[AddrC]; |
assign DOCL = RegsL[AddrC]; |
|
// break out ram bits for waveform debug |
// synopsys translate_off |
wire [7:0] B = RegsH[0]; |
wire [7:0] C = RegsL[0]; |
wire [7:0] D = RegsH[1]; |
wire [7:0] E = RegsL[1]; |
wire [7:0] H = RegsH[2]; |
wire [7:0] L = RegsL[2]; |
|
wire [15:0] IX = { RegsH[3], RegsL[3] }; |
wire [15:0] IY = { RegsH[7], RegsL[7] }; |
// synopsys translate_on |
|
endmodule |
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/rom.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6e |
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/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/teclado_ps2.v
0,0 → 1,334
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Dept. Architecture and Computing Technology. University of Seville |
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es |
// |
// Create Date: 19:13:39 4-Apr-2012 |
// Design Name: ZX Spectrum |
// Module Name: PS2 keyboard interface for ZX Spectrum. |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 1.00 - File Created |
// Additional Comments: GPL License policies apply to the contents of this file. |
// |
////////////////////////////////////////////////////////////////////////////////// |
module ps2kbd ( |
input clk, |
input reset, |
input clkps2, |
input dataps2, |
output ledextended, |
output ledreleased, |
output ledmayus, |
output [7:0] scancode, |
input [7:0] semifila, |
output [4:0] columna |
); |
|
reg rload = 0; |
reg [1:0] estado = 0; |
|
wire [7:0] tecla; |
wire recibida; |
|
reg [7:0] rscancode=8'h00; |
assign scancode = rscancode; |
|
reg extended = 0; |
reg released = 0; |
reg mayus = 0; |
assign ledextended = extended; |
assign ledreleased = released; |
assign ledmayus = mayus; |
|
ps2_keyboard ps2_get_scancode ( |
.clk(clk), |
.reset(reset), |
.ps2_clk(clkps2), |
.ps2_data(dataps2), |
.interrupt(recibida), |
.rx_scan_code(tecla) |
); |
|
matrix scancode_to_zx_keyboard ( |
.clk(clk), |
.keyreceived(rload), |
.scancode(tecla), |
.mayus(mayus), |
.extended(extended), |
.released(released), |
.semifila(semifila), |
.columna(columna) |
); |
|
always @(posedge clk) |
begin |
case (estado) |
0: if (recibida) // if a new key has just been received at the PS2 port... |
begin |
if (tecla==8'h12 || tecla==8'h59) begin // if it's one of the two shift keys, |
mayus <= 1; // signal it. |
end |
else if (tecla==8'hE0) begin // if this is the beginning of an extended key |
extended <= 1; // signal it... |
released <= 0; // (this is not a released key) |
estado <= 1; // ...and wait for the next code |
end |
else if (tecla==8'hF0) begin // if this is the beginning of a released key |
extended <= 0; // then it's not an extended key |
released <= 1; // signal it... |
estado <= 2; // ... and wait for the next code |
end |
else if (tecla!=8'hE0 && tecla!=8'hF0 && tecla!=8'h12 && tecla!=8'h59) begin // if this is a "normal" key |
rscancode <= tecla; // store its scancode |
extended <= 0; // |
released <= 0; // signal it as "normal": not released, not extended |
rload <= 1; //no estaba // a new key has arrived. Signal that to the matrix module |
estado <= 0; //3; // and go for another key (the next clock will have "recibida" = 0, so |
end // it will go to the "else" part of this "if" statement, to deassert "rload") |
end |
else |
rload <= 0; // if a new key has not been received, just turn off the "new key arrived" signal |
|
1: if (recibida) // if a new extended key has just been received at the PS2 port... |
begin |
if (tecla==8'hF0) begin // if this is the beginning of a released extended key... |
released <= 1; // ... signal it, and |
estado <= 2; // ... wait for the actual scancode of the released key |
end |
else if (tecla!=8'hE0 && tecla!=8'hF0 && tecla!=8'h12 && tecla!=8'h59) begin // if this is the actual scancode of a new pressed extended key... |
rscancode <= tecla; // store it... |
rload <= 1; //no estaba // assert "rload"... |
estado <= 0; //3; // and go for another key... |
end |
end |
else |
rload <= 0; |
|
2: if (recibida) // if a new released key has just been received at the PS2 port... |
begin |
if (tecla==8'h12 || tecla==8'h59) begin // if it is one of the shift keys |
mayus <= 0; // deassert "mayus" to signal that shift is no longer pressed |
estado <= 0; |
end |
else if (tecla!=8'hE0 && tecla!=8'hF0 && tecla!=8'h12 && tecla!=8'h59) begin // if this is any other key... |
rscancode <= tecla; // store it... |
rload <= 1; // assert "rload" |
estado <= 0; // and go for another key |
end |
end |
else |
rload <= 0; |
endcase |
end |
endmodule |
|
module matrix ( |
input clk, |
input keyreceived, |
input [7:0] scancode, |
input mayus, |
input extended, |
input released, |
input [7:0] semifila, |
output [4:0] columna |
); |
|
reg [4:0] thematrix[0:7]; // memory representing 40 keys |
initial begin // initially, all keys are released (0=pressed) |
thematrix[0] = 5'b11111; |
thematrix[1] = 5'b11111; |
thematrix[2] = 5'b11111; |
thematrix[3] = 5'b11111; |
thematrix[4] = 5'b11111; |
thematrix[5] = 5'b11111; |
thematrix[6] = 5'b11111; |
thematrix[7] = 5'b11111; |
end |
|
// output bits to ULA are composed with data from the eight half-rows, depending upon which |
// bits were resetted at CPU address bus bits 8-15 (row selection) |
assign columna = ((!semifila[0])? thematrix[0] : 5'b11111) & |
((!semifila[1])? thematrix[1] : 5'b11111) & |
((!semifila[2])? thematrix[2] : 5'b11111) & |
((!semifila[3])? thematrix[3] : 5'b11111) & |
((!semifila[4])? thematrix[4] : 5'b11111) & |
((!semifila[5])? thematrix[5] : 5'b11111) & |
((!semifila[6])? thematrix[6] : 5'b11111) & |
((!semifila[7])? thematrix[7] : 5'b11111); |
|
// ROM's containing the ZX Spectrum equivalent key(s) for each PS2 key. For Spectrum shifted keys |
// (such as = * + ! CURSOR-LEFT, DELETE, EDIT, etc), a memory location contains two values: one of |
// them is either CAPS SHIFT or SYMBOL SHIFT. The other one is the key that would have to be pressed along |
// with the shift key on the ZX Spectrum keyboard. |
// These ROM's are filled in the file "mapa_es.inc". This file contains the mapping for a spanish keyboard. |
// There is a ROM for normal PS2 keys, another one for PS2 shifted keys, another one for extended, non shifted |
// keys, and the last one is for extended shifted keys. |
// Cada posicion tiene: CODSEMIFILA1(3) , VALORSEMIFILA1(5) , CODSEMIFILA1(3) , VALORSEMIFILA1(5) |
// These ROM's will be infered as BLOCK RAM because the address will be registered |
reg [15:0] mapa_noshift_noext[0:131]; |
reg [15:0] mapa_shift_noext[0:131]; |
reg [15:0] mapa_noshift_ext[0:131]; |
reg [15:0] mapa_shift_ext[0:131]; |
|
`include "mapa_es.inc" |
|
reg [2:0] row_key1_nosh_noex; |
reg [2:0] row_key2_nosh_noex; |
reg [2:0] row_key1_sh_noex; |
reg [2:0] row_key2_sh_noex; |
reg [2:0] row_key1_nosh_ex; |
reg [2:0] row_key2_nosh_ex; |
reg [2:0] row_key1_sh_ex; |
reg [2:0] row_key2_sh_ex; |
|
reg [4:0] col_key1_nosh_noex; |
reg [4:0] col_key2_nosh_noex; |
reg [4:0] col_key1_sh_noex; |
reg [4:0] col_key2_sh_noex; |
reg [4:0] col_key1_nosh_ex; |
reg [4:0] col_key2_nosh_ex; |
reg [4:0] col_key1_sh_ex; |
reg [4:0] col_key2_sh_ex; |
|
reg [7:0] addrmap; // to make the addr registered, so XST will infer block RAM. |
reg [4:0] matrixstate = 0; |
|
always @(posedge clk) begin |
case (matrixstate) |
0 : begin |
if (keyreceived) begin // wait until a key is received. |
matrixstate <= 1; |
addrmap <= scancode; |
end |
end |
1 : begin // paralell read the same in the four possible combinations |
{row_key1_nosh_noex, |
col_key1_nosh_noex, |
row_key2_nosh_noex, |
col_key2_nosh_noex} <= mapa_noshift_noext[addrmap]; |
{row_key1_sh_noex, |
col_key1_sh_noex, |
row_key2_sh_noex, |
col_key2_sh_noex} <= mapa_shift_noext[addrmap]; |
{row_key1_nosh_ex, |
col_key1_nosh_ex, |
row_key2_nosh_ex, |
col_key2_nosh_ex} <= mapa_noshift_ext[addrmap]; |
{row_key1_sh_ex, |
col_key1_sh_ex, |
row_key2_sh_ex, |
col_key2_sh_ex} <= mapa_shift_ext[addrmap]; |
matrixstate <= 3; |
end |
3 : begin // apply matrix updates according to the actual combination pressed or released |
case ( {mayus,extended,released} ) |
3'b000 : matrixstate <= 4; //non shifted, non extended, key pressed |
3'b001 : matrixstate <= 6; //non shifted, non extended, key released |
3'b010 : matrixstate <= 10; //non shifted, extended... |
3'b011 : matrixstate <= 12; // |
3'b100 : matrixstate <= 16; //shifted, non extended... |
3'b101 : matrixstate <= 18; // |
3'b110 : matrixstate <= 20; //shifted, extended... |
3'b111 : matrixstate <= 22; // |
default : matrixstate <= 0; |
endcase |
end |
4 : begin // non shifted, non extended, key pressed, update key1 status |
thematrix[row_key1_nosh_noex] <= thematrix[row_key1_nosh_noex] & col_key1_nosh_noex; |
matrixstate <= 5; |
end |
5 : begin // update key2 status |
thematrix[row_key2_nosh_noex] <= thematrix[row_key2_nosh_noex] & col_key2_nosh_noex; |
matrixstate <= 0; // go for another key |
end |
|
6 : begin // non shifted, non extended, key released... |
thematrix[row_key1_nosh_noex] <= thematrix[row_key1_nosh_noex] | ~col_key1_nosh_noex; |
matrixstate <= 7; |
end |
7 : begin |
thematrix[row_key2_nosh_noex] <= thematrix[row_key2_nosh_noex] | ~col_key2_nosh_noex; |
matrixstate <= 8; |
end |
8 : begin // when a non shifted key releases, it released shifted version too... |
thematrix[row_key1_sh_noex] <= thematrix[row_key1_sh_noex] | ~col_key1_sh_noex; |
matrixstate <= 9; |
end |
9 : begin |
thematrix[row_key2_sh_noex] <= thematrix[row_key2_sh_noex] | ~col_key2_sh_noex; |
matrixstate <= 0; |
end |
|
10: begin // non shifted, extended, key pressed... |
thematrix[row_key1_nosh_ex] <= thematrix[row_key1_nosh_ex] & col_key1_nosh_ex; |
matrixstate <= 11; |
end |
11: begin |
thematrix[row_key2_nosh_ex] <= thematrix[row_key2_nosh_ex] & col_key2_nosh_ex; |
matrixstate <= 0; // go for another key |
end |
|
12: begin // non shifted, extended, key released... |
thematrix[row_key1_nosh_ex] <= thematrix[row_key1_nosh_ex] | ~col_key1_nosh_ex; |
matrixstate <= 13; |
end |
13: begin |
thematrix[row_key2_nosh_ex] <= thematrix[row_key2_nosh_ex] | ~col_key2_nosh_ex; |
matrixstate <= 14; |
end |
14: begin // when a non shifted key releases, it released shifted version too... |
thematrix[row_key1_sh_ex] <= thematrix[row_key1_sh_ex] | ~col_key1_sh_ex; |
matrixstate <= 15; |
end |
15: begin |
thematrix[row_key2_sh_ex] <= thematrix[row_key2_sh_ex] | ~col_key2_sh_ex; |
matrixstate <= 0; |
end |
|
16: begin // shifted, non extended, key pressed, update key1 status |
thematrix[row_key1_sh_noex] <= thematrix[row_key1_sh_noex] & col_key1_sh_noex; |
matrixstate <= 17; |
end |
17: begin // update key2 status |
thematrix[row_key2_sh_noex] <= thematrix[row_key2_sh_noex] & col_key2_sh_noex; |
matrixstate <= 0; // go for another key |
end |
|
18: begin // shifted, non extended, key released... |
thematrix[row_key1_sh_noex] <= thematrix[row_key1_sh_noex] | ~col_key1_sh_noex; |
matrixstate <= 19; |
end |
19: begin |
thematrix[row_key2_sh_noex] <= thematrix[row_key2_sh_noex] | ~col_key2_sh_noex; |
matrixstate <= 0; |
end |
|
20: begin // shifted, extended, key pressed, update key1 status |
thematrix[row_key1_sh_ex] <= thematrix[row_key1_sh_ex] & col_key1_sh_ex; |
matrixstate <= 21; |
end |
21: begin // update key2 status |
thematrix[row_key2_sh_ex] <= thematrix[row_key2_sh_ex] & col_key2_sh_ex; |
matrixstate <= 0; // go for another key |
end |
|
22: begin // shifted, extended, key released... |
thematrix[row_key1_sh_ex] <= thematrix[row_key1_sh_ex] | ~col_key1_sh_ex; |
matrixstate <= 23; |
end |
23: begin |
thematrix[row_key2_sh_ex] <= thematrix[row_key2_sh_ex] | ~col_key2_sh_ex; |
matrixstate <= 0; |
end |
endcase |
end |
endmodule |
|
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ram64bytes.v
0,0 → 1,36
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 20:57:11 04/29/2012 |
// Design Name: |
// Module Name: ram64bytes |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module ram64bytes( |
input clk, |
input [5:0] a, |
input [7:0] din, |
output [7:0] dout, |
input we |
); |
|
reg [7:0] mem[0:63]; |
assign dout = mem[a]; //non registered address. Ugly, but works :( |
|
always @(posedge clk) begin |
if (we) |
mem[a] <= din; |
end |
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tv80_alu.v
0,0 → 1,442
// |
// TV80 8-Bit Microprocessor Core |
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
// |
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
// |
// Permission is hereby granted, free of charge, to any person obtaining a |
// copy of this software and associated documentation files (the "Software"), |
// to deal in the Software without restriction, including without limitation |
// the rights to use, copy, modify, merge, publish, distribute, sublicense, |
// and/or sell copies of the Software, and to permit persons to whom the |
// Software is furnished to do so, subject to the following conditions: |
// |
// The above copyright notice and this permission notice shall be included |
// in all copies or substantial portions of the Software. |
// |
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
module tv80_alu (/*AUTOARG*/ |
// Outputs |
Q, F_Out, |
// Inputs |
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In |
); |
|
parameter Mode = 0; |
parameter Flag_C = 0; |
parameter Flag_N = 1; |
parameter Flag_P = 2; |
parameter Flag_X = 3; |
parameter Flag_H = 4; |
parameter Flag_Y = 5; |
parameter Flag_Z = 6; |
parameter Flag_S = 7; |
|
input Arith16; |
input Z16; |
input [3:0] ALU_Op ; |
input [5:0] IR; |
input [1:0] ISet; |
input [7:0] BusA; |
input [7:0] BusB; |
input [7:0] F_In; |
output [7:0] Q; |
output [7:0] F_Out; |
reg [7:0] Q; |
reg [7:0] F_Out; |
|
function [4:0] AddSub4; |
input [3:0] A; |
input [3:0] B; |
input Sub; |
input Carry_In; |
begin |
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In}; |
end |
endfunction // AddSub4 |
|
function [3:0] AddSub3; |
input [2:0] A; |
input [2:0] B; |
input Sub; |
input Carry_In; |
begin |
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In}; |
end |
endfunction // AddSub4 |
|
function [1:0] AddSub1; |
input A; |
input B; |
input Sub; |
input Carry_In; |
begin |
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In}; |
end |
endfunction // AddSub4 |
|
// AddSub variables (temporary signals) |
reg UseCarry; |
reg Carry7_v; |
reg OverFlow_v; |
reg HalfCarry_v; |
reg Carry_v; |
reg [7:0] Q_v; |
|
reg [7:0] BitMask; |
|
|
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) |
begin |
case (IR[5:3]) |
3'b000 : BitMask = 8'b00000001; |
3'b001 : BitMask = 8'b00000010; |
3'b010 : BitMask = 8'b00000100; |
3'b011 : BitMask = 8'b00001000; |
3'b100 : BitMask = 8'b00010000; |
3'b101 : BitMask = 8'b00100000; |
3'b110 : BitMask = 8'b01000000; |
default: BitMask = 8'b10000000; |
endcase // case(IR[5:3]) |
|
UseCarry = ~ ALU_Op[2] && ALU_Op[0]; |
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); |
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); |
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); |
OverFlow_v = Carry_v ^ Carry7_v; |
end // always @ * |
|
reg [7:0] Q_t; |
reg [8:0] DAA_Q; |
|
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB |
or Carry_v or F_In or HalfCarry_v or IR or ISet |
or OverFlow_v or Q_v or Z16) |
begin |
Q_t = 8'hxx; |
DAA_Q = {9{1'bx}}; |
|
F_Out = F_In; |
case (ALU_Op) |
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : |
begin |
F_Out[Flag_N] = 1'b0; |
F_Out[Flag_C] = 1'b0; |
|
case (ALU_Op[2:0]) |
|
3'b000, 3'b001 : // ADD, ADC |
begin |
Q_t = Q_v; |
F_Out[Flag_C] = Carry_v; |
F_Out[Flag_H] = HalfCarry_v; |
F_Out[Flag_P] = OverFlow_v; |
end |
|
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP |
begin |
Q_t = Q_v; |
F_Out[Flag_N] = 1'b1; |
F_Out[Flag_C] = ~ Carry_v; |
F_Out[Flag_H] = ~ HalfCarry_v; |
F_Out[Flag_P] = OverFlow_v; |
end |
|
3'b100 : // AND |
begin |
Q_t[7:0] = BusA & BusB; |
F_Out[Flag_H] = 1'b1; |
end |
|
3'b101 : // XOR |
begin |
Q_t[7:0] = BusA ^ BusB; |
F_Out[Flag_H] = 1'b0; |
end |
|
default : // OR 3'b110 |
begin |
Q_t[7:0] = BusA | BusB; |
F_Out[Flag_H] = 1'b0; |
end |
|
endcase // case(ALU_OP[2:0]) |
|
if (ALU_Op[2:0] == 3'b111 ) |
begin // CP |
F_Out[Flag_X] = BusB[3]; |
F_Out[Flag_Y] = BusB[5]; |
end |
else |
begin |
F_Out[Flag_X] = Q_t[3]; |
F_Out[Flag_Y] = Q_t[5]; |
end |
|
if (Q_t[7:0] == 8'b00000000 ) |
begin |
F_Out[Flag_Z] = 1'b1; |
if (Z16 == 1'b1 ) |
begin |
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC |
end |
end |
else |
begin |
F_Out[Flag_Z] = 1'b0; |
end // else: !if(Q_t[7:0] == 8'b00000000 ) |
|
F_Out[Flag_S] = Q_t[7]; |
case (ALU_Op[2:0]) |
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP |
; |
|
default : |
F_Out[Flag_P] = ~(^Q_t); |
endcase // case(ALU_Op[2:0]) |
|
if (Arith16 == 1'b1 ) |
begin |
F_Out[Flag_S] = F_In[Flag_S]; |
F_Out[Flag_Z] = F_In[Flag_Z]; |
F_Out[Flag_P] = F_In[Flag_P]; |
end |
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 |
|
4'b1100 : |
begin |
// DAA |
F_Out[Flag_H] = F_In[Flag_H]; |
F_Out[Flag_C] = F_In[Flag_C]; |
DAA_Q[7:0] = BusA; |
DAA_Q[8] = 1'b0; |
if (F_In[Flag_N] == 1'b0 ) |
begin |
// After addition |
// Alow > 9 || H == 1 |
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
begin |
if ((DAA_Q[3:0] > 9) ) |
begin |
F_Out[Flag_H] = 1'b1; |
end |
else |
begin |
F_Out[Flag_H] = 1'b0; |
end |
DAA_Q = DAA_Q + 6; |
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
|
// new Ahigh > 9 || C == 1 |
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) |
begin |
DAA_Q = DAA_Q + 96; // 0x60 |
end |
end |
else |
begin |
// After subtraction |
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
begin |
if (DAA_Q[3:0] > 5 ) |
begin |
F_Out[Flag_H] = 1'b0; |
end |
DAA_Q[7:0] = DAA_Q[7:0] - 6; |
end |
if (BusA > 153 || F_In[Flag_C] == 1'b1 ) |
begin |
DAA_Q = DAA_Q - 352; // 0x160 |
end |
end // else: !if(F_In[Flag_N] == 1'b0 ) |
|
F_Out[Flag_X] = DAA_Q[3]; |
F_Out[Flag_Y] = DAA_Q[5]; |
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; |
Q_t = DAA_Q[7:0]; |
|
if (DAA_Q[7:0] == 8'b00000000 ) |
begin |
F_Out[Flag_Z] = 1'b1; |
end |
else |
begin |
F_Out[Flag_Z] = 1'b0; |
end |
|
F_Out[Flag_S] = DAA_Q[7]; |
F_Out[Flag_P] = ~ (^DAA_Q); |
end // case: 4'b1100 |
|
4'b1101, 4'b1110 : |
begin |
// RLD, RRD |
Q_t[7:4] = BusA[7:4]; |
if (ALU_Op[0] == 1'b1 ) |
begin |
Q_t[3:0] = BusB[7:4]; |
end |
else |
begin |
Q_t[3:0] = BusB[3:0]; |
end |
F_Out[Flag_H] = 1'b0; |
F_Out[Flag_N] = 1'b0; |
F_Out[Flag_X] = Q_t[3]; |
F_Out[Flag_Y] = Q_t[5]; |
if (Q_t[7:0] == 8'b00000000 ) |
begin |
F_Out[Flag_Z] = 1'b1; |
end |
else |
begin |
F_Out[Flag_Z] = 1'b0; |
end |
F_Out[Flag_S] = Q_t[7]; |
F_Out[Flag_P] = ~(^Q_t); |
end // case: when 4'b1101, 4'b1110 |
|
4'b1001 : |
begin |
// BIT |
Q_t[7:0] = BusB & BitMask; |
F_Out[Flag_S] = Q_t[7]; |
if (Q_t[7:0] == 8'b00000000 ) |
begin |
F_Out[Flag_Z] = 1'b1; |
F_Out[Flag_P] = 1'b1; |
end |
else |
begin |
F_Out[Flag_Z] = 1'b0; |
F_Out[Flag_P] = 1'b0; |
end |
F_Out[Flag_H] = 1'b1; |
F_Out[Flag_N] = 1'b0; |
F_Out[Flag_X] = 1'b0; |
F_Out[Flag_Y] = 1'b0; |
if (IR[2:0] != 3'b110 ) |
begin |
F_Out[Flag_X] = BusB[3]; |
F_Out[Flag_Y] = BusB[5]; |
end |
end // case: when 4'b1001 |
|
4'b1010 : |
// SET |
Q_t[7:0] = BusB | BitMask; |
|
4'b1011 : |
// RES |
Q_t[7:0] = BusB & ~ BitMask; |
|
4'b1000 : |
begin |
// ROT |
case (IR[5:3]) |
3'b000 : // RLC |
begin |
Q_t[7:1] = BusA[6:0]; |
Q_t[0] = BusA[7]; |
F_Out[Flag_C] = BusA[7]; |
end |
|
3'b010 : // RL |
begin |
Q_t[7:1] = BusA[6:0]; |
Q_t[0] = F_In[Flag_C]; |
F_Out[Flag_C] = BusA[7]; |
end |
|
3'b001 : // RRC |
begin |
Q_t[6:0] = BusA[7:1]; |
Q_t[7] = BusA[0]; |
F_Out[Flag_C] = BusA[0]; |
end |
|
3'b011 : // RR |
begin |
Q_t[6:0] = BusA[7:1]; |
Q_t[7] = F_In[Flag_C]; |
F_Out[Flag_C] = BusA[0]; |
end |
|
3'b100 : // SLA |
begin |
Q_t[7:1] = BusA[6:0]; |
Q_t[0] = 1'b0; |
F_Out[Flag_C] = BusA[7]; |
end |
|
3'b110 : // SLL (Undocumented) / SWAP |
begin |
if (Mode == 3 ) |
begin |
Q_t[7:4] = BusA[3:0]; |
Q_t[3:0] = BusA[7:4]; |
F_Out[Flag_C] = 1'b0; |
end |
else |
begin |
Q_t[7:1] = BusA[6:0]; |
Q_t[0] = 1'b1; |
F_Out[Flag_C] = BusA[7]; |
end // else: !if(Mode == 3 ) |
end // case: 3'b110 |
|
3'b101 : // SRA |
begin |
Q_t[6:0] = BusA[7:1]; |
Q_t[7] = BusA[7]; |
F_Out[Flag_C] = BusA[0]; |
end |
|
default : // SRL |
begin |
Q_t[6:0] = BusA[7:1]; |
Q_t[7] = 1'b0; |
F_Out[Flag_C] = BusA[0]; |
end |
endcase // case(IR[5:3]) |
|
F_Out[Flag_H] = 1'b0; |
F_Out[Flag_N] = 1'b0; |
F_Out[Flag_X] = Q_t[3]; |
F_Out[Flag_Y] = Q_t[5]; |
F_Out[Flag_S] = Q_t[7]; |
if (Q_t[7:0] == 8'b00000000 ) |
begin |
F_Out[Flag_Z] = 1'b1; |
end |
else |
begin |
F_Out[Flag_Z] = 1'b0; |
end |
F_Out[Flag_P] = ~(^Q_t); |
|
if (ISet == 2'b00 ) |
begin |
F_Out[Flag_P] = F_In[Flag_P]; |
F_Out[Flag_S] = F_In[Flag_S]; |
F_Out[Flag_Z] = F_In[Flag_Z]; |
end |
end // case: 4'b1000 |
|
|
default : |
; |
|
endcase // case(ALU_Op) |
|
Q = Q_t; |
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) |
|
endmodule // T80_ALU |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/rom.mif
0,0 → 1,16384
11110011 |
10101111 |
00010001 |
11111111 |
11111111 |
11000011 |
11001011 |
00010001 |
00101010 |
01011101 |
01011100 |
00100010 |
01011111 |
01011100 |
00011000 |
01000011 |
11000011 |
11110010 |
00010101 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
00101010 |
01011101 |
01011100 |
01111110 |
11001101 |
01111101 |
00000000 |
11010000 |
11001101 |
01110100 |
00000000 |
00011000 |
11110111 |
11111111 |
11111111 |
11111111 |
11000011 |
01011011 |
00110011 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11000101 |
00101010 |
01100001 |
01011100 |
11100101 |
11000011 |
10011110 |
00010110 |
11110101 |
11100101 |
00101010 |
01111000 |
01011100 |
00100011 |
00100010 |
01111000 |
01011100 |
01111100 |
10110101 |
00100000 |
00000011 |
11111101 |
00110100 |
01000000 |
11000101 |
11010101 |
11001101 |
10111111 |
00000010 |
11010001 |
11000001 |
11100001 |
11110001 |
11111011 |
11001001 |
11100001 |
01101110 |
11111101 |
01110101 |
00000000 |
11101101 |
01111011 |
00111101 |
01011100 |
11000011 |
11000101 |
00010110 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11110101 |
11100101 |
00101010 |
10110000 |
01011100 |
01111100 |
10110101 |
00100000 |
00000001 |
11101001 |
11100001 |
11110001 |
11101101 |
01000101 |
00101010 |
01011101 |
01011100 |
00100011 |
00100010 |
01011101 |
01011100 |
01111110 |
11001001 |
11111110 |
00100001 |
11010000 |
11111110 |
00001101 |
11001000 |
11111110 |
00010000 |
11011000 |
11111110 |
00011000 |
00111111 |
11011000 |
00100011 |
11111110 |
00010110 |
00111000 |
00000001 |
00100011 |
00110111 |
00100010 |
01011101 |
01011100 |
11001001 |
10111111 |
01010010 |
01001110 |
11000100 |
01001001 |
01001110 |
01001011 |
01000101 |
01011001 |
10100100 |
01010000 |
11001001 |
01000110 |
11001110 |
01010000 |
01001111 |
01001001 |
01001110 |
11010100 |
01010011 |
01000011 |
01010010 |
01000101 |
01000101 |
01001110 |
10100100 |
01000001 |
01010100 |
01010100 |
11010010 |
01000001 |
11010100 |
01010100 |
01000001 |
11000010 |
01010110 |
01000001 |
01001100 |
10100100 |
01000011 |
01001111 |
01000100 |
11000101 |
01010110 |
01000001 |
11001100 |
01001100 |
01000101 |
11001110 |
01010011 |
01001001 |
11001110 |
01000011 |
01001111 |
11010011 |
01010100 |
01000001 |
11001110 |
01000001 |
01010011 |
11001110 |
01000001 |
01000011 |
11010011 |
01000001 |
01010100 |
11001110 |
01001100 |
11001110 |
01000101 |
01011000 |
11010000 |
01001001 |
01001110 |
11010100 |
01010011 |
01010001 |
11010010 |
01010011 |
01000111 |
11001110 |
01000001 |
01000010 |
11010011 |
01010000 |
01000101 |
01000101 |
11001011 |
01001001 |
11001110 |
01010101 |
01010011 |
11010010 |
01010011 |
01010100 |
01010010 |
10100100 |
01000011 |
01001000 |
01010010 |
10100100 |
01001110 |
01001111 |
11010100 |
01000010 |
01001001 |
11001110 |
01001111 |
11010010 |
01000001 |
01001110 |
11000100 |
00111100 |
10111101 |
00111110 |
10111101 |
00111100 |
10111110 |
01001100 |
01001001 |
01001110 |
11000101 |
01010100 |
01001000 |
01000101 |
11001110 |
01010100 |
11001111 |
01010011 |
01010100 |
01000101 |
11010000 |
01000100 |
01000101 |
01000110 |
00100000 |
01000110 |
11001110 |
01000011 |
01000001 |
11010100 |
01000110 |
01001111 |
01010010 |
01001101 |
01000001 |
11010100 |
01001101 |
01001111 |
01010110 |
11000101 |
01000101 |
01010010 |
01000001 |
01010011 |
11000101 |
01001111 |
01010000 |
01000101 |
01001110 |
00100000 |
10100011 |
01000011 |
01001100 |
01001111 |
01010011 |
01000101 |
00100000 |
10100011 |
01001101 |
01000101 |
01010010 |
01000111 |
11000101 |
01010110 |
01000101 |
01010010 |
01001001 |
01000110 |
11011001 |
01000010 |
01000101 |
01000101 |
11010000 |
01000011 |
01001001 |
01010010 |
01000011 |
01001100 |
11000101 |
01001001 |
01001110 |
11001011 |
01010000 |
01000001 |
01010000 |
01000101 |
11010010 |
01000110 |
01001100 |
01000001 |
01010011 |
11001000 |
01000010 |
01010010 |
01001001 |
01000111 |
01001000 |
11010100 |
01001001 |
01001110 |
01010110 |
01000101 |
01010010 |
01010011 |
11000101 |
01001111 |
01010110 |
01000101 |
11010010 |
01001111 |
01010101 |
11010100 |
01001100 |
01010000 |
01010010 |
01001001 |
01001110 |
11010100 |
01001100 |
01001100 |
01001001 |
01010011 |
11010100 |
01010011 |
01010100 |
01001111 |
11010000 |
01010010 |
01000101 |
01000001 |
11000100 |
01000100 |
01000001 |
01010100 |
11000001 |
01010010 |
01000101 |
01010011 |
01010100 |
01001111 |
01010010 |
11000101 |
01001110 |
01000101 |
11010111 |
01000010 |
01001111 |
01010010 |
01000100 |
01000101 |
11010010 |
01000011 |
01001111 |
01001110 |
01010100 |
01001001 |
01001110 |
01010101 |
11000101 |
01000100 |
01001001 |
11001101 |
01010010 |
01000101 |
11001101 |
01000110 |
01001111 |
11010010 |
01000111 |
01001111 |
00100000 |
01010100 |
11001111 |
01000111 |
01001111 |
00100000 |
01010011 |
01010101 |
11000010 |
01001001 |
01001110 |
01010000 |
01010101 |
11010100 |
01001100 |
01001111 |
01000001 |
11000100 |
01001100 |
01001001 |
01010011 |
11010100 |
01001100 |
01000101 |
11010100 |
01010000 |
01000001 |
01010101 |
01010011 |
11000101 |
01001110 |
01000101 |
01011000 |
11010100 |
01010000 |
01001111 |
01001011 |
11000101 |
01010000 |
01010010 |
01001001 |
01001110 |
11010100 |
01010000 |
01001100 |
01001111 |
11010100 |
01010010 |
01010101 |
11001110 |
01010011 |
01000001 |
01010110 |
11000101 |
01010010 |
01000001 |
01001110 |
01000100 |
01001111 |
01001101 |
01001001 |
01011010 |
11000101 |
01001001 |
11000110 |
01000011 |
01001100 |
11010011 |
01000100 |
01010010 |
01000001 |
11010111 |
01000011 |
01001100 |
01000101 |
01000001 |
11010010 |
01010010 |
01000101 |
01010100 |
01010101 |
01010010 |
11001110 |
01000011 |
01001111 |
01010000 |
11011001 |
01000010 |
01001000 |
01011001 |
00110110 |
00110101 |
01010100 |
01000111 |
01010110 |
01001110 |
01001010 |
01010101 |
00110111 |
00110100 |
01010010 |
01000110 |
01000011 |
01001101 |
01001011 |
01001001 |
00111000 |
00110011 |
01000101 |
01000100 |
01011000 |
00001110 |
01001100 |
01001111 |
00111001 |
00110010 |
01010111 |
01010011 |
01011010 |
00100000 |
00001101 |
01010000 |
00110000 |
00110001 |
01010001 |
01000001 |
11100011 |
11000100 |
11100000 |
11100100 |
10110100 |
10111100 |
10111101 |
10111011 |
10101111 |
10110000 |
10110001 |
11000000 |
10100111 |
10100110 |
10111110 |
10101101 |
10110010 |
10111010 |
11100101 |
10100101 |
11000010 |
11100001 |
10110011 |
10111001 |
11000001 |
10111000 |
01111110 |
11011100 |
11011010 |
01011100 |
10110111 |
01111011 |
01111101 |
11011000 |
10111111 |
10101110 |
10101010 |
10101011 |
11011101 |
11011110 |
11011111 |
01111111 |
10110101 |
11010110 |
01111100 |
11010101 |
01011101 |
11011011 |
10110110 |
11011001 |
01011011 |
11010111 |
00001100 |
00000111 |
00000110 |
00000100 |
00000101 |
00001000 |
00001010 |
00001011 |
00001001 |
00001111 |
11100010 |
00101010 |
00111111 |
11001101 |
11001000 |
11001100 |
11001011 |
01011110 |
10101100 |
00101101 |
00101011 |
00111101 |
00101110 |
00101100 |
00111011 |
00100010 |
11000111 |
00111100 |
11000011 |
00111110 |
11000101 |
00101111 |
11001001 |
01100000 |
11000110 |
00111010 |
11010000 |
11001110 |
10101000 |
11001010 |
11010011 |
11010100 |
11010001 |
11010010 |
10101001 |
11001111 |
00101110 |
00101111 |
00010001 |
11111111 |
11111111 |
00000001 |
11111110 |
11111110 |
11101101 |
01111000 |
00101111 |
11100110 |
00011111 |
00101000 |
00001110 |
01100111 |
01111101 |
00010100 |
11000000 |
11010110 |
00001000 |
11001011 |
00111100 |
00110000 |
11111010 |
01010011 |
01011111 |
00100000 |
11110100 |
00101101 |
11001011 |
00000000 |
00111000 |
11100110 |
01111010 |
00111100 |
11001000 |
11111110 |
00101000 |
11001000 |
11111110 |
00011001 |
11001000 |
01111011 |
01011010 |
01010111 |
11111110 |
00011000 |
11001001 |
11001101 |
10001110 |
00000010 |
11000000 |
00100001 |
00000000 |
01011100 |
11001011 |
01111110 |
00100000 |
00000111 |
00100011 |
00110101 |
00101011 |
00100000 |
00000010 |
00110110 |
11111111 |
01111101 |
00100001 |
00000100 |
01011100 |
10111101 |
00100000 |
11101110 |
11001101 |
00011110 |
00000011 |
11010000 |
00100001 |
00000000 |
01011100 |
10111110 |
00101000 |
00101110 |
11101011 |
00100001 |
00000100 |
01011100 |
10111110 |
00101000 |
00100111 |
11001011 |
01111110 |
00100000 |
00000100 |
11101011 |
11001011 |
01111110 |
11001000 |
01011111 |
01110111 |
00100011 |
00110110 |
00000101 |
00100011 |
00111010 |
00001001 |
01011100 |
01110111 |
00100011 |
11111101 |
01001110 |
00000111 |
11111101 |
01010110 |
00000001 |
11100101 |
11001101 |
00110011 |
00000011 |
11100001 |
01110111 |
00110010 |
00001000 |
01011100 |
11111101 |
11001011 |
00000001 |
11101110 |
11001001 |
00100011 |
00110110 |
00000101 |
00100011 |
00110101 |
11000000 |
00111010 |
00001010 |
01011100 |
01110111 |
00100011 |
01111110 |
00011000 |
11101010 |
01000010 |
00010110 |
00000000 |
01111011 |
11111110 |
00100111 |
11010000 |
11111110 |
00011000 |
00100000 |
00000011 |
11001011 |
01111000 |
11000000 |
00100001 |
00000101 |
00000010 |
00011001 |
01111110 |
00110111 |
11001001 |
01111011 |
11111110 |
00111010 |
00111000 |
00101111 |
00001101 |
11111010 |
01001111 |
00000011 |
00101000 |
00000011 |
11000110 |
01001111 |
11001001 |
00100001 |
11101011 |
00000001 |
00000100 |
00101000 |
00000011 |
00100001 |
00000101 |
00000010 |
00010110 |
00000000 |
00011001 |
01111110 |
11001001 |
00100001 |
00101001 |
00000010 |
11001011 |
01000000 |
00101000 |
11110100 |
11001011 |
01011010 |
00101000 |
00001010 |
11111101 |
11001011 |
00110000 |
01011110 |
11000000 |
00000100 |
11000000 |
11000110 |
00100000 |
11001001 |
11000110 |
10100101 |
11001001 |
11111110 |
00110000 |
11011000 |
00001101 |
11111010 |
10011101 |
00000011 |
00100000 |
00011001 |
00100001 |
01010100 |
00000010 |
11001011 |
01101000 |
00101000 |
11010011 |
11111110 |
00111000 |
00110000 |
00000111 |
11010110 |
00100000 |
00000100 |
11001000 |
11000110 |
00001000 |
11001001 |
11010110 |
00110110 |
00000100 |
11001000 |
11000110 |
11111110 |
11001001 |
00100001 |
00110000 |
00000010 |
11111110 |
00111001 |
00101000 |
10111010 |
11111110 |
00110000 |
00101000 |
10110110 |
11100110 |
00000111 |
11000110 |
10000000 |
00000100 |
11001000 |
11101110 |
00001111 |
11001001 |
00000100 |
11001000 |
11001011 |
01101000 |
00100001 |
00110000 |
00000010 |
00100000 |
10100100 |
11010110 |
00010000 |
11111110 |
00100010 |
00101000 |
00000110 |
11111110 |
00100000 |
11000000 |
00111110 |
01011111 |
11001001 |
00111110 |
01000000 |
11001001 |
11110011 |
01111101 |
11001011 |
00111101 |
11001011 |
00111101 |
00101111 |
11100110 |
00000011 |
01001111 |
00000110 |
00000000 |
11011101 |
00100001 |
11010001 |
00000011 |
11011101 |
00001001 |
00111010 |
01001000 |
01011100 |
11100110 |
00111000 |
00001111 |
00001111 |
00001111 |
11110110 |
00001000 |
00000000 |
00000000 |
00000000 |
00000100 |
00001100 |
00001101 |
00100000 |
11111101 |
00001110 |
00111111 |
00000101 |
11000010 |
11010110 |
00000011 |
11101110 |
00010000 |
11010011 |
11111110 |
01000100 |
01001111 |
11001011 |
01100111 |
00100000 |
00001001 |
01111010 |
10110011 |
00101000 |
00001001 |
01111001 |
01001101 |
00011011 |
11011101 |
11101001 |
01001101 |
00001100 |
11011101 |
11101001 |
11111011 |
11001001 |
11101111 |
00110001 |
00100111 |
11000000 |
00000011 |
00110100 |
11101100 |
01101100 |
10011000 |
00011111 |
11110101 |
00000100 |
10100001 |
00001111 |
00111000 |
00100001 |
10010010 |
01011100 |
01111110 |
10100111 |
00100000 |
01011110 |
00100011 |
01001110 |
00100011 |
01000110 |
01111000 |
00010111 |
10011111 |
10111001 |
00100000 |
01010100 |
00100011 |
10111110 |
00100000 |
01010000 |
01111000 |
11000110 |
00111100 |
11110010 |
00100101 |
00000100 |
11100010 |
01101100 |
00000100 |
00000110 |
11111010 |
00000100 |
11010110 |
00001100 |
00110000 |
11111011 |
11000110 |
00001100 |
11000101 |
00100001 |
01101110 |
00000100 |
11001101 |
00000110 |
00110100 |
11001101 |
10110100 |
00110011 |
11101111 |
00000100 |
00111000 |
11110001 |
10000110 |
01110111 |
11101111 |
11000000 |
00000010 |
00110001 |
00111000 |
11001101 |
10010100 |
00011110 |
11111110 |
00001011 |
00110000 |
00100010 |
11101111 |
11100000 |
00000100 |
11100000 |
00110100 |
10000000 |
01000011 |
01010101 |
10011111 |
10000000 |
00000001 |
00000101 |
00110100 |
00110101 |
01110001 |
00000011 |
00111000 |
11001101 |
10011001 |
00011110 |
11000101 |
11001101 |
10011001 |
00011110 |
11100001 |
01010000 |
01011001 |
01111010 |
10110011 |
11001000 |
00011011 |
11000011 |
10110101 |
00000011 |
11001111 |
00001010 |
10001001 |
00000010 |
11010000 |
00010010 |
10000110 |
10001001 |
00001010 |
10010111 |
01100000 |
01110101 |
10001001 |
00010010 |
11010101 |
00010111 |
00011111 |
10001001 |
00011011 |
10010000 |
01000001 |
00000010 |
10001001 |
00100100 |
11010000 |
01010011 |
11001010 |
10001001 |
00101110 |
10011101 |
00110110 |
10110001 |
10001001 |
00111000 |
11111111 |
01001001 |
00111110 |
10001001 |
01000011 |
11111111 |
01101010 |
01110011 |
10001001 |
01001111 |
10100111 |
00000000 |
01010100 |
10001001 |
01011100 |
00000000 |
00000000 |
00000000 |
10001001 |
01101001 |
00010100 |
11110110 |
00100100 |
10001001 |
01110110 |
11110001 |
00010000 |
00000101 |
11001101 |
11111011 |
00100100 |
00111010 |
00111011 |
01011100 |
10000111 |
11111010 |
10001010 |
00011100 |
11100001 |
11010000 |
11100101 |
11001101 |
11110001 |
00101011 |
01100010 |
01101011 |
00001101 |
11111000 |
00001001 |
11001011 |
11111110 |
11001001 |
00100001 |
00111111 |
00000101 |
11100101 |
00100001 |
10000000 |
00011111 |
11001011 |
01111111 |
00101000 |
00000011 |
00100001 |
10011000 |
00001100 |
00001000 |
00010011 |
11011101 |
00101011 |
11110011 |
00111110 |
00000010 |
01000111 |
00010000 |
11111110 |
11010011 |
11111110 |
11101110 |
00001111 |
00000110 |
10100100 |
00101101 |
00100000 |
11110101 |
00000101 |
00100101 |
11110010 |
11011000 |
00000100 |
00000110 |
00101111 |
00010000 |
11111110 |
11010011 |
11111110 |
00111110 |
00001101 |
00000110 |
00110111 |
00010000 |
11111110 |
11010011 |
11111110 |
00000001 |
00001110 |
00111011 |
00001000 |
01101111 |
11000011 |
00000111 |
00000101 |
01111010 |
10110011 |
00101000 |
00001100 |
11011101 |
01101110 |
00000000 |
01111100 |
10101101 |
01100111 |
00111110 |
00000001 |
00110111 |
11000011 |
00100101 |
00000101 |
01101100 |
00011000 |
11110100 |
01111001 |
11001011 |
01111000 |
00010000 |
11111110 |
00110000 |
00000100 |
00000110 |
01000010 |
00010000 |
11111110 |
11010011 |
11111110 |
00000110 |
00111110 |
00100000 |
11101111 |
00000101 |
10101111 |
00111100 |
11001011 |
00010101 |
11000010 |
00010100 |
00000101 |
00011011 |
11011101 |
00100011 |
00000110 |
00110001 |
00111110 |
01111111 |
11011011 |
11111110 |
00011111 |
11010000 |
01111010 |
00111100 |
11000010 |
11111110 |
00000100 |
00000110 |
00111011 |
00010000 |
11111110 |
11001001 |
11110101 |
00111010 |
01001000 |
01011100 |
11100110 |
00111000 |
00001111 |
00001111 |
00001111 |
11010011 |
11111110 |
00111110 |
01111111 |
11011011 |
11111110 |
00011111 |
11111011 |
00111000 |
00000010 |
11001111 |
00001100 |
11110001 |
11001001 |
00010100 |
00001000 |
00010101 |
11110011 |
00111110 |
00001111 |
11010011 |
11111110 |
00100001 |
00111111 |
00000101 |
11100101 |
11011011 |
11111110 |
00011111 |
11100110 |
00100000 |
11110110 |
00000010 |
01001111 |
10111111 |
11000000 |
11001101 |
11100111 |
00000101 |
00110000 |
11111010 |
00100001 |
00010101 |
00000100 |
00010000 |
11111110 |
00101011 |
01111100 |
10110101 |
00100000 |
11111001 |
11001101 |
11100011 |
00000101 |
00110000 |
11101011 |
00000110 |
10011100 |
11001101 |
11100011 |
00000101 |
00110000 |
11100100 |
00111110 |
11000110 |
10111000 |
00110000 |
11100000 |
00100100 |
00100000 |
11110001 |
00000110 |
11001001 |
11001101 |
11100111 |
00000101 |
00110000 |
11010101 |
01111000 |
11111110 |
11010100 |
00110000 |
11110100 |
11001101 |
11100111 |
00000101 |
11010000 |
01111001 |
11101110 |
00000011 |
01001111 |
00100110 |
00000000 |
00000110 |
10110000 |
00011000 |
00011111 |
00001000 |
00100000 |
00000111 |
00110000 |
00001111 |
11011101 |
01110101 |
00000000 |
00011000 |
00001111 |
11001011 |
00010001 |
10101101 |
11000000 |
01111001 |
00011111 |
01001111 |
00010011 |
00011000 |
00000111 |
11011101 |
01111110 |
00000000 |
10101101 |
11000000 |
11011101 |
00100011 |
00011011 |
00001000 |
00000110 |
10110010 |
00101110 |
00000001 |
11001101 |
11100011 |
00000101 |
11010000 |
00111110 |
11001011 |
10111000 |
11001011 |
00010101 |
00000110 |
10110000 |
11010010 |
11001010 |
00000101 |
01111100 |
10101101 |
01100111 |
01111010 |
10110011 |
00100000 |
11001010 |
01111100 |
11111110 |
00000001 |
11001001 |
11001101 |
11100111 |
00000101 |
11010000 |
00111110 |
00010110 |
00111101 |
00100000 |
11111101 |
10100111 |
00000100 |
11001000 |
00111110 |
01111111 |
11011011 |
11111110 |
00011111 |
11010000 |
10101001 |
11100110 |
00100000 |
00101000 |
11110011 |
01111001 |
00101111 |
01001111 |
11100110 |
00000111 |
11110110 |
00001000 |
11010011 |
11111110 |
00110111 |
11001001 |
11110001 |
00111010 |
01110100 |
01011100 |
11010110 |
11100000 |
00110010 |
01110100 |
01011100 |
11001101 |
10001100 |
00011100 |
11001101 |
00110000 |
00100101 |
00101000 |
00111100 |
00000001 |
00010001 |
00000000 |
00111010 |
01110100 |
01011100 |
10100111 |
00101000 |
00000010 |
00001110 |
00100010 |
11110111 |
11010101 |
11011101 |
11100001 |
00000110 |
00001011 |
00111110 |
00100000 |
00010010 |
00010011 |
00010000 |
11111100 |
11011101 |
00110110 |
00000001 |
11111111 |
11001101 |
11110001 |
00101011 |
00100001 |
11110110 |
11111111 |
00001011 |
00001001 |
00000011 |
00110000 |
00001111 |
00111010 |
01110100 |
01011100 |
10100111 |
00100000 |
00000010 |
11001111 |
00001110 |
01111000 |
10110001 |
00101000 |
00001010 |
00000001 |
00001010 |
00000000 |
11011101 |
11100101 |
11100001 |
00100011 |
11101011 |
11101101 |
10110000 |
11011111 |
11111110 |
11100100 |
00100000 |
01001001 |
00111010 |
01110100 |
01011100 |
11111110 |
00000011 |
11001010 |
10001010 |
00011100 |
11100111 |
11001101 |
10110010 |
00101000 |
11001011 |
11111001 |
00110000 |
00001011 |
00100001 |
00000000 |
00000000 |
00111010 |
01110100 |
01011100 |
00111101 |
00101000 |
00010101 |
11001111 |
00000001 |
11000010 |
10001010 |
00011100 |
11001101 |
00110000 |
00100101 |
00101000 |
00011000 |
00100011 |
01111110 |
11011101 |
01110111 |
00001011 |
00100011 |
01111110 |
11011101 |
01110111 |
00001100 |
00100011 |
11011101 |
01110001 |
00001110 |
00111110 |
00000001 |
11001011 |
01110001 |
00101000 |
00000001 |
00111100 |
11011101 |
01110111 |
00000000 |
11101011 |
11100111 |
11111110 |
00101001 |
00100000 |
11011010 |
11100111 |
11001101 |
11101110 |
00011011 |
11101011 |
11000011 |
01011010 |
00000111 |
11111110 |
10101010 |
00100000 |
00011111 |
00111010 |
01110100 |
01011100 |
11111110 |
00000011 |
11001010 |
10001010 |
00011100 |
11100111 |
11001101 |
11101110 |
00011011 |
11011101 |
00110110 |
00001011 |
00000000 |
11011101 |
00110110 |
00001100 |
00011011 |
00100001 |
00000000 |
01000000 |
11011101 |
01110101 |
00001101 |
11011101 |
01110100 |
00001110 |
00011000 |
01001101 |
11111110 |
10101111 |
00100000 |
01001111 |
00111010 |
01110100 |
01011100 |
11111110 |
00000011 |
11001010 |
10001010 |
00011100 |
11100111 |
11001101 |
01001000 |
00100000 |
00100000 |
00001100 |
00111010 |
01110100 |
01011100 |
10100111 |
11001010 |
10001010 |
00011100 |
11001101 |
11100110 |
00011100 |
00011000 |
00001111 |
11001101 |
10000010 |
00011100 |
11011111 |
11111110 |
00101100 |
00101000 |
00001100 |
00111010 |
01110100 |
01011100 |
10100111 |
11001010 |
10001010 |
00011100 |
11001101 |
11100110 |
00011100 |
00011000 |
00000100 |
11100111 |
11001101 |
10000010 |
00011100 |
11001101 |
11101110 |
00011011 |
11001101 |
10011001 |
00011110 |
11011101 |
01110001 |
00001011 |
11011101 |
01110000 |
00001100 |
11001101 |
10011001 |
00011110 |
11011101 |
01110001 |
00001101 |
11011101 |
01110000 |
00001110 |
01100000 |
01101001 |
11011101 |
00110110 |
00000000 |
00000011 |
00011000 |
01000100 |
11111110 |
11001010 |
00101000 |
00001001 |
11001101 |
11101110 |
00011011 |
11011101 |
00110110 |
00001110 |
10000000 |
00011000 |
00010111 |
00111010 |
01110100 |
01011100 |
10100111 |
11000010 |
10001010 |
00011100 |
11100111 |
11001101 |
10000010 |
00011100 |
11001101 |
11101110 |
00011011 |
11001101 |
10011001 |
00011110 |
11011101 |
01110001 |
00001101 |
11011101 |
01110000 |
00001110 |
11011101 |
00110110 |
00000000 |
00000000 |
00101010 |
01011001 |
01011100 |
11101101 |
01011011 |
01010011 |
01011100 |
00110111 |
11101101 |
01010010 |
11011101 |
01110101 |
00001011 |
11011101 |
01110100 |
00001100 |
00101010 |
01001011 |
01011100 |
11101101 |
01010010 |
11011101 |
01110101 |
00001111 |
11011101 |
01110100 |
00010000 |
11101011 |
00111010 |
01110100 |
01011100 |
10100111 |
11001010 |
01110000 |
00001001 |
11100101 |
00000001 |
00010001 |
00000000 |
11011101 |
00001001 |
11011101 |
11100101 |
00010001 |
00010001 |
00000000 |
10101111 |
00110111 |
11001101 |
01010110 |
00000101 |
11011101 |
11100001 |
00110000 |
11110010 |
00111110 |
11111110 |
11001101 |
00000001 |
00010110 |
11111101 |
00110110 |
01010010 |
00000011 |
00001110 |
10000000 |
11011101 |
01111110 |
00000000 |
11011101 |
10111110 |
11101111 |
00100000 |
00000010 |
00001110 |
11110110 |
11111110 |
00000100 |
00110000 |
11011001 |
00010001 |
11000000 |
00001001 |
11000101 |
11001101 |
00001010 |
00001100 |
11000001 |
11011101 |
11100101 |
11010001 |
00100001 |
11110000 |
11111111 |
00011001 |
00000110 |
00001010 |
01111110 |
00111100 |
00100000 |
00000011 |
01111001 |
10000000 |
01001111 |
00010011 |
00011010 |
10111110 |
00100011 |
00100000 |
00000001 |
00001100 |
11010111 |
00010000 |
11110110 |
11001011 |
01111001 |
00100000 |
10110011 |
00111110 |
00001101 |
11010111 |
11100001 |
11011101 |
01111110 |
00000000 |
11111110 |
00000011 |
00101000 |
00001100 |
00111010 |
01110100 |
01011100 |
00111101 |
11001010 |
00001000 |
00001000 |
11111110 |
00000010 |
11001010 |
10110110 |
00001000 |
11100101 |
11011101 |
01101110 |
11111010 |
11011101 |
01100110 |
11111011 |
11011101 |
01011110 |
00001011 |
11011101 |
01010110 |
00001100 |
01111100 |
10110101 |
00101000 |
00001101 |
11101101 |
01010010 |
00111000 |
00100110 |
00101000 |
00000111 |
11011101 |
01111110 |
00000000 |
11111110 |
00000011 |
00100000 |
00011101 |
11100001 |
01111100 |
10110101 |
00100000 |
00000110 |
11011101 |
01101110 |
00001101 |
11011101 |
01100110 |
00001110 |
11100101 |
11011101 |
11100001 |
00111010 |
01110100 |
01011100 |
11111110 |
00000010 |
00110111 |
00100000 |
00000001 |
10100111 |
00111110 |
11111111 |
11001101 |
01010110 |
00000101 |
11011000 |
11001111 |
00011010 |
11011101 |
01011110 |
00001011 |
11011101 |
01010110 |
00001100 |
11100101 |
01111100 |
10110101 |
00100000 |
00000110 |
00010011 |
00010011 |
00010011 |
11101011 |
00011000 |
00001100 |
11011101 |
01101110 |
11111010 |
11011101 |
01100110 |
11111011 |
11101011 |
00110111 |
11101101 |
01010010 |
00111000 |
00001001 |
00010001 |
00000101 |
00000000 |
00011001 |
01000100 |
01001101 |
11001101 |
00000101 |
00011111 |
11100001 |
11011101 |
01111110 |
00000000 |
10100111 |
00101000 |
00111110 |
01111100 |
10110101 |
00101000 |
00010011 |
00101011 |
01000110 |
00101011 |
01001110 |
00101011 |
00000011 |
00000011 |
00000011 |
11011101 |
00100010 |
01011111 |
01011100 |
11001101 |
11101000 |
00011001 |
11011101 |
00101010 |
01011111 |
01011100 |
00101010 |
01011001 |
01011100 |
00101011 |
11011101 |
01001110 |
00001011 |
11011101 |
01000110 |
00001100 |
11000101 |
00000011 |
00000011 |
00000011 |
11011101 |
01111110 |
11111101 |
11110101 |
11001101 |
01010101 |
00010110 |
00100011 |
11110001 |
01110111 |
11010001 |
00100011 |
01110011 |
00100011 |
01110010 |
00100011 |
11100101 |
11011101 |
11100001 |
00110111 |
00111110 |
11111111 |
11000011 |
00000010 |
00001000 |
11101011 |
00101010 |
01011001 |
01011100 |
00101011 |
11011101 |
00100010 |
01011111 |
01011100 |
11011101 |
01001110 |
00001011 |
11011101 |
01000110 |
00001100 |
11000101 |
11001101 |
11100101 |
00011001 |
11000001 |
11100101 |
11000101 |
11001101 |
01010101 |
00010110 |
11011101 |
00101010 |
01011111 |
01011100 |
00100011 |
11011101 |
01001110 |
00001111 |
11011101 |
01000110 |
00010000 |
00001001 |
00100010 |
01001011 |
01011100 |
11011101 |
01100110 |
00001110 |
01111100 |
11100110 |
11000000 |
00100000 |
00001010 |
11011101 |
01101110 |
00001101 |
00100010 |
01000010 |
01011100 |
11111101 |
00110110 |
00001010 |
00000000 |
11010001 |
11011101 |
11100001 |
00110111 |
00111110 |
11111111 |
11000011 |
00000010 |
00001000 |
11011101 |
01001110 |
00001011 |
11011101 |
01000110 |
00001100 |
11000101 |
00000011 |
11110111 |
00110110 |
10000000 |
11101011 |
11010001 |
11100101 |
11100101 |
11011101 |
11100001 |
00110111 |
00111110 |
11111111 |
11001101 |
00000010 |
00001000 |
11100001 |
11101101 |
01011011 |
01010011 |
01011100 |
01111110 |
11100110 |
11000000 |
00100000 |
00011001 |
00011010 |
00010011 |
10111110 |
00100011 |
00100000 |
00000010 |
00011010 |
10111110 |
00011011 |
00101011 |
00110000 |
00001000 |
11100101 |
11101011 |
11001101 |
10111000 |
00011001 |
11100001 |
00011000 |
11101100 |
11001101 |
00101100 |
00001001 |
00011000 |
11100010 |
01111110 |
01001111 |
11111110 |
10000000 |
11001000 |
11100101 |
00101010 |
01001011 |
01011100 |
01111110 |
11111110 |
10000000 |
00101000 |
00100101 |
10111001 |
00101000 |
00001000 |
11000101 |
11001101 |
10111000 |
00011001 |
11000001 |
11101011 |
00011000 |
11110000 |
11100110 |
11100000 |
11111110 |
10100000 |
00100000 |
00010010 |
11010001 |
11010101 |
11100101 |
00100011 |
00010011 |
00011010 |
10111110 |
00100000 |
00000110 |
00010111 |
00110000 |
11110111 |
11100001 |
00011000 |
00000011 |
11100001 |
00011000 |
11100000 |
00111110 |
11111111 |
11010001 |
11101011 |
00111100 |
00110111 |
11001101 |
00101100 |
00001001 |
00011000 |
11000100 |
00100000 |
00010000 |
00001000 |
00100010 |
01011111 |
01011100 |
11101011 |
11001101 |
10111000 |
00011001 |
11001101 |
11101000 |
00011001 |
11101011 |
00101010 |
01011111 |
01011100 |
00001000 |
00001000 |
11010101 |
11001101 |
10111000 |
00011001 |
00100010 |
01011111 |
01011100 |
00101010 |
01010011 |
01011100 |
11100011 |
11000101 |
00001000 |
00111000 |
00000111 |
00101011 |
11001101 |
01010101 |
00010110 |
00100011 |
00011000 |
00000011 |
11001101 |
01010101 |
00010110 |
00100011 |
11000001 |
11010001 |
11101101 |
01010011 |
01010011 |
01011100 |
11101101 |
01011011 |
01011111 |
01011100 |
11000101 |
11010101 |
11101011 |
11101101 |
10110000 |
11100001 |
11000001 |
11010101 |
11001101 |
11101000 |
00011001 |
11010001 |
11001001 |
11100101 |
00111110 |
11111101 |
11001101 |
00000001 |
00010110 |
10101111 |
00010001 |
10100001 |
00001001 |
11001101 |
00001010 |
00001100 |
11111101 |
11001011 |
00000010 |
11101110 |
11001101 |
11010100 |
00010101 |
11011101 |
11100101 |
00010001 |
00010001 |
00000000 |
10101111 |
11001101 |
11000010 |
00000100 |
11011101 |
11100001 |
00000110 |
00110010 |
01110110 |
00010000 |
11111101 |
11011101 |
01011110 |
00001011 |
11011101 |
01010110 |
00001100 |
00111110 |
11111111 |
11011101 |
11100001 |
11000011 |
11000010 |
00000100 |
10000000 |
01010011 |
01110100 |
01100001 |
01110010 |
01110100 |
00100000 |
01110100 |
01100001 |
01110000 |
01100101 |
00101100 |
00100000 |
01110100 |
01101000 |
01100101 |
01101110 |
00100000 |
01110000 |
01110010 |
01100101 |
01110011 |
01110011 |
00100000 |
01100001 |
01101110 |
01111001 |
00100000 |
01101011 |
01100101 |
01111001 |
10101110 |
00001101 |
01010000 |
01110010 |
01101111 |
01100111 |
01110010 |
01100001 |
01101101 |
00111010 |
10100000 |
00001101 |
01001110 |
01110101 |
01101101 |
01100010 |
01100101 |
01110010 |
00100000 |
01100001 |
01110010 |
01110010 |
01100001 |
01111001 |
00111010 |
10100000 |
00001101 |
01000011 |
01101000 |
01100001 |
01110010 |
01100001 |
01100011 |
01110100 |
01100101 |
01110010 |
00100000 |
01100001 |
01110010 |
01110010 |
01100001 |
01111001 |
00111010 |
10100000 |
00001101 |
01000010 |
01111001 |
01110100 |
01100101 |
01110011 |
00111010 |
10100000 |
11001101 |
00000011 |
00001011 |
11111110 |
00100000 |
11010010 |
11011001 |
00001010 |
11111110 |
00000110 |
00111000 |
01101001 |
11111110 |
00011000 |
00110000 |
01100101 |
00100001 |
00001011 |
00001010 |
01011111 |
00010110 |
00000000 |
00011001 |
01011110 |
00011001 |
11100101 |
11000011 |
00000011 |
00001011 |
01001110 |
01010111 |
00010000 |
00101001 |
01010100 |
01010011 |
01010010 |
00110111 |
01010000 |
01001111 |
01011111 |
01011110 |
01011101 |
01011100 |
01011011 |
01011010 |
01010100 |
01010011 |
00001100 |
00111110 |
00100010 |
10111001 |
00100000 |
00010001 |
11111101 |
11001011 |
00000001 |
01001110 |
00100000 |
00001001 |
00000100 |
00001110 |
00000010 |
00111110 |
00011000 |
10111000 |
00100000 |
00000011 |
00000101 |
00001110 |
00100001 |
11000011 |
11011001 |
00001101 |
00111010 |
10010001 |
01011100 |
11110101 |
11111101 |
00110110 |
01010111 |
00000001 |
00111110 |
00100000 |
11001101 |
01100101 |
00001011 |
11110001 |
00110010 |
10010001 |
01011100 |
11001001 |
11111101 |
11001011 |
00000001 |
01001110 |
11000010 |
11001101 |
00001110 |
00001110 |
00100001 |
11001101 |
01010101 |
00001100 |
00000101 |
11000011 |
11011001 |
00001101 |
11001101 |
00000011 |
00001011 |
01111001 |
00111101 |
00111101 |
11100110 |
00010000 |
00011000 |
01011010 |
00111110 |
00111111 |
00011000 |
01101100 |
00010001 |
10000111 |
00001010 |
00110010 |
00001111 |
01011100 |
00011000 |
00001011 |
00010001 |
01101101 |
00001010 |
00011000 |
00000011 |
00010001 |
10000111 |
00001010 |
00110010 |
00001110 |
01011100 |
00101010 |
01010001 |
01011100 |
01110011 |
00100011 |
01110010 |
11001001 |
00010001 |
11110100 |
00001001 |
11001101 |
10000000 |
00001010 |
00101010 |
00001110 |
01011100 |
01010111 |
01111101 |
11111110 |
00010110 |
11011010 |
00010001 |
00100010 |
00100000 |
00101001 |
01000100 |
01001010 |
00111110 |
00011111 |
10010001 |
00111000 |
00001100 |
11000110 |
00000010 |
01001111 |
11111101 |
11001011 |
00000001 |
01001110 |
00100000 |
00010110 |
00111110 |
00010110 |
10010000 |
11011010 |
10011111 |
00011110 |
00111100 |
01000111 |
00000100 |
11111101 |
11001011 |
00000010 |
01000110 |
11000010 |
01010101 |
00001100 |
11111101 |
10111110 |
00110001 |
11011010 |
10000110 |
00001100 |
11000011 |
11011001 |
00001101 |
01111100 |
11001101 |
00000011 |
00001011 |
10000001 |
00111101 |
11100110 |
00011111 |
11001000 |
01010111 |
11111101 |
11001011 |
00000001 |
11000110 |
00111110 |
00100000 |
11001101 |
00111011 |
00001100 |
00010101 |
00100000 |
11111000 |
11001001 |
11001101 |
00100100 |
00001011 |
11111101 |
11001011 |
00000001 |
01001110 |
00100000 |
00011010 |
11111101 |
11001011 |
00000010 |
01000110 |
00100000 |
00001000 |
11101101 |
01000011 |
10001000 |
01011100 |
00100010 |
10000100 |
01011100 |
11001001 |
11101101 |
01000011 |
10001010 |
01011100 |
11101101 |
01000011 |
10000010 |
01011100 |
00100010 |
10000110 |
01011100 |
11001001 |
11111101 |
01110001 |
01000101 |
00100010 |
10000000 |
01011100 |
11001001 |
11111101 |
11001011 |
00000001 |
01001110 |
00100000 |
00010100 |
11101101 |
01001011 |
10001000 |
01011100 |
00101010 |
10000100 |
01011100 |
11111101 |
11001011 |
00000010 |
01000110 |
11001000 |
11101101 |
01001011 |
10001010 |
01011100 |
00101010 |
10000110 |
01011100 |
11001001 |
11111101 |
01001110 |
01000101 |
00101010 |
10000000 |
01011100 |
11001001 |
11111110 |
10000000 |
00111000 |
00111101 |
11111110 |
10010000 |
00110000 |
00100110 |
01000111 |
11001101 |
00111000 |
00001011 |
11001101 |
00000011 |
00001011 |
00010001 |
10010010 |
01011100 |
00011000 |
01000111 |
00100001 |
10010010 |
01011100 |
11001101 |
00111110 |
00001011 |
11001011 |
00011000 |
10011111 |
11100110 |
00001111 |
01001111 |
11001011 |
00011000 |
10011111 |
11100110 |
11110000 |
10110001 |
00001110 |
00000100 |
01110111 |
00100011 |
00001101 |
00100000 |
11111011 |
11001001 |
11010110 |
10100101 |
00110000 |
00001001 |
11000110 |
00010101 |
11000101 |
11101101 |
01001011 |
01111011 |
01011100 |
00011000 |
00001011 |
11001101 |
00010000 |
00001100 |
11000011 |
00000011 |
00001011 |
11000101 |
11101101 |
01001011 |
00110110 |
01011100 |
11101011 |
00100001 |
00111011 |
01011100 |
11001011 |
10000110 |
11111110 |
00100000 |
00100000 |
00000010 |
11001011 |
11000110 |
00100110 |
00000000 |
01101111 |
00101001 |
00101001 |
00101001 |
00001001 |
11000001 |
11101011 |
01111001 |
00111101 |
00111110 |
00100001 |
00100000 |
00001110 |
00000101 |
01001111 |
11111101 |
11001011 |
00000001 |
01001110 |
00101000 |
00000110 |
11010101 |
11001101 |
11001101 |
00001110 |
11010001 |
01111001 |
10111001 |
11010101 |
11001100 |
01010101 |
00001100 |
11010001 |
11000101 |
11100101 |
00111010 |
10010001 |
01011100 |
00000110 |
11111111 |
00011111 |
00111000 |
00000001 |
00000100 |
00011111 |
00011111 |
10011111 |
01001111 |
00111110 |
00001000 |
10100111 |
11111101 |
11001011 |
00000001 |
01001110 |
00101000 |
00000101 |
11111101 |
11001011 |
00110000 |
11001110 |
00110111 |
11101011 |
00001000 |
00011010 |
10100000 |
10101110 |
10101001 |
00010010 |
00001000 |
00111000 |
00010011 |
00010100 |
00100011 |
00111101 |
00100000 |
11110010 |
11101011 |
00100101 |
11111101 |
11001011 |
00000001 |
01001110 |
11001100 |
11011011 |
00001011 |
11100001 |
11000001 |
00001101 |
00100011 |
11001001 |
00001000 |
00111110 |
00100000 |
10000011 |
01011111 |
00001000 |
00011000 |
11100110 |
01111100 |
00001111 |
00001111 |
00001111 |
11100110 |
00000011 |
11110110 |
01011000 |
01100111 |
11101101 |
01011011 |
10001111 |
01011100 |
01111110 |
10101011 |
10100010 |
10101011 |
11111101 |
11001011 |
01010111 |
01110110 |
00101000 |
00001000 |
11100110 |
11000111 |
11001011 |
01010111 |
00100000 |
00000010 |
11101110 |
00111000 |
11111101 |
11001011 |
01010111 |
01100110 |
00101000 |
00001000 |
11100110 |
11111000 |
11001011 |
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00000000 |
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10010101 |
00000000 |
11110101 |
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00100000 |
11111101 |
11001011 |
00000001 |
01000110 |
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01111111 |
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11011000 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000000 |
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00000001 |
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00000001 |
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00000000 |
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00000001 |
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00000001 |
00000001 |
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00000000 |
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00000001 |
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00000001 |
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00000000 |
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11111111 |
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00000000 |
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11111111 |
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00000001 |
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00000000 |
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00000001 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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11111111 |
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00000000 |
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00000001 |
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00000000 |
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00000000 |
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00000000 |
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10010111 |
00010000 |
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01010001 |
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00111110 |
11111111 |
11001101 |
00000001 |
00010110 |
11100001 |
00101011 |
11111101 |
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00001111 |
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01010101 |
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11100001 |
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00000000 |
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11111110 |
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01011011 |
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00010000 |
00000001 |
00000001 |
00000000 |
11000011 |
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00010101 |
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00000000 |
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11111110 |
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00010111 |
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00000000 |
00100000 |
00000001 |
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10010101 |
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00111110 |
00000000 |
11000011 |
00000001 |
00010110 |
11111101 |
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01111110 |
00101000 |
10101000 |
11000011 |
10000001 |
00001111 |
11111101 |
11001011 |
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01100110 |
00101000 |
10100001 |
11111101 |
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00000000 |
11111111 |
00010110 |
00000000 |
11111101 |
01011110 |
11111110 |
00100001 |
10010000 |
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10110101 |
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00000000 |
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11001001 |
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11111101 |
11001011 |
00000001 |
01101110 |
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00001000 |
01011100 |
11111101 |
11001011 |
00000001 |
10101110 |
11110101 |
11111101 |
11001011 |
00000010 |
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00001101 |
11110001 |
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11111110 |
00010000 |
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00101101 |
11111110 |
00000110 |
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00001010 |
01000111 |
11100110 |
00000001 |
01001111 |
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00011111 |
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00010010 |
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00101010 |
00100000 |
00001001 |
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00000000 |
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00100000 |
00000001 |
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11100001 |
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11111101 |
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11110100 |
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11010001 |
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00010110 |
00000000 |
11111101 |
01011110 |
11111110 |
00100001 |
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10110101 |
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11111101 |
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00000000 |
11111111 |
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11010001 |
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11100001 |
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10000010 |
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11111101 |
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00100110 |
00000000 |
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11111101 |
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01011011 |
01100001 |
01011100 |
11011000 |
00101010 |
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01011100 |
11001001 |
01111110 |
11111110 |
00001110 |
00000001 |
00000110 |
00000000 |
11001100 |
11101000 |
00011001 |
01111110 |
00100011 |
11111110 |
00001101 |
00100000 |
11110001 |
11001001 |
11110011 |
00111110 |
11111111 |
11101101 |
01011011 |
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01011011 |
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00000111 |
11010011 |
11111110 |
00111110 |
00111111 |
11101101 |
01000111 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
01100010 |
01101011 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
00000001 |
00000000 |
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00000001 |
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00000001 |
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00000001 |
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00000000 |
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00000001 |
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11000110 |
11111101 |
01000110 |
00110001 |
11001101 |
01000100 |
00001110 |
11111101 |
11001011 |
00000010 |
10000110 |
11111101 |
11001011 |
00110000 |
11000110 |
00101010 |
01001001 |
01011100 |
11101101 |
01011011 |
01101100 |
01011100 |
10100111 |
11101101 |
01010010 |
00011001 |
00111000 |
00100010 |
11010101 |
11001101 |
01101110 |
00011001 |
00010001 |
11000000 |
00000010 |
11101011 |
11101101 |
01010010 |
11100011 |
11001101 |
01101110 |
00011001 |
11000001 |
11000101 |
11001101 |
10111000 |
00011001 |
11000001 |
00001001 |
00111000 |
00001110 |
11101011 |
01010110 |
00100011 |
01011110 |
00101011 |
11101101 |
01010011 |
01101100 |
01011100 |
00011000 |
11101101 |
00100010 |
01101100 |
01011100 |
00101010 |
01101100 |
01011100 |
11001101 |
01101110 |
00011001 |
00101000 |
00000001 |
11101011 |
11001101 |
00110011 |
00011000 |
11111101 |
11001011 |
00000010 |
10100110 |
11001001 |
00111110 |
00000011 |
00011000 |
00000010 |
00111110 |
00000010 |
11111101 |
00110110 |
00000010 |
00000000 |
11001101 |
00110000 |
00100101 |
11000100 |
00000001 |
00010110 |
11011111 |
11001101 |
01110000 |
00100000 |
00111000 |
00010100 |
11011111 |
11111110 |
00111011 |
00101000 |
00000100 |
11111110 |
00101100 |
00100000 |
00000110 |
11100111 |
11001101 |
10000010 |
00011100 |
00011000 |
00001000 |
11001101 |
11100110 |
00011100 |
00011000 |
00000011 |
11001101 |
11011110 |
00011100 |
11001101 |
11101110 |
00011011 |
11001101 |
10011001 |
00011110 |
01111000 |
11100110 |
00111111 |
01100111 |
01101001 |
00100010 |
01001001 |
01011100 |
11001101 |
01101110 |
00011001 |
00011110 |
00000001 |
11001101 |
01010101 |
00011000 |
11010111 |
11111101 |
11001011 |
00000010 |
01100110 |
00101000 |
11110110 |
00111010 |
01101011 |
01011100 |
11111101 |
10010110 |
01001111 |
00100000 |
11101110 |
10101011 |
11001000 |
11100101 |
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00100001 |
01101100 |
01011100 |
11001101 |
00001111 |
00011001 |
11010001 |
11100001 |
00011000 |
11100000 |
11101101 |
01001011 |
01001001 |
01011100 |
11001101 |
10000000 |
00011001 |
00010110 |
00111110 |
00101000 |
00000101 |
00010001 |
00000000 |
00000000 |
11001011 |
00010011 |
11111101 |
01110011 |
00101101 |
01111110 |
11111110 |
01000000 |
11000001 |
11010000 |
11000101 |
11001101 |
00101000 |
00011010 |
00100011 |
00100011 |
00100011 |
11111101 |
11001011 |
00000001 |
10000110 |
01111010 |
10100111 |
00101000 |
00000101 |
11010111 |
11111101 |
11001011 |
00000001 |
11000110 |
11010101 |
11101011 |
11111101 |
11001011 |
00110000 |
10010110 |
00100001 |
00111011 |
01011100 |
11001011 |
10010110 |
11111101 |
11001011 |
00110111 |
01101110 |
00101000 |
00000010 |
11001011 |
11010110 |
00101010 |
01011111 |
01011100 |
10100111 |
11101101 |
01010010 |
00100000 |
00000101 |
00111110 |
00111111 |
11001101 |
11000001 |
00011000 |
11001101 |
11100001 |
00011000 |
11101011 |
01111110 |
11001101 |
10110110 |
00011000 |
00100011 |
11111110 |
00001101 |
00101000 |
00000110 |
11101011 |
11001101 |
00110111 |
00011001 |
00011000 |
11100000 |
11010001 |
11001001 |
11111110 |
00001110 |
11000000 |
00100011 |
00100011 |
00100011 |
00100011 |
00100011 |
00100011 |
01111110 |
11001001 |
11011001 |
00101010 |
10001111 |
01011100 |
11100101 |
11001011 |
10111100 |
11001011 |
11111101 |
00100010 |
10001111 |
01011100 |
00100001 |
10010001 |
01011100 |
01010110 |
11010101 |
00110110 |
00000000 |
11001101 |
11110100 |
00001001 |
11100001 |
11111101 |
01110100 |
01010111 |
11100001 |
00100010 |
10001111 |
01011100 |
11011001 |
11001001 |
00101010 |
01011011 |
01011100 |
10100111 |
11101101 |
01010010 |
11000000 |
00111010 |
01000001 |
01011100 |
11001011 |
00000111 |
00101000 |
00000100 |
11000110 |
01000011 |
00011000 |
00010110 |
00100001 |
00111011 |
01011100 |
11001011 |
10011110 |
00111110 |
01001011 |
11001011 |
01010110 |
00101000 |
00001011 |
11001011 |
11011110 |
00111100 |
11111101 |
11001011 |
00110000 |
01011110 |
00101000 |
00000010 |
00111110 |
01000011 |
11010101 |
11001101 |
11000001 |
00011000 |
11010001 |
11001001 |
01011110 |
00100011 |
01010110 |
11100101 |
11101011 |
00100011 |
11001101 |
01101110 |
00011001 |
11001101 |
10010101 |
00010110 |
11100001 |
11111101 |
11001011 |
00110111 |
01101110 |
11000000 |
01110010 |
00101011 |
01110011 |
11001001 |
01111011 |
10100111 |
11111000 |
00011000 |
00001101 |
10101111 |
00001001 |
00111100 |
00111000 |
11111100 |
11101101 |
01000010 |
00111101 |
00101000 |
11110001 |
11000011 |
11101111 |
00010101 |
11001101 |
00011011 |
00101101 |
00110000 |
00110000 |
11111110 |
00100001 |
00111000 |
00101100 |
11111101 |
11001011 |
00000001 |
10010110 |
11111110 |
11001011 |
00101000 |
00100100 |
11111110 |
00111010 |
00100000 |
00001110 |
11111101 |
11001011 |
00110111 |
01101110 |
00100000 |
00010110 |
11111101 |
11001011 |
00110000 |
01010110 |
00101000 |
00010100 |
00011000 |
00001110 |
11111110 |
00100010 |
00100000 |
00001010 |
11110101 |
00111010 |
01101010 |
01011100 |
11101110 |
00000100 |
00110010 |
01101010 |
01011100 |
11110001 |
11111101 |
11001011 |
00000001 |
11010110 |
11010111 |
11001001 |
11100101 |
00101010 |
01010011 |
01011100 |
01010100 |
01011101 |
11000001 |
11001101 |
10000000 |
00011001 |
11010000 |
11000101 |
11001101 |
10111000 |
00011001 |
11101011 |
00011000 |
11110100 |
01111110 |
10111000 |
11000000 |
00100011 |
01111110 |
00101011 |
10111001 |
11001001 |
00100011 |
00100011 |
00100011 |
00100010 |
01011101 |
01011100 |
00001110 |
00000000 |
00010101 |
11001000 |
11100111 |
10111011 |
00100000 |
00000100 |
10100111 |
11001001 |
00100011 |
01111110 |
11001101 |
10110110 |
00011000 |
00100010 |
01011101 |
01011100 |
11111110 |
00100010 |
00100000 |
00000001 |
00001101 |
11111110 |
00111010 |
00101000 |
00000100 |
11111110 |
11001011 |
00100000 |
00000100 |
11001011 |
01000001 |
00101000 |
11011111 |
11111110 |
00001101 |
00100000 |
11100011 |
00010101 |
00110111 |
11001001 |
11100101 |
01111110 |
11111110 |
01000000 |
00111000 |
00010111 |
11001011 |
01101111 |
00101000 |
00010100 |
10000111 |
11111010 |
11000111 |
00011001 |
00111111 |
00000001 |
00000101 |
00000000 |
00110000 |
00000010 |
00001110 |
00010010 |
00010111 |
00100011 |
01111110 |
00110000 |
11111011 |
00011000 |
00000110 |
00100011 |
00100011 |
01001110 |
00100011 |
01000110 |
00100011 |
00001001 |
11010001 |
10100111 |
11101101 |
01010010 |
01000100 |
01001101 |
00011001 |
11101011 |
11001001 |
11001101 |
11011101 |
00011001 |
11000101 |
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00101111 |
01000111 |
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00101111 |
01001111 |
00000011 |
11001101 |
01100100 |
00010110 |
11101011 |
11100001 |
00011001 |
11010101 |
11101101 |
10110000 |
11100001 |
11001001 |
00101010 |
01011001 |
01011100 |
00101011 |
00100010 |
01011101 |
01011100 |
11100111 |
00100001 |
10010010 |
01011100 |
00100010 |
01100101 |
01011100 |
11001101 |
00111011 |
00101101 |
11001101 |
10100010 |
00101101 |
00111000 |
00000100 |
00100001 |
11110000 |
11011000 |
00001001 |
11011010 |
10001010 |
00011100 |
11000011 |
11000101 |
00010110 |
11010101 |
11100101 |
10101111 |
11001011 |
01111000 |
00100000 |
00100000 |
01100000 |
01101001 |
00011110 |
11111111 |
00011000 |
00001000 |
11010101 |
01010110 |
00100011 |
01011110 |
11100101 |
11101011 |
00011110 |
00100000 |
00000001 |
00011000 |
11111100 |
11001101 |
00101010 |
00011001 |
00000001 |
10011100 |
11111111 |
11001101 |
00101010 |
00011001 |
00001110 |
11110110 |
11001101 |
00101010 |
00011001 |
01111101 |
11001101 |
11101111 |
00010101 |
11100001 |
11010001 |
11001001 |
10110001 |
11001011 |
10111100 |
10111111 |
11000100 |
10101111 |
10110100 |
10010011 |
10010001 |
10010010 |
10010101 |
10011000 |
10011000 |
10011000 |
10011000 |
10011000 |
10011000 |
10011000 |
01111111 |
10000001 |
00101110 |
01101100 |
01101110 |
01110000 |
01001000 |
10010100 |
01010110 |
00111111 |
01000001 |
00101011 |
00010111 |
00011111 |
00110111 |
01110111 |
01000100 |
00001111 |
01011001 |
00101011 |
01000011 |
00101101 |
01010001 |
00111010 |
01101101 |
01000010 |
00001101 |
01001001 |
01011100 |
01000100 |
00010101 |
01011101 |
00000001 |
00111101 |
00000010 |
00000110 |
00000000 |
01100111 |
00011110 |
00000110 |
11001011 |
00000101 |
11110000 |
00011100 |
00000110 |
00000000 |
11101101 |
00011110 |
00000000 |
11101110 |
00011100 |
00000000 |
00100011 |
00011111 |
00000100 |
00111101 |
00000110 |
11001100 |
00000110 |
00000101 |
00000011 |
00011101 |
00000100 |
00000000 |
10101011 |
00011101 |
00000101 |
11001101 |
00011111 |
00000101 |
10001001 |
00100000 |
00000101 |
00000010 |
00101100 |
00000101 |
10110010 |
00011011 |
00000000 |
10110111 |
00010001 |
00000011 |
10100001 |
00011110 |
00000101 |
11111001 |
00010111 |
00001000 |
00000000 |
10000000 |
00011110 |
00000011 |
01001111 |
00011110 |
00000000 |
01011111 |
00011110 |
00000011 |
10101100 |
00011110 |
00000000 |
01101011 |
00001101 |
00001001 |
00000000 |
11011100 |
00100010 |
00000110 |
00000000 |
00111010 |
00011111 |
00000101 |
11101101 |
00011101 |
00000101 |
00100111 |
00011110 |
00000011 |
01000010 |
00011110 |
00001001 |
00000101 |
10000010 |
00100011 |
00000000 |
10101100 |
00001110 |
00000101 |
11001001 |
00011111 |
00000101 |
11110101 |
00010111 |
00001011 |
00001011 |
00001011 |
00001011 |
00001000 |
00000000 |
11111000 |
00000011 |
00001001 |
00000101 |
00100000 |
00100011 |
00000111 |
00000111 |
00000111 |
00000111 |
00000111 |
00000111 |
00001000 |
00000000 |
01111010 |
00011110 |
00000110 |
00000000 |
10010100 |
00100010 |
00000101 |
01100000 |
00011111 |
00000110 |
00101100 |
00001010 |
00000000 |
00110110 |
00010111 |
00000110 |
00000000 |
11100101 |
00010110 |
00001010 |
00000000 |
10010011 |
00010111 |
00001010 |
00101100 |
00001010 |
00000000 |
10010011 |
00010111 |
00001010 |
00000000 |
10010011 |
00010111 |
00000000 |
10010011 |
00010111 |
11111101 |
11001011 |
00000001 |
10111110 |
11001101 |
11111011 |
00011001 |
10101111 |
00110010 |
01000111 |
01011100 |
00111101 |
00110010 |
00111010 |
01011100 |
00011000 |
00000001 |
11100111 |
11001101 |
10111111 |
00010110 |
11111101 |
00110100 |
00001101 |
11111010 |
10001010 |
00011100 |
11011111 |
00000110 |
00000000 |
11111110 |
00001101 |
00101000 |
01111010 |
11111110 |
00111010 |
00101000 |
11101011 |
00100001 |
01110110 |
00011011 |
11100101 |
01001111 |
11100111 |
01111001 |
11010110 |
11001110 |
11011010 |
10001010 |
00011100 |
01001111 |
00100001 |
01001000 |
00011010 |
00001001 |
01001110 |
00001001 |
00011000 |
00000011 |
00101010 |
01110100 |
01011100 |
01111110 |
00100011 |
00100010 |
01110100 |
01011100 |
00000001 |
01010010 |
00011011 |
11000101 |
01001111 |
11111110 |
00100000 |
00110000 |
00001100 |
00100001 |
00000001 |
00011100 |
00000110 |
00000000 |
00001001 |
01001110 |
00001001 |
11100101 |
11011111 |
00000101 |
11001001 |
11011111 |
10111001 |
11000010 |
10001010 |
00011100 |
11100111 |
11001001 |
11001101 |
01010100 |
00011111 |
00111000 |
00000010 |
11001111 |
00010100 |
11111101 |
11001011 |
00001010 |
01111110 |
00100000 |
01110001 |
00101010 |
01000010 |
01011100 |
11001011 |
01111100 |
00101000 |
00010100 |
00100001 |
11111110 |
11111111 |
00100010 |
01000101 |
01011100 |
00101010 |
01100001 |
01011100 |
00101011 |
11101101 |
01011011 |
01011001 |
01011100 |
00011011 |
00111010 |
01000100 |
01011100 |
00011000 |
00110011 |
11001101 |
01101110 |
00011001 |
00111010 |
01000100 |
01011100 |
00101000 |
00011001 |
10100111 |
00100000 |
01000011 |
01000111 |
01111110 |
11100110 |
11000000 |
01111000 |
00101000 |
00001111 |
11001111 |
11111111 |
11000001 |
11001101 |
00110000 |
00100101 |
11001000 |
00101010 |
01010101 |
01011100 |
00111110 |
11000000 |
10100110 |
11000000 |
10101111 |
11111110 |
00000001 |
11001110 |
00000000 |
01010110 |
00100011 |
01011110 |
11101101 |
01010011 |
01000101 |
01011100 |
00100011 |
01011110 |
00100011 |
01010110 |
11101011 |
00011001 |
00100011 |
00100010 |
01010101 |
01011100 |
11101011 |
00100010 |
01011101 |
01011100 |
01010111 |
00011110 |
00000000 |
11111101 |
00110110 |
00001010 |
11111111 |
00010101 |
11111101 |
01110010 |
00001101 |
11001010 |
00101000 |
00011011 |
00010100 |
11001101 |
10001011 |
00011001 |
00101000 |
00001000 |
11001111 |
00010110 |
11001101 |
00110000 |
00100101 |
11000000 |
11000001 |
11000001 |
11011111 |
11111110 |
00001101 |
00101000 |
10111010 |
11111110 |
00111010 |
11001010 |
00101000 |
00011011 |
11000011 |
10001010 |
00011100 |
00001111 |
00011101 |
01001011 |
00001001 |
01100111 |
00001011 |
01111011 |
10001110 |
01110001 |
10110100 |
10000001 |
11001111 |
11001101 |
11011110 |
00011100 |
10111111 |
11000001 |
11001100 |
11101110 |
00011011 |
11101011 |
00101010 |
01110100 |
01011100 |
01001110 |
00100011 |
01000110 |
11101011 |
11000101 |
11001001 |
11001101 |
10110010 |
00101000 |
11111101 |
00110110 |
00110111 |
00000000 |
00110000 |
00001000 |
11111101 |
11001011 |
00110111 |
11001110 |
00100000 |
00011000 |
11001111 |
00000001 |
11001100 |
10010110 |
00101001 |
11111101 |
11001011 |
00000001 |
01110110 |
00100000 |
00001101 |
10101111 |
11001101 |
00110000 |
00100101 |
11000100 |
11110001 |
00101011 |
00100001 |
01110001 |
01011100 |
10110110 |
01110111 |
11101011 |
11101101 |
01000011 |
01110010 |
01011100 |
00100010 |
01001101 |
01011100 |
11001001 |
11000001 |
11001101 |
01010110 |
00011100 |
11001101 |
11101110 |
00011011 |
11001001 |
00111010 |
00111011 |
01011100 |
11110101 |
11001101 |
11111011 |
00100100 |
11110001 |
11111101 |
01010110 |
00000001 |
10101010 |
11100110 |
01000000 |
00100000 |
00100100 |
11001011 |
01111010 |
11000010 |
11111111 |
00101010 |
11001001 |
11001101 |
10110010 |
00101000 |
11110101 |
01111001 |
11110110 |
10011111 |
00111100 |
00100000 |
00010100 |
11110001 |
00011000 |
10101001 |
11100111 |
11001101 |
10000010 |
00011100 |
11111110 |
00101100 |
00100000 |
00001001 |
11100111 |
11001101 |
11111011 |
00100100 |
11111101 |
11001011 |
00000001 |
01110110 |
11000000 |
11001111 |
00001011 |
11001101 |
11111011 |
00100100 |
11111101 |
11001011 |
00000001 |
01110110 |
11001000 |
00011000 |
11110100 |
11111101 |
11001011 |
00000001 |
01111110 |
11111101 |
11001011 |
00000010 |
10000110 |
11000100 |
01001101 |
00001101 |
11110001 |
00111010 |
01110100 |
01011100 |
11010110 |
00010011 |
11001101 |
11111100 |
00100001 |
11001101 |
11101110 |
00011011 |
00101010 |
10001111 |
01011100 |
00100010 |
10001101 |
01011100 |
00100001 |
10010001 |
01011100 |
01111110 |
00000111 |
10101110 |
11100110 |
10101010 |
10101110 |
01110111 |
11001001 |
11001101 |
00110000 |
00100101 |
00101000 |
00010011 |
11111101 |
11001011 |
00000010 |
10000110 |
11001101 |
01001101 |
00001101 |
00100001 |
10010000 |
01011100 |
01111110 |
11110110 |
11111000 |
01110111 |
11111101 |
11001011 |
01010111 |
10110110 |
11011111 |
11001101 |
11100010 |
00100001 |
00011000 |
10011111 |
11000011 |
00000101 |
00000110 |
11111110 |
00001101 |
00101000 |
00000100 |
11111110 |
00111010 |
00100000 |
10011100 |
11001101 |
00110000 |
00100101 |
11001000 |
11101111 |
10100000 |
00111000 |
11001001 |
11001111 |
00001000 |
11000001 |
11001101 |
00110000 |
00100101 |
00101000 |
00001010 |
11101111 |
00000010 |
00111000 |
11101011 |
11001101 |
11101001 |
00110100 |
11011010 |
10110011 |
00011011 |
11000011 |
00101001 |
00011011 |
11111110 |
11001101 |
00100000 |
00001001 |
11100111 |
11001101 |
10000010 |
00011100 |
11001101 |
11101110 |
00011011 |
00011000 |
00000110 |
11001101 |
11101110 |
00011011 |
11101111 |
10100001 |
00111000 |
11101111 |
11000000 |
00000010 |
00000001 |
11100000 |
00000001 |
00111000 |
11001101 |
11111111 |
00101010 |
00100010 |
01101000 |
01011100 |
00101011 |
01111110 |
11001011 |
11111110 |
00000001 |
00000110 |
00000000 |
00001001 |
00000111 |
00111000 |
00000110 |
00001110 |
00001101 |
11001101 |
01010101 |
00010110 |
00100011 |
11100101 |
11101111 |
00000010 |
00000010 |
00111000 |
11100001 |
11101011 |
00001110 |
00001010 |
11101101 |
10110000 |
00101010 |
01000101 |
01011100 |
11101011 |
01110011 |
00100011 |
01110010 |
11111101 |
01010110 |
00001101 |
00010100 |
00100011 |
01110010 |
11001101 |
11011010 |
00011101 |
11010000 |
11111101 |
01000110 |
00111000 |
00101010 |
01000101 |
01011100 |
00100010 |
01000010 |
01011100 |
00111010 |
01000111 |
01011100 |
11101101 |
01000100 |
01010111 |
00101010 |
01011101 |
01011100 |
00011110 |
11110011 |
11000101 |
11101101 |
01001011 |
01010101 |
01011100 |
11001101 |
10000110 |
00011101 |
11101101 |
01000011 |
01010101 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000000 |
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00000000 |
00000001 |
00000000 |
00000000 |
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00000001 |
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00000001 |
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00000001 |
10101110 |
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00000001 |
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00000001 |
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00000001 |
00000110 |
00000000 |
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01010101 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
00000001 |
00000000 |
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01111110 |
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00000000 |
11111111 |
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00000001 |
10111110 |
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10111001 |
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00000000 |
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00000001 |
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00000000 |
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11111111 |
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00000000 |
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00000000 |
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11111110 |
00000001 |
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00000110 |
00000001 |
00100000 |
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00100100 |
00101000 |
00000001 |
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10000000 |
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00100000 |
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00111110 |
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10101010 |
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01000111 |
00000100 |
01111110 |
00000111 |
00010000 |
11111101 |
11100110 |
00000001 |
11000011 |
00101000 |
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00000111 |
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11100101 |
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00001111 |
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11111101 |
01001110 |
01010111 |
11001011 |
01000001 |
00100000 |
00000001 |
10100000 |
11001011 |
01010001 |
00100000 |
00000010 |
10101000 |
00101111 |
01110111 |
11000011 |
11011011 |
00001011 |
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00010100 |
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00010100 |
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01011001 |
11000001 |
01010001 |
01001111 |
11001001 |
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00101101 |
11011010 |
11111001 |
00100100 |
00001110 |
00000001 |
11001000 |
00001110 |
11111111 |
11001001 |
11011111 |
11111110 |
00101100 |
11000010 |
10001010 |
00011100 |
11100111 |
11001101 |
10000010 |
00011100 |
11001101 |
11101110 |
00011011 |
11101111 |
00101010 |
00111101 |
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01111110 |
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10000000 |
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11000001 |
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11011100 |
00100010 |
11101111 |
11000010 |
00000001 |
11000000 |
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00000001 |
11100000 |
00001111 |
11000000 |
00000001 |
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11100000 |
00000001 |
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11100000 |
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11111101 |
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00000000 |
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11100001 |
00000001 |
11100001 |
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11100000 |
00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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00000001 |
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11000000 |
00001111 |
00000001 |
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00001111 |
11000000 |
00000001 |
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00000001 |
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01111101 |
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00101000 |
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11101111 |
00000011 |
00000001 |
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01111110 |
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00101000 |
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00000011 |
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00000000 |
00000001 |
00000101 |
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00000001 |
00000101 |
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00000001 |
00000101 |
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00011111 |
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00000100 |
00011111 |
11000001 |
00000001 |
11000000 |
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00001111 |
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00000000 |
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00011111 |
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00000111 |
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10000100 |
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01001111 |
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00010000 |
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11010001 |
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00101000 |
11110011 |
11001111 |
00001010 |
11011111 |
00000110 |
00000000 |
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01001111 |
00100001 |
10010110 |
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11011100 |
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11010010 |
10000100 |
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00000110 |
00000000 |
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00000000 |
00000011 |
11111110 |
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11111110 |
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00100000 |
11110011 |
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00000000 |
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11011111 |
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11111101 |
11001011 |
00000001 |
01111110 |
11001001 |
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00000111 |
00100011 |
00101010 |
00110110 |
01011100 |
00010001 |
00000000 |
00000001 |
00011001 |
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00001111 |
00001111 |
00001111 |
11100110 |
11100000 |
10101000 |
01011111 |
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00100000 |
00001111 |
00010000 |
11110111 |
11000001 |
11000001 |
11000001 |
00111110 |
10000000 |
10010000 |
00000001 |
00000001 |
00000000 |
11110111 |
00010010 |
00011000 |
00001010 |
11100001 |
00010001 |
00001000 |
00000000 |
00011001 |
11010001 |
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10000100 |
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11000111 |
10101001 |
11001110 |
00000000 |
11100111 |
11000011 |
11111111 |
00100100 |
11011111 |
00100011 |
11100101 |
00000001 |
00000000 |
00000000 |
11001101 |
00001111 |
00100101 |
00100000 |
00011011 |
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00001111 |
00100101 |
00101000 |
11111011 |
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00010001 |
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11100001 |
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11111000 |
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00101101 |
11101111 |
10100001 |
00001111 |
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00010110 |
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10000000 |
01000001 |
00000000 |
00000000 |
10000000 |
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10100010 |
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00101000 |
00000100 |
11101111 |
10100011 |
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00110100 |
11100111 |
11000011 |
11000011 |
00100110 |
00000001 |
01011010 |
00010000 |
11100111 |
11111110 |
00100011 |
11001010 |
00001101 |
00100111 |
00100001 |
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01011100 |
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00011111 |
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00000000 |
00100000 |
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00011110 |
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00010101 |
01011111 |
11001101 |
00110011 |
00000011 |
11110101 |
00000001 |
00000001 |
00000000 |
11110111 |
11110001 |
00010010 |
00001110 |
00000001 |
00000110 |
00000000 |
11001101 |
10110010 |
00101010 |
11000011 |
00010010 |
00100111 |
11001101 |
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11000100 |
00110101 |
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11000011 |
11011011 |
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11000100 |
10000000 |
00100101 |
11100111 |
00011000 |
01001000 |
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11001011 |
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11100111 |
00011000 |
00111111 |
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01000001 |
00110000 |
00111100 |
11001101 |
00110000 |
00100101 |
00100000 |
00100011 |
11001101 |
10011011 |
00101100 |
11011111 |
00000001 |
00000110 |
00000000 |
11001101 |
01010101 |
00010110 |
00100011 |
00110110 |
00001110 |
00100011 |
11101011 |
00101010 |
01100101 |
01011100 |
00001110 |
00000101 |
10100111 |
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01000010 |
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10110000 |
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01110111 |
00000000 |
00011000 |
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11011111 |
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01111110 |
11111110 |
00001110 |
00100000 |
11111010 |
00100011 |
11001101 |
10110100 |
00110011 |
00100010 |
01011101 |
01011100 |
11111101 |
11001011 |
00000001 |
11110110 |
00011000 |
00010100 |
11001101 |
10110010 |
00101000 |
11011010 |
00101110 |
00011100 |
11001100 |
10010110 |
00101001 |
00111010 |
00111011 |
01011100 |
11111110 |
11000000 |
00111000 |
00000100 |
00100011 |
11001101 |
10110100 |
00110011 |
00011000 |
00110011 |
00000001 |
11011011 |
00001001 |
11111110 |
00101101 |
00101000 |
00100111 |
00000001 |
00011000 |
00010000 |
11111110 |
10101110 |
00101000 |
00100000 |
11010110 |
10101111 |
11011010 |
10001010 |
00011100 |
00000001 |
11110000 |
00000100 |
11111110 |
00010100 |
00101000 |
00010100 |
11010010 |
10001010 |
00011100 |
00000110 |
00010000 |
11000110 |
11011100 |
01001111 |
11111110 |
11011111 |
00110000 |
00000010 |
11001011 |
10110001 |
11111110 |
11101110 |
00111000 |
00000010 |
11001011 |
10111001 |
11000101 |
11100111 |
11000011 |
11111111 |
00100100 |
11011111 |
11111110 |
00101000 |
00100000 |
00001100 |
11111101 |
11001011 |
00000001 |
01110110 |
00100000 |
00010111 |
11001101 |
01010010 |
00101010 |
11100111 |
00011000 |
11110000 |
00000110 |
00000000 |
01001111 |
00100001 |
10010101 |
00100111 |
11001101 |
11011100 |
00010110 |
00110000 |
00000110 |
01001110 |
00100001 |
11101101 |
00100110 |
00001001 |
01000110 |
11010001 |
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10111000 |
00111000 |
00111010 |
10100111 |
11001010 |
00011000 |
00000000 |
11000101 |
00100001 |
00111011 |
01011100 |
01111011 |
11111110 |
11101101 |
00100000 |
00000110 |
11001011 |
01110110 |
00100000 |
00000010 |
00011110 |
10011001 |
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11001101 |
00110000 |
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00101000 |
00001001 |
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11100110 |
00111111 |
01000111 |
11101111 |
00111011 |
00111000 |
00011000 |
00001001 |
01111011 |
11111101 |
10101110 |
00000001 |
11100110 |
01000000 |
11000010 |
10001010 |
00011100 |
11010001 |
00100001 |
00111011 |
01011100 |
11001011 |
11110110 |
11001011 |
01111011 |
00100000 |
00000010 |
11001011 |
10110110 |
11000001 |
00011000 |
11000001 |
11010101 |
01111001 |
11111101 |
11001011 |
00000001 |
01110110 |
00100000 |
00010101 |
11100110 |
00111111 |
11000110 |
00001000 |
01001111 |
11111110 |
00010000 |
00100000 |
00000100 |
11001011 |
11110001 |
00011000 |
00001000 |
00111000 |
11010111 |
11111110 |
00010111 |
00101000 |
00000010 |
11001011 |
11111001 |
11000101 |
11100111 |
11000011 |
11111111 |
00100100 |
00101011 |
11001111 |
00101101 |
11000011 |
00101010 |
11000100 |
00101111 |
11000101 |
01011110 |
11000110 |
00111101 |
11001110 |
00111110 |
11001100 |
00111100 |
11001101 |
11000111 |
11001001 |
11001000 |
11001010 |
11001001 |
11001011 |
11000101 |
11000111 |
11000110 |
11001000 |
00000000 |
00000110 |
00001000 |
00001000 |
00001010 |
00000010 |
00000011 |
00000101 |
00000101 |
00000101 |
00000101 |
00000101 |
00000101 |
00000110 |
11001101 |
00110000 |
00100101 |
00100000 |
00110101 |
11100111 |
11001101 |
10001101 |
00101100 |
11010010 |
10001010 |
00011100 |
11100111 |
11111110 |
00100100 |
11110101 |
00100000 |
00000001 |
11100111 |
11111110 |
00101000 |
00100000 |
00010010 |
11100111 |
11111110 |
00101001 |
00101000 |
00010000 |
11001101 |
11111011 |
00100100 |
11011111 |
11111110 |
00101100 |
00100000 |
00000011 |
11100111 |
00011000 |
11110101 |
11111110 |
00101001 |
11000010 |
10001010 |
00011100 |
11100111 |
00100001 |
00111011 |
01011100 |
11001011 |
10110110 |
11110001 |
00101000 |
00000010 |
11001011 |
11110110 |
11000011 |
00010010 |
00100111 |
11100111 |
11100110 |
11011111 |
01000111 |
11100111 |
11010110 |
00100100 |
01001111 |
00100000 |
00000001 |
11100111 |
11100111 |
11100101 |
00101010 |
01010011 |
01011100 |
00101011 |
00010001 |
11001110 |
00000000 |
11000101 |
11001101 |
10000110 |
00011101 |
11000001 |
00110000 |
00000010 |
11001111 |
00011000 |
11100101 |
11001101 |
10101011 |
00101000 |
11100110 |
11011111 |
10111000 |
00100000 |
00001000 |
11001101 |
10101011 |
00101000 |
11010110 |
00100100 |
10111001 |
00101000 |
00001100 |
11100001 |
00101011 |
00010001 |
00000000 |
00000010 |
11000101 |
11001101 |
10001011 |
00011001 |
11000001 |
00011000 |
11010111 |
10100111 |
11001100 |
10101011 |
00101000 |
11010001 |
11010001 |
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01010011 |
01011101 |
01011100 |
11001101 |
10101011 |
00101000 |
11100101 |
11111110 |
00101001 |
00101000 |
01000010 |
00100011 |
01111110 |
11111110 |
00001110 |
00010110 |
01000000 |
00101000 |
00000111 |
00101011 |
11001101 |
10101011 |
00101000 |
00100011 |
00010110 |
00000000 |
00100011 |
11100101 |
11010101 |
11001101 |
11111011 |
00100100 |
11110001 |
11111101 |
10101110 |
00000001 |
11100110 |
01000000 |
00100000 |
00101011 |
11100001 |
11101011 |
00101010 |
01100101 |
01011100 |
00000001 |
00000101 |
00000000 |
11101101 |
01000010 |
00100010 |
01100101 |
01011100 |
11101101 |
10110000 |
11101011 |
00101011 |
11001101 |
10101011 |
00101000 |
11111110 |
00101001 |
00101000 |
00001101 |
11100101 |
11011111 |
11111110 |
00101100 |
00100000 |
00001101 |
11100111 |
11100001 |
11001101 |
10101011 |
00101000 |
00011000 |
10111110 |
11100101 |
11011111 |
11111110 |
00101001 |
00101000 |
00000010 |
11001111 |
00011001 |
11010001 |
11101011 |
00100010 |
01011101 |
01011100 |
00101010 |
00001011 |
01011100 |
11100011 |
00100010 |
00001011 |
01011100 |
11010101 |
11100111 |
11100111 |
11001101 |
11111011 |
00100100 |
11100001 |
00100010 |
01011101 |
01011100 |
11100001 |
00100010 |
00001011 |
01011100 |
11100111 |
11000011 |
00010010 |
00100111 |
00100011 |
01111110 |
11111110 |
00100001 |
00111000 |
11111010 |
11001001 |
11111101 |
11001011 |
00000001 |
11110110 |
11011111 |
11001101 |
10001101 |
00101100 |
11010010 |
10001010 |
00011100 |
11100101 |
11100110 |
00011111 |
01001111 |
11100111 |
11100101 |
11111110 |
00101000 |
00101000 |
00101000 |
11001011 |
11110001 |
11111110 |
00100100 |
00101000 |
00010001 |
11001011 |
11101001 |
11001101 |
10001000 |
00101100 |
00110000 |
00001111 |
11001101 |
10001000 |
00101100 |
00110000 |
00010110 |
11001011 |
10110001 |
11100111 |
00011000 |
11110110 |
11100111 |
11111101 |
11001011 |
00000001 |
10110110 |
00111010 |
00001100 |
01011100 |
10100111 |
00101000 |
00000110 |
11001101 |
00110000 |
00100101 |
11000010 |
01010001 |
00101001 |
01000001 |
11001101 |
00110000 |
00100101 |
00100000 |
00001000 |
01111001 |
11100110 |
11100000 |
11001011 |
11111111 |
01001111 |
00011000 |
00110111 |
00101010 |
01001011 |
01011100 |
01111110 |
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10000111 |
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10000000 |
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11100001 |
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00000001 |
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00000001 |
00000000 |
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00000001 |
00000000 |
00000000 |
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00000001 |
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00000001 |
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00000000 |
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00000001 |
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10000000 |
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11100001 |
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11100001 |
00000001 |
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00000000 |
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00000001 |
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00000000 |
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00000000 |
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00100001 |
00000001 |
00000000 |
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00101110 |
00000101 |
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11100111 |
00100110 |
11111111 |
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00101010 |
11011010 |
00100000 |
00101010 |
11100001 |
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00100100 |
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00000000 |
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00011011 |
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00000000 |
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00100000 |
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00111101 |
00100000 |
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11010000 |
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11111110 |
01100001 |
00111111 |
11010000 |
11111110 |
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11111110 |
11000100 |
00100000 |
00011001 |
00010001 |
00000000 |
00000000 |
11100111 |
11010110 |
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00000000 |
00100000 |
00001010 |
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00111111 |
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11011010 |
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11111111 |
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00000000 |
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11110001 |
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00100010 |
00101101 |
11011000 |
11101111 |
00000001 |
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00000000 |
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11110001 |
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00000000 |
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00000000 |
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00000000 |
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01110111 |
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00110110 |
00000000 |
11100001 |
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01111111 |
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10101111 |
10010000 |
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11010001 |
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01010111 |
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00000000 |
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00000000 |
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00000001 |
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01111110 |
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00100000 |
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01111111 |
00101101 |
00000110 |
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11010001 |
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01111110 |
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11100001 |
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00010111 |
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10101011 |
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01110111 |
00100011 |
10000110 |
01110111 |
11100001 |
11000011 |
11001111 |
00101110 |
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10000000 |
11111110 |
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00010011 |
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00101101 |
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00000111 |
01000111 |
00100001 |
10101100 |
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10000110 |
01110111 |
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01000100 |
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01001111 |
00101101 |
00011000 |
10010010 |
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10111010 |
00101111 |
11011001 |
11001011 |
11111010 |
01111101 |
11011001 |
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10000000 |
01000111 |
11001011 |
00100011 |
11001011 |
00010010 |
11011001 |
11001011 |
00010011 |
11001011 |
00010010 |
11011001 |
00100001 |
10101010 |
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11111000 |
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10101111 |
00100001 |
10100110 |
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00000110 |
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00001110 |
11111111 |
11101101 |
01101111 |
00100000 |
00000100 |
00001101 |
00001100 |
00100000 |
00001010 |
00010010 |
00010011 |
11111101 |
00110100 |
01110001 |
11111101 |
00110100 |
01110010 |
00001110 |
00000000 |
11001011 |
01000000 |
00101000 |
00000001 |
00100011 |
00010000 |
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10111110 |
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11101111 |
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00101111 |
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10000000 |
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00000000 |
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11011101 |
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11111101 |
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01110001 |
11111110 |
00001000 |
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00000110 |
11011001 |
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00010010 |
11011001 |
00011000 |
00100000 |
00000001 |
00000000 |
00000010 |
01111011 |
11001101 |
10001011 |
00101111 |
01011111 |
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10001011 |
00101111 |
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00000000 |
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00000000 |
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10100111 |
00101000 |
00000101 |
11111110 |
00001010 |
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00110000 |
00001000 |
00010000 |
11110001 |
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00000001 |
00000100 |
11111101 |
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11111101 |
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11101111 |
00000010 |
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11100001 |
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00111110 |
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11111011 |
01000001 |
00011000 |
11100110 |
01010000 |
00010101 |
00000110 |
00000001 |
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00101111 |
00111110 |
01000101 |
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10100111 |
11110010 |
10000011 |
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00000000 |
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00100110 |
00000000 |
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00000000 |
10100111 |
11001000 |
00100011 |
11001011 |
01111110 |
11001011 |
11111110 |
00101011 |
11001000 |
11000101 |
00000001 |
00000101 |
00000000 |
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01001111 |
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00101011 |
01111110 |
00101111 |
11001110 |
00000000 |
01110111 |
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00000000 |
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00000000 |
00000000 |
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00000001 |
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11100001 |
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00000000 |
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00011111 |
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11100001 |
00011111 |
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00001000 |
00111110 |
00000001 |
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11011101 |
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00101000 |
00100011 |
11011001 |
01111101 |
11100110 |
10000000 |
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01011111 |
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00000000 |
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00000000 |
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00101111 |
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00000000 |
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00000000 |
00000000 |
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01001111 |
11100001 |
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10101001 |
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11100001 |
00111000 |
00001010 |
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10110011 |
00100000 |
00000001 |
01001111 |
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10001110 |
00101101 |
11010001 |
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11010001 |
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10010011 |
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11011001 |
11000001 |
11100001 |
01111000 |
10000001 |
00100000 |
00000001 |
10100111 |
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00111111 |
00010111 |
00111111 |
00011111 |
11110010 |
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11011001 |
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00010101 |
01111110 |
10100111 |
00111110 |
10000000 |
00101000 |
00000001 |
10101111 |
11011001 |
10100010 |
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11111011 |
00101111 |
00000111 |
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10000000 |
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11100001 |
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00000000 |
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10000000 |
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10000000 |
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01110111 |
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11111111 |
00101011 |
00111110 |
00011000 |
00011000 |
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00101100 |
11010101 |
00101111 |
11000110 |
10010001 |
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01010110 |
00100011 |
01011110 |
00101011 |
00101011 |
00001110 |
00000000 |
11001011 |
01111010 |
00101000 |
00000001 |
00001101 |
11001011 |
11111010 |
00000110 |
00001000 |
10010000 |
10000000 |
00111000 |
00000100 |
01011010 |
00010110 |
00000000 |
10010000 |
00101000 |
00000111 |
01000111 |
11001011 |
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11001011 |
00011011 |
00010000 |
11111010 |
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10001110 |
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11010001 |
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10100000 |
11110000 |
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00000000 |
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11111011 |
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00000111 |
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00001001 |
01000111 |
00111110 |
11111111 |
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00010000 |
11111100 |
10100110 |
01110111 |
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11010001 |
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01111111 |
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01110111 |
00000110 |
10010001 |
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10100111 |
00100000 |
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00010000 |
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11010001 |
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00000000 |
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00000000 |
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00000000 |
00000001 |
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00000000 |
11110001 |
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11011010 |
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00000000 |
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00000001 |
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10000110 |
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10000000 |
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11100110 |
00011111 |
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11111110 |
00011000 |
00110000 |
00001000 |
11011001 |
00000001 |
11111011 |
11111111 |
01010100 |
01011101 |
00001001 |
11011001 |
00000111 |
01101111 |
00010001 |
11010111 |
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00100110 |
00000000 |
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00000001 |
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00000000 |
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00000000 |
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00000101 |
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11111010 |
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11110101 |
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00010001 |
00000000 |
00000000 |
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11010001 |
11110001 |
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01001111 |
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10000001 |
01001111 |
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00000000 |
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11000000 |
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11000000 |
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11100001 |
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00010011 |
00010000 |
11110111 |
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11001001 |
01000111 |
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01011110 |
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11100010 |
11000001 |
00000011 |
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11000110 |
00110011 |
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01100010 |
00110011 |
00001111 |
00000001 |
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11101110 |
11100001 |
00000011 |
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11001001 |
00000110 |
11111111 |
00011000 |
00000110 |
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00110100 |
11011000 |
00000110 |
00000000 |
01111110 |
10100111 |
00101000 |
00001011 |
00100011 |
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11100110 |
10000000 |
10110110 |
00010111 |
00111111 |
00011111 |
01110111 |
00101011 |
11001001 |
11010101 |
11100101 |
11001101 |
01111111 |
00101101 |
11100001 |
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11111111 |
11111111 |
11111111 |
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11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
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11111111 |
11111111 |
11111111 |
11111111 |
11111111 |
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00000000 |
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00100100 |
00100100 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00100100 |
01111110 |
00100100 |
00100100 |
01111110 |
00100100 |
00000000 |
00000000 |
00001000 |
00111110 |
00101000 |
00111110 |
00001010 |
00111110 |
00001000 |
00000000 |
01100010 |
01100100 |
00001000 |
00010000 |
00100110 |
01000110 |
00000000 |
00000000 |
00010000 |
00101000 |
00010000 |
00101010 |
01000100 |
00111010 |
00000000 |
00000000 |
00001000 |
00010000 |
00000000 |
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00000000 |
00000000 |
00000000 |
00000000 |
00000100 |
00001000 |
00001000 |
00001000 |
00001000 |
00000100 |
00000000 |
00000000 |
00100000 |
00010000 |
00010000 |
00010000 |
00010000 |
00100000 |
00000000 |
00000000 |
00000000 |
00010100 |
00001000 |
00111110 |
00001000 |
00010100 |
00000000 |
00000000 |
00000000 |
00001000 |
00001000 |
00111110 |
00001000 |
00001000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00001000 |
00001000 |
00010000 |
00000000 |
00000000 |
00000000 |
00000000 |
00111110 |
00000000 |
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00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00011000 |
00011000 |
00000000 |
00000000 |
00000000 |
00000010 |
00000100 |
00001000 |
00010000 |
00100000 |
00000000 |
00000000 |
00111100 |
01000110 |
01001010 |
01010010 |
01100010 |
00111100 |
00000000 |
00000000 |
00011000 |
00101000 |
00001000 |
00001000 |
00001000 |
00111110 |
00000000 |
00000000 |
00111100 |
01000010 |
00000010 |
00111100 |
01000000 |
01111110 |
00000000 |
00000000 |
00111100 |
01000010 |
00001100 |
00000010 |
01000010 |
00111100 |
00000000 |
00000000 |
00001000 |
00011000 |
00101000 |
01001000 |
01111110 |
00001000 |
00000000 |
00000000 |
01111110 |
01000000 |
01111100 |
00000010 |
01000010 |
00111100 |
00000000 |
00000000 |
00111100 |
01000000 |
01111100 |
01000010 |
01000010 |
00111100 |
00000000 |
00000000 |
01111110 |
00000010 |
00000100 |
00001000 |
00010000 |
00010000 |
00000000 |
00000000 |
00111100 |
01000010 |
00111100 |
01000010 |
01000010 |
00111100 |
00000000 |
00000000 |
00111100 |
01000010 |
01000010 |
00111110 |
00000010 |
00111100 |
00000000 |
00000000 |
00000000 |
00000000 |
00010000 |
00000000 |
00000000 |
00010000 |
00000000 |
00000000 |
00000000 |
00010000 |
00000000 |
00000000 |
00010000 |
00010000 |
00100000 |
00000000 |
00000000 |
00000100 |
00001000 |
00010000 |
00001000 |
00000100 |
00000000 |
00000000 |
00000000 |
00000000 |
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00000000 |
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00000000 |
00000000 |
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00010000 |
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00001000 |
00010000 |
00000000 |
00000000 |
00111100 |
01000010 |
00000100 |
00001000 |
00000000 |
00001000 |
00000000 |
00000000 |
00111100 |
01001010 |
01010110 |
01011110 |
01000000 |
00111100 |
00000000 |
00000000 |
00111100 |
01000010 |
01000010 |
01111110 |
01000010 |
01000010 |
00000000 |
00000000 |
01111100 |
01000010 |
01111100 |
01000010 |
01000010 |
01111100 |
00000000 |
00000000 |
00111100 |
01000010 |
01000000 |
01000000 |
01000010 |
00111100 |
00000000 |
00000000 |
01111000 |
01000100 |
01000010 |
01000010 |
01000100 |
01111000 |
00000000 |
00000000 |
01111110 |
01000000 |
01111100 |
01000000 |
01000000 |
01111110 |
00000000 |
00000000 |
01111110 |
01000000 |
01111100 |
01000000 |
01000000 |
01000000 |
00000000 |
00000000 |
00111100 |
01000010 |
01000000 |
01001110 |
01000010 |
00111100 |
00000000 |
00000000 |
01000010 |
01000010 |
01111110 |
01000010 |
01000010 |
01000010 |
00000000 |
00000000 |
00111110 |
00001000 |
00001000 |
00001000 |
00001000 |
00111110 |
00000000 |
00000000 |
00000010 |
00000010 |
00000010 |
01000010 |
01000010 |
00111100 |
00000000 |
00000000 |
01000100 |
01001000 |
01110000 |
01001000 |
01000100 |
01000010 |
00000000 |
00000000 |
01000000 |
01000000 |
01000000 |
01000000 |
01000000 |
01111110 |
00000000 |
00000000 |
01000010 |
01100110 |
01011010 |
01000010 |
01000010 |
01000010 |
00000000 |
00000000 |
01000010 |
01100010 |
01010010 |
01001010 |
01000110 |
01000010 |
00000000 |
00000000 |
00111100 |
01000010 |
01000010 |
01000010 |
01000010 |
00111100 |
00000000 |
00000000 |
01111100 |
01000010 |
01000010 |
01111100 |
01000000 |
01000000 |
00000000 |
00000000 |
00111100 |
01000010 |
01000010 |
01010010 |
01001010 |
00111100 |
00000000 |
00000000 |
01111100 |
01000010 |
01000010 |
01111100 |
01000100 |
01000010 |
00000000 |
00000000 |
00111100 |
01000000 |
00111100 |
00000010 |
01000010 |
00111100 |
00000000 |
00000000 |
11111110 |
00010000 |
00010000 |
00010000 |
00010000 |
00010000 |
00000000 |
00000000 |
01000010 |
01000010 |
01000010 |
01000010 |
01000010 |
00111100 |
00000000 |
00000000 |
01000010 |
01000010 |
01000010 |
01000010 |
00100100 |
00011000 |
00000000 |
00000000 |
01000010 |
01000010 |
01000010 |
01000010 |
01011010 |
00100100 |
00000000 |
00000000 |
01000010 |
00100100 |
00011000 |
00011000 |
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00000000 |
00000000 |
10000010 |
01000100 |
00101000 |
00010000 |
00010000 |
00010000 |
00000000 |
00000000 |
01111110 |
00000100 |
00001000 |
00010000 |
00100000 |
01111110 |
00000000 |
00000000 |
00001110 |
00001000 |
00001000 |
00001000 |
00001000 |
00001110 |
00000000 |
00000000 |
00000000 |
01000000 |
00100000 |
00010000 |
00001000 |
00000100 |
00000000 |
00000000 |
01110000 |
00010000 |
00010000 |
00010000 |
00010000 |
01110000 |
00000000 |
00000000 |
00010000 |
00111000 |
01010100 |
00010000 |
00010000 |
00010000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
11111111 |
00000000 |
00011100 |
00100010 |
01111000 |
00100000 |
00100000 |
01111110 |
00000000 |
00000000 |
00000000 |
00111000 |
00000100 |
00111100 |
01000100 |
00111100 |
00000000 |
00000000 |
00100000 |
00100000 |
00111100 |
00100010 |
00100010 |
00111100 |
00000000 |
00000000 |
00000000 |
00011100 |
00100000 |
00100000 |
00100000 |
00011100 |
00000000 |
00000000 |
00000100 |
00000100 |
00111100 |
01000100 |
01000100 |
00111100 |
00000000 |
00000000 |
00000000 |
00111000 |
01000100 |
01111000 |
01000000 |
00111100 |
00000000 |
00000000 |
00001100 |
00010000 |
00011000 |
00010000 |
00010000 |
00010000 |
00000000 |
00000000 |
00000000 |
00111100 |
01000100 |
01000100 |
00111100 |
00000100 |
00111000 |
00000000 |
01000000 |
01000000 |
01111000 |
01000100 |
01000100 |
01000100 |
00000000 |
00000000 |
00010000 |
00000000 |
00110000 |
00010000 |
00010000 |
00111000 |
00000000 |
00000000 |
00000100 |
00000000 |
00000100 |
00000100 |
00000100 |
00100100 |
00011000 |
00000000 |
00100000 |
00101000 |
00110000 |
00110000 |
00101000 |
00100100 |
00000000 |
00000000 |
00010000 |
00010000 |
00010000 |
00010000 |
00010000 |
00001100 |
00000000 |
00000000 |
00000000 |
01101000 |
01010100 |
01010100 |
01010100 |
01010100 |
00000000 |
00000000 |
00000000 |
01111000 |
01000100 |
01000100 |
01000100 |
01000100 |
00000000 |
00000000 |
00000000 |
00111000 |
01000100 |
01000100 |
01000100 |
00111000 |
00000000 |
00000000 |
00000000 |
01111000 |
01000100 |
01000100 |
01111000 |
01000000 |
01000000 |
00000000 |
00000000 |
00111100 |
01000100 |
01000100 |
00111100 |
00000100 |
00000110 |
00000000 |
00000000 |
00011100 |
00100000 |
00100000 |
00100000 |
00100000 |
00000000 |
00000000 |
00000000 |
00111000 |
01000000 |
00111000 |
00000100 |
01111000 |
00000000 |
00000000 |
00010000 |
00111000 |
00010000 |
00010000 |
00010000 |
00001100 |
00000000 |
00000000 |
00000000 |
01000100 |
01000100 |
01000100 |
01000100 |
00111000 |
00000000 |
00000000 |
00000000 |
01000100 |
01000100 |
00101000 |
00101000 |
00010000 |
00000000 |
00000000 |
00000000 |
01000100 |
01010100 |
01010100 |
01010100 |
00101000 |
00000000 |
00000000 |
00000000 |
01000100 |
00101000 |
00010000 |
00101000 |
01000100 |
00000000 |
00000000 |
00000000 |
01000100 |
01000100 |
01000100 |
00111100 |
00000100 |
00111000 |
00000000 |
00000000 |
01111100 |
00001000 |
00010000 |
00100000 |
01111100 |
00000000 |
00000000 |
00001110 |
00001000 |
00110000 |
00001000 |
00001000 |
00001110 |
00000000 |
00000000 |
00001000 |
00001000 |
00001000 |
00001000 |
00001000 |
00001000 |
00000000 |
00000000 |
01110000 |
00010000 |
00001100 |
00010000 |
00010000 |
01110000 |
00000000 |
00000000 |
00010100 |
00101000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00111100 |
01000010 |
10011001 |
10100001 |
10100001 |
10011001 |
01000010 |
00111100 |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/display.v
0,0 → 1,78
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: Dept. Architecture and Computing Technology. University of Seville |
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es |
// |
// Create Date: 19:13:39 20-May-2011 |
// Design Name: 7-segment display for Spartan 3 Starter Board |
// Module Name: 7-segment display for Spartan 3 Starter Board |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 1.00 - File Created |
// Additional Comments: GPL License policies apply to the contents of this file. |
// |
////////////////////////////////////////////////////////////////////////////////// |
module display( |
input clk, // some megahertzs are enough |
input load, // positive-edge load signal |
input [15:0] valor, // 16-bit (4 hex digit) value to show |
output [3:0] an, // 4 anodes (4 displays) |
output [6:0] seg // 7 cathodes per display |
); |
|
reg [3:0] ranodo = 4'b1110; |
assign an = ranodo; |
reg [6:0] rseg = 7'b0000000; |
assign seg = rseg; |
|
reg [3:0] rvalor[0:3]; |
reg [1:0] digito = 2'b00; |
|
reg [15:0] contador = 16'h0000; |
wire clkdisplay = contador[15]; |
always @(posedge clk) |
contador <= contador + 1; |
|
always @(posedge load) |
begin |
rvalor[0] <= valor[3:0]; |
rvalor[1] <= valor[7:4]; |
rvalor[2] <= valor[11:8]; |
rvalor[3] <= valor[15:12]; |
end |
|
always @(posedge clkdisplay) |
begin |
digito = digito + 1; |
ranodo = {ranodo[2:0],ranodo[3]}; |
rseg = ~hex2seg(rvalor[digito]); |
end |
|
function [6:0] hex2seg (input [3:0] v); |
case (v) |
0: hex2seg = 7'b1101111; |
1: hex2seg = 7'b0100100; |
2: hex2seg = 7'b1110011; |
3: hex2seg = 7'b1110110; |
4: hex2seg = 7'b0111100; |
5: hex2seg = 7'b1011110; |
6: hex2seg = 7'b1011111; |
7: hex2seg = 7'b1101100; |
8: hex2seg = 7'b1111111; |
9: hex2seg = 7'b1111110; |
10: hex2seg = 7'b1111101; |
11: hex2seg = 7'b0011111; |
12: hex2seg = 7'b1001011; |
13: hex2seg = 7'b0110111; |
14: hex2seg = 7'b1011011; |
15: hex2seg = 7'b1011001; |
endcase |
endfunction |
|
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/master_clock.v
0,0 → 1,75
//////////////////////////////////////////////////////////////////////////////// |
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
//////////////////////////////////////////////////////////////////////////////// |
// ____ ____ |
// / /\/ / |
// /___/ \ / Vendor: Xilinx |
// \ \ \/ Version : 12.4 |
// \ \ Application : xaw2verilog |
// / / Filename : master_clock.v |
// /___/ /\ Timestamp : 04/21/2012 19:26:35 |
// \ \ / \ |
// \___\/\___\ |
// |
//Command: xaw2verilog -st C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock.xaw C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock |
//Design Name: master_clock |
//Device: xc3s1000-ft256-4 |
// |
// Module master_clock |
// Generated by Xilinx Architecture Wizard |
// Written for synthesis tool: XST |
// Period Jitter (unit interval) for block DCM_INST = 0.05 UI |
// Period Jitter (Peak-to-Peak) for block DCM_INST = 1.92 ns |
`timescale 1ns / 1ps |
|
module master_clock(CLKIN_IN, |
CLKFX_OUT, |
CLKIN_IBUFG_OUT, |
CLK0_OUT); |
|
input CLKIN_IN; |
output CLKFX_OUT; |
output CLKIN_IBUFG_OUT; |
output CLK0_OUT; |
|
wire CLKFB_IN; |
wire CLKFX_BUF; |
wire CLKIN_IBUFG; |
wire CLK0_BUF; |
wire GND_BIT; |
|
assign GND_BIT = 0; |
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; |
assign CLK0_OUT = CLKFB_IN; |
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), |
.O(CLKFX_OUT)); |
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), |
.O(CLKIN_IBUFG)); |
BUFG CLK0_BUFG_INST (.I(CLK0_BUF), |
.O(CLKFB_IN)); |
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25), |
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"), |
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), |
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), |
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), |
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) |
DCM_INST (.CLKFB(CLKFB_IN), |
.CLKIN(CLKIN_IBUFG), |
.DSSEN(GND_BIT), |
.PSCLK(GND_BIT), |
.PSEN(GND_BIT), |
.PSINCDEC(GND_BIT), |
.RST(GND_BIT), |
.CLKDV(), |
.CLKFX(CLKFX_BUF), |
.CLKFX180(), |
.CLK0(CLK0_BUF), |
.CLK2X(), |
.CLK2X180(), |
.CLK90(), |
.CLK180(), |
.CLK270(), |
.LOCKED(), |
.PSDONE(), |
.STATUS()); |
endmodule |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tv80_mcode.v
0,0 → 1,2650
// |
// TV80 8-Bit Microprocessor Core |
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
// |
// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org) |
// |
// Permission is hereby granted, free of charge, to any person obtaining a |
// copy of this software and associated documentation files (the "Software"), |
// to deal in the Software without restriction, including without limitation |
// the rights to use, copy, modify, merge, publish, distribute, sublicense, |
// and/or sell copies of the Software, and to permit persons to whom the |
// Software is furnished to do so, subject to the following conditions: |
// |
// The above copyright notice and this permission notice shall be included |
// in all copies or substantial portions of the Software. |
// |
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
module tv80_mcode |
(/*AUTOARG*/ |
// Outputs |
MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, |
Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, |
Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, |
LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, |
ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, |
I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, |
// Inputs |
IR, ISet, MCycle, F, NMICycle, IntCycle |
); |
|
parameter Mode = 0; |
parameter Flag_C = 0; |
parameter Flag_N = 1; |
parameter Flag_P = 2; |
parameter Flag_X = 3; |
parameter Flag_H = 4; |
parameter Flag_Y = 5; |
parameter Flag_Z = 6; |
parameter Flag_S = 7; |
|
input [7:0] IR; |
input [1:0] ISet ; |
input [6:0] MCycle ; |
input [7:0] F ; |
input NMICycle ; |
input IntCycle ; |
output [2:0] MCycles ; |
output [2:0] TStates ; |
output [1:0] Prefix ; // None,BC,ED,DD/FD |
output Inc_PC ; |
output Inc_WZ ; |
output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc |
output Read_To_Reg ; |
output Read_To_Acc ; |
output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F |
output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 |
output [3:0] ALU_Op ; |
output Save_ALU ; |
output PreserveC ; |
output Arith16 ; |
output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI |
output IORQ ; |
output Jump ; |
output JumpE ; |
output JumpXY ; |
output Call ; |
output RstP ; |
output LDZ ; |
output LDW ; |
output LDSPHL ; |
output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None |
output ExchangeDH ; |
output ExchangeRp ; |
output ExchangeAF ; |
output ExchangeRS ; |
output I_DJNZ ; |
output I_CPL ; |
output I_CCF ; |
output I_SCF ; |
output I_RETN ; |
output I_BT ; |
output I_BC ; |
output I_BTR ; |
output I_RLD ; |
output I_RRD ; |
output I_INRC ; |
output SetDI ; |
output SetEI ; |
output [1:0] IMode ; |
output Halt ; |
output NoRead ; |
output Write ; |
|
// regs |
reg [2:0] MCycles ; |
reg [2:0] TStates ; |
reg [1:0] Prefix ; // None,BC,ED,DD/FD |
reg Inc_PC ; |
reg Inc_WZ ; |
reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc |
reg Read_To_Reg ; |
reg Read_To_Acc ; |
reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F |
reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 |
reg [3:0] ALU_Op ; |
reg Save_ALU ; |
reg PreserveC ; |
reg Arith16 ; |
reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI |
reg IORQ ; |
reg Jump ; |
reg JumpE ; |
reg JumpXY ; |
reg Call ; |
reg RstP ; |
reg LDZ ; |
reg LDW ; |
reg LDSPHL ; |
reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None |
reg ExchangeDH ; |
reg ExchangeRp ; |
reg ExchangeAF ; |
reg ExchangeRS ; |
reg I_DJNZ ; |
reg I_CPL ; |
reg I_CCF ; |
reg I_SCF ; |
reg I_RETN ; |
reg I_BT ; |
reg I_BC ; |
reg I_BTR ; |
reg I_RLD ; |
reg I_RRD ; |
reg I_INRC ; |
reg SetDI ; |
reg SetEI ; |
reg [1:0] IMode ; |
reg Halt ; |
reg NoRead ; |
reg Write ; |
|
parameter aNone = 3'b111; |
parameter aBC = 3'b000; |
parameter aDE = 3'b001; |
parameter aXY = 3'b010; |
parameter aIOA = 3'b100; |
parameter aSP = 3'b101; |
parameter aZI = 3'b110; |
// constant aNone : std_logic_vector[2:0] = 3'b000; |
// constant aXY : std_logic_vector[2:0] = 3'b001; |
// constant aIOA : std_logic_vector[2:0] = 3'b010; |
// constant aSP : std_logic_vector[2:0] = 3'b011; |
// constant aBC : std_logic_vector[2:0] = 3'b100; |
// constant aDE : std_logic_vector[2:0] = 3'b101; |
// constant aZI : std_logic_vector[2:0] = 3'b110; |
|
function is_cc_true; |
input [7:0] FF; |
input [2:0] cc; |
begin |
if (Mode == 3 ) |
begin |
case (cc) |
3'b000 : is_cc_true = FF[7] == 1'b0; // NZ |
3'b001 : is_cc_true = FF[7] == 1'b1; // Z |
3'b010 : is_cc_true = FF[4] == 1'b0; // NC |
3'b011 : is_cc_true = FF[4] == 1'b1; // C |
3'b100 : is_cc_true = 0; |
3'b101 : is_cc_true = 0; |
3'b110 : is_cc_true = 0; |
3'b111 : is_cc_true = 0; |
endcase |
end |
else |
begin |
case (cc) |
3'b000 : is_cc_true = FF[6] == 1'b0; // NZ |
3'b001 : is_cc_true = FF[6] == 1'b1; // Z |
3'b010 : is_cc_true = FF[0] == 1'b0; // NC |
3'b011 : is_cc_true = FF[0] == 1'b1; // C |
3'b100 : is_cc_true = FF[2] == 1'b0; // PO |
3'b101 : is_cc_true = FF[2] == 1'b1; // PE |
3'b110 : is_cc_true = FF[7] == 1'b0; // P |
3'b111 : is_cc_true = FF[7] == 1'b1; // M |
endcase |
end |
end |
endfunction // is_cc_true |
|
|
reg [2:0] DDD; |
reg [2:0] SSS; |
reg [1:0] DPAIR; |
|
always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle |
or NMICycle) |
begin |
DDD = IR[5:3]; |
SSS = IR[2:0]; |
DPAIR = IR[5:4]; |
|
MCycles = 3'b001; |
if (MCycle[0] ) |
begin |
TStates = 3'b100; |
end |
else |
begin |
TStates = 3'b011; |
end |
Prefix = 2'b00; |
Inc_PC = 1'b0; |
Inc_WZ = 1'b0; |
IncDec_16 = 4'b0000; |
Read_To_Acc = 1'b0; |
Read_To_Reg = 1'b0; |
Set_BusB_To = 4'b0000; |
Set_BusA_To = 4'b0000; |
ALU_Op = { 1'b0, IR[5:3] }; |
Save_ALU = 1'b0; |
PreserveC = 1'b0; |
Arith16 = 1'b0; |
IORQ = 1'b0; |
Set_Addr_To = aNone; |
Jump = 1'b0; |
JumpE = 1'b0; |
JumpXY = 1'b0; |
Call = 1'b0; |
RstP = 1'b0; |
LDZ = 1'b0; |
LDW = 1'b0; |
LDSPHL = 1'b0; |
Special_LD = 3'b000; |
ExchangeDH = 1'b0; |
ExchangeRp = 1'b0; |
ExchangeAF = 1'b0; |
ExchangeRS = 1'b0; |
I_DJNZ = 1'b0; |
I_CPL = 1'b0; |
I_CCF = 1'b0; |
I_SCF = 1'b0; |
I_RETN = 1'b0; |
I_BT = 1'b0; |
I_BC = 1'b0; |
I_BTR = 1'b0; |
I_RLD = 1'b0; |
I_RRD = 1'b0; |
I_INRC = 1'b0; |
SetDI = 1'b0; |
SetEI = 1'b0; |
IMode = 2'b11; |
Halt = 1'b0; |
NoRead = 1'b0; |
Write = 1'b0; |
|
case (ISet) |
2'b00 : |
begin |
|
//---------------------------------------------------------------------------- |
// |
// Unprefixed instructions |
// |
//---------------------------------------------------------------------------- |
|
casez (IR) |
// 8 BIT LOAD GROUP |
8'b01zzzzzz : |
begin |
if (IR[5:0] == 6'b110110) |
Halt = 1'b1; |
else if (IR[2:0] == 3'b110) |
begin |
// LD r,(HL) |
MCycles = 3'b010; |
if (MCycle[0]) |
Set_Addr_To = aXY; |
if (MCycle[1]) |
begin |
Set_BusA_To[2:0] = DDD; |
Read_To_Reg = 1'b1; |
end |
end // if (IR[2:0] == 3'b110) |
else if (IR[5:3] == 3'b110) |
begin |
// LD (HL),r |
MCycles = 3'b010; |
if (MCycle[0]) |
begin |
Set_Addr_To = aXY; |
Set_BusB_To[2:0] = SSS; |
Set_BusB_To[3] = 1'b0; |
end |
if (MCycle[1]) |
Write = 1'b1; |
end // if (IR[5:3] == 3'b110) |
else |
begin |
Set_BusB_To[2:0] = SSS; |
ExchangeRp = 1'b1; |
Set_BusA_To[2:0] = DDD; |
Read_To_Reg = 1'b1; |
end // else: !if(IR[5:3] == 3'b110) |
end // case: 8'b01zzzzzz |
|
8'b00zzz110 : |
begin |
if (IR[5:3] == 3'b110) |
begin |
// LD (HL),n |
MCycles = 3'b011; |
if (MCycle[1]) |
begin |
Inc_PC = 1'b1; |
Set_Addr_To = aXY; |
Set_BusB_To[2:0] = SSS; |
Set_BusB_To[3] = 1'b0; |
end |
if (MCycle[2]) |
Write = 1'b1; |
end // if (IR[5:3] == 3'b110) |
else |
begin |
// LD r,n |
MCycles = 3'b010; |
if (MCycle[1]) |
begin |
Inc_PC = 1'b1; |
Set_BusA_To[2:0] = DDD; |
Read_To_Reg = 1'b1; |
end |
end |
end |
|
8'b00001010 : |
begin |
// LD A,(BC) |
MCycles = 3'b010; |
if (MCycle[0]) |
Set_Addr_To = aBC; |
if (MCycle[1]) |
Read_To_Acc = 1'b1; |
end // case: 8'b00001010 |
|
8'b00011010 : |
begin |
// LD A,(DE) |
MCycles = 3'b010; |
if (MCycle[0]) |
Set_Addr_To = aDE; |
if (MCycle[1]) |
Read_To_Acc = 1'b1; |
end // case: 8'b00011010 |
|
8'b00111010 : |
begin |
if (Mode == 3 ) |
begin |
// LDD A,(HL) |
MCycles = 3'b010; |
if (MCycle[0]) |
Set_Addr_To = aXY; |
if (MCycle[1]) |
begin |
Read_To_Acc = 1'b1; |
IncDec_16 = 4'b1110; |
end |
end |
else |
begin |
// LD A,(nn) |
MCycles = 3'b100; |
if (MCycle[1]) |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
if (MCycle[2]) |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
end |
if (MCycle[3]) |
begin |
Read_To_Acc = 1'b1; |
end |
end // else: !if(Mode == 3 ) |
end // case: 8'b00111010 |
|
8'b00000010 : |
begin |
// LD (BC),A |
MCycles = 3'b010; |
if (MCycle[0]) |
begin |
Set_Addr_To = aBC; |
Set_BusB_To = 4'b0111; |
end |
if (MCycle[1]) |
begin |
Write = 1'b1; |
end |
end // case: 8'b00000010 |
|
8'b00010010 : |
begin |
// LD (DE),A |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aDE; |
Set_BusB_To = 4'b0111; |
end |
MCycle[1] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b00010010 |
|
8'b00110010 : |
begin |
if (Mode == 3 ) |
begin |
// LDD (HL),A |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aXY; |
Set_BusB_To = 4'b0111; |
end |
MCycle[1] : |
begin |
Write = 1'b1; |
IncDec_16 = 4'b1110; |
end |
default :; |
endcase // case(MCycle) |
|
end |
else |
begin |
// LD (nn),A |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
Set_BusB_To = 4'b0111; |
end |
MCycle[3] : |
begin |
Write = 1'b1; |
end |
default :; |
endcase |
end // else: !if(Mode == 3 ) |
end // case: 8'b00110010 |
|
|
// 16 BIT LOAD GROUP |
8'b00000001,8'b00010001,8'b00100001,8'b00110001 : |
begin |
// LD dd,nn |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
Read_To_Reg = 1'b1; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusA_To[3:0] = 4'b1000; |
end |
else |
begin |
Set_BusA_To[2:1] = DPAIR; |
Set_BusA_To[0] = 1'b1; |
end |
end // case: 2 |
|
MCycle[2] : |
begin |
Inc_PC = 1'b1; |
Read_To_Reg = 1'b1; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusA_To[3:0] = 4'b1001; |
end |
else |
begin |
Set_BusA_To[2:1] = DPAIR; |
Set_BusA_To[0] = 1'b0; |
end |
end // case: 3 |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 |
|
8'b00101010 : |
begin |
if (Mode == 3 ) |
begin |
// LDI A,(HL) |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
Read_To_Acc = 1'b1; |
IncDec_16 = 4'b0110; |
end |
|
default :; |
endcase |
end |
else |
begin |
// LD HL,(nn) |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
end |
MCycle[3] : |
begin |
Set_BusA_To[2:0] = 3'b101; // L |
Read_To_Reg = 1'b1; |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
end |
MCycle[4] : |
begin |
Set_BusA_To[2:0] = 3'b100; // H |
Read_To_Reg = 1'b1; |
end |
default :; |
endcase |
end // else: !if(Mode == 3 ) |
end // case: 8'b00101010 |
|
8'b00100010 : |
begin |
if (Mode == 3 ) |
begin |
// LDI (HL),A |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aXY; |
Set_BusB_To = 4'b0111; |
end |
MCycle[1] : |
begin |
Write = 1'b1; |
IncDec_16 = 4'b0110; |
end |
default :; |
endcase |
end |
else |
begin |
// LD (nn),HL |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
Set_BusB_To = 4'b0101; // L |
end |
|
MCycle[3] : |
begin |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
Write = 1'b1; |
Set_BusB_To = 4'b0100; // H |
end |
MCycle[4] : |
Write = 1'b1; |
default :; |
endcase |
end // else: !if(Mode == 3 ) |
end // case: 8'b00100010 |
|
8'b11111001 : |
begin |
// LD SP,HL |
TStates = 3'b110; |
LDSPHL = 1'b1; |
end |
|
8'b11zz0101 : |
begin |
// PUSH qq |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusB_To = 4'b0111; |
end |
else |
begin |
Set_BusB_To[2:1] = DPAIR; |
Set_BusB_To[0] = 1'b0; |
Set_BusB_To[3] = 1'b0; |
end |
end // case: 1 |
|
MCycle[1] : |
begin |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusB_To = 4'b1011; |
end |
else |
begin |
Set_BusB_To[2:1] = DPAIR; |
Set_BusB_To[0] = 1'b1; |
Set_BusB_To[3] = 1'b0; |
end |
Write = 1'b1; |
end // case: 2 |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 |
|
8'b11zz0001 : |
begin |
// POP qq |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aSP; |
MCycle[1] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
Read_To_Reg = 1'b1; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusA_To[3:0] = 4'b1011; |
end |
else |
begin |
Set_BusA_To[2:1] = DPAIR; |
Set_BusA_To[0] = 1'b1; |
end |
end // case: 2 |
|
MCycle[2] : |
begin |
IncDec_16 = 4'b0111; |
Read_To_Reg = 1'b1; |
if (DPAIR == 2'b11 ) |
begin |
Set_BusA_To[3:0] = 4'b0111; |
end |
else |
begin |
Set_BusA_To[2:1] = DPAIR; |
Set_BusA_To[0] = 1'b0; |
end |
end // case: 3 |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 |
|
|
// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP |
8'b11101011 : |
begin |
if (Mode != 3 ) |
begin |
// EX DE,HL |
ExchangeDH = 1'b1; |
end |
end |
|
8'b00001000 : |
begin |
if (Mode == 3 ) |
begin |
// LD (nn),SP |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
Set_BusB_To = 4'b1000; |
end |
|
MCycle[3] : |
begin |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
Write = 1'b1; |
Set_BusB_To = 4'b1001; |
end |
|
MCycle[4] : |
Write = 1'b1; |
default :; |
endcase |
end |
else if (Mode < 2 ) |
begin |
// EX AF,AF' |
ExchangeAF = 1'b1; |
end |
end // case: 8'b00001000 |
|
8'b11011001 : |
begin |
if (Mode == 3 ) |
begin |
// RETI |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aSP; |
MCycle[1] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Jump = 1'b1; |
IncDec_16 = 4'b0111; |
I_RETN = 1'b1; |
SetEI = 1'b1; |
end |
default :; |
endcase |
end |
else if (Mode < 2 ) |
begin |
// EXX |
ExchangeRS = 1'b1; |
end |
end // case: 8'b11011001 |
|
8'b11100011 : |
begin |
if (Mode != 3 ) |
begin |
// EX (SP),HL |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aSP; |
MCycle[1] : |
begin |
Read_To_Reg = 1'b1; |
Set_BusA_To = 4'b0101; |
Set_BusB_To = 4'b0101; |
Set_Addr_To = aSP; |
end |
MCycle[2] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
TStates = 3'b100; |
Write = 1'b1; |
end |
MCycle[3] : |
begin |
Read_To_Reg = 1'b1; |
Set_BusA_To = 4'b0100; |
Set_BusB_To = 4'b0100; |
Set_Addr_To = aSP; |
end |
MCycle[4] : |
begin |
IncDec_16 = 4'b1111; |
TStates = 3'b101; |
Write = 1'b1; |
end |
|
default :; |
endcase |
end // if (Mode != 3 ) |
end // case: 8'b11100011 |
|
|
// 8 BIT ARITHMETIC AND LOGICAL GROUP |
8'b10zzzzzz : |
begin |
if (IR[2:0] == 3'b110) |
begin |
// ADD A,(HL) |
// ADC A,(HL) |
// SUB A,(HL) |
// SBC A,(HL) |
// AND A,(HL) |
// OR A,(HL) |
// XOR A,(HL) |
// CP A,(HL) |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusB_To[2:0] = SSS; |
Set_BusA_To[2:0] = 3'b111; |
end |
|
default :; |
endcase // case(MCycle) |
end // if (IR[2:0] == 3'b110) |
else |
begin |
// ADD A,r |
// ADC A,r |
// SUB A,r |
// SBC A,r |
// AND A,r |
// OR A,r |
// XOR A,r |
// CP A,r |
Set_BusB_To[2:0] = SSS; |
Set_BusA_To[2:0] = 3'b111; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
end // else: !if(IR[2:0] == 3'b110) |
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... |
|
8'b11zzz110 : |
begin |
// ADD A,n |
// ADC A,n |
// SUB A,n |
// SBC A,n |
// AND A,n |
// OR A,n |
// XOR A,n |
// CP A,n |
MCycles = 3'b010; |
if (MCycle[1] ) |
begin |
Inc_PC = 1'b1; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusB_To[2:0] = SSS; |
Set_BusA_To[2:0] = 3'b111; |
end |
end |
|
8'b00zzz100 : |
begin |
if (IR[5:3] == 3'b110) |
begin |
// INC (HL) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
TStates = 3'b100; |
Set_Addr_To = aXY; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
PreserveC = 1'b1; |
ALU_Op = 4'b0000; |
Set_BusB_To = 4'b1010; |
Set_BusA_To[2:0] = DDD; |
end // case: 2 |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b00110100 |
else |
begin |
// INC r |
Set_BusB_To = 4'b1010; |
Set_BusA_To[2:0] = DDD; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
PreserveC = 1'b1; |
ALU_Op = 4'b0000; |
end |
end |
|
8'b00zzz101 : |
begin |
if (IR[5:3] == 3'b110) |
begin |
// DEC (HL) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
TStates = 3'b100; |
Set_Addr_To = aXY; |
ALU_Op = 4'b0010; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
PreserveC = 1'b1; |
Set_BusB_To = 4'b1010; |
Set_BusA_To[2:0] = DDD; |
end // case: 2 |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end |
else |
begin |
// DEC r |
Set_BusB_To = 4'b1010; |
Set_BusA_To[2:0] = DDD; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
PreserveC = 1'b1; |
ALU_Op = 4'b0010; |
end |
end |
|
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS |
8'b00100111 : |
begin |
// DAA |
Set_BusA_To[2:0] = 3'b111; |
Read_To_Reg = 1'b1; |
ALU_Op = 4'b1100; |
Save_ALU = 1'b1; |
end |
|
8'b00101111 : |
// CPL |
I_CPL = 1'b1; |
|
8'b00111111 : |
// CCF |
I_CCF = 1'b1; |
|
8'b00110111 : |
// SCF |
I_SCF = 1'b1; |
|
8'b00000000 : |
begin |
if (NMICycle == 1'b1 ) |
begin |
// NMI |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1101; |
end |
|
MCycle[1] : |
begin |
TStates = 3'b100; |
Write = 1'b1; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1100; |
end |
|
MCycle[2] : |
begin |
TStates = 3'b100; |
Write = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
|
end |
else if (IntCycle == 1'b1 ) |
begin |
// INT (IM 2) |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
LDZ = 1'b1; |
TStates = 3'b101; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1101; |
end |
|
MCycle[1] : |
begin |
TStates = 3'b100; |
Write = 1'b1; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1100; |
end |
|
MCycle[2] : |
begin |
TStates = 3'b100; |
Write = 1'b1; |
end |
|
MCycle[3] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[4] : |
Jump = 1'b1; |
default :; |
endcase |
end |
end // case: 8'b00000000 |
|
8'b11110011 : |
// DI |
SetDI = 1'b1; |
|
8'b11111011 : |
// EI |
SetEI = 1'b1; |
|
// 16 BIT ARITHMETIC GROUP |
8'b00zz1001 : |
begin |
// ADD HL,ss |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
NoRead = 1'b1; |
ALU_Op = 4'b0000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusA_To[2:0] = 3'b101; |
case (IR[5:4]) |
0,1,2 : |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b1; |
end |
|
default : |
Set_BusB_To = 4'b1000; |
endcase // case(IR[5:4]) |
|
TStates = 3'b100; |
Arith16 = 1'b1; |
end // case: 2 |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0001; |
Set_BusA_To[2:0] = 3'b100; |
case (IR[5:4]) |
0,1,2 : |
Set_BusB_To[2:1] = IR[5:4]; |
default : |
Set_BusB_To = 4'b1001; |
endcase |
Arith16 = 1'b1; |
end // case: 3 |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 |
|
8'b00zz0011 : |
begin |
// INC ss |
TStates = 3'b110; |
IncDec_16[3:2] = 2'b01; |
IncDec_16[1:0] = DPAIR; |
end |
|
8'b00zz1011 : |
begin |
// DEC ss |
TStates = 3'b110; |
IncDec_16[3:2] = 2'b11; |
IncDec_16[1:0] = DPAIR; |
end |
|
// ROTATE AND SHIFT GROUP |
8'b00000111, |
// RLCA |
8'b00010111, |
// RLA |
8'b00001111, |
// RRCA |
8'b00011111 : |
// RRA |
begin |
Set_BusA_To[2:0] = 3'b111; |
ALU_Op = 4'b1000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
end // case: 8'b00000111,... |
|
|
// JUMP GROUP |
8'b11000011 : |
begin |
// JP nn |
MCycles = 3'b011; |
if (MCycle[1]) |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
if (MCycle[2]) |
begin |
Inc_PC = 1'b1; |
Jump = 1'b1; |
end |
|
end // case: 8'b11000011 |
|
8'b11zzz010 : |
begin |
if (IR[5] == 1'b1 && Mode == 3 ) |
begin |
case (IR[4:3]) |
2'b00 : |
begin |
// LD ($FF00+C),A |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aBC; |
Set_BusB_To = 4'b0111; |
end |
MCycle[1] : |
begin |
Write = 1'b1; |
IORQ = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 2'b00 |
|
2'b01 : |
begin |
// LD (nn),A |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
Set_BusB_To = 4'b0111; |
end |
|
MCycle[3] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: default :... |
|
2'b10 : |
begin |
// LD A,($FF00+C) |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aBC; |
MCycle[1] : |
begin |
Read_To_Acc = 1'b1; |
IORQ = 1'b1; |
end |
default :; |
endcase // case(MCycle) |
end // case: 2'b10 |
|
2'b11 : |
begin |
// LD A,(nn) |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
end |
MCycle[3] : |
Read_To_Acc = 1'b1; |
default :; |
endcase // case(MCycle) |
end |
endcase |
end |
else |
begin |
// JP cc,nn |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Inc_PC = 1'b1; |
if (is_cc_true(F, IR[5:3]) ) |
begin |
Jump = 1'b1; |
end |
end |
|
default :; |
endcase |
end // else: !if(DPAIR == 2'b11 ) |
end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 |
|
8'b00011000 : |
begin |
if (Mode != 2 ) |
begin |
// JR e |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
Inc_PC = 1'b1; |
MCycle[2] : |
begin |
NoRead = 1'b1; |
JumpE = 1'b1; |
TStates = 3'b101; |
end |
default :; |
endcase |
end // if (Mode != 2 ) |
end // case: 8'b00011000 |
|
// Conditional relative jumps (JR [C/NC/Z/NZ], e) |
8'b001zz000 : |
begin |
if (Mode != 2 ) |
begin |
MCycles = 3'd3; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
|
case (IR[4:3]) |
0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3; |
1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3; |
2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3; |
3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3; |
endcase |
end |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
JumpE = 1'b1; |
TStates = 3'd5; |
end |
default :; |
endcase |
end // if (Mode != 2 ) |
end // case: 8'b00111000 |
|
8'b11101001 : |
// JP (HL) |
JumpXY = 1'b1; |
|
8'b00010000 : |
begin |
if (Mode == 3 ) |
begin |
I_DJNZ = 1'b1; |
end |
else if (Mode < 2 ) |
begin |
// DJNZ,e |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
I_DJNZ = 1'b1; |
Set_BusB_To = 4'b1010; |
Set_BusA_To[2:0] = 3'b000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0010; |
end |
MCycle[1] : |
begin |
I_DJNZ = 1'b1; |
Inc_PC = 1'b1; |
end |
MCycle[2] : |
begin |
NoRead = 1'b1; |
JumpE = 1'b1; |
TStates = 3'b101; |
end |
default :; |
endcase |
end // if (Mode < 2 ) |
end // case: 8'b00010000 |
|
|
// CALL AND RETURN GROUP |
8'b11001101 : |
begin |
// CALL nn |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
IncDec_16 = 4'b1111; |
Inc_PC = 1'b1; |
TStates = 3'b100; |
Set_Addr_To = aSP; |
LDW = 1'b1; |
Set_BusB_To = 4'b1101; |
end |
MCycle[3] : |
begin |
Write = 1'b1; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1100; |
end |
MCycle[4] : |
begin |
Write = 1'b1; |
Call = 1'b1; |
end |
default :; |
endcase // case(MCycle) |
end // case: 8'b11001101 |
|
8'b11zzz100 : |
begin |
if (IR[5] == 1'b0 || Mode != 3 ) |
begin |
// CALL cc,nn |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Inc_PC = 1'b1; |
LDW = 1'b1; |
if (is_cc_true(F, IR[5:3]) ) |
begin |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
TStates = 3'b100; |
Set_BusB_To = 4'b1101; |
end |
else |
begin |
MCycles = 3'b011; |
end // else: !if(is_cc_true(F, IR[5:3]) ) |
end // case: 3 |
|
MCycle[3] : |
begin |
Write = 1'b1; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1100; |
end |
|
MCycle[4] : |
begin |
Write = 1'b1; |
Call = 1'b1; |
end |
|
default :; |
endcase |
end // if (IR[5] == 1'b0 || Mode != 3 ) |
end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 |
|
8'b11001001 : |
begin |
// RET |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
Set_Addr_To = aSP; |
end |
|
MCycle[1] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Jump = 1'b1; |
IncDec_16 = 4'b0111; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b11001001 |
|
8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : |
begin |
if (IR[5] == 1'b1 && Mode == 3 ) |
begin |
case (IR[4:3]) |
2'b00 : |
begin |
// LD ($FF00+nn),A |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
Set_Addr_To = aIOA; |
Set_BusB_To = 4'b0111; |
end |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 2'b00 |
|
2'b01 : |
begin |
// ADD SP,n |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
ALU_Op = 4'b0000; |
Inc_PC = 1'b1; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusA_To = 4'b1000; |
Set_BusB_To = 4'b0110; |
end |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0001; |
Set_BusA_To = 4'b1001; |
Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 2'b01 |
|
2'b10 : |
begin |
// LD A,($FF00+nn) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
Set_Addr_To = aIOA; |
end |
|
MCycle[2] : |
Read_To_Acc = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 2'b10 |
|
2'b11 : |
begin |
// LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
end |
|
MCycle[3] : |
begin |
Set_BusA_To[2:0] = 3'b101; // L |
Read_To_Reg = 1'b1; |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
end |
|
MCycle[4] : |
begin |
Set_BusA_To[2:0] = 3'b100; // H |
Read_To_Reg = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 2'b11 |
|
endcase // case(IR[4:3]) |
|
end |
else |
begin |
// RET cc |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
if (is_cc_true(F, IR[5:3]) ) |
begin |
Set_Addr_To = aSP; |
end |
else |
begin |
MCycles = 3'b001; |
end |
TStates = 3'b101; |
end // case: 1 |
|
MCycle[1] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
LDZ = 1'b1; |
end |
MCycle[2] : |
begin |
Jump = 1'b1; |
IncDec_16 = 4'b0111; |
end |
default :; |
endcase |
end // else: !if(IR[5] == 1'b1 && Mode == 3 ) |
end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 |
|
8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : |
begin |
// RST p |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1101; |
end |
|
MCycle[1] : |
begin |
Write = 1'b1; |
IncDec_16 = 4'b1111; |
Set_Addr_To = aSP; |
Set_BusB_To = 4'b1100; |
end |
|
MCycle[2] : |
begin |
Write = 1'b1; |
RstP = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 |
|
// INPUT AND OUTPUT GROUP |
8'b11011011 : |
begin |
if (Mode != 3 ) |
begin |
// IN A,(n) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
Set_Addr_To = aIOA; |
end |
|
MCycle[2] : |
begin |
Read_To_Acc = 1'b1; |
IORQ = 1'b1; |
end |
|
default :; |
endcase |
end // if (Mode != 3 ) |
end // case: 8'b11011011 |
|
8'b11010011 : |
begin |
if (Mode != 3 ) |
begin |
// OUT (n),A |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
Set_Addr_To = aIOA; |
Set_BusB_To = 4'b0111; |
end |
|
MCycle[2] : |
begin |
Write = 1'b1; |
IORQ = 1'b1; |
end |
|
default :; |
endcase |
end // if (Mode != 3 ) |
end // case: 8'b11010011 |
|
|
//---------------------------------------------------------------------------- |
//---------------------------------------------------------------------------- |
// MULTIBYTE INSTRUCTIONS |
//---------------------------------------------------------------------------- |
//---------------------------------------------------------------------------- |
|
8'b11001011 : |
begin |
if (Mode != 2 ) |
begin |
Prefix = 2'b01; |
end |
end |
|
8'b11101101 : |
begin |
if (Mode < 2 ) |
begin |
Prefix = 2'b10; |
end |
end |
|
8'b11011101,8'b11111101 : |
begin |
if (Mode < 2 ) |
begin |
Prefix = 2'b11; |
end |
end |
|
endcase // case(IR) |
end // case: 2'b00 |
|
|
2'b01 : |
begin |
|
|
//---------------------------------------------------------------------------- |
// |
// CB prefixed instructions |
// |
//---------------------------------------------------------------------------- |
|
Set_BusA_To[2:0] = IR[2:0]; |
Set_BusB_To[2:0] = IR[2:0]; |
|
casez (IR) |
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, |
8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, |
8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, |
8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, |
8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, |
8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, |
8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, |
8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : |
begin |
// RLC r |
// RL r |
// RRC r |
// RR r |
// SLA r |
// SRA r |
// SRL r |
// SLL r (Undocumented) / SWAP r |
if (MCycle[0] ) begin |
ALU_Op = 4'b1000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
end |
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... |
|
8'b00zzz110 : |
begin |
// RLC (HL) |
// RL (HL) |
// RRC (HL) |
// RR (HL) |
// SRA (HL) |
// SRL (HL) |
// SLA (HL) |
// SLL (HL) (Undocumented) / SWAP (HL) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0], MCycle[6] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
ALU_Op = 4'b1000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_Addr_To = aXY; |
TStates = 3'b100; |
end |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 |
|
8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, |
8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, |
8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, |
8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, |
8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, |
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, |
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, |
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : |
begin |
// BIT b,r |
if (MCycle[0] ) |
begin |
Set_BusB_To[2:0] = IR[2:0]; |
ALU_Op = 4'b1001; |
end |
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... |
|
8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : |
begin |
// BIT b,(HL) |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0], MCycle[6] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
ALU_Op = 4'b1001; |
TStates = 3'b100; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 |
|
8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, |
8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, |
8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, |
8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, |
8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, |
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, |
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, |
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : |
begin |
// SET b,r |
if (MCycle[0] ) |
begin |
ALU_Op = 4'b1010; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
end |
end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... |
|
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : |
begin |
// SET b,(HL) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0], MCycle[6] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
ALU_Op = 4'b1010; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_Addr_To = aXY; |
TStates = 3'b100; |
end |
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 |
|
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, |
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, |
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, |
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, |
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, |
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, |
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, |
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : |
begin |
// RES b,r |
if (MCycle[0] ) |
begin |
ALU_Op = 4'b1011; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
end |
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... |
|
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : |
begin |
// RES b,(HL) |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0], MCycle[6] : |
Set_Addr_To = aXY; |
MCycle[1] : |
begin |
ALU_Op = 4'b1011; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_Addr_To = aXY; |
TStates = 3'b100; |
end |
|
MCycle[2] : |
Write = 1'b1; |
default :; |
endcase // case(MCycle) |
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 |
|
endcase // case(IR) |
end // case: 2'b01 |
|
|
default : |
begin : default_ed_block |
|
//---------------------------------------------------------------------------- |
// |
// ED prefixed instructions |
// |
//---------------------------------------------------------------------------- |
|
casez (IR) |
/* |
* Undocumented NOP instructions commented out to reduce size of mcode |
* |
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 |
,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 |
,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 |
,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 |
,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 |
,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 |
,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 |
,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 |
|
|
,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 |
,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 |
,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 |
,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 |
, 8'b10100100,8'b10100101,8'b10100110,8'b10100111 |
, 8'b10101100,8'b10101101,8'b10101110,8'b10101111 |
, 8'b10110100,8'b10110101,8'b10110110,8'b10110111 |
, 8'b10111100,8'b10111101,8'b10111110,8'b10111111 |
,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 |
,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 |
,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 |
,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 |
,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 |
,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 |
,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 |
,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : |
; // NOP, undocumented |
|
8'b01111110,8'b01111111 : |
// NOP, undocumented |
; |
*/ |
|
// 8 BIT LOAD GROUP |
8'b01010111 : |
begin |
// LD A,I |
Special_LD = 3'b100; |
TStates = 3'b101; |
end |
|
8'b01011111 : |
begin |
// LD A,R |
Special_LD = 3'b101; |
TStates = 3'b101; |
end |
|
8'b01000111 : |
begin |
// LD I,A |
Special_LD = 3'b110; |
TStates = 3'b101; |
end |
|
8'b01001111 : |
begin |
// LD R,A |
Special_LD = 3'b111; |
TStates = 3'b101; |
end |
|
// 16 BIT LOAD GROUP |
8'b01001011,8'b01011011,8'b01101011,8'b01111011 : |
begin |
// LD dd,(nn) |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
end |
|
MCycle[3] : |
begin |
Read_To_Reg = 1'b1; |
if (IR[5:4] == 2'b11 ) |
begin |
Set_BusA_To = 4'b1000; |
end |
else |
begin |
Set_BusA_To[2:1] = IR[5:4]; |
Set_BusA_To[0] = 1'b1; |
end |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
end // case: 4 |
|
MCycle[4] : |
begin |
Read_To_Reg = 1'b1; |
if (IR[5:4] == 2'b11 ) |
begin |
Set_BusA_To = 4'b1001; |
end |
else |
begin |
Set_BusA_To[2:1] = IR[5:4]; |
Set_BusA_To[0] = 1'b0; |
end |
end // case: 5 |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 |
|
|
8'b01000011,8'b01010011,8'b01100011,8'b01110011 : |
begin |
// LD (nn),dd |
MCycles = 3'b101; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
Inc_PC = 1'b1; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Set_Addr_To = aZI; |
Inc_PC = 1'b1; |
LDW = 1'b1; |
if (IR[5:4] == 2'b11 ) |
begin |
Set_BusB_To = 4'b1000; |
end |
else |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b1; |
Set_BusB_To[3] = 1'b0; |
end |
end // case: 3 |
|
MCycle[3] : |
begin |
Inc_WZ = 1'b1; |
Set_Addr_To = aZI; |
Write = 1'b1; |
if (IR[5:4] == 2'b11 ) |
begin |
Set_BusB_To = 4'b1001; |
end |
else |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b0; |
Set_BusB_To[3] = 1'b0; |
end |
end // case: 4 |
|
MCycle[4] : |
begin |
Write = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 |
|
8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : |
begin |
// LDI, LDD, LDIR, LDDR |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aXY; |
IncDec_16 = 4'b1100; // BC |
end |
|
MCycle[1] : |
begin |
Set_BusB_To = 4'b0110; |
Set_BusA_To[2:0] = 3'b111; |
ALU_Op = 4'b0000; |
Set_Addr_To = aDE; |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0110; // IX |
end |
else |
begin |
IncDec_16 = 4'b1110; |
end |
end // case: 2 |
|
MCycle[2] : |
begin |
I_BT = 1'b1; |
TStates = 3'b101; |
Write = 1'b1; |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0101; // DE |
end |
else |
begin |
IncDec_16 = 4'b1101; |
end |
end // case: 3 |
|
MCycle[3] : |
begin |
NoRead = 1'b1; |
TStates = 3'b101; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 |
|
8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : |
begin |
// CPI, CPD, CPIR, CPDR |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aXY; |
IncDec_16 = 4'b1100; // BC |
end |
|
MCycle[1] : |
begin |
Set_BusB_To = 4'b0110; |
Set_BusA_To[2:0] = 3'b111; |
ALU_Op = 4'b0111; |
Save_ALU = 1'b1; |
PreserveC = 1'b1; |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0110; |
end |
else |
begin |
IncDec_16 = 4'b1110; |
end |
end // case: 2 |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
I_BC = 1'b1; |
TStates = 3'b101; |
end |
|
MCycle[3] : |
begin |
NoRead = 1'b1; |
TStates = 3'b101; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 |
|
8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : |
begin |
// NEG |
ALU_Op = 4'b0010; |
Set_BusB_To = 4'b0111; |
Set_BusA_To = 4'b1010; |
Read_To_Acc = 1'b1; |
Save_ALU = 1'b1; |
end |
|
8'b01000110,8'b01001110,8'b01100110,8'b01101110 : |
begin |
// IM 0 |
IMode = 2'b00; |
end |
|
8'b01010110,8'b01110110 : |
// IM 1 |
IMode = 2'b01; |
|
8'b01011110,8'b01110111 : |
// IM 2 |
IMode = 2'b10; |
|
// 16 bit arithmetic |
8'b01001010,8'b01011010,8'b01101010,8'b01111010 : |
begin |
// ADC HL,ss |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
NoRead = 1'b1; |
ALU_Op = 4'b0001; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusA_To[2:0] = 3'b101; |
case (IR[5:4]) |
0,1,2 : |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b1; |
end |
default : |
Set_BusB_To = 4'b1000; |
endcase |
TStates = 3'b100; |
end // case: 2 |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0001; |
Set_BusA_To[2:0] = 3'b100; |
case (IR[5:4]) |
0,1,2 : |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b0; |
end |
default : |
Set_BusB_To = 4'b1001; |
endcase // case(IR[5:4]) |
end // case: 3 |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 |
|
8'b01000010,8'b01010010,8'b01100010,8'b01110010 : |
begin |
// SBC HL,ss |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
NoRead = 1'b1; |
ALU_Op = 4'b0011; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusA_To[2:0] = 3'b101; |
case (IR[5:4]) |
0,1,2 : |
begin |
Set_BusB_To[2:1] = IR[5:4]; |
Set_BusB_To[0] = 1'b1; |
end |
default : |
Set_BusB_To = 4'b1000; |
endcase |
TStates = 3'b100; |
end // case: 2 |
|
MCycle[2] : |
begin |
NoRead = 1'b1; |
ALU_Op = 4'b0011; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
Set_BusA_To[2:0] = 3'b100; |
case (IR[5:4]) |
0,1,2 : |
Set_BusB_To[2:1] = IR[5:4]; |
default : |
Set_BusB_To = 4'b1001; |
endcase |
end // case: 3 |
|
default :; |
|
endcase // case(MCycle) |
end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 |
|
8'b01101111 : |
begin |
// RLD |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[1] : |
begin |
NoRead = 1'b1; |
Set_Addr_To = aXY; |
end |
|
MCycle[2] : |
begin |
Read_To_Reg = 1'b1; |
Set_BusB_To[2:0] = 3'b110; |
Set_BusA_To[2:0] = 3'b111; |
ALU_Op = 4'b1101; |
TStates = 3'b100; |
Set_Addr_To = aXY; |
Save_ALU = 1'b1; |
end |
|
MCycle[3] : |
begin |
I_RLD = 1'b1; |
Write = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01101111 |
|
8'b01100111 : |
begin |
// RRD |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[1] : |
Set_Addr_To = aXY; |
MCycle[2] : |
begin |
Read_To_Reg = 1'b1; |
Set_BusB_To[2:0] = 3'b110; |
Set_BusA_To[2:0] = 3'b111; |
ALU_Op = 4'b1110; |
TStates = 3'b100; |
Set_Addr_To = aXY; |
Save_ALU = 1'b1; |
end |
|
MCycle[3] : |
begin |
I_RRD = 1'b1; |
Write = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01100111 |
|
8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : |
begin |
// RETI, RETN |
MCycles = 3'b011; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aSP; |
|
MCycle[1] : |
begin |
IncDec_16 = 4'b0111; |
Set_Addr_To = aSP; |
LDZ = 1'b1; |
end |
|
MCycle[2] : |
begin |
Jump = 1'b1; |
IncDec_16 = 4'b0111; |
I_RETN = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 |
|
8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : |
begin |
// IN r,(C) |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
Set_Addr_To = aBC; |
|
MCycle[1] : |
begin |
IORQ = 1'b1; |
if (IR[5:3] != 3'b110 ) |
begin |
Read_To_Reg = 1'b1; |
Set_BusA_To[2:0] = IR[5:3]; |
end |
I_INRC = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 |
|
8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : |
begin |
// OUT (C),r |
// OUT (C),0 |
MCycles = 3'b010; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aBC; |
Set_BusB_To[2:0] = IR[5:3]; |
if (IR[5:3] == 3'b110 ) |
begin |
Set_BusB_To[3] = 1'b1; |
end |
end |
|
MCycle[1] : |
begin |
Write = 1'b1; |
IORQ = 1'b1; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 |
|
8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : |
begin |
// INI, IND, INIR, INDR |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
Set_Addr_To = aBC; |
Set_BusB_To = 4'b1010; |
Set_BusA_To = 4'b0000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0010; |
end |
|
MCycle[1] : |
begin |
IORQ = 1'b1; |
Set_BusB_To = 4'b0110; |
Set_Addr_To = aXY; |
end |
|
MCycle[2] : |
begin |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0110; |
end |
else |
begin |
IncDec_16 = 4'b1110; |
end |
TStates = 3'b100; |
Write = 1'b1; |
I_BTR = 1'b1; |
end // case: 3 |
|
MCycle[3] : |
begin |
NoRead = 1'b1; |
TStates = 3'b101; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 |
|
8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : |
begin |
// OUTI, OUTD, OTIR, OTDR |
MCycles = 3'b100; |
case (1'b1) // MCycle |
MCycle[0] : |
begin |
TStates = 3'b101; |
Set_Addr_To = aXY; |
Set_BusB_To = 4'b1010; |
Set_BusA_To = 4'b0000; |
Read_To_Reg = 1'b1; |
Save_ALU = 1'b1; |
ALU_Op = 4'b0010; |
end |
|
MCycle[1] : |
begin |
Set_BusB_To = 4'b0110; |
Set_Addr_To = aBC; |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0110; |
end |
else |
begin |
IncDec_16 = 4'b1110; |
end |
end |
|
MCycle[2] : |
begin |
if (IR[3] == 1'b0 ) |
begin |
IncDec_16 = 4'b0010; |
end |
else |
begin |
IncDec_16 = 4'b1010; |
end |
IORQ = 1'b1; |
Write = 1'b1; |
I_BTR = 1'b1; |
end // case: 3 |
|
MCycle[3] : |
begin |
NoRead = 1'b1; |
TStates = 3'b101; |
end |
|
default :; |
endcase // case(MCycle) |
end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 |
|
default : ; |
|
endcase // case(IR) |
end // block: default_ed_block |
endcase // case(ISet) |
|
if (Mode == 1 ) |
begin |
if (MCycle[0] ) |
begin |
//TStates = 3'b100; |
end |
else |
begin |
TStates = 3'b011; |
end |
end |
|
if (Mode == 3 ) |
begin |
if (MCycle[0] ) |
begin |
//TStates = 3'b100; |
end |
else |
begin |
TStates = 3'b100; |
end |
end |
|
if (Mode < 2 ) |
begin |
if (MCycle[5] ) |
begin |
Inc_PC = 1'b1; |
if (Mode == 1 ) |
begin |
Set_Addr_To = aXY; |
TStates = 3'b100; |
Set_BusB_To[2:0] = SSS; |
Set_BusB_To[3] = 1'b0; |
end |
if (IR == 8'b00110110 || IR == 8'b11001011 ) |
begin |
Set_Addr_To = aNone; |
end |
end |
if (MCycle[6] ) |
begin |
if (Mode == 0 ) |
begin |
TStates = 3'b101; |
end |
if (ISet != 2'b01 ) |
begin |
Set_Addr_To = aXY; |
end |
Set_BusB_To[2:0] = SSS; |
Set_BusB_To[3] = 1'b0; |
if (IR == 8'b00110110 || ISet == 2'b01 ) |
begin |
// LD (HL),n |
Inc_PC = 1'b1; |
end |
else |
begin |
NoRead = 1'b1; |
end |
end |
end // if (Mode < 2 ) |
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) |
endmodule // T80_MCode |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ps2controller.v
0,0 → 1,365
//------------------------------------------------------------------------------------- |
// |
// Author: John Clayton |
// Date : April 30, 2001 |
// Update: 4/30/01 copied this file from lcd_2.v (pared down). |
// Update: 5/24/01 changed the first module from "ps2_keyboard_receiver" |
// to "ps2_keyboard_interface" |
// Update: 5/29/01 Added input synchronizing flip-flops. Changed state |
// encoding (m1) for good operation after part config. |
// Update: 5/31/01 Added low drive strength and slow transitions to ps2_clk |
// and ps2_data in the constraints file. Added the signal |
// "tx_shifting_done" as distinguished from "rx_shifting_done." |
// Debugged the transmitter portion in the lab. |
// Update: 6/01/01 Added horizontal tab to the ascii output. |
// Update: 6/01/01 Added parameter TRAP_SHIFT_KEYS. |
// Update: 6/05/01 Debugged the "debounce" timer functionality. |
// Used 60usec timer as a "watchdog" timeout during |
// receive from the keyboard. This means that a keyboard |
// can now be "hot plugged" into the interface, without |
// messing up the bit_count, since the bit_count is reset |
// to zero during periods of inactivity anyway. This was |
// difficult to debug. I ended up using the logic analyzer, |
// and had to scratch my head quite a bit. |
// Update: 6/06/01 Removed extra comments before the input synchronizing |
// flip-flops. Used the correct parameter to size the |
// 5usec_timer_count. Changed the name of this file from |
// ps2.v to ps2_keyboard.v |
// Update: 6/06/01 Removed "&& q[7:0]" in output_strobe logic. Removed extra |
// commented out "else" condition in the shift register and |
// bit counter. |
// Update: 6/07/01 Changed default values for 60usec timer parameters so that |
// they correspond to 60usec for a 49.152MHz clock. |
// |
// |
// |
// |
// |
// Description |
//------------------------------------------------------------------------------------- |
// This is a state-machine driven serial-to-parallel and parallel-to-serial |
// interface to the ps2 style keyboard interface. The details of the operation |
// of the keyboard interface were obtained from the following website: |
// |
// http://www.beyondlogic.org/keyboard/keybrd.htm |
// |
// Some aspects of the keyboard interface are not implemented (e.g, parity |
// checking for the receive side, and recognition of the various commands |
// which the keyboard sends out, such as "power on selt test passed," "Error" |
// and "Resend.") However, if the user wishes to recognize these reply |
// messages, the scan code output can always be used to extend functionality |
// as desired. |
// |
// Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized. |
// The rx interface provides separate indicator flags for these two conditions |
// with every valid character scan code which it provides. The shift keys are |
// also trapped by the interface, in order to provide correct uppercase ASCII |
// characters at the ascii output, although the scan codes for the shift keys |
// are still provided at the scan code output. So, the left/right ALT keys |
// can be differentiated by the presence of the rx_entended signal, while the |
// left/right shift keys are differentiable by the different scan codes |
// received. |
// |
// The interface to the ps2 keyboard uses ps2_clk clock rates of |
// 30-40 kHz, dependent upon the keyboard itself. The rate at which the state |
// machine runs should be at least twice the rate of the ps2_clk, so that the |
// states can accurately follow the clock signal itself. Four times |
// oversampling is better. Say 200kHz at least. The upper limit for clocking |
// the state machine will undoubtedly be determined by delays in the logic |
// which decodes the scan codes into ASCII equivalents. The maximum speed |
// will be most likely many megahertz, depending upon target technology. |
// In order to run the state machine extremely fast, synchronizing flip-flops |
// have been added to the ps2_clk and ps2_data inputs of the state machine. |
// This avoids poor performance related to slow transitions of the inputs. |
// |
// Because this is a bi-directional interface, while reading from the keyboard |
// the ps2_clk and ps2_data lines are used as inputs. While writing to the |
// keyboard, however (which may be done at any time. If writing interrupts a |
// read from the keyboard, the keyboard will buffer up its data, and send |
// it later) both the ps2_clk and ps2_data lines are occasionally pulled low, |
// and pullup resistors are used to bring the lines high again, by setting |
// the drivers to high impedance state. |
// |
// The tx interface, for writing to the keyboard, does not provide any special |
// pre-processing. It simply transmits the 8-bit command value to the |
// keyboard. |
// |
// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design, |
// whether they be internal to an FPGA I/O pad, or externally placed. |
// If internal pullups are used, they may be fairly weak, causing bounces |
// due to crosstalk, etc. There is a "debounce timer" implemented in order |
// to eliminate erroneous state transitions which would occur based on bounce. |
// |
// Parameters are provided in order to configure and appropriately size the |
// counter of a 60 microsecond timer used in the transmitter, depending on |
// the clock frequency used. The 60 microsecond period is guaranteed to be |
// more than one period of the ps2_clk_s signal. |
// |
// Also, a smaller 5 microsecond timer has been included for "debounce". |
// This is used because, with internal pullups on the ps2_clk and ps2_data |
// lines, there is some bouncing around which occurs |
// |
// A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses |
// from producing scan codes (along with their "undefined" ASCII equivalents) |
// at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift |
// key status will only be reported by rx_shift_key_on. No ascii or scan |
// codes will be reported for the shift keys. This is useful for those who |
// wish to use the ASCII data stream, and who don't want to have to "filter |
// out" the shift key codes. |
// |
//------------------------------------------------------------------------------------- |
`resetall |
`timescale 1ns/100ps |
|
`define TOTAL_BITS 11 //total data bits of the data package |
`define EXTEND_CODE 8'hE0 //extend code |
`define RELEASE_CODE 8'hF0 //release code |
|
module ps2_keyboard( |
clk, |
reset, |
ps2_clk, |
ps2_data, |
interrupt, |
rx_scan_code |
); |
|
// Parameters |
|
// The timer value can be up to (2^bits) inclusive. |
parameter TIMER_60USEC_VALUE_PP = 840; // Number of sys_clks for 60usec. (for a 14Mhz clock) |
parameter TIMER_60USEC_BITS_PP = 10; // Number of bits needed for timer |
|
// State encodings, provided as parameters |
// for flexibility to the one instantiating the module. |
// In general, the default values need not be changed. |
|
// State "m1_rx_clk_l" has been chosen on purpose. Since the input |
// synchronizing flip-flops initially contain zero, it takes one clk |
// for them to update to reflect the actual (idle = high) status of |
// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l |
// allows the state machine to transition to m1_rx_clk_h when the true |
// values of the input signals become present at the outputs of the |
// synchronizing flip-flops. This initial transition is harmless, and it |
// eliminates the need for a "reset" pulse before the interface can operate. |
|
parameter m1_rx_clk_h = 1; |
parameter m1_rx_clk_l = 0; |
parameter m1_rx_falling_edge_marker = 3; |
parameter m1_rx_rising_edge_marker = 4; |
|
|
// I/O declarations |
input clk; |
input reset; |
input ps2_clk; |
input ps2_data; |
output interrupt; |
output [7:0] rx_scan_code; |
//output [7:0] rx_ascii; |
|
reg rx_extended; |
reg rx_released; |
reg [7:0] rx_scan_code; |
reg interrupt; |
|
|
|
// Internal signal declarations |
wire timer_60usec_done; |
wire extended; |
wire released; |
// NOTE: These two signals used to be one. They |
// were split into two signals because of |
// shift key trapping. With shift key |
// trapping, no event is generated externally, |
// but the "hold" data must still be cleared |
// anyway regardless, in preparation for the |
// next scan codes. |
wire rx_output_strobe; // Used to produce the actual output. |
wire rx_shifting_done; |
|
|
reg [`TOTAL_BITS-1:0] q; |
reg [3:0] m1_state; |
reg [3:0] m1_next_state; |
reg [3:0] bit_count; |
|
reg enable_timer_60usec; |
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count; |
|
|
reg ps2_clk_s; // Synchronous version of this input |
reg ps2_data_s; // Synchronous version of this input |
|
|
//-------------------------------------------------------------------------- |
// Module code |
|
// Input "synchronizing" logic -- synchronizes the inputs to the state |
// machine clock, thus avoiding errors related to |
// spurious state machine transitions. |
always @(posedge clk) |
begin |
ps2_clk_s <= ps2_clk; |
ps2_data_s <= ps2_data; |
end |
|
// State register |
always @(posedge clk) |
begin : m1_state_register |
if (reset) m1_state <= m1_rx_clk_h; |
else m1_state <= m1_next_state; |
end |
|
// State transition logic |
always @(m1_state |
or q |
or ps2_clk_s |
or ps2_data_s |
or timer_60usec_done |
) |
begin : m1_state_logic |
|
// Output signals default to this value, unless changed in a state condition. |
|
enable_timer_60usec <= 0; |
|
case (m1_state) |
|
m1_rx_clk_h : |
begin |
enable_timer_60usec <= 1; |
if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker; |
else m1_next_state <= m1_rx_clk_h; |
end |
|
m1_rx_falling_edge_marker : |
begin |
enable_timer_60usec <= 0; |
m1_next_state <= m1_rx_clk_l; |
end |
|
m1_rx_rising_edge_marker : |
begin |
enable_timer_60usec <= 0; |
m1_next_state <= m1_rx_clk_h; |
end |
|
m1_rx_clk_l : |
begin |
enable_timer_60usec <= 1; |
if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker; |
else m1_next_state <= m1_rx_clk_l; |
end |
default : m1_next_state <= m1_rx_clk_h; |
endcase |
end |
|
|
// This is the bit counter |
|
always @(posedge clk) |
begin |
if ( reset |
|| rx_shifting_done |
) |
bit_count <= 0; // normal reset |
else if (timer_60usec_done |
&& (m1_state == m1_rx_clk_h) |
&& (ps2_clk_s) |
) |
bit_count <= 0; // rx watchdog timer reset |
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx |
) |
bit_count <= bit_count + 1; |
end |
// This signal is high for one clock at the end of the timer count. |
|
assign rx_shifting_done = (bit_count == `TOTAL_BITS); |
|
|
|
// This is the signal which enables loading of the shift register. |
// It also indicates "ack" to the device writing to the transmitter. |
|
|
// This is the ODD parity bit for the transmitted word. |
|
|
// This is the shift register |
always @(posedge clk) |
begin |
if (reset) q <= 0; |
else if ( (m1_state == m1_rx_falling_edge_marker) ) |
q <= {ps2_data_s,q[`TOTAL_BITS-1:1]}; |
end |
|
// This is the 60usec timer counter |
|
always @(posedge clk) |
begin |
if (~enable_timer_60usec) timer_60usec_count <= 0; |
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1; |
end |
|
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1)); |
|
|
|
// Create the signals which indicate special scan codes received. |
// These are the "unlatched versions." |
|
assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done; |
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done; |
|
|
// Store the special scan code status bits |
// Not the final output, but an intermediate storage place, |
// until the entire set of output data can be assembled. |
|
// Output the special scan code flags, the scan code and the ascii |
always @(posedge clk) |
begin |
if (reset) |
begin |
rx_scan_code <= 0; |
interrupt<=0; |
end |
else if (rx_output_strobe) //if not extended, not relaeased,get the scan_code |
begin |
rx_scan_code <= q[8:1]; |
interrupt<=1; |
end |
else |
begin |
//rx_scan_code<=rx_scan_code; |
interrupt<=0; |
end |
end |
|
// Store the final rx output data only when all extend and release codes |
// are received and the next (actual key) scan code is also ready. |
// (the presence of rx_extended or rx_released refers to the |
// the current latest scan code received, not the previously latched flags.) |
|
|
assign rx_output_strobe = rx_shifting_done; |
// && ~extended |
// && ~released |
// ); |
|
// This part translates the scan code into an ASCII value... |
// Only the ASCII codes which I considered important have been included. |
// if you want more, just add the appropriate case statement lines... |
// (You will need to know the keyboard scan codes you wish to assign.) |
// The entries are listed in ascending order of ASCII value. |
|
endmodule |
|
//`undefine TOTAL_BITS |
//`undefine EXTEND_CODE |
//`undefine RELEASE_CODE |
//`undefine LEFT_SHIFT |
//`undefine RIGHT_SHIFT |
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tv80_core.v
0,0 → 1,1389
// |
// TV80 8-Bit Microprocessor Core |
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
// |
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
// |
// Permission is hereby granted, free of charge, to any person obtaining a |
// copy of this software and associated documentation files (the "Software"), |
// to deal in the Software without restriction, including without limitation |
// the rights to use, copy, modify, merge, publish, distribute, sublicense, |
// and/or sell copies of the Software, and to permit persons to whom the |
// Software is furnished to do so, subject to the following conditions: |
// |
// The above copyright notice and this permission notice shall be included |
// in all copies or substantial portions of the Software. |
// |
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|
module tv80_core (/*AUTOARG*/ |
// Outputs |
m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, |
ts, intcycle_n, IntE, stop, |
// Inputs |
reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di |
); |
// Beginning of automatic inputs (from unused autoinst inputs) |
// End of automatics |
|
parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB |
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle |
parameter Flag_C = 0; |
parameter Flag_N = 1; |
parameter Flag_P = 2; |
parameter Flag_X = 3; |
parameter Flag_H = 4; |
parameter Flag_Y = 5; |
parameter Flag_Z = 6; |
parameter Flag_S = 7; |
|
input reset_n; |
input clk; |
input cen; |
input wait_n; |
input int_n; |
input nmi_n; |
input busrq_n; |
output m1_n; |
output iorq; |
output no_read; |
output write; |
output rfsh_n; |
output halt_n; |
output busak_n; |
output [15:0] A; |
input [7:0] dinst; |
input [7:0] di; |
output [7:0] dout; |
output [6:0] mc; |
output [6:0] ts; |
output intcycle_n; |
output IntE; |
output stop; |
|
reg m1_n; |
reg iorq; |
`ifdef TV80_REFRESH |
reg rfsh_n; |
`endif |
reg halt_n; |
reg busak_n; |
reg [15:0] A; |
reg [7:0] dout; |
reg [6:0] mc; |
reg [6:0] ts; |
reg intcycle_n; |
reg IntE; |
reg stop; |
|
parameter aNone = 3'b111; |
parameter aBC = 3'b000; |
parameter aDE = 3'b001; |
parameter aXY = 3'b010; |
parameter aIOA = 3'b100; |
parameter aSP = 3'b101; |
parameter aZI = 3'b110; |
|
// Registers |
reg [7:0] ACC, F; |
reg [7:0] Ap, Fp; |
reg [7:0] I; |
`ifdef TV80_REFRESH |
reg [7:0] R; |
`endif |
reg [15:0] SP, PC; |
reg [7:0] RegDIH; |
reg [7:0] RegDIL; |
wire [15:0] RegBusA; |
wire [15:0] RegBusB; |
wire [15:0] RegBusC; |
reg [2:0] RegAddrA_r; |
reg [2:0] RegAddrA; |
reg [2:0] RegAddrB_r; |
reg [2:0] RegAddrB; |
reg [2:0] RegAddrC; |
reg RegWEH; |
reg RegWEL; |
reg Alternate; |
|
// Help Registers |
reg [15:0] TmpAddr; // Temporary address register |
reg [7:0] IR; // Instruction register |
reg [1:0] ISet; // Instruction set selector |
reg [15:0] RegBusA_r; |
|
reg [15:0] ID16; |
reg [7:0] Save_Mux; |
|
reg [6:0] tstate; |
reg [6:0] mcycle; |
reg last_mcycle, last_tstate; |
reg IntE_FF1; |
reg IntE_FF2; |
reg Halt_FF; |
reg BusReq_s; |
reg BusAck; |
reg ClkEn; |
reg NMI_s; |
reg INT_s; |
reg [1:0] IStatus; |
|
reg [7:0] DI_Reg; |
reg T_Res; |
reg [1:0] XY_State; |
reg [2:0] Pre_XY_F_M; |
reg NextIs_XY_Fetch; |
reg XY_Ind; |
reg No_BTR; |
reg BTR_r; |
reg Auto_Wait; |
reg Auto_Wait_t1; |
reg Auto_Wait_t2; |
reg IncDecZ; |
|
// ALU signals |
reg [7:0] BusB; |
reg [7:0] BusA; |
wire [7:0] ALU_Q; |
wire [7:0] F_Out; |
|
// Registered micro code outputs |
reg [4:0] Read_To_Reg_r; |
reg Arith16_r; |
reg Z16_r; |
reg [3:0] ALU_Op_r; |
reg Save_ALU_r; |
reg PreserveC_r; |
reg [2:0] mcycles; |
|
// Micro code outputs |
wire [2:0] mcycles_d; |
wire [2:0] tstates; |
reg IntCycle; |
reg NMICycle; |
wire Inc_PC; |
wire Inc_WZ; |
wire [3:0] IncDec_16; |
wire [1:0] Prefix; |
wire Read_To_Acc; |
wire Read_To_Reg; |
wire [3:0] Set_BusB_To; |
wire [3:0] Set_BusA_To; |
wire [3:0] ALU_Op; |
wire Save_ALU; |
wire PreserveC; |
wire Arith16; |
wire [2:0] Set_Addr_To; |
wire Jump; |
wire JumpE; |
wire JumpXY; |
wire Call; |
wire RstP; |
wire LDZ; |
wire LDW; |
wire LDSPHL; |
wire iorq_i; |
wire [2:0] Special_LD; |
wire ExchangeDH; |
wire ExchangeRp; |
wire ExchangeAF; |
wire ExchangeRS; |
wire I_DJNZ; |
wire I_CPL; |
wire I_CCF; |
wire I_SCF; |
wire I_RETN; |
wire I_BT; |
wire I_BC; |
wire I_BTR; |
wire I_RLD; |
wire I_RRD; |
wire I_INRC; |
wire SetDI; |
wire SetEI; |
wire [1:0] IMode; |
wire Halt; |
|
reg [15:0] PC16; |
reg [15:0] PC16_B; |
reg [15:0] SP16, SP16_A, SP16_B; |
reg [15:0] ID16_B; |
reg Oldnmi_n; |
|
tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode |
( |
.IR (IR), |
.ISet (ISet), |
.MCycle (mcycle), |
.F (F), |
.NMICycle (NMICycle), |
.IntCycle (IntCycle), |
.MCycles (mcycles_d), |
.TStates (tstates), |
.Prefix (Prefix), |
.Inc_PC (Inc_PC), |
.Inc_WZ (Inc_WZ), |
.IncDec_16 (IncDec_16), |
.Read_To_Acc (Read_To_Acc), |
.Read_To_Reg (Read_To_Reg), |
.Set_BusB_To (Set_BusB_To), |
.Set_BusA_To (Set_BusA_To), |
.ALU_Op (ALU_Op), |
.Save_ALU (Save_ALU), |
.PreserveC (PreserveC), |
.Arith16 (Arith16), |
.Set_Addr_To (Set_Addr_To), |
.IORQ (iorq_i), |
.Jump (Jump), |
.JumpE (JumpE), |
.JumpXY (JumpXY), |
.Call (Call), |
.RstP (RstP), |
.LDZ (LDZ), |
.LDW (LDW), |
.LDSPHL (LDSPHL), |
.Special_LD (Special_LD), |
.ExchangeDH (ExchangeDH), |
.ExchangeRp (ExchangeRp), |
.ExchangeAF (ExchangeAF), |
.ExchangeRS (ExchangeRS), |
.I_DJNZ (I_DJNZ), |
.I_CPL (I_CPL), |
.I_CCF (I_CCF), |
.I_SCF (I_SCF), |
.I_RETN (I_RETN), |
.I_BT (I_BT), |
.I_BC (I_BC), |
.I_BTR (I_BTR), |
.I_RLD (I_RLD), |
.I_RRD (I_RRD), |
.I_INRC (I_INRC), |
.SetDI (SetDI), |
.SetEI (SetEI), |
.IMode (IMode), |
.Halt (Halt), |
.NoRead (no_read), |
.Write (write) |
); |
|
tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu |
( |
.Arith16 (Arith16_r), |
.Z16 (Z16_r), |
.ALU_Op (ALU_Op_r), |
.IR (IR[5:0]), |
.ISet (ISet), |
.BusA (BusA), |
.BusB (BusB), |
.F_In (F), |
.Q (ALU_Q), |
.F_Out (F_Out) |
); |
|
function [6:0] number_to_bitvec; |
input [2:0] num; |
begin |
case (num) |
1 : number_to_bitvec = 7'b0000001; |
2 : number_to_bitvec = 7'b0000010; |
3 : number_to_bitvec = 7'b0000100; |
4 : number_to_bitvec = 7'b0001000; |
5 : number_to_bitvec = 7'b0010000; |
6 : number_to_bitvec = 7'b0100000; |
7 : number_to_bitvec = 7'b1000000; |
default : number_to_bitvec = 7'bx; |
endcase // case(num) |
end |
endfunction // number_to_bitvec |
|
function [2:0] mcyc_to_number; |
input [6:0] mcyc; |
begin |
casez (mcyc) |
7'b1zzzzzz : mcyc_to_number = 3'h7; |
7'b01zzzzz : mcyc_to_number = 3'h6; |
7'b001zzzz : mcyc_to_number = 3'h5; |
7'b0001zzz : mcyc_to_number = 3'h4; |
7'b00001zz : mcyc_to_number = 3'h3; |
7'b000001z : mcyc_to_number = 3'h2; |
7'b0000001 : mcyc_to_number = 3'h1; |
default : mcyc_to_number = 3'h1; |
endcase |
end |
endfunction |
|
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates) |
begin |
case (mcycles) |
1 : last_mcycle = mcycle[0]; |
2 : last_mcycle = mcycle[1]; |
3 : last_mcycle = mcycle[2]; |
4 : last_mcycle = mcycle[3]; |
5 : last_mcycle = mcycle[4]; |
6 : last_mcycle = mcycle[5]; |
7 : last_mcycle = mcycle[6]; |
default : last_mcycle = 1'bx; |
endcase // case(mcycles) |
|
case (tstates) |
0 : last_tstate = tstate[0]; |
1 : last_tstate = tstate[1]; |
2 : last_tstate = tstate[2]; |
3 : last_tstate = tstate[3]; |
4 : last_tstate = tstate[4]; |
5 : last_tstate = tstate[5]; |
6 : last_tstate = tstate[6]; |
default : last_tstate = 1'bx; |
endcase |
end // always @ (... |
|
|
always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg |
or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind |
or XY_State or cen or last_tstate or mcycle) |
begin |
ClkEn = cen && ~ BusAck; |
|
if (last_tstate) |
T_Res = 1'b1; |
else T_Res = 1'b0; |
|
if (XY_State != 2'b00 && XY_Ind == 1'b0 && |
((Set_Addr_To == aXY) || |
(mcycle[0] && IR == 8'b11001011) || |
(mcycle[0] && IR == 8'b00110110))) |
NextIs_XY_Fetch = 1'b1; |
else |
NextIs_XY_Fetch = 1'b0; |
|
if (ExchangeRp) |
Save_Mux = BusB; |
else if (!Save_ALU_r) |
Save_Mux = DI_Reg; |
else |
Save_Mux = ALU_Q; |
end // always @ * |
|
always @ (posedge clk or negedge reset_n) |
begin |
if (reset_n == 1'b0 ) |
begin |
PC <= #1 0; // Program Counter |
A <= #1 0; |
TmpAddr <= #1 0; |
IR <= #1 8'b00000000; |
ISet <= #1 2'b00; |
XY_State <= #1 2'b00; |
IStatus <= #1 2'b00; |
mcycles <= #1 3'b000; |
dout <= #1 8'b00000000; |
|
ACC <= #1 8'hFF; |
F <= #1 8'hFF; |
Ap <= #1 8'hFF; |
Fp <= #1 8'hFF; |
I <= #1 0; |
`ifdef TV80_REFRESH |
R <= #1 0; |
`endif |
SP <= #1 16'hFFFF; |
Alternate <= #1 1'b0; |
|
Read_To_Reg_r <= #1 5'b00000; |
Arith16_r <= #1 1'b0; |
BTR_r <= #1 1'b0; |
Z16_r <= #1 1'b0; |
ALU_Op_r <= #1 4'b0000; |
Save_ALU_r <= #1 1'b0; |
PreserveC_r <= #1 1'b0; |
XY_Ind <= #1 1'b0; |
end |
else |
begin |
|
if (ClkEn == 1'b1 ) |
begin |
|
ALU_Op_r <= #1 4'b0000; |
Save_ALU_r <= #1 1'b0; |
Read_To_Reg_r <= #1 5'b00000; |
|
mcycles <= #1 mcycles_d; |
|
if (IMode != 2'b11 ) |
begin |
IStatus <= #1 IMode; |
end |
|
Arith16_r <= #1 Arith16; |
PreserveC_r <= #1 PreserveC; |
if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) |
begin |
Z16_r <= #1 1'b1; |
end |
else |
begin |
Z16_r <= #1 1'b0; |
end |
|
if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) |
begin |
// mcycle == 1 && tstate == 1, 2, || 3 |
if (tstate[2] && wait_n == 1'b1 ) |
begin |
`ifdef TV80_REFRESH |
if (Mode < 2 ) |
begin |
A[7:0] <= #1 R; |
A[15:8] <= #1 I; |
R[6:0] <= #1 R[6:0] + 1; |
end |
`endif |
if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) |
begin |
PC <= #1 PC16; |
end |
|
if (IntCycle == 1'b1 && IStatus == 2'b01 ) |
begin |
IR <= #1 8'b11111111; |
end |
else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) |
begin |
IR <= #1 8'b00000000; |
TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch |
end |
else |
begin |
IR <= #1 dinst; |
end |
|
ISet <= #1 2'b00; |
if (Prefix != 2'b00 ) |
begin |
if (Prefix == 2'b11 ) |
begin |
if (IR[5] == 1'b1 ) |
begin |
XY_State <= #1 2'b10; |
end |
else |
begin |
XY_State <= #1 2'b01; |
end |
end |
else |
begin |
if (Prefix == 2'b10 ) |
begin |
XY_State <= #1 2'b00; |
XY_Ind <= #1 1'b0; |
end |
ISet <= #1 Prefix; |
end |
end |
else |
begin |
XY_State <= #1 2'b00; |
XY_Ind <= #1 1'b0; |
end |
end // if (tstate == 2 && wait_n == 1'b1 ) |
|
|
end |
else |
begin |
// either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) |
|
if (mcycle[5] ) |
begin |
XY_Ind <= #1 1'b1; |
if (Prefix == 2'b01 ) |
begin |
ISet <= #1 2'b01; |
end |
end |
|
if (T_Res == 1'b1 ) |
begin |
BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; |
if (Jump == 1'b1 ) |
begin |
A[15:8] <= #1 DI_Reg; |
A[7:0] <= #1 TmpAddr[7:0]; |
PC[15:8] <= #1 DI_Reg; |
PC[7:0] <= #1 TmpAddr[7:0]; |
end |
else if (JumpXY == 1'b1 ) |
begin |
A <= #1 RegBusC; |
PC <= #1 RegBusC; |
end else if (Call == 1'b1 || RstP == 1'b1 ) |
begin |
A <= #1 TmpAddr; |
PC <= #1 TmpAddr; |
end |
else if (last_mcycle && NMICycle == 1'b1 ) |
begin |
A <= #1 16'b0000000001100110; |
PC <= #1 16'b0000000001100110; |
end |
else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) |
begin |
A[15:8] <= #1 I; |
A[7:0] <= #1 TmpAddr[7:0]; |
PC[15:8] <= #1 I; |
PC[7:0] <= #1 TmpAddr[7:0]; |
end |
else |
begin |
case (Set_Addr_To) |
aXY : |
begin |
if (XY_State == 2'b00 ) |
begin |
A <= #1 RegBusC; |
end |
else |
begin |
if (NextIs_XY_Fetch == 1'b1 ) |
begin |
A <= #1 PC; |
end |
else |
begin |
A <= #1 TmpAddr; |
end |
end // else: !if(XY_State == 2'b00 ) |
end // case: aXY |
|
aIOA : |
begin |
if (Mode == 3 ) |
begin |
// Memory map I/O on GBZ80 |
A[15:8] <= #1 8'hFF; |
end |
else if (Mode == 2 ) |
begin |
// Duplicate I/O address on 8080 |
A[15:8] <= #1 DI_Reg; |
end |
else |
begin |
A[15:8] <= #1 ACC; |
end |
A[7:0] <= #1 DI_Reg; |
end // case: aIOA |
|
|
aSP : |
begin |
A <= #1 SP; |
end |
|
aBC : |
begin |
if (Mode == 3 && iorq_i == 1'b1 ) |
begin |
// Memory map I/O on GBZ80 |
A[15:8] <= #1 8'hFF; |
A[7:0] <= #1 RegBusC[7:0]; |
end |
else |
begin |
A <= #1 RegBusC; |
end |
end // case: aBC |
|
aDE : |
begin |
A <= #1 RegBusC; |
end |
|
aZI : |
begin |
if (Inc_WZ == 1'b1 ) |
begin |
A <= #1 TmpAddr + 1; |
end |
else |
begin |
A[15:8] <= #1 DI_Reg; |
A[7:0] <= #1 TmpAddr[7:0]; |
end |
end // case: aZI |
|
default : |
begin |
A <= #1 PC; |
end |
endcase // case(Set_Addr_To) |
|
end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) |
|
|
Save_ALU_r <= #1 Save_ALU; |
ALU_Op_r <= #1 ALU_Op; |
|
if (I_CPL == 1'b1 ) |
begin |
// CPL |
ACC <= #1 ~ ACC; |
F[Flag_Y] <= #1 ~ ACC[5]; |
F[Flag_H] <= #1 1'b1; |
F[Flag_X] <= #1 ~ ACC[3]; |
F[Flag_N] <= #1 1'b1; |
end |
if (I_CCF == 1'b1 ) |
begin |
// CCF |
F[Flag_C] <= #1 ~ F[Flag_C]; |
F[Flag_Y] <= #1 ACC[5]; |
F[Flag_H] <= #1 F[Flag_C]; |
F[Flag_X] <= #1 ACC[3]; |
F[Flag_N] <= #1 1'b0; |
end |
if (I_SCF == 1'b1 ) |
begin |
// SCF |
F[Flag_C] <= #1 1'b1; |
F[Flag_Y] <= #1 ACC[5]; |
F[Flag_H] <= #1 1'b0; |
F[Flag_X] <= #1 ACC[3]; |
F[Flag_N] <= #1 1'b0; |
end |
end // if (T_Res == 1'b1 ) |
|
|
if (tstate[2] && wait_n == 1'b1 ) |
begin |
if (ISet == 2'b01 && mcycle[6] ) |
begin |
IR <= #1 dinst; |
end |
if (JumpE == 1'b1 ) |
begin |
PC <= #1 PC16; |
end |
else if (Inc_PC == 1'b1 ) |
begin |
//PC <= #1 PC + 1; |
PC <= #1 PC16; |
end |
if (BTR_r == 1'b1 ) |
begin |
//PC <= #1 PC - 2; |
PC <= #1 PC16; |
end |
if (RstP == 1'b1 ) |
begin |
TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; |
//TmpAddr <= #1 (others =>1'b0); |
//TmpAddr[5:3] <= #1 IR[5:3]; |
end |
end |
if (tstate[3] && mcycle[5] ) |
begin |
TmpAddr <= #1 SP16; |
end |
|
if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) |
begin |
if (IncDec_16[2:0] == 3'b111 ) |
begin |
SP <= #1 SP16; |
end |
end |
|
if (LDSPHL == 1'b1 ) |
begin |
SP <= #1 RegBusC; |
end |
if (ExchangeAF == 1'b1 ) |
begin |
Ap <= #1 ACC; |
ACC <= #1 Ap; |
Fp <= #1 F; |
F <= #1 Fp; |
end |
if (ExchangeRS == 1'b1 ) |
begin |
Alternate <= #1 ~ Alternate; |
end |
end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) |
|
|
if (tstate[3] ) |
begin |
if (LDZ == 1'b1 ) |
begin |
TmpAddr[7:0] <= #1 DI_Reg; |
end |
if (LDW == 1'b1 ) |
begin |
TmpAddr[15:8] <= #1 DI_Reg; |
end |
|
if (Special_LD[2] == 1'b1 ) |
begin |
case (Special_LD[1:0]) |
2'b00 : |
begin |
ACC <= #1 I; |
F[Flag_P] <= #1 IntE_FF2; |
F[Flag_Z] <= (I == 0); |
F[Flag_S] <= I[7]; |
F[Flag_H] <= 0; |
F[Flag_N] <= 0; |
end |
|
2'b01 : |
begin |
`ifdef TV80_REFRESH |
ACC <= #1 R; |
`else |
ACC <= #1 0; |
`endif |
F[Flag_P] <= #1 IntE_FF2; |
F[Flag_Z] <= (I == 0); |
F[Flag_S] <= I[7]; |
F[Flag_H] <= 0; |
F[Flag_N] <= 0; |
end |
|
2'b10 : |
I <= #1 ACC; |
|
`ifdef TV80_REFRESH |
default : |
R <= #1 ACC; |
`else |
default : ; |
`endif |
endcase |
end |
end // if (tstate == 3 ) |
|
|
if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) |
begin |
if (Mode == 3 ) |
begin |
F[6] <= #1 F_Out[6]; |
F[5] <= #1 F_Out[5]; |
F[7] <= #1 F_Out[7]; |
if (PreserveC_r == 1'b0 ) |
begin |
F[4] <= #1 F_Out[4]; |
end |
end |
else |
begin |
F[7:1] <= #1 F_Out[7:1]; |
if (PreserveC_r == 1'b0 ) |
begin |
F[Flag_C] <= #1 F_Out[0]; |
end |
end |
end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) |
|
if (T_Res == 1'b1 && I_INRC == 1'b1 ) |
begin |
F[Flag_H] <= #1 1'b0; |
F[Flag_N] <= #1 1'b0; |
if (DI_Reg[7:0] == 8'b00000000 ) |
begin |
F[Flag_Z] <= #1 1'b1; |
end |
else |
begin |
F[Flag_Z] <= #1 1'b0; |
end |
F[Flag_S] <= #1 DI_Reg[7]; |
F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); |
end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) |
|
|
if (tstate[1] && Auto_Wait_t1 == 1'b0 ) |
begin |
dout <= #1 BusB; |
if (I_RLD == 1'b1 ) |
begin |
dout[3:0] <= #1 BusA[3:0]; |
dout[7:4] <= #1 BusB[3:0]; |
end |
if (I_RRD == 1'b1 ) |
begin |
dout[3:0] <= #1 BusB[7:4]; |
dout[7:4] <= #1 BusA[3:0]; |
end |
end |
|
if (T_Res == 1'b1 ) |
begin |
Read_To_Reg_r[3:0] <= #1 Set_BusA_To; |
Read_To_Reg_r[4] <= #1 Read_To_Reg; |
if (Read_To_Acc == 1'b1 ) |
begin |
Read_To_Reg_r[3:0] <= #1 4'b0111; |
Read_To_Reg_r[4] <= #1 1'b1; |
end |
end |
|
if (tstate[1] && I_BT == 1'b1 ) |
begin |
F[Flag_X] <= #1 ALU_Q[3]; |
F[Flag_Y] <= #1 ALU_Q[1]; |
F[Flag_H] <= #1 1'b0; |
F[Flag_N] <= #1 1'b0; |
end |
if (I_BC == 1'b1 || I_BT == 1'b1 ) |
begin |
F[Flag_P] <= #1 IncDecZ; |
end |
|
if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || |
(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) |
begin |
case (Read_To_Reg_r) |
5'b10111 : |
ACC <= #1 Save_Mux; |
5'b10110 : |
dout <= #1 Save_Mux; |
5'b11000 : |
SP[7:0] <= #1 Save_Mux; |
5'b11001 : |
SP[15:8] <= #1 Save_Mux; |
5'b11011 : |
F <= #1 Save_Mux; |
default : ; |
endcase |
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... |
end // if (ClkEn == 1'b1 ) |
end // else: !if(reset_n == 1'b0 ) |
end |
|
|
//------------------------------------------------------------------------- |
// |
// BC('), DE('), HL('), IX && IY |
// |
//------------------------------------------------------------------------- |
always @ (posedge clk) |
begin |
if (ClkEn == 1'b1 ) |
begin |
// Bus A / Write |
RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; |
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) |
begin |
RegAddrA_r <= #1 { XY_State[1], 2'b11 }; |
end |
|
// Bus B |
RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; |
if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) |
begin |
RegAddrB_r <= #1 { XY_State[1], 2'b11 }; |
end |
|
// Address from register |
RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; |
// Jump (HL), LD SP,HL |
if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) |
begin |
RegAddrC <= #1 { Alternate, 2'b10 }; |
end |
if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) |
begin |
RegAddrC <= #1 { XY_State[1], 2'b11 }; |
end |
|
if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) |
begin |
IncDecZ <= #1 F_Out[Flag_Z]; |
end |
if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) |
begin |
if (ID16 == 0 ) |
begin |
IncDecZ <= #1 1'b0; |
end |
else |
begin |
IncDecZ <= #1 1'b1; |
end |
end |
|
RegBusA_r <= #1 RegBusA; |
end |
|
end // always @ (posedge clk) |
|
|
always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 |
or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) |
begin |
if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) |
RegAddrA = { Alternate, IncDec_16[1:0] }; |
else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) |
RegAddrA = { XY_State[1], 2'b11 }; |
else if (ExchangeDH == 1'b1 && tstate[3]) |
RegAddrA = { Alternate, 2'b10 }; |
else if (ExchangeDH == 1'b1 && tstate[4]) |
RegAddrA = { Alternate, 2'b01 }; |
else |
RegAddrA = RegAddrA_r; |
|
if (ExchangeDH == 1'b1 && tstate[3]) |
RegAddrB = { Alternate, 2'b01 }; |
else |
RegAddrB = RegAddrB_r; |
end // always @ * |
|
|
always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH |
or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle |
or tstate or wait_n) |
begin |
RegWEH = 1'b0; |
RegWEL = 1'b0; |
if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) || |
(Save_ALU_r && (ALU_Op_r != 4'b0111)) ) |
begin |
case (Read_To_Reg_r) |
5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : |
begin |
RegWEH = ~ Read_To_Reg_r[0]; |
RegWEL = Read_To_Reg_r[0]; |
end // UNMATCHED !! |
default : ; |
endcase // case(Read_To_Reg_r) |
|
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... |
|
|
if (ExchangeDH && (tstate[3] || tstate[4]) ) |
begin |
RegWEH = 1'b1; |
RegWEL = 1'b1; |
end |
|
if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) |
begin |
case (IncDec_16[1:0]) |
2'b00 , 2'b01 , 2'b10 : |
begin |
RegWEH = 1'b1; |
RegWEL = 1'b1; |
end // UNMATCHED !! |
default : ; |
endcase |
end |
end // always @ * |
|
|
always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r |
or RegBusB or Save_Mux or mcycle or tstate) |
begin |
RegDIH = Save_Mux; |
RegDIL = Save_Mux; |
|
if (ExchangeDH == 1'b1 && tstate[3] ) |
begin |
RegDIH = RegBusB[15:8]; |
RegDIL = RegBusB[7:0]; |
end |
else if (ExchangeDH == 1'b1 && tstate[4] ) |
begin |
RegDIH = RegBusA_r[15:8]; |
RegDIL = RegBusA_r[7:0]; |
end |
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) ) |
begin |
RegDIH = ID16[15:8]; |
RegDIL = ID16[7:0]; |
end |
end |
|
tv80_reg i_reg |
( |
.clk (clk), |
.CEN (ClkEn), |
.WEH (RegWEH), |
.WEL (RegWEL), |
.AddrA (RegAddrA), |
.AddrB (RegAddrB), |
.AddrC (RegAddrC), |
.DIH (RegDIH), |
.DIL (RegDIL), |
.DOAH (RegBusA[15:8]), |
.DOAL (RegBusA[7:0]), |
.DOBH (RegBusB[15:8]), |
.DOBL (RegBusB[7:0]), |
.DOCH (RegBusC[15:8]), |
.DOCL (RegBusC[7:0]) |
); |
|
//------------------------------------------------------------------------- |
// |
// Buses |
// |
//------------------------------------------------------------------------- |
|
always @ (posedge clk) |
begin |
if (ClkEn == 1'b1 ) |
begin |
case (Set_BusB_To) |
4'b0111 : |
BusB <= #1 ACC; |
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : |
begin |
if (Set_BusB_To[0] == 1'b1 ) |
begin |
BusB <= #1 RegBusB[7:0]; |
end |
else |
begin |
BusB <= #1 RegBusB[15:8]; |
end |
end |
4'b0110 : |
BusB <= #1 DI_Reg; |
4'b1000 : |
BusB <= #1 SP[7:0]; |
4'b1001 : |
BusB <= #1 SP[15:8]; |
4'b1010 : |
BusB <= #1 8'b00000001; |
4'b1011 : |
BusB <= #1 F; |
4'b1100 : |
BusB <= #1 PC[7:0]; |
4'b1101 : |
BusB <= #1 PC[15:8]; |
4'b1110 : |
BusB <= #1 8'b00000000; |
default : |
BusB <= #1 8'h0; |
endcase |
|
case (Set_BusA_To) |
4'b0111 : |
BusA <= #1 ACC; |
4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : |
begin |
if (Set_BusA_To[0] == 1'b1 ) |
begin |
BusA <= #1 RegBusA[7:0]; |
end |
else |
begin |
BusA <= #1 RegBusA[15:8]; |
end |
end |
4'b0110 : |
BusA <= #1 DI_Reg; |
4'b1000 : |
BusA <= #1 SP[7:0]; |
4'b1001 : |
BusA <= #1 SP[15:8]; |
4'b1010 : |
BusA <= #1 8'b00000000; |
default : |
BusA <= #1 8'h0; |
endcase |
end |
end |
|
//------------------------------------------------------------------------- |
// |
// Generate external control signals |
// |
//------------------------------------------------------------------------- |
`ifdef TV80_REFRESH |
always @ (posedge clk or negedge reset_n) |
begin |
if (reset_n == 1'b0 ) |
begin |
rfsh_n <= #1 1'b1; |
end |
else |
begin |
if (cen == 1'b1 ) |
begin |
if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) ) |
begin |
rfsh_n <= #1 1'b0; |
end |
else |
begin |
rfsh_n <= #1 1'b1; |
end |
end |
end |
end // always @ (posedge clk or negedge reset_n) |
`else // !`ifdef TV80_REFRESH |
assign rfsh_n = 1'b1; |
`endif |
|
always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle |
or IntE_FF1 or di or iorq_i or mcycle or tstate) |
begin |
mc = mcycle; |
ts = tstate; |
DI_Reg = di; |
halt_n = ~ Halt_FF; |
busak_n = ~ BusAck; |
intcycle_n = ~ IntCycle; |
IntE = IntE_FF1; |
iorq = iorq_i; |
stop = I_DJNZ; |
end |
|
//----------------------------------------------------------------------- |
// |
// Syncronise inputs |
// |
//----------------------------------------------------------------------- |
|
always @ (posedge clk or negedge reset_n) |
begin : sync_inputs |
if (~reset_n) |
begin |
BusReq_s <= #1 1'b0; |
INT_s <= #1 1'b0; |
NMI_s <= #1 1'b0; |
Oldnmi_n <= #1 1'b0; |
end |
else |
begin |
if (cen == 1'b1 ) |
begin |
BusReq_s <= #1 ~ busrq_n; |
INT_s <= #1 ~ int_n; |
if (NMICycle == 1'b1 ) |
begin |
NMI_s <= #1 1'b0; |
end |
else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) |
begin |
NMI_s <= #1 1'b1; |
end |
Oldnmi_n <= #1 nmi_n; |
end |
end |
end |
|
//----------------------------------------------------------------------- |
// |
// Main state machine |
// |
//----------------------------------------------------------------------- |
|
always @ (posedge clk or negedge reset_n) |
begin |
if (reset_n == 1'b0 ) |
begin |
mcycle <= #1 7'b0000001; |
tstate <= #1 7'b0000001; |
Pre_XY_F_M <= #1 3'b000; |
Halt_FF <= #1 1'b0; |
BusAck <= #1 1'b0; |
NMICycle <= #1 1'b0; |
IntCycle <= #1 1'b0; |
IntE_FF1 <= #1 1'b0; |
IntE_FF2 <= #1 1'b0; |
No_BTR <= #1 1'b0; |
Auto_Wait_t1 <= #1 1'b0; |
Auto_Wait_t2 <= #1 1'b0; |
m1_n <= #1 1'b1; |
end |
else |
begin |
if (cen == 1'b1 ) |
begin |
if (T_Res == 1'b1 ) |
begin |
Auto_Wait_t1 <= #1 1'b0; |
end |
else |
begin |
Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2); |
end |
Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res; |
No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || |
(I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || |
(I_BTR && (~ IR[4] || F[Flag_Z])); |
if (tstate[2] ) |
begin |
if (SetEI == 1'b1 ) |
begin |
if (!NMICycle) |
IntE_FF1 <= #1 1'b1; |
IntE_FF2 <= #1 1'b1; |
end |
if (I_RETN == 1'b1 ) |
begin |
IntE_FF1 <= #1 IntE_FF2; |
end |
end |
if (tstate[3] ) |
begin |
if (SetDI == 1'b1 ) |
begin |
IntE_FF1 <= #1 1'b0; |
IntE_FF2 <= #1 1'b0; |
end |
end |
if (IntCycle == 1'b1 || NMICycle == 1'b1 ) |
begin |
Halt_FF <= #1 1'b0; |
end |
if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) |
begin |
m1_n <= #1 1'b1; |
end |
if (BusReq_s == 1'b1 && BusAck == 1'b1 ) |
begin |
end |
else |
begin |
BusAck <= #1 1'b0; |
if (tstate[2] && wait_n == 1'b0 ) |
begin |
end |
else if (T_Res == 1'b1 ) |
begin |
if (Halt == 1'b1 ) |
begin |
Halt_FF <= #1 1'b1; |
end |
if (BusReq_s == 1'b1 ) |
begin |
BusAck <= #1 1'b1; |
end |
else |
begin |
tstate <= #1 7'b0000010; |
if (NextIs_XY_Fetch == 1'b1 ) |
begin |
mcycle <= #1 7'b0100000; |
Pre_XY_F_M <= #1 mcyc_to_number(mcycle); |
if (IR == 8'b00110110 && Mode == 0 ) |
begin |
Pre_XY_F_M <= #1 3'b010; |
end |
end |
else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) |
begin |
mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1); |
end |
else if ((last_mcycle) || |
No_BTR == 1'b1 || |
(mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) |
begin |
m1_n <= #1 1'b0; |
mcycle <= #1 7'b0000001; |
IntCycle <= #1 1'b0; |
NMICycle <= #1 1'b0; |
if (NMI_s == 1'b1 && Prefix == 2'b00 ) |
begin |
NMICycle <= #1 1'b1; |
IntE_FF1 <= #1 1'b0; |
end |
else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) |
begin |
IntCycle <= #1 1'b1; |
IntE_FF1 <= #1 1'b0; |
IntE_FF2 <= #1 1'b0; |
end |
end |
else |
begin |
mcycle <= #1 { mcycle[5:0], mcycle[6] }; |
end |
end |
end |
else |
begin // verilog has no "nor" operator |
if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && |
~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) |
begin |
tstate <= #1 { tstate[5:0], tstate[6] }; |
end |
end |
end |
if (tstate[0]) |
begin |
m1_n <= #1 1'b0; |
end |
end |
end |
end |
|
always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC |
or RegBusA or RegBusC or SP or tstate) |
begin |
if (JumpE == 1'b1 ) |
begin |
PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; |
end |
else if (BTR_r == 1'b1 ) |
begin |
PC16_B = -2; |
end |
else |
begin |
PC16_B = 1; |
end |
|
if (tstate[3]) |
begin |
SP16_A = RegBusC; |
SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; |
end |
else |
begin |
// suspect that ID16 and SP16 could be shared |
SP16_A = SP; |
|
if (IncDec_16[3] == 1'b1) |
SP16_B = -1; |
else |
SP16_B = 1; |
end |
|
if (IncDec_16[3]) |
ID16_B = -1; |
else |
ID16_B = 1; |
|
ID16 = RegBusA + ID16_B; |
PC16 = PC + PC16_B; |
SP16 = SP16_A + SP16_B; |
end // always @ * |
|
|
always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) |
begin |
Auto_Wait = 1'b0; |
if (IntCycle == 1'b1 || NMICycle == 1'b1 ) |
begin |
if (mcycle[0] ) |
begin |
Auto_Wait = 1'b1; |
end |
end |
end // always @ * |
|
endmodule // T80 |
|
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/mapa_es.inc
0,0 → 1,360
// Teclas con scancode simple |
`define KEY_ESC 8'h76 |
`define KEY_F1 8'h05 |
`define KEY_F2 8'h06 |
`define KEY_F3 8'h04 |
`define KEY_F4 8'h0C |
`define KEY_F5 8'h03 |
`define KEY_F6 8'h0B |
`define KEY_F7 8'h83 |
`define KEY_F8 8'h0A |
`define KEY_F9 8'h01 |
`define KEY_F10 8'h09 |
`define KEY_F11 8'h78 |
`define KEY_F12 8'h07 |
|
`define KEY_BL 8'h0E |
`define KEY_1 8'h16 |
`define KEY_2 8'h1E |
`define KEY_3 8'h26 |
`define KEY_4 8'h25 |
`define KEY_5 8'h2E |
`define KEY_6 8'h36 |
`define KEY_7 8'h3D |
`define KEY_8 8'h3E |
`define KEY_9 8'h46 |
`define KEY_0 8'h45 |
`define KEY_APOS 8'h4E |
`define KEY_AEXC 8'h55 |
`define KEY_BKSP 8'h66 |
|
`define KEY_TAB 8'h0D |
`define KEY_Q 8'h15 |
`define KEY_W 8'h1D |
`define KEY_E 8'h24 |
`define KEY_R 8'h2D |
`define KEY_T 8'h2C |
`define KEY_Y 8'h35 |
`define KEY_U 8'h3C |
`define KEY_I 8'h43 |
`define KEY_O 8'h44 |
`define KEY_P 8'h4D |
`define KEY_CORCHA 8'h54 |
`define KEY_CORCHC 8'h5B |
`define KEY_ENTER 8'h5A |
|
`define KEY_CPSLK 8'h58 |
`define KEY_A 8'h1C |
`define KEY_S 8'h1B |
`define KEY_D 8'h23 |
`define KEY_F 8'h2B |
`define KEY_G 8'h34 |
`define KEY_H 8'h33 |
`define KEY_J 8'h3B |
`define KEY_K 8'h42 |
`define KEY_L 8'h4B |
`define KEY_NT 8'h4C |
`define KEY_LLAVA 8'h52 |
`define KEY_LLAVC 8'h5D |
|
`define KEY_LSHIFT 8'h12 |
`define KEY_LT 8'h61 |
`define KEY_Z 8'h1A |
`define KEY_X 8'h22 |
`define KEY_C 8'h21 |
`define KEY_V 8'h2A |
`define KEY_B 8'h32 |
`define KEY_N 8'h31 |
`define KEY_M 8'h3A |
`define KEY_COMA 8'h41 |
`define KEY_PUNTO 8'h49 |
`define KEY_MENOS 8'h4A |
`define KEY_RSHIFT 8'h59 |
|
`define KEY_CTRLI 8'h14 |
`define KEY_ALTI 8'h11 |
`define KEY_SPACE 8'h29 |
|
`define KEY_KP0 8'h70 |
`define KEY_KP1 8'h69 |
`define KEY_KP2 8'h72 |
`define KEY_KP3 8'h7A |
`define KEY_KP4 8'h6B |
`define KEY_KP5 8'h73 |
`define KEY_KP6 8'h74 |
`define KEY_KP7 8'h6C |
`define KEY_KP8 8'h75 |
`define KEY_KP9 8'h7D |
`define KEY_KPPUNTO 8'h71 |
`define KEY_KPMAS 8'h79 |
`define KEY_KPMENOS 8'h7B |
`define KEY_KPASTER 8'h7C |
|
`define KEY_BLKNUM 8'h77 |
`define KEY_BLKSCR 8'h7E |
|
// Teclas con E0 + scancode |
`define KEY_WAKEUP 8'h5E |
`define KEY_SLEEP 8'h3F |
`define KEY_POWER 8'h37 |
`define KEY_INS 8'h70 |
`define KEY_SUP 8'h71 |
`define KEY_HOME 8'h6C |
`define KEY_END 8'h69 |
`define KEY_PGU 8'h7D |
`define KEY_PGD 8'h7A |
`define KEY_UP 8'h75 |
`define KEY_DOWN 8'h72 |
`define KEY_LEFT 8'h6B |
`define KEY_RIGHT 8'h74 |
`define KEY_CTRLD 8'h14 |
`define KEY_ALTGR 8'h11 |
`define KEY_KPENTER 8'h5A |
`define KEY_KPSLASH 8'h4A |
`define KEY_PRTSCR 8'h7C |
|
// Matriz del ZX Spectrum |
`define SP_CS {3'b000,5'b11110} |
`define SP_Z {3'b000,5'b11101} |
`define SP_X {3'b000,5'b11011} |
`define SP_C {3'b000,5'b10111} |
`define SP_V {3'b000,5'b01111} |
|
`define SP_A {3'b001,5'b11110} |
`define SP_S {3'b001,5'b11101} |
`define SP_D {3'b001,5'b11011} |
`define SP_F {3'b001,5'b10111} |
`define SP_G {3'b001,5'b01111} |
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`define SP_Q {3'b010,5'b11110} |
`define SP_W {3'b010,5'b11101} |
`define SP_E {3'b010,5'b11011} |
`define SP_R {3'b010,5'b10111} |
`define SP_T {3'b010,5'b01111} |
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`define SP_1 {3'b011,5'b11110} |
`define SP_2 {3'b011,5'b11101} |
`define SP_3 {3'b011,5'b11011} |
`define SP_4 {3'b011,5'b10111} |
`define SP_5 {3'b011,5'b01111} |
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`define SP_0 {3'b100,5'b11110} |
`define SP_9 {3'b100,5'b11101} |
`define SP_8 {3'b100,5'b11011} |
`define SP_7 {3'b100,5'b10111} |
`define SP_6 {3'b100,5'b01111} |
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`define SP_P {3'b101,5'b11110} |
`define SP_O {3'b101,5'b11101} |
`define SP_I {3'b101,5'b11011} |
`define SP_U {3'b101,5'b10111} |
`define SP_Y {3'b101,5'b01111} |
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`define SP_ENT {3'b110,5'b11110} |
`define SP_L {3'b110,5'b11101} |
`define SP_K {3'b110,5'b11011} |
`define SP_J {3'b110,5'b10111} |
`define SP_H {3'b110,5'b01111} |
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`define SP_SPC {3'b111,5'b11110} |
`define SP_SS {3'b111,5'b11101} |
`define SP_M {3'b111,5'b11011} |
`define SP_N {3'b111,5'b10111} |
`define SP_B {3'b111,5'b01111} |
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`define SP_NOKEY {3'b111,5'b11111} |
`define NADA {`SP_NOKEY,`SP_NOKEY} |
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integer relleno; |
initial begin |
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for (relleno=0;relleno<=131; relleno=relleno+1) |
begin |
mapa_noshift_noext[relleno]={`NADA}; |
mapa_noshift_ext[relleno]={`NADA}; |
mapa_shift_noext[relleno]={`NADA}; |
mapa_shift_ext[relleno]={`NADA}; |
end |
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/* TRADUCCION DE TECLAS SIN SHIFT PULSADO */ |
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// Fila de teclas de funcion (13 teclas) |
mapa_noshift_noext[`KEY_ESC] ={`SP_CS,`SP_SPC}; |
mapa_noshift_noext[`KEY_F2] ={`SP_CS,`SP_1}; |
|
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mapa_noshift_noext[`KEY_BL] ={`SP_SS,`SP_D}; |
mapa_noshift_noext[`KEY_1] ={`SP_1,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_2] ={`SP_2,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_3] ={`SP_3,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_4] ={`SP_4,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_5] ={`SP_5,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_6] ={`SP_6,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_7] ={`SP_7,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_8] ={`SP_8,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_9] ={`SP_9,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_0] ={`SP_0,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_APOS] ={`SP_SS,`SP_7}; |
mapa_noshift_noext[`KEY_BKSP] ={`SP_CS,`SP_0}; |
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// Fila Q-P (14 teclas) |
mapa_noshift_noext[`KEY_TAB] ={`SP_CS,`SP_SS}; |
mapa_noshift_noext[`KEY_Q] ={`SP_Q,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_W] ={`SP_W,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_E] ={`SP_E,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_R] ={`SP_R,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_T] ={`SP_T,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_Y] ={`SP_Y,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_U] ={`SP_U,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_I] ={`SP_I,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_O] ={`SP_O,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_P] ={`SP_P,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_CORCHA]={`SP_SS,`SP_H}; |
mapa_noshift_noext[`KEY_CORCHC]={`SP_SS,`SP_K}; |
mapa_noshift_noext[`KEY_ENTER]={`SP_ENT,`SP_NOKEY}; |
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// Fila A-L (13 teclas) |
mapa_noshift_noext[`KEY_CPSLK]={`SP_CS,`SP_2}; |
mapa_noshift_noext[`KEY_A] ={`SP_A,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_S] ={`SP_S,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_D] ={`SP_D,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_F] ={`SP_F,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_G] ={`SP_G,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_H] ={`SP_H,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_J] ={`SP_J,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_K] ={`SP_K,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_L] ={`SP_L,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_LLAVA]={`SP_SS,`SP_F}; |
mapa_noshift_noext[`KEY_LLAVC]={`SP_SS,`SP_P}; |
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// Fila Z-M (13 teclas) |
mapa_noshift_noext[`KEY_LT] ={`SP_SS,`SP_R}; |
mapa_noshift_noext[`KEY_Z] ={`SP_Z,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_X] ={`SP_X,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_C] ={`SP_C,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_V] ={`SP_V,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_B] ={`SP_B,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_N] ={`SP_N,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_M] ={`SP_M,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_COMA] ={`SP_SS,`SP_N}; |
mapa_noshift_noext[`KEY_PUNTO]={`SP_SS,`SP_M}; |
mapa_noshift_noext[`KEY_MENOS]={`SP_SS,`SP_J}; |
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// Fila CTRL-SPACE (3 teclas) |
mapa_noshift_noext[`KEY_CTRLI]={`SP_CS,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_SPACE]={`SP_SPC,`SP_NOKEY}; |
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// Keypad (14 teclas) |
mapa_noshift_noext[`KEY_KP0] ={`SP_0,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP1] ={`SP_1,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP2] ={`SP_2,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP3] ={`SP_3,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP4] ={`SP_4,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP5] ={`SP_5,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP6] ={`SP_6,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP7] ={`SP_7,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP8] ={`SP_8,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KP9] ={`SP_9,`SP_NOKEY}; |
mapa_noshift_noext[`KEY_KPPUNTO] ={`SP_SS,`SP_M}; |
mapa_noshift_noext[`KEY_KPMAS] ={`SP_SS,`SP_K}; |
mapa_noshift_noext[`KEY_KPMENOS] ={`SP_SS,`SP_J}; |
mapa_noshift_noext[`KEY_KPASTER] ={`SP_SS,`SP_B}; |
|
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/* TRADUCCION DE TECLAS CON SHIFT PULSADO */ |
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// Fila de teclas de funcion (13 teclas) |
mapa_shift_noext[`KEY_ESC] ={`SP_CS,`SP_SPC}; |
mapa_shift_noext[`KEY_F2] ={`SP_CS,`SP_1}; |
|
|
mapa_shift_noext[`KEY_1] ={`SP_1,`SP_SS}; |
mapa_shift_noext[`KEY_2] ={`SP_P,`SP_SS}; |
mapa_shift_noext[`KEY_3] ={`SP_3,`SP_SS}; |
mapa_shift_noext[`KEY_4] ={`SP_4,`SP_SS}; |
mapa_shift_noext[`KEY_5] ={`SP_5,`SP_SS}; |
mapa_shift_noext[`KEY_6] ={`SP_6,`SP_SS}; |
mapa_shift_noext[`KEY_7] ={`SP_V,`SP_SS}; |
mapa_shift_noext[`KEY_8] ={`SP_8,`SP_SS}; |
mapa_shift_noext[`KEY_9] ={`SP_9,`SP_SS}; |
mapa_shift_noext[`KEY_0] ={`SP_L,`SP_SS}; |
mapa_shift_noext[`KEY_APOS] ={`SP_C,`SP_SS}; |
mapa_shift_noext[`KEY_BKSP] ={`SP_CS,`SP_0}; |
|
// Fila Q-P (14 teclas) |
mapa_shift_noext[`KEY_TAB] ={`SP_CS,`SP_SS}; |
mapa_shift_noext[`KEY_Q] ={`SP_Q,`SP_CS}; |
mapa_shift_noext[`KEY_W] ={`SP_W,`SP_CS}; |
mapa_shift_noext[`KEY_E] ={`SP_E,`SP_CS}; |
mapa_shift_noext[`KEY_R] ={`SP_R,`SP_CS}; |
mapa_shift_noext[`KEY_T] ={`SP_T,`SP_CS}; |
mapa_shift_noext[`KEY_Y] ={`SP_Y,`SP_CS}; |
mapa_shift_noext[`KEY_U] ={`SP_U,`SP_CS}; |
mapa_shift_noext[`KEY_I] ={`SP_I,`SP_CS}; |
mapa_shift_noext[`KEY_O] ={`SP_O,`SP_CS}; |
mapa_shift_noext[`KEY_P] ={`SP_P,`SP_CS}; |
mapa_shift_noext[`KEY_CORCHA] ={`SP_SS,`SP_H}; |
mapa_shift_noext[`KEY_CORCHC] ={`SP_SS,`SP_B}; |
mapa_shift_noext[`KEY_ENTER] ={`SP_ENT,`SP_NOKEY}; |
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// Fila A-L (13 teclas) |
mapa_shift_noext[`KEY_CPSLK] ={`SP_CS,`SP_2}; |
mapa_shift_noext[`KEY_A] ={`SP_A,`SP_CS}; |
mapa_shift_noext[`KEY_S] ={`SP_S,`SP_CS}; |
mapa_shift_noext[`KEY_D] ={`SP_D,`SP_CS}; |
mapa_shift_noext[`KEY_F] ={`SP_F,`SP_CS}; |
mapa_shift_noext[`KEY_G] ={`SP_G,`SP_CS}; |
mapa_shift_noext[`KEY_H] ={`SP_H,`SP_CS}; |
mapa_shift_noext[`KEY_J] ={`SP_J,`SP_CS}; |
mapa_shift_noext[`KEY_K] ={`SP_K,`SP_CS}; |
mapa_shift_noext[`KEY_L] ={`SP_L,`SP_CS}; |
mapa_shift_noext[`KEY_LLAVA] ={`SP_SS,`SP_F}; |
mapa_shift_noext[`KEY_LLAVC] ={`SP_SS,`SP_G}; |
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// Fila Z-M (13 teclas) |
mapa_shift_noext[`KEY_LT] ={`SP_SS,`SP_T}; |
mapa_shift_noext[`KEY_Z] ={`SP_Z,`SP_CS}; |
mapa_shift_noext[`KEY_X] ={`SP_X,`SP_CS}; |
mapa_shift_noext[`KEY_C] ={`SP_C,`SP_CS}; |
mapa_shift_noext[`KEY_V] ={`SP_V,`SP_CS}; |
mapa_shift_noext[`KEY_B] ={`SP_B,`SP_CS}; |
mapa_shift_noext[`KEY_N] ={`SP_N,`SP_CS}; |
mapa_shift_noext[`KEY_M] ={`SP_M,`SP_CS}; |
mapa_shift_noext[`KEY_COMA] ={`SP_SS,`SP_O}; |
mapa_shift_noext[`KEY_PUNTO]={`SP_SS,`SP_Z}; |
mapa_shift_noext[`KEY_MENOS]={`SP_SS,`SP_0}; |
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// Fila CTRL-SPACE (3 teclas) |
mapa_shift_noext[`KEY_CTRLI]={`SP_CS,`SP_NOKEY}; |
mapa_shift_noext[`KEY_SPACE]={`SP_SPC,`SP_NOKEY}; |
|
// Keypad (14 teclas) |
mapa_shift_noext[`KEY_KP0] ={`SP_0,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP1] ={`SP_1,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP2] ={`SP_2,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP3] ={`SP_3,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP4] ={`SP_4,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP5] ={`SP_5,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP6] ={`SP_6,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP7] ={`SP_7,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP8] ={`SP_8,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KP9] ={`SP_9,`SP_NOKEY}; |
mapa_shift_noext[`KEY_KPPUNTO] ={`SP_SS,`SP_M}; |
mapa_shift_noext[`KEY_KPMAS] ={`SP_SS,`SP_K}; |
mapa_shift_noext[`KEY_KPMENOS] ={`SP_SS,`SP_J}; |
mapa_shift_noext[`KEY_KPASTER] ={`SP_SS,`SP_B}; |
|
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/* TRADUCCION DE TECLAS EXTENDIDAS SIN SHIFT PULSADO */ |
|
mapa_noshift_ext[`KEY_UP] ={`SP_7,`SP_CS}; |
mapa_noshift_ext[`KEY_DOWN] ={`SP_6,`SP_CS}; |
mapa_noshift_ext[`KEY_LEFT] ={`SP_5,`SP_CS}; |
mapa_noshift_ext[`KEY_RIGHT] ={`SP_8,`SP_CS}; |
mapa_noshift_ext[`KEY_CTRLD] ={`SP_SS,`SP_NOKEY}; |
mapa_noshift_ext[`KEY_KPENTER] ={`SP_ENT,`SP_NOKEY}; |
mapa_noshift_ext[`KEY_KPSLASH] ={`SP_V,`SP_SS}; |
|
end |
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