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URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

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Rev 17 → Rev 18

/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/zx_spectrum_48k.xise
78,6 → 78,10
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="rgbdtoa.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
130,7 → 134,7
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/ula.v
54,6 → 54,8
output g, // RGB TTL signal
output b, // with separate bright
output i, // and composite sync
output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
output csync //
);
 
60,21 → 62,22
reg [2:0] BorderColor = 3'b100;
reg TimexHiColorMode = 0;
reg ULAPlusConfig = 0;
reg [7:0] ULAPlusAddrReg = 0;
reg ULAPlusConfig = 0; // bit 0 of reg.64
reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
assign ulaplus_enabled = ULAPlusConfig;
wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00);
reg [5:0] paletteaddr;
wire [7:0] palettedout;
reg palettewe;
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
reg [5:0] paletteaddr; // address bus of palette RAM
wire [7:0] palettedout; // data out port of palette RAM
reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
 
ram64bytes palette (
.clk(clk14),
.a(paletteaddr),
.clk(clk14), // only for write operations. Read operations are asynchronous
.a(paletteaddr),
.din(din),
.dout(palettedout),
.we(palettewe)
.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
);
 
// Pixel clock
301,7 → 304,7
end
end
 
// Palette addr and control bus multiplexing
// ULA+ : palette RAM address and control bus multiplexing
always @(*) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
palettewe = 0;
315,12 → 318,49
paletteaddr = ULAPlusAddrReg[5:0];
palettewe = cpu_writes_palette;
end
else begin
else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
end
end
//ULA+ : palette reading and attribute generation
// First buffers for paper and ink
reg [7:0] ULAPlusPaper = 0;
reg [7:0] ULAPlusInk = 0;
reg [7:0] ULAPlusBorder = 0;
wire ULAPlusPixel = SRegister[7];
always @(negedge clk14) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusPaper <= palettedout;
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusInk <= palettedout;
else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
// Second buffers for paper and ink
reg [7:0] ULAPlusPaperOut = 0;
reg [7:0] ULAPlusInkOut = 0;
always @(negedge AOLatch_n) begin
if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
ULAPlusPaperOut <= ULAPlusPaper;
ULAPlusInkOut <= ULAPlusInk;
end
else begin // if not, it's "border/blanking time", so load output buffers with current border color
ULAPlusPaperOut <= ULAPlusBorder;
ULAPlusInkOut <= ULAPlusBorder;
end
end
// ULA+ : final RGB generation depending on pixel value and blanking period.
reg [7:0] rRGBULAPlus;
assign rgbulaplus = rRGBULAPlus;
always @(*) begin
if (HBlank_n && VBlank_n)
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
else
rRGBULAPlus = 8'h00;
end
// CPU contention
reg CPUClk = 0;
assign clkcpu = CPUClk;
349,7 → 389,7
mreqt23 <= mreq_n;
end
// ULA+ palette management
// ULA+ : palette management
always @(posedge clk7 or posedge reset) begin
if (reset)
ULAPlusConfig <= 0;
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/rgbdtoa.v
0,0 → 1,131
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:10:16 04/04/2012
// Design Name:
// Module Name: rgbdtoa
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rgbdtoa(
input clk, // 56MHz (or more) clock
input reset,
input select, // 0=ULA, 1=ULA+
input ri, //
input gi, // digital IRGB
input bi, // inputs from standar ULA
input hi, //
input [7:0] rgbulap, // 8-bit input from ULA+
output r, //
output g, // sigma-delta encoded analog RGB signals
output b //
);
 
reg [2:0] dacr;
reg [2:0] dacg;
reg [2:0] dacb;
always @(*) begin
if (!select) begin
case ({hi,ri})
2'b00 : dacr = 3'b000;
2'b01 : dacr = 3'b101;
2'b10 : dacr = 3'b000;
2'b11 : dacr = 3'b111;
endcase
end
else
dacr = rgbulap[4:2];
end
always @(*) begin
if (!select) begin
case ({hi,gi})
2'b00 : dacg = 3'b000;
2'b01 : dacg = 3'b101;
2'b10 : dacg = 3'b000;
2'b11 : dacg = 3'b111;
endcase
end
else
dacg = rgbulap[7:5];
end
always @(*) begin
if (!select) begin
case ({hi,bi})
2'b00 : dacb = 3'b000;
2'b01 : dacb = 3'b101;
2'b10 : dacb = 3'b000;
2'b11 : dacb = 3'b111;
endcase
end
else
dacb = {rgbulap[1:0],rgbulap[1]};
end
dac3bit dtoarojo (
.DACout(r),
.DACin(dacr),
.Clk(clk),
.Reset(reset)
);
dac3bit dtoaverde (
.DACout(g),
.DACin(dacg),
.Clk(clk),
.Reset(reset)
);
dac3bit dtoaazul (
.DACout(b),
.DACin(dacb),
.Clk(clk),
.Reset(reset)
);
endmodule
 
`define MSBI 2 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac3bit (DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
 
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
 
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/spectrum48k_tld.v
95,22 → 95,25
wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
 
/////////////////////////////////////
// Master clock (14MHz) generation
// Clock generation
/////////////////////////////////////
wire clk28mhz;
master_clock clock28mhz (
wire clk56mhz;
master_clock clock56mhz (
.CLKIN_IN(clk50),
.CLKFX_OUT(clk28mhz),
.CLKFX_OUT(clk56mhz),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
reg clk14 = 0;
always @(posedge clk28mhz) begin
clk14 = !clk14;
reg [1:0] cnt56;
always @(posedge clk56mhz) begin
cnt56 = cnt56 + 1;
end
wire clk28 = cnt56[0];
wire clk14 = cnt56[1];
wire clkula = clk14;
wire clkmem = clk28mhz;
wire clkaudio = clk14;
wire clkdacvideo = clk56mhz;
wire clkmem = clk28;
wire clkdacaudio = clk14;
wire clkkbd = clk14;
/////////////////////////////////////
155,6 → 158,8
/////////////////////////////////////
// The ULA
/////////////////////////////////////
wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;
wire [7:0] rgbulaplus;
ula the_ula (
.clk14(clkula),
.reset(reset),
179,14 → 184,34
.spk(spk),
.kbrows(),
.kbcolumns(kbd_columns),
.r(r),
.g(g),
.b(b),
.i(i),
.r(ula_r),
.g(ula_g),
.b(ula_b),
.i(ula_i),
.rgbulaplus(rgbulaplus),
.ulaplus_enabled(ulaplus_enabled),
.csync(csync)
);
 
/////////////////////////////////////
// ULA/ULA+ video selector and enconding
/////////////////////////////////////
assign i = 1;
rgbdtoa video_final_stage (
.clk(clkdacvideo),
.reset(reset),
.select(ulaplus_enabled),
.ri(ula_r),
.gi(ula_g),
.bi(ula_b),
.hi(ula_i),
.rgbulap(rgbulaplus),
.r(r),
.g(g),
.b(b)
);
 
/////////////////////////////////////
// The CPU Z80A
/////////////////////////////////////
tv80n cpu (
225,7 → 250,7
// Audio mixer
/////////////////////////////////////
mixer audio_mix (
.clkdac(clkaudio),
.clkdac(clkdacaudio),
.reset(reset),
.ear(ear),
.mic(mic),
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/tld_spartan3_sp48k_bitgen.xwbt
0,0 → 1,8
INTSTYLE=ise
INFILE=C:\Documents and Settings\rodriguj\Mis documentos\opencores\zx_ula\branches\xilinx\spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus\tld_spartan3_sp48k.ncd
OUTFILE=C:\Documents and Settings\rodriguj\Mis documentos\opencores\zx_ula\branches\xilinx\spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus\tld_spartan3_sp48k.bit
FAMILY=Spartan3
PART=xc3s200-4ft256
WORKINGDIR=C:\Documents and Settings\rodriguj\Mis documentos\opencores\zx_ula\branches\xilinx\spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus
LICENSE=WebPack
USER_INFO=0_0_433
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/master_clock.v
48,7 → 48,7
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKFX_MULTIPLY(28), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-1000_sp48k.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-1000_sp48k.bit
zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-1000_sp48k.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-200_sp48k.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-200_sp48k.bit =================================================================== --- zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-200_sp48k.bit (nonexistent) +++ zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-200_sp48k.bit (revision 18)
zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-200_sp48k.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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