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URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

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/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/signalview_ulaplus.wcfg
0,0 → 1,247
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/rodriguj/Desktop/opencores/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/test_ulaplus_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="test_ulaplus" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="47" />
<wvobject fp_name="/test_ulaplus/uut/clk7" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk7</obj_property>
<obj_property name="ObjectShortName">clk7</obj_property>
</wvobject>
<wvobject fp_name="divider14" type="divider">
<obj_property name="label">Counters</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/hc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">hc[8:0]</obj_property>
<obj_property name="ObjectShortName">hc[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/vc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vc[8:0]</obj_property>
<obj_property name="ObjectShortName">vc[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider5" type="divider">
<obj_property name="label">Syncs</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/HBlank_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">HBlank_n</obj_property>
<obj_property name="ObjectShortName">HBlank_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/HSync_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">HSync_n</obj_property>
<obj_property name="ObjectShortName">HSync_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/VSync_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">VSync_n</obj_property>
<obj_property name="ObjectShortName">VSync_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/msk_int_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">msk_int_n</obj_property>
<obj_property name="ObjectShortName">msk_int_n</obj_property>
</wvobject>
<wvobject fp_name="divider9" type="divider">
<obj_property name="label">Control clocks</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/Border_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Border_n</obj_property>
<obj_property name="ObjectShortName">Border_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/VidEN_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">VidEN_n</obj_property>
<obj_property name="ObjectShortName">VidEN_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/DataLatch_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">DataLatch_n</obj_property>
<obj_property name="ObjectShortName">DataLatch_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/AttrLatch_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">AttrLatch_n</obj_property>
<obj_property name="ObjectShortName">AttrLatch_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/SLoad" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SLoad</obj_property>
<obj_property name="ObjectShortName">SLoad</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/AOLatch_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">AOLatch_n</obj_property>
<obj_property name="ObjectShortName">AOLatch_n</obj_property>
</wvobject>
<wvobject fp_name="divider17" type="divider">
<obj_property name="label">Data</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/clk14" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk14</obj_property>
<obj_property name="ObjectShortName">clk14</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/va" type="array" db_ref_id="1">
<obj_property name="ElementShortName">va[13:0]</obj_property>
<obj_property name="ObjectShortName">va[13:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/BitmapReg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">BitmapReg[7:0]</obj_property>
<obj_property name="ObjectShortName">BitmapReg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/SRegister" type="array" db_ref_id="1">
<obj_property name="ElementShortName">SRegister[7:0]</obj_property>
<obj_property name="ObjectShortName">SRegister[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/AttrReg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">AttrReg[7:0]</obj_property>
<obj_property name="ObjectShortName">AttrReg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/AttrOut" type="array" db_ref_id="1">
<obj_property name="ElementShortName">AttrOut[7:0]</obj_property>
<obj_property name="ObjectShortName">AttrOut[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider43" type="divider">
<obj_property name="label">ULA+ palette address and data buses</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/paletteaddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">paletteaddr[5:0]</obj_property>
<obj_property name="ObjectShortName">paletteaddr[5:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/ULAPlusPaper" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ULAPlusPaper[7:0]</obj_property>
<obj_property name="ObjectShortName">ULAPlusPaper[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/ULAPlusInk" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ULAPlusInk[7:0]</obj_property>
<obj_property name="ObjectShortName">ULAPlusInk[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/ULAPlusBorder" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ULAPlusBorder[7:0]</obj_property>
<obj_property name="ObjectShortName">ULAPlusBorder[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/ULAPlusPaperOut" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ULAPlusPaperOut[7:0]</obj_property>
<obj_property name="ObjectShortName">ULAPlusPaperOut[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/ULAPlusInkOut" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ULAPlusInkOut[7:0]</obj_property>
<obj_property name="ObjectShortName">ULAPlusInkOut[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/rRGBULAPlus" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rRGBULAPlus[7:0]</obj_property>
<obj_property name="ObjectShortName">rRGBULAPlus[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider26" type="divider">
<obj_property name="label">TV Output</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="vbus29" type="vbus" db_ref_id="1">
<obj_property name="label">RGB</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<wvobject fp_name="/test_ulaplus/g" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">g</obj_property>
<obj_property name="ObjectShortName">g</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/r" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">r</obj_property>
<obj_property name="ObjectShortName">r</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/b" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">b</obj_property>
<obj_property name="ObjectShortName">b</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/test_ulaplus/i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i</obj_property>
<obj_property name="ObjectShortName">i</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/csync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">csync</obj_property>
<obj_property name="ObjectShortName">csync</obj_property>
</wvobject>
<wvobject fp_name="divider39" type="divider">
<obj_property name="label">Contention handler</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/CLKContention" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">CLKContention</obj_property>
<obj_property name="ObjectShortName">CLKContention</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/Nor1" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Nor1</obj_property>
<obj_property name="ObjectShortName">Nor1</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/Nor2" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Nor2</obj_property>
<obj_property name="ObjectShortName">Nor2</obj_property>
</wvobject>
<wvobject fp_name="divider34" type="divider">
<obj_property name="label">CPU</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/uut/clk7" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk7</obj_property>
<obj_property name="ObjectShortName">clk7</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a[15:0]</obj_property>
<obj_property name="ObjectShortName">a[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/mreq_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mreq_n</obj_property>
<obj_property name="ObjectShortName">mreq_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/iorq_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">iorq_n</obj_property>
<obj_property name="ObjectShortName">iorq_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/wr_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_n</obj_property>
<obj_property name="ObjectShortName">wr_n</obj_property>
</wvobject>
<wvobject fp_name="/test_ulaplus/cpu/d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">d[7:0]</obj_property>
<obj_property name="ObjectShortName">d[7:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/test_ula.v
22,7 → 22,7
//
////////////////////////////////////////////////////////////////////////////////
 
module test_reference_ula;
module test_standard_ula;
 
// Inputs
reg clk14;
107,162 → 107,3
clk14 = #35.714286 ~clk14;
end
endmodule
 
module z80memr (
input clk,
output [15:0] a,
output [7:0] d,
output mreq,
output rd
);
reg rmreq = 1;
reg rrd = 1;
assign mreq = rmreq;
assign rd = rrd;
reg [1:0] estado = 2;
assign d = 8'bzzzzzzzz;
 
reg [15:0] ra = 16'h7FFF;
assign a = ra;
 
always @(posedge clk) begin
if (estado==2) begin
estado <= 0;
ra <= ~ra;
end
else
estado <= estado + 1;
end
 
always @(*) begin
if (estado==0 && clk)
{rmreq,rrd} = 2'b11;
else if (estado==0 && !clk)
{rmreq,rrd} = 2'b00;
else if (estado==1)
{rmreq,rrd} = 2'b00;
else if (estado==2 && clk)
{rmreq,rrd} = 2'b00;
else
{rmreq,rrd} = 2'b11;
end
endmodule
 
 
module z80memio (
input clk,
output [15:0] a,
output [7:0] d,
output mreq_n,
output iorq_n,
output wr_n,
output rfsh_n
);
reg rmreq = 1;
reg riorq = 1;
reg rwr = 1;
reg rrfsh = 1;
assign mreq_n = rmreq;
assign iorq_n = riorq;
assign wr_n = rwr;
assign rfsh_n = rrfsh;
reg [1:0] estado = 0;
reg [5:0] memioseq = 6'b011001;
reg [5:0] io2seq = 5'b011000;
reg [4:0] hiloseq = 5'b01010;
wire memio = memioseq[0]; // 0 = mem, 1 = io
wire hilo = hiloseq[0]; // 0 = access to lower RAM/Port FEh
wire iohi = io2seq[0]; // 0 = port 00FF/00FE, 1 = port 40FE,40FF
 
reg [15:0] ra;
assign a = ra;
reg [7:0] rd;
assign d = rd;
reg [7:0] iodata = 0;
reg [7:0] memdata = 0;
reg [15:0] memaddr = 16384;
 
always @(posedge clk) begin
if (estado==2 && !memio) begin
estado <= 0;
memioseq <= { memioseq[0], memioseq[5:1] };
hiloseq <= { hiloseq[0], hiloseq[4:1] };
io2seq <= { io2seq[0], io2seq[5:1] };
memdata <= memdata + 1;
if (memaddr == 23295)
memaddr <= 16384;
else
memaddr <= memaddr + 1;
end
else if (estado==3 && memio) begin
estado <= 0;
memioseq <= { memioseq[0], memioseq[5:1] };
hiloseq <= { hiloseq[0], hiloseq[4:1] };
io2seq <= { io2seq[0], io2seq[5:1] };
iodata <= iodata + 1;
end
else
estado <= estado + 1;
end
 
always @(*) begin
if (memio) begin // if this is an I/O bus cycle...
case ({estado,clk})
3'b001 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = 8'bzzzzzzzz;
end
3'b000 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
3'b011,3'b010,3'b101,3'b100,3'b111 :
begin
{rmreq,riorq,rwr} = 3'b100;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
3'b110 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
endcase
end
else begin // this is a MEM bus cycle
case ({estado,clk})
3'b001 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {hilo,memaddr[14:0]};
rd = 8'bzzzzzzzz;
end
3'b000,3'b011 :
begin
{rmreq,riorq,rwr} = 3'b011;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
3'b010,3'b101 :
begin
{rmreq,riorq,rwr} = 3'b010;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
3'b100 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
endcase
end
end
endmodule
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/ram64bytes.v
0,0 → 1,42
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:57:11 04/29/2012
// Design Name:
// Module Name: ram64bytes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ram64bytes(
input clk,
input [5:0] a,
input [7:0] din,
output [7:0] dout,
input we
);
reg [7:0] mem[0:63];
assign dout = mem[a]; //non registered address. Ugly, but works :(
 
integer i;
initial begin
for (i=0;i<=63;i=i+1)
mem[i] = i/8;
end
always @(posedge clk) begin
if (we)
mem[a] <= din;
end
endmodule
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/test_ulaplus.v
0,0 → 1,118
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:16:22 04/08/2012
// Design Name: ula
// Module Name: C:/proyectos_xilinx/ulaplus/test_reference_ula.v
// Project Name: ulaplus
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ula
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module test_ulaplus;
 
// Inputs
reg clk14;
reg reset;
wire [15:0] a;
wire [7:0] din;
wire mreq_n;
wire iorq_n;
wire wr_n;
wire rfsh_n;
reg [7:0] vramdout;
reg ear;
reg [4:0] kbcolumns;
 
// Outputs
wire [7:0] dout;
wire clkcpu;
wire msk_int_n;
wire [13:0] va;
wire [7:0] vramdin;
wire vramoe;
wire vramcs;
wire vramwe;
wire mic;
wire spk;
wire [7:0] kbrows;
wire r;
wire g;
wire b;
wire i;
wire [7:0] rgbulaplus;
wire ulaplus_enabled;
wire csync;
 
// Instantiate the Unit Under Test (UUT)
ulaplus uut (
.clk14(clk14),
.reset(reset),
.a(a),
.din(din),
.dout(dout),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(1'b1),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.clkcpu(clkcpu),
.msk_int_n(msk_int_n),
.va(va),
.vramdout(vramdout),
.vramdin(vramdin),
.vramoe(vramoe),
.vramcs(vramcs),
.vramwe(vramwe),
.ear(ear),
.mic(mic),
.spk(spk),
.kbrows(kbrows),
.kbcolumns(kbcolumns),
.r(r),
.g(g),
.b(b),
.i(i),
.rgbulaplus(rgbulaplus),
.ulaplus_enabled(ulaplus_enabled),
.csync(csync)
);
 
z80memio cpu (
.clk(clkcpu),
.a(a),
.d(din),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n)
);
 
initial begin
// Initialize Inputs
clk14 = 0;
vramdout = 8'b01010101;
ear = 0;
kbcolumns = 0;
reset = 1;
reset = #20 0;
end
always begin
clk14 = #35.714286 ~clk14;
end
endmodule
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/ula_with_timex_hicolor_support_and_ulaplus.v
0,0 → 1,434
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Dept. Architecture and Computing Technology. University of Seville
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
//
// Create Date: 19:13:39 4-Apr-2012
// Design Name: ZX Spectrum
// Module Name: ula
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.00 - File Created
// Additional Comments: GPL License policies apply to the contents of this file.
//
//////////////////////////////////////////////////////////////////////////////////
 
`define cyclestart(a,b) ((a)==(b))
`define cycleend(a,b) ((a)==(b+1))
 
module ulaplus (
input clk14, // 14MHz master clock
input reset, // to reset the ULA to normal color mode.
// CPU interfacing
input [15:0] a, // Address bus from CPU (not all lines are used)
input [7:0] din, // Input data bus from CPU
output [7:0] dout, // Output data bus to CPU
input mreq_n, // MREQ from CPU
input iorq_n, // IORQ from CPU
input rd_n, // RD from CPU
input wr_n, // WR from CPU
input rfsh_n, // RFSH from CPU
output clkcpu, // CLK to CPU
output msk_int_n, // Vertical retrace interrupt, to CPU
// VRAM interfacing
output [13:0] va, // Address bus to VRAM (16K)
input [7:0] vramdout,// Data from VRAM to ULA/CPU
output [7:0] vramdin,// Data from CPU to VRAM
output vramoe, //
output vramcs, // Control signals for VRAM
output vramwe, //
// ULA I/O
input ear, //
output mic, // I/O ports
output spk, //
output [7:0] kbrows, // Keyboard rows
input [4:0] kbcolumns, // Keyboard columns
// Video output
output r, //
output g, // RGB TTL signal
output b, // with separate bright
output i, // and composite sync
output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
output csync //
);
 
reg [2:0] BorderColor = 3'b100;
reg TimexHiColorMode = 0;
reg ULAPlusConfig = 0; // bit 0 of reg.64
reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
assign ulaplus_enabled = ULAPlusConfig;
wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
reg [5:0] paletteaddr; // address bus of palette RAM
wire [7:0] palettedout; // data out port of palette RAM
reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
 
ram64bytes palette (
.clk(clk14), // only for write operations. Read operations are asynchronous
.a(paletteaddr),
.din(din),
.dout(palettedout),
.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
);
 
// Pixel clock
reg clk7 = 0;
always @(posedge clk14)
clk7 <= !clk7;
// Horizontal counter
reg [8:0] hc = 0;
always @(posedge clk7) begin
if (hc==447)
hc <= 0;
else
hc <= hc + 1;
end
// Vertical counter
reg [8:0] vc = 0;
always @(posedge clk7) begin
if (hc==447) begin
if (vc == 311)
vc <= 0;
else
vc <= vc + 1;
end
end
// HBlank generation
reg HBlank_n = 1;
always @(negedge clk7) begin
if (`cyclestart(hc,320))
HBlank_n <= 0;
else if (`cycleend(hc,415))
HBlank_n <= 1;
end
 
// HSync generation (6C ULA version)
reg HSync_n = 1;
always @(negedge clk7) begin
if (`cyclestart(hc,344))
HSync_n <= 0;
else if (`cycleend(hc,375))
HSync_n <= 1;
end
 
// VBlank generation
reg VBlank_n = 1;
always @(negedge clk7) begin
if (`cyclestart(vc,248))
VBlank_n <= 0;
else if (`cycleend(vc,255))
VBlank_n <= 1;
end
// VSync generation (PAL)
reg VSync_n = 1;
always @(negedge clk7) begin
if (`cyclestart(vc,248))
VSync_n <= 0;
else if (`cycleend(vc,251))
VSync_n <= 1;
end
// INT generation
reg INT_n = 1;
assign msk_int_n = INT_n;
always @(negedge clk7) begin
if (`cyclestart(vc,248) && `cyclestart(hc,0))
INT_n <= 0;
else if (`cyclestart(vc,248) && `cycleend(hc,31))
INT_n <= 1;
end
 
// Border control signal (=0 when we're not displaying paper/ink pixels)
reg Border_n = 1;
always @(negedge clk7) begin
if ( (vc[7] & vc[6]) | vc[8] | hc[8])
Border_n <= 0;
else
Border_n <= 1;
end
// VidEN generation (delaying Border 8 clocks)
reg VidEN_n = 1;
always @(negedge clk7) begin
if (hc[3])
VidEN_n <= !Border_n;
end
// DataLatch generation (posedge to capture data from memory)
reg DataLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & hc[1] & Border_n & hc[3])
DataLatch_n <= 0;
else
DataLatch_n <= 1;
end
// AttrLatch generation (posedge to capture data from memory)
reg AttrLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & !hc[1] & Border_n & hc[3])
AttrLatch_n <= 0;
else
AttrLatch_n <= 1;
end
 
// SLoad generation (negedge to load shift register)
reg SLoad = 0;
always @(negedge clk7) begin
if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
SLoad <= 1;
else
SLoad <= 0;
end
// AOLatch generation (negedge to update attr output latch)
reg AOLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & !hc[1] & hc[2])
AOLatch_n <= 0;
else
AOLatch_n <= 1;
end
 
// First buffer for bitmap
reg [7:0] BitmapReg = 0;
always @(negedge DataLatch_n) begin
BitmapReg <= vramdout;
end
// Shift register (second bitmap register)
reg [7:0] SRegister = 0;
always @(negedge clk7) begin
if (SLoad)
SRegister <= BitmapReg;
else
SRegister <= {SRegister[6:0],1'b0};
end
 
// First buffer for attribute
reg [7:0] AttrReg = 0;
always @(negedge AttrLatch_n) begin
AttrReg <= vramdout;
end
// Second buffer for attribute
reg [7:0] AttrOut = 0;
always @(negedge AOLatch_n) begin
if (!VidEN_n)
AttrOut <= AttrReg;
else
AttrOut <= {2'b00,BorderColor,BorderColor};
end
 
// Flash counter and pixel generation
reg [4:0] FlashCnt = 0;
always @(negedge VSync_n) begin
FlashCnt <= FlashCnt + 1;
end
wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
 
// RGB generation
reg rI,rG,rR,rB;
assign r = rR;
assign g = rG;
assign b = rB;
assign i = rI;
always @(*) begin
if (HBlank_n && VBlank_n)
{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
else
{rI,rG,rR,rB} = 4'b0000;
end
//CSync generation
assign csync = HSync_n & VSync_n;
// VRAM address and control line generation
reg [13:0] rVA = 0;
reg rVCS = 0;
reg rVOE = 0;
reg rVWE = 0;
assign va = rVA;
assign vramcs = rVCS;
assign vramoe = rVOE;
assign vramwe = rVWE;
// Latches to hold delayed versions of V and H counters
reg [8:0] v = 0;
reg [8:0] c = 0;
// Address and control line multiplexor ULA/CPU
always @(negedge clk7) begin
if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
c <= hc;
v <= vc;
end
end
// Address and control line multiplexor ULA/CPU
always @(*) begin
if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present attribute address to VRAM
rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte).
{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected
rVCS = 1;
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present display address to VRAM
rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte)
rVCS = 1;
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && hc[3:0]==4'b0000) begin
rVA = a[13:0];
rVCS = 0;
rVOE = 0;
rVWE = 0;
end
else begin // when VRAM is not in use by ULA, give it to CPU
rVA = a[13:0];
rVCS = !a[15] & a[14] & !mreq_n;
rVOE = !rd_n;
rVWE = !wr_n;
end
end
 
// ULA+ : palette RAM address and control bus multiplexing
always @(*) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
palettewe = 0;
paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
end
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15)) begin // present address of ink to palette RAM
palettewe = 0;
paletteaddr = { AttrReg[7:6],1'b0,AttrReg[2:0] };
end
else if (dataportsel) begin // if CPU requests access, give it palette control
paletteaddr = ULAPlusAddrReg[5:0];
palettewe = cpu_writes_palette;
end
else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
end
end
//ULA+ : palette reading and attribute generation
// First buffers for paper and ink
reg [7:0] ULAPlusPaper = 0;
reg [7:0] ULAPlusInk = 0;
reg [7:0] ULAPlusBorder = 0;
wire ULAPlusPixel = SRegister[7];
always @(negedge clk14) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusPaper <= palettedout;
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusInk <= palettedout;
else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
// Second buffers for paper and ink
reg [7:0] ULAPlusPaperOut = 0;
reg [7:0] ULAPlusInkOut = 0;
always @(negedge AOLatch_n) begin
if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
ULAPlusPaperOut <= ULAPlusPaper;
ULAPlusInkOut <= ULAPlusInk;
end
else begin // if not, it's "border/blanking time", so load output buffers with current border color
ULAPlusPaperOut <= ULAPlusBorder;
ULAPlusInkOut <= ULAPlusBorder;
end
end
// ULA+ : final RGB generation depending on pixel value and blanking period.
reg [7:0] rRGBULAPlus;
assign rgbulaplus = rRGBULAPlus;
always @(*) begin
if (HBlank_n && VBlank_n)
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
else
rRGBULAPlus = 8'h00;
end
// CPU contention
reg CPUClk = 0;
assign clkcpu = CPUClk;
reg ioreqtw3 = 0;
reg mreqt23 = 0;
wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
wire Nor1 = (~(a[14] | ~ioreq_n)) |
(~(~a[15] | ~ioreq_n)) |
(~(hc[2] | hc[3])) |
(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
wire Nor2 = (~(hc[2] | hc[3])) |
~Border_n |
~CPUClk |
ioreq_n |
~ioreqtw3;
wire CLKContention = ~Nor1 | ~Nor2;
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
CPUClk <= 0;
else
CPUClk <= 1;
end
always @(posedge CPUClk) begin
ioreqtw3 <= ioreq_n;
mreqt23 <= mreq_n;
end
// ULA+ : palette management
always @(posedge clk7 or posedge reset) begin
if (reset)
ULAPlusConfig <= 0;
else begin
if (addrportsel && !wr_n)
ULAPlusAddrReg <= din;
else if (dataportsel && !wr_n && ULAPlusAddrReg[7:6]==2'b01)
ULAPlusConfig <= din[0];
end
end
 
// ULA-CPU interface
assign dout = (!a[15] && a[14] && !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
(!iorq_n && !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
(Border_n)? AttrReg : // to emulate
8'hFF; // port FF (well, cannot be actually FF anymore)
assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
a[9]? 1'bz : 1'b0, // there's no need to do this.
a[12]? 1'bz : 1'b0,
a[13]? 1'bz : 1'b0,
a[8]? 1'bz : 1'b0,
a[14]? 1'bz : 1'b0,
a[15]? 1'bz : 1'b0 };
reg rMic = 0;
reg rSpk = 0;
assign mic = rMic;
assign spk = rSpk;
always @(negedge clk7 or posedge reset) begin
if (reset)
TimexHiColorMode <= 0;
else if (!iorq_n && a[7:0]==8'hFF && !wr_n)
TimexHiColorMode <= din[1];
else if (!iorq_n & !a[0] & !wr_n)
{rSpk,rMic,BorderColor} <= din[5:0];
end
endmodule
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/cpu.v
0,0 → 1,179
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:50:27 05/02/2012
// Design Name:
// Module Name: cpu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module z80memr (
input clk,
output [15:0] a,
output [7:0] d,
output mreq,
output rd
);
reg rmreq = 1;
reg rrd = 1;
assign mreq = rmreq;
assign rd = rrd;
reg [1:0] estado = 2;
assign d = 8'bzzzzzzzz;
 
reg [15:0] ra = 16'h7FFF;
assign a = ra;
 
always @(posedge clk) begin
if (estado==2) begin
estado <= 0;
ra <= ~ra;
end
else
estado <= estado + 1;
end
 
always @(*) begin
if (estado==0 && clk)
{rmreq,rrd} = 2'b11;
else if (estado==0 && !clk)
{rmreq,rrd} = 2'b00;
else if (estado==1)
{rmreq,rrd} = 2'b00;
else if (estado==2 && clk)
{rmreq,rrd} = 2'b00;
else
{rmreq,rrd} = 2'b11;
end
endmodule
 
 
module z80memio (
input clk,
output [15:0] a,
output [7:0] d,
output mreq_n,
output iorq_n,
output wr_n,
output rfsh_n
);
reg rmreq = 1;
reg riorq = 1;
reg rwr = 1;
reg rrfsh = 1;
assign mreq_n = rmreq;
assign iorq_n = riorq;
assign wr_n = rwr;
assign rfsh_n = rrfsh;
reg [1:0] estado = 0;
reg [5:0] memioseq = 6'b011001;
reg [5:0] io2seq = 5'b011000;
reg [4:0] hiloseq = 5'b01010;
wire memio = memioseq[0]; // 0 = mem, 1 = io
wire hilo = hiloseq[0]; // 0 = access to lower RAM/Port FEh
wire iohi = io2seq[0]; // 0 = port 00FF/00FE, 1 = port 40FE,40FF
 
reg [15:0] ra;
assign a = ra;
reg [7:0] rd;
assign d = rd;
reg [7:0] iodata = 0;
reg [7:0] memdata = 0;
reg [15:0] memaddr = 16384;
 
always @(posedge clk) begin
if (estado==2 && !memio) begin
estado <= 0;
memioseq <= { memioseq[0], memioseq[5:1] };
hiloseq <= { hiloseq[0], hiloseq[4:1] };
io2seq <= { io2seq[0], io2seq[5:1] };
memdata <= memdata + 1;
if (memaddr == 23295)
memaddr <= 16384;
else
memaddr <= memaddr + 1;
end
else if (estado==3 && memio) begin
estado <= 0;
memioseq <= { memioseq[0], memioseq[5:1] };
hiloseq <= { hiloseq[0], hiloseq[4:1] };
io2seq <= { io2seq[0], io2seq[5:1] };
iodata <= iodata + 1;
end
else
estado <= estado + 1;
end
 
always @(*) begin
if (memio) begin // if this is an I/O bus cycle...
case ({estado,clk})
3'b001 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = 8'bzzzzzzzz;
end
3'b000 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
3'b011,3'b010,3'b101,3'b100,3'b111 :
begin
{rmreq,riorq,rwr} = 3'b100;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
3'b110 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {1'b0, iohi, 13'b0000001111111, hilo};
rd = iodata;
end
endcase
end
else begin // this is a MEM bus cycle
case ({estado,clk})
3'b001 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {hilo,memaddr[14:0]};
rd = 8'bzzzzzzzz;
end
3'b000,3'b011 :
begin
{rmreq,riorq,rwr} = 3'b011;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
3'b010,3'b101 :
begin
{rmreq,riorq,rwr} = 3'b010;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
3'b100 : begin
{rmreq,riorq,rwr} = 3'b111;
ra = {hilo,memaddr[14:0]};
rd = memdata;
end
endcase
end
end
endmodule
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/isim_test_for_ula.gise
0,0 → 1,28
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<!-- -->
 
<!-- For tool use only. Do not edit. -->
 
<!-- -->
 
<!-- ProjectNavigator created generated project file. -->
 
<!-- For use in tracking generated file and other information -->
 
<!-- allowing preservation of process status. -->
 
<!-- -->
 
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
 
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="isim_test_for_ula.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema"/>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
 
</generated_project>
/zx_ula/trunk/fpga_version/ula_test_for_ise_and_isim/isim_test_for_ula.xise
0,0 → 1,364
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="test_ula.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
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</file>
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<association xil_pn:name="Implementation"/>
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<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
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</files>
 
<properties>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_ulaplus" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="128us" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test_ulaplus" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|test_ulaplus" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="isim_test_for_ula" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-02T16:12:41" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F1BB10A56BB44DE3895223E6C8C9F491" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>

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