URL
https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
Subversion Repositories zx_ula
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- This comparison shows the changes necessary to convert path
/
- from Rev 23 to Rev 24
- ↔ Reverse comparison
Rev 23 → Rev 24
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/zx_spectrum_48k.xise
34,11 → 34,6
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
</file> |
<file xil_pn:name="tv80_alu.v" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="tv80_core.v" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="tv80_mcode.v" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="tv80_reg.v" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="tv80n.v" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="ula.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation"/> |
<association xil_pn:name="Implementation"/> |
259,7 → 254,7
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/T80.vhd
88,7 → 88,7
entity T80 is |
generic( |
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB |
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle |
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle |
Flag_C : integer := 0; |
Flag_N : integer := 1; |
Flag_P : integer := 2; |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/T80_MCode.vhd
1876,11 → 1876,11
end case; |
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => |
-- IN r,(C) |
MCycles <= "010"; |
MCycles <= "011"; -- Should be 3 MCycles (mcleod_ideafix) |
case to_integer(unsigned(MCycle)) is |
when 1 => |
when 2 => |
Set_Addr_To <= aBC; |
when 2 => |
when 3 => |
TStates <= "100"; -- MIKEJ should be 4 for IO cycle |
IORQ <= '1'; |
if IR(5 downto 3) /= "110" then |
1893,15 → 1893,15
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => |
-- OUT (C),r |
-- OUT (C),0 |
MCycles <= "010"; |
MCycles <= "011"; -- Should be 3 MCycles (mcleod_ideafix) |
case to_integer(unsigned(MCycle)) is |
when 1 => |
when 2 => |
Set_Addr_To <= aBC; |
Set_BusB_To(2 downto 0) <= IR(5 downto 3); |
if IR(5 downto 3) = "110" then |
Set_BusB_To(3) <= '1'; |
end if; |
when 2 => |
when 3 => |
TStates <= "100"; -- MIKEJ should be 4 for IO cycle |
Write <= '1'; |
IORQ <= '1'; |
1969,7 → 1969,7
I_BTR <= '1'; |
when 4 => |
NoRead <= '1'; |
TStates <= "101"; |
TStates <= "100"; -- Was "101", to make OUTI to last 16 t-cycles (mcleod_ideafix) |
when others => null; |
end case; |
end case; |
/zx_ula/branches/xilinx/spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/bitstreams/spartan3-1000_sp48k.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream