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/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$9;x5>6339$;8<5>4:31*14<9=20=;)gC1:36>7_928=7?>!0121?7333:$9<<5;2:735>103HXHDZGU169BVR\XGGFRSNO\C@FJJBYDDB;37L\XZ^MMH\YDDBCESHV[ESLBH43<I[]QSB@CY^AOOLHX^HF^I<l4ASUY[JHKQVNHAR]XIUAKMKAXKEA:<6O]W[]LJI_XLMXTO=??;@PT^ZIIDPUOH_QL1038EWQ]WFDGURJKR^AOO40<I[]QSB@CY^FGVZ@KAYLGC]?:;@PT^ZIIDPUMNRKWTDPMEI753HX\VRAALX]JJVRXF\Gn7L\XZ^MMH\YWEJN:96O]W[]LJI_XZLYNXRB@GHA2<>GU_SUDBAWPV@NJ@ZBA[VGDHHo4ARQLGZQN\Al0MZTPCMIAQCR^XL;::6OXZ^AOOGSA\PZN=R@@EEKW56=F_SUH@FQ@UURVPZR^XLi0MZTPFMMTP\VB02K\VR^NRUf8ER\X[PD_DYA@L59AKQN33K_MKlo4C;^_@jereld-oad!QfpqoiozVyci|fgth_Ilu'lfi~ah`{or^lt`hdg{oxPwvPumc_fwgikaoxPugcioz_qigwd|yT~h~cabgnakr*}ymymikPfnp\wu71%=2`Pzc_tnbtistT`zhckPdhp_*Ykf{}oySxbn_bnlgn(i~>0OAE?8:AOO5YE]Oo0OAE?_CWECZOI[]20OAE?_NWW2>EKC82;:6MCK3531>EKC;R37NBD2Y3;40=DDB3;96MCKET`?FJLL_UOE[GKE49@HN@E02IGGKLPIO78GIMAP11H@FHW192:?FJLNQUIYKh4CMIE\ZDRNNUBB^Zl;BNHB]YCA_COIh5LLJD[[HSK\@ZGU45LLJD[[JSS=2IGGD@>1:AOOLHXL@\BHHQMY^0a?FJLAGUBNXHH119@HNOIW@H^JJQFNRVe?FJLAGUBNXHH_NWW<>EKC@DTECm4CMIJJZVBZ@EOi6MCKHL\WWEX\PZN=?5LLJMVPZVOIZOT_EGITb9@HNYAMLNIMNE6;BMNILRSMM=0O_KNTDF5?AEJWZZi7IMB_RR\MKUSl2NN_FKX_@FIQVR6:2NM_RH]EPWFJF_XEFNNm6JCL^CM@Z@_9;1O@AQIRDSVAKE^WDEOI85KSRGM50=C]]STOTMCE^ALVWCD\@EE;6JPV@NVA==BP]OYBLBn;GC@PJT^WCL>7KOCSD;8BGYTG\XHIn5IEDFAEFMXJ\L27KGA_TLJPV><NF__S^Z]a:DLQQYRF@^Xm6H@UU]UEISB92C>7DLZFF:8MKRBZGKG=<5EIUVFVZOIX\^TXT^Jc:HJPQCUWYA9\Fm4JHVWAWYQIE_N:6B@AEGG2>JHKBOO?6B@W29NL_1<EV\J@XK8;OGWSJTL<2DDBH?4O99LBABUKYOi7]FNSD]PLL@S12ZBBEO\BTQb?UOIAZMEHHJ7;QKMSLBS@11[^DC[YQG24>VUGYU[ECG\ABVJR@3<XZIGG;5_SEMMA1=W[LD37]]FNBFFG6=U[]h0_DIJXUGQJDJ13ZCEKAKl;RVBVQSWW^KBX;5\T@VVW44<[PY_I@Q\YOAKVJHH]Z90XB^;;UPVA==R[LUIYKI6;TQF[GSAOZ?0ZDKX1c9[ERYQM[YBCC?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED=4XRV5?]beW@n:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n49X4?6Z=2Q;6:S;;`pt~6=ckd=0zh|flnea?scu{`ee,< ?f:z`7v778l'>z|??0|BCt61<HIr997H54;3xW13=0=03;7?<3176`?40llnpb5>51:l;5?0<,>l1;i5rS569<1<??3;8?=;:d;0;5<6<[<o149477;307532l383>8>4S569<1<??3;8?=;:d;0;6cg<l1>1<7?51zQ71?>321=1=>=?54f962bbl2|_;o4?:082>=}T<<038768:010403c2;=oii5m7683>5<321q/i76:;%03>=0<,;;1455+2384a>"0k390n9950;30>5<7s-<i6984$g81b>"683=87)?=:348 45=:?1/=94=a:&21?413-;=6;84$05936=#91097)?6:768 4g==81/=o4=3:&77?0<,::1;6*<7;;8 6>=l2.8n7;>;%63>==#<80?j6*;2;47?!2?2><0(9k52:&7=?073->i6;>4$5f93==#=90>7);=:4c8 02=>81/9;491:&63?2<,<h1985+638a?!00291/;94:1:&4=?1f3-;:6n5+1g87e>"2l3;0(8m5a:k0e?6=,?k14?5+6b84<>=n;80;6)8n:908 3e=?110e:?50;&5e?>53-<26:64;h4e>5<#>h03>6*99;5;?>o083:1(;o5839'2<<0021b:i4?:%4b>=4<,?31;554i5a94?"1i3297)86:6:8?j41290/:l472:&5g?1?3-;o6?:4$0g916=<g;o1<7*9a;:1?>i5i3:1(;o58398k7d=83.=m76=;:m1b?6=,?k14?54o3a94?"1i32976a=d;29 3g=0;10c>=50;&5e?>53-<h6:64$0f961=<g:>1<7*9a;:1?>i0=3:1(;o5829'2=<0021d9k4?:%4b>=4<3f<n6=4+6`8;6>=zj:n1<7<50;2x 3d==01b954?:%4b>=4<,?i1;554o7794?"1i3297)8l:6:8?xd503:1>7>50z&5f?433`?36=4+6`8;6>"1k3=376a95;29 3g=0;1/:n488:9~f60=8381<7>t$7`961=n=10;6)8n:908 3e=?110c;;50;&5e?>53-<h6:64;|q0g?6=:r7?;7=n;<1g>33<,8i1?h5rs2094?4|5==1?<5229851>"6k3827p}=7;296~;3?38=70<7:4:8yv522909w0:8:218960==11v>h50;3x96b==11/;?4:8:p7<<728q6?;495:&46?023ty8i7>50z&46?023ty957>50z&46?023twe>:4?:0y~j7>=83;pqc<6:182xh5i3:1=vsa2c83>4}zf;i1<7?t}o0g>5<6std9i7>51z~yxFGKr9<6;m737577xFGJr:vLM^t}AB
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock_flist.txt
0,0 → 1,4
# Output products list for <master_ula_clock>
master_ula_clock_flist.txt
master_ula_clock_readme.txt
master_ula_clock_xmdf.tcl
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock_arwz.ucf
0,0 → 1,17
# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 25;
INST DCM_SP_INST CLKFX_MULTIPLY = 14;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 20.000;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock_xmdf.tcl
0,0 → 1,48
# The package naming convention is <core_name>_xmdf
package provide master_ula_clock_xmdf 1.0
 
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
 
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::master_ula_clock_xmdf {
# Use this to define any statics
}
 
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::master_ula_clock_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name master_ula_clock
}
# ::master_ula_clock_xmdf::xmdfInit
 
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::master_ula_clock_xmdf::xmdfApplyParams { instance } {
 
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
 
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path master_ula_clock_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
 
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module master_ula_clock
incr fcount
 
}
 
# ::gen_comp_name_xmdf::xmdfApplyParams
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/xaw2verilog.log
0,0 → 1,48
xaw2verilog: Completed successfully
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.v
0,0 → 1,75
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_ula_clock.v
// /___/ /\ Timestamp : 09/25/2012 18:42:40
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st C:\\Documents and Settings\rodriguj\Mis documentos\opencores\zx_ula\branches\xilinx\ulaplus_replacement-upgrade_for_sp16-48k\rtl_ulaplus\ipcore_dir\.\master_ula_clock.xaw C:\\Documents and Settings\rodriguj\Mis documentos\opencores\zx_ula\branches\xilinx\ulaplus_replacement-upgrade_for_sp16-48k\rtl_ulaplus\ipcore_dir\.\master_ula_clock
//Design Name: master_ula_clock
//Device: xc3s100e-5vq100
//
// Module master_ula_clock
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.92 ns
`timescale 1ns / 1ps
 
module master_ula_clock(CLKIN_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
 
input CLKIN_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/audio_management.v
0,0 → 1,81
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:04:00 04/01/2012
// Design Name:
// Module Name: sigma_delta_dac
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
`define MSBI 7 // Most significant Bit of DAC input
 
//This is a Delta-Sigma Digital to Analog Converter
module dac (DACout, DACin, Clk, Reset_n);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset_n;
 
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
 
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(!Reset_n)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
 
module mixer (
input clkdac,
input reset_n,
input ear,
input mic,
input spk,
output audio
);
reg [7:0] mix = 0;
always @(posedge clkdac)
mix <= ({ear,spk,mic}==3'b000)? 17 :
({ear,spk,mic}==3'b001)? 36 :
({ear,spk,mic}==3'b010)? 184 :
({ear,spk,mic}==3'b011)? 192 :
({ear,spk,mic}==3'b100)? 22 :
({ear,spk,mic}==3'b101)? 48 :
({ear,spk,mic}==3'b110)? 244 : 255;
 
dac audio_dac (
.DACout(audio),
.DACin(mix),
.Clk(clkdac),
.Reset_n(reset_n)
);
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ram64bytes.v
0,0 → 1,36
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:57:11 04/29/2012
// Design Name:
// Module Name: ram64bytes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ram64bytes(
input clk,
input [5:0] a,
input [7:0] din,
output [7:0] dout,
input we
);
reg [7:0] mem[0:63];
assign dout = mem[a]; //non registered address. Ugly, but works :(
always @(posedge clk) begin
if (we)
mem[a] <= din;
end
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/rgb_builder.v
0,0 → 1,72
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:10:16 04/04/2012
// Design Name:
// Module Name: rgb_builder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rgb_builder(
input reset,
input select, // 0=ULA, 1=ULA+
input ri, //
input gi, // digital IRGB
input bi, // inputs from standar ULA
input hi, //
input [7:0] rgbulap, // 8-bit input from ULA+
output reg [2:0] r, //
output reg [2:0] g, // 3-bit final RGB signals
output reg [2:0] b //
);
 
always @(*) begin
if (!select) begin
case ({hi,ri})
2'b00 : r = 3'b000;
2'b01 : r = 3'b101;
2'b10 : r = 3'b000;
2'b11 : r = 3'b111;
endcase
end
else
r = rgbulap[4:2];
end
always @(*) begin
if (!select) begin
case ({hi,gi})
2'b00 : g = 3'b000;
2'b01 : g = 3'b101;
2'b10 : g = 3'b000;
2'b11 : g = 3'b111;
endcase
end
else
g = rgbulap[7:5];
end
always @(*) begin
if (!select) begin
case ({hi,bi})
2'b00 : b = 3'b000;
2'b01 : b = 3'b101;
2'b10 : b = 3'b000;
2'b11 : b = 3'b111;
endcase
end
else
b = {rgbulap[1:0],rgbulap[1]};
end
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ula.v
0,0 → 1,462
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Dept. Architecture and Computing Technology. University of Seville
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
//
// Create Date: 19:13:39 4-Apr-2012
// Design Name: ZX Spectrum
// Module Name: ula
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.00 - File Created
// Additional Comments: GPL License policies apply to the contents of this file.
//
//////////////////////////////////////////////////////////////////////////////////
 
`define cyclestart(a,b) ((a)==(b))
`define cycleend(a,b) ((a)==(b+1))
 
module ula(
input clk14, // 14MHz master clock
input reset_n, // to reset the ULA to normal color mode.
// CPU interfacing
input [15:0] a, // Address bus from CPU (not all lines are used)
input [7:0] din, // Input data bus from CPU
output [7:0] dout, // Output data bus to CPU
input mreq_n, // MREQ from CPU
input ioreq_n, // IORQ+A0 from main board
input iorq_n, // IORQ from CPU
input rd_n, // RD from CPU
input wr_n, // WR from CPU
output clkcpu, // CLK to CPU
output msk_int_n, // Vertical retrace interrupt, to CPU
// VRAM interfacing
output [13:0] va, // Address bus to VRAM (16K)
input [7:0] vramdout,// Data from VRAM to ULA/CPU
output [7:0] vramdin,// Data from CPU to VRAM
output vramoe, //
output vramcs, // Control signals for VRAM
output vramwe, //
// ULA I/O
input ear, //
output mic, // I/O ports
output spk, //
input [4:0] kbcolumns, // Keyboard columns
// Video output
output r, //
output g, // RGB TTL signal
output b, // with separate bright
output i, // and composite sync
output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
output csync //
);
 
reg [2:0] BorderColor = 3'b100;
reg TimexHiColorMode = 0;
reg ULAPlusConfig = 0; // bit 0 of reg.64
reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
assign ulaplus_enabled = ULAPlusConfig;
wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
reg [5:0] paletteaddr; // address bus of palette RAM
wire [7:0] palettedout; // data out port of palette RAM
reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
 
ram64bytes palette (
.clk(clk14), // only for write operations. Read operations are asynchronous
.a(paletteaddr),
.din(din),
.dout(palettedout),
.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
);
 
// Pixel clock
reg clk7 = 0;
always @(posedge clk14)
clk7 <= !clk7;
// Horizontal counter
reg [8:0] hc = 0;
always @(posedge clk7) begin
if (hc==447)
hc <= 0;
else
hc <= hc + 1;
end
// Vertical counter
reg [8:0] vc = 0;
always @(posedge clk7) begin
if (hc==447) begin
if (vc == 311)
vc <= 0;
else
vc <= vc + 1;
end
end
// HBlank generation
reg HBlank_n = 1;
always @(negedge clk7) begin
if (`cyclestart(hc,320))
HBlank_n <= 0;
else if (`cycleend(hc,415))
HBlank_n <= 1;
end
 
// HSync generation (6C ULA version)
reg HSync_n = 1;
always @(negedge clk7) begin
if (`cyclestart(hc,344))
HSync_n <= 0;
else if (`cycleend(hc,375))
HSync_n <= 1;
end
 
// VBlank generation
reg VBlank_n = 1;
always @(negedge clk7) begin
if (`cyclestart(vc,248))
VBlank_n <= 0;
else if (`cycleend(vc,255))
VBlank_n <= 1;
end
// VSync generation (PAL)
reg VSync_n = 1;
always @(negedge clk7) begin
if (`cyclestart(vc,248))
VSync_n <= 0;
else if (`cycleend(vc,251))
VSync_n <= 1;
end
// INT generation
reg INT_n = 1;
assign msk_int_n = INT_n;
always @(negedge clk7) begin
if (`cyclestart(vc,248) && `cyclestart(hc,0))
INT_n <= 0;
else if (`cyclestart(vc,248) && `cycleend(hc,31))
INT_n <= 1;
end
 
// Border control signal (=0 when we're not displaying paper/ink pixels)
reg Border_n = 1;
always @(negedge clk7) begin
if ( (vc[7] & vc[6]) | vc[8] | hc[8])
Border_n <= 0;
else
Border_n <= 1;
end
// VidEN generation (delaying Border 8 clocks)
reg VidEN_n = 1;
always @(negedge clk7) begin
if (hc[3])
VidEN_n <= !Border_n;
end
// DataLatch generation (posedge to capture data from memory)
reg DataLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & hc[1] & Border_n & hc[3])
DataLatch_n <= 0;
else
DataLatch_n <= 1;
end
// AttrLatch generation (posedge to capture data from memory)
reg AttrLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & !hc[1] & Border_n & hc[3])
AttrLatch_n <= 0;
else
AttrLatch_n <= 1;
end
 
// SLoad generation (negedge to load shift register)
reg SLoad = 0;
always @(negedge clk7) begin
if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
SLoad <= 1;
else
SLoad <= 0;
end
// AOLatch generation (negedge to update attr output latch)
reg AOLatch_n = 1;
always @(negedge clk7) begin
if (hc[0] & !hc[1] & hc[2])
AOLatch_n <= 0;
else
AOLatch_n <= 1;
end
 
// First buffer for bitmap
reg [7:0] BitmapReg = 0;
always @(negedge DataLatch_n) begin
BitmapReg <= vramdout;
end
// Shift register (second bitmap register)
reg [7:0] SRegister = 0;
always @(negedge clk7) begin
if (SLoad)
SRegister <= BitmapReg;
else
SRegister <= {SRegister[6:0],1'b0};
end
 
// First buffer for attribute
reg [7:0] AttrReg = 0;
always @(negedge AttrLatch_n) begin
AttrReg <= vramdout;
end
// Second buffer for attribute
reg [7:0] AttrOut = 0;
always @(negedge AOLatch_n) begin
if (!VidEN_n)
AttrOut <= AttrReg;
else
AttrOut <= {2'b00,BorderColor,BorderColor};
end
 
// Flash counter and pixel generation
reg [4:0] FlashCnt = 0;
always @(negedge VSync_n) begin
FlashCnt <= FlashCnt + 1;
end
wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
 
// RGB generation
reg rI,rG,rR,rB;
assign r = rR;
assign g = rG;
assign b = rB;
assign i = rI;
always @(*) begin
if (HBlank_n && VBlank_n)
{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
else
{rI,rG,rR,rB} = 4'b0000;
end
//CSync generation
assign csync = HSync_n & VSync_n;
// VRAM address and control line generation
reg [13:0] rVA = 0;
reg rVCS = 0;
reg rVOE = 0;
reg rVWE = 0;
assign va = rVA;
assign vramcs = rVCS;
assign vramoe = rVOE;
assign vramwe = rVWE;
// Latches to hold delayed versions of V and H counters
reg [8:0] v = 0;
reg [8:0] c = 0;
// Address and control line multiplexor ULA/CPU
always @(negedge clk7) begin
if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
c <= hc;
v <= vc;
end
end
// Address and control line multiplexor ULA/CPU
always @(*) begin
if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present attribute address to VRAM
rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte).
{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected
rVCS = 1;
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present display address to VRAM
rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte)
rVCS = 1;
rVOE = !hc[0];
rVWE = 0;
end
else if (Border_n && hc[3:0]==4'b0000) begin
rVA = a[13:0];
rVCS = 0;
rVOE = 0;
rVWE = 0;
end
else begin // when VRAM is not in use by ULA, give it to CPU
rVA = a[13:0];
rVCS = !a[15] & a[14] & !mreq_n;
rVOE = !rd_n;
rVWE = !wr_n;
end
end
 
// ULA+ : palette RAM address and control bus multiplexing
always @(*) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
palettewe = 0;
paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
end
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15)) begin // present address of ink to palette RAM
palettewe = 0;
paletteaddr = { AttrReg[7:6],1'b0,AttrReg[2:0] };
end
else if (dataportsel) begin // if CPU requests access, give it palette control
paletteaddr = ULAPlusAddrReg[5:0];
palettewe = cpu_writes_palette;
end
else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
end
end
//ULA+ : palette reading and attribute generation
// First buffers for paper and ink
reg [7:0] ULAPlusPaper = 0;
reg [7:0] ULAPlusInk = 0;
reg [7:0] ULAPlusBorder = 0;
wire ULAPlusPixel = SRegister[7];
always @(negedge clk14) begin
if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusPaper <= palettedout;
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
ULAPlusInk <= palettedout;
else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
// Second buffers for paper and ink
reg [7:0] ULAPlusPaperOut = 0;
reg [7:0] ULAPlusInkOut = 0;
always @(negedge AOLatch_n) begin
if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
ULAPlusPaperOut <= ULAPlusPaper;
ULAPlusInkOut <= ULAPlusInk;
end
else begin // if not, it's "border/blanking time", so load output buffers with current border color
ULAPlusPaperOut <= ULAPlusBorder;
ULAPlusInkOut <= ULAPlusBorder;
end
end
// ULA+ : final RGB generation depending on pixel value and blanking period.
reg [7:0] rRGBULAPlus;
assign rgbulaplus = rRGBULAPlus;
always @(*) begin
if (HBlank_n && VBlank_n)
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
else
rRGBULAPlus = 8'h00;
end
// CPU contention handler (Altwasser version)
/////////////////////////////////////////////////////////////////////
reg CPUClk = 0;
assign clkcpu = !CPUClk; // will be negated again off ULA
reg ioreqtw3 = 0;
reg mreqt23 = 0;
wire iorequest_n = ioreq_n & ~dataportsel & ~addrportsel;
wire Nor1 = (~(a[14] | ~iorequest_n)) |
(~(~a[15] | ~iorequest_n)) |
(~(hc[2] | hc[3])) |
(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
wire Nor2 = (~(hc[2] | hc[3])) |
~Border_n |
~CPUClk |
iorequest_n |
~ioreqtw3;
wire CLKContention = ~Nor1 | ~Nor2;
 
always @(posedge CPUClk) begin
ioreqtw3 <= iorequest_n;
mreqt23 <= mreq_n;
end
/////////////////////////////////////////////////////////////////////
 
// // CPU contention handler (Chris version)
// /////////////////////////////////////////////////////////////////////
// reg CPUClk = 0;
// assign clkcpu = CPUClk;
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
// reg ULANotReadingVRAM = 1;
// reg CycleMayContend = 0;
//
// always @(negedge clk7) begin
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
// end
// always @(posedge CPUClk) begin
// CycleMayContend <= ioreq_n & mreq_n;
// end
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & ioreq_n) | ~CycleMayContend));
// /////////////////////////////////////////////////////////////////////
 
// // CPU modified contention handler for broken IO bus cycle of T80 core (Chris version)
// /////////////////////////////////////////////////////////////////////
// reg CPUClk = 0;
// assign clkcpu = CPUClk;
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
// reg ULANotReadingVRAM = 1;
// reg CycleMayContend = 0;
//
// always @(negedge clk7) begin
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
// end
// always @(posedge CPUClk) begin
// CycleMayContend <= (ioreq_n | CPUClk) & mreq_n;
// end
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & (ioreq_n | ~CPUClk)) | ~CycleMayContend));
// /////////////////////////////////////////////////////////////////////
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
CPUClk <= 0;
else
CPUClk <= 1;
end
// ULA+ : palette management
always @(posedge clk7 or negedge reset) begin
if (!reset_n)
ULAPlusConfig <= 0;
else begin
if (addrportsel && !wr_n)
ULAPlusAddrReg <= din;
else if (dataportsel && !wr_n && ULAPlusAddrReg[7:6]==2'b01)
ULAPlusConfig <= din[0];
end
end
 
// ULA-CPU interface
assign dout = (!a[15] && a[14] && !mreq_n && !rd_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
(!iorq_n && !a[0] && !rd_n)? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
(Border_n)? AttrReg : // to emulate
8'hFF; // port FF (well, cannot be actually FF anymore)
assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
reg rMic = 0;
reg rSpk = 0;
assign mic = rMic;
assign spk = rSpk;
always @(negedge clk7 or negedge reset) begin
if (!reset_n)
TimexHiColorMode <= 0;
else if (!iorq_n && a[7:0]==8'hFF && !wr_n)
TimexHiColorMode <= din[1];
else if (!ioreq_n & !wr_n)
{rSpk,rMic,BorderColor} <= din[5:0];
end
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/iseconfig/ulaplus_replacement.projectmgr
0,0 → 1,107
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0,0 → 1,217
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<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="!module_name!.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="!module_name!.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="!module_name!.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="!module_name!.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="!module_name!_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="!module_name!.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="!module_name!.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="!module_name!.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="!module_name!.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="!module_name!.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="!module_name!.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/!module_name!_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/!module_name!_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="!module_name!_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="!module_name!_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/!module_name!_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="!module_name!_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="!module_name!.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="!module_name!_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/!module_name!_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="!module_name!_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="!module_name!.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="!module_name!.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/!module_name!_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/master_ula_clock_arwz.ucf
0,0 → 1,17
# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 25;
INST DCM_SP_INST CLKFX_MULTIPLY = 14;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 20.000;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ula_pins.ucf
0,0 → 1,61
# Clock and reset lines
NET "clk50" LOC = "P38" | IOSTANDARD = LVCMOS33;
 
# CPU interface
NET "cpuclk_n" LOC = "P5" | IOSTANDARD = LVCMOS33;
NET "a15" LOC = "P89" | IOSTANDARD = LVCMOS33;
NET "a14" LOC = "P91" | IOSTANDARD = LVCMOS33;
NET "a7" LOC = "P" | IOSTANDARD = LVCMOS33;
NET "a6" LOC = "P" | IOSTANDARD = LVCMOS33;
NET "a2" LOC = "P" | IOSTANDARD = LVCMOS33;
 
NET "ioreq_n" LOC = "P3" | IOSTANDARD = LVCMOS33;
NET "mreq_n" LOC = "P86" | IOSTANDARD = LVCMOS33;
NET "iorq_n" LOC = "P" | IOSTANDARD = LVCMOS33;
NET "rd_n" LOC = "P85" | IOSTANDARD = LVCMOS33;
NET "wr_n" LOC = "P84" | IOSTANDARD = LVCMOS33;
NET "int_n" LOC = "P15" | IOSTANDARD = LVCMOS33;
NET "romcs_n" LOC = "P98" | IOSTANDARD = LVCMOS33;
NET "reset_n" LOC = "P" | IOSTANDARD = LVCMOS33;
 
NET "d<7>" LOC = "P10" | IOSTANDARD = LVCMOS33;
NET "d<6>" LOC = "P12" | IOSTANDARD = LVCMOS33;
NET "d<5>" LOC = "P16" | IOSTANDARD = LVCMOS33;
NET "d<4>" LOC = "P18" | IOSTANDARD = LVCMOS33;
NET "d<3>" LOC = "P23" | IOSTANDARD = LVCMOS33;
NET "d<2>" LOC = "P57" | IOSTANDARD = LVCMOS33;
NET "d<1>" LOC = "P60" | IOSTANDARD = LVCMOS33;
NET "d<0>" LOC = "P49" | IOSTANDARD = LVCMOS33;
 
# DRAM interface
NET "va<6>" LOC = "P11" | IOSTANDARD = LVCMOS33;
NET "va<5>" LOC = "P9" | IOSTANDARD = LVCMOS33;
NET "va<4>" LOC = "P4" | IOSTANDARD = LVCMOS33;
NET "va<3>" LOC = "P2" | IOSTANDARD = LVCMOS33;
NET "va<2>" LOC = "P95" | IOSTANDARD = LVCMOS33;
NET "va<1>" LOC = "P92" | IOSTANDARD = LVCMOS33;
NET "va<0>" LOC = "P90" | IOSTANDARD = LVCMOS33;
NET "ras_n" LOC = "P94" | IOSTANDARD = LVCMOS33;
NET "cas_n" LOC = "P83" | IOSTANDARD = LVCMOS33;
NET "dramwe_n" LOC = "P88" | IOSTANDARD = LVCMOS33;
 
# I/O
NET "audio_out" LOC = "P17" | IOSTANDARD = LVCMOS33;
NET "kbd<0>" LOC = "P54" | IOSTANDARD = LVCMOS33;
NET "kbd<1>" LOC = "P58" | IOSTANDARD = LVCMOS33;
NET "kbd<2>" LOC = "P53" | IOSTANDARD = LVCMOS33;
NET "kbd<3>" LOC = "P48" | IOSTANDARD = LVCMOS33;
NET "kbd<4>" LOC = "P22" | IOSTANDARD = LVCMOS33;
NET "ear" LOC = "P13" | IOSTANDARD = LVCMOS33;
 
# RGB output
NET "r<2>" LOC = "P26" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC = "P27" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC = "P32" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC = "P33" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC = "P34" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC = "P35" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC = "P36" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC = "P40" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC = "P41" | IOSTANDARD = LVCMOS33;
NET "csync" LOC = "P47" | IOSTANDARD = LVCMOS33;
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ulaplus_replacement.gise
0,0 → 1,30
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<!-- -->
 
<!-- For tool use only. Do not edit. -->
 
<!-- -->
 
<!-- ProjectNavigator created generated project file. -->
 
<!-- For use in tracking generated file and other information -->
 
<!-- allowing preservation of process status. -->
 
<!-- -->
 
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
 
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ulaplus_replacement.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_UCF" xil_pn:name="master_ula_clock_arwz.ucf" xil_pn:origination="imported"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
 
</generated_project>
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/master_ula_clock.v
0,0 → 1,75
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_ula_clock.v
// /___/ /\ Timestamp : 09/25/2012 18:42:48
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw -st master_ula_clock.v
//Design Name: master_ula_clock
//Device: xc3s100e-5vq100
//
// Module master_ula_clock
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.92 ns
`timescale 1ns / 1ps
 
module master_ula_clock(CLKIN_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
 
input CLKIN_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ulaplus_replacement.xise
0,0 → 1,348
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="ula_pins.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ulaplus_tld.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="audio_management.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ram64bytes.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ula.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ipcore_dir/master_ula_clock.xaw" xil_pn:type="FILE_XAW">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="rgb_builder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
 
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc3s100e" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Up" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="test1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-09-19T06:30:10" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A19204D9A3C34611BD9DE39FB56BA0F4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/coregen_xil_3244_19.cgp
0,0 → 1,22
# Date: Tue Sep 25 16:31:44 2012
 
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
 
# CRC: e2b133ab
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ulaplus_tld.v
0,0 → 1,134
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Dept. Architecture and Computing Technology. University of Seville
// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
//
// Create Date: 19:13:39 4-Apr-2012
// Design Name: ULAplus replacement
// Module Name: ulaplus_tld
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.00 - File Created
// Additional Comments: GPL License policies apply to the contents of this file.
//
//////////////////////////////////////////////////////////////////////////////////
module ulaplus_tld(
// Clock and reset
input clk50,
input reset,
 
// CPU interface
input a15,
input a14,
input a7,
input a6,
input a2,
input mreq_n,
input ioreq_n,
input iorq_n,
input rd_n,
input wr_n,
inout [7:0] d,
output int_n,
output cpuclk_n,
 
// DRAM interface
output [6:0] va,
output ras_n,
output cas_n,
output dramwe_n,
// ROM interface
output romcs_n,
 
// Keyboard & audio interface
input [4:0] kbd,
output audio_out,
input ear,
 
// RGB video interface
output [2:0] r,
output [2:0] g,
output [2:0] b,
output csync
);
 
wire clk14;
master_ula_clock clock14mhz (
.CLKIN_IN(clk50),
.CLKFX_OUT(clk14),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
 
/////////////////////////////////////
// The ULA
/////////////////////////////////////
wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;
wire mic,spk;
wire [7:0] rgbulaplus;
ula the_ula (
.clk14(clk14),
.reset_n(reset_n),
.a15(a15),
.a14(a14),
.a7(a7),
.a6(a6),
.a2(a2),
.din(uladin),
.dout(uladout),
.mreq_n(mreq_n),
.ioreq_n(ioreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.clkcpu(cpuclk_n),
.int_n(int_n),
.va(va),
.ear(ear),
.mic(mic),
.spk(spk),
.kbd(kbd),
.r(ula_r),
.g(ula_g),
.b(ula_b),
.i(ula_i),
.rgbulaplus(rgbulaplus),
.ulaplus_enabled(ulaplus_enabled),
.csync(csync)
);
 
/////////////////////////////////////
// ULA/ULA+ video selector and enconding
/////////////////////////////////////
rgb_builder video_final_stage (
.select(ulaplus_enabled),
.ri(ula_r),
.gi(ula_g),
.bi(ula_b),
.hi(ula_i),
.rgbulap(rgbulaplus),
.r(r),
.g(g),
.b(b)
);
 
/////////////////////////////////////
// Audio mixer
/////////////////////////////////////
mixer audio_mix (
.clkdac(clk14),
.reset_n(reset_n),
.ear(ear),
.mic(mic),
.spk(spk),
.audio(audio_out)
);
endmodule
/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/coregen_xil_3244_19.cgc
0,0 → 1,40
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>CoreGen</spirit:library>
<spirit:name>coregen_xil_3244_19</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:description></spirit:description>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen_xil_3244_19</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc5vlx20t</xilinx:device>
<xilinx:deviceFamily>virtex5</xilinx:deviceFamily>
<xilinx:package>ff323</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>

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