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https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
Subversion Repositories zx_ula
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/zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/rom.ngc
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Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/bitstreams/spartan3-200_sp48k.bit
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Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/bitstreams/spartan3-200_sp48k.bit
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/bitstreams/spartan3-200_sp48k.bit (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/bitstreams/spartan3-200_sp48k.bit (nonexistent)
zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/bitstreams/spartan3-200_sp48k.bit
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Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise (nonexistent)
@@ -1,373 +0,0 @@
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Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf (nonexistent)
@@ -1,83 +0,0 @@
-NET "clk50" LOC = "T9" | IOSTANDARD = LVCMOS33;
-# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
-# NET "clk50" PERIOD = 20.0ns HIGH 40%;
-
-NET "reset" LOC = "L14" | IOSTANDARD = LVCMOS33;
-
-# I/O
-NET "r" LOC = "E7" | IOSTANDARD = LVCMOS33;
-NET "g" LOC = "D6" | IOSTANDARD = LVCMOS33;
-NET "b" LOC = "D5" | IOSTANDARD = LVCMOS33;
-NET "i" LOC = "D7" | IOSTANDARD = LVCMOS33;
-
-NET "csync" LOC = "D8" | IOSTANDARD = LVCMOS33;
-NET "audio_out" LOC = "D10" | IOSTANDARD = LVCMOS33;
-NET "ear" LOC = "T13" | IOSTANDARD = LVCMOS33;
-
-NET "kbd_rows<0>" LOC = "E6" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<1>" LOC = "C5" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<2>" LOC = "C6" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<3>" LOC = "C7" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<4>" LOC = "C8" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<5>" LOC = "C9" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<6>" LOC = "A3" | IOSTANDARD = LVCMOS33;
-NET "kbd_rows<7>" LOC = "A4" | IOSTANDARD = LVCMOS33;
-
-NET "kbd_columns<0>" LOC = "B4" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "kbd_columns<1>" LOC = "B5" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "kbd_columns<2>" LOC = "B6" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "kbd_columns<3>" LOC = "A7" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "kbd_columns<4>" LOC = "A8" | IOSTANDARD = LVCMOS33 | PULLUP;
-
-# Debug LED's
-NET "leds<7>" LOC = "P11" | IOSTANDARD = LVCMOS33;
-NET "leds<6>" LOC = "P12" | IOSTANDARD = LVCMOS33;
-NET "leds<5>" LOC = "N12" | IOSTANDARD = LVCMOS33;
-NET "leds<4>" LOC = "P13" | IOSTANDARD = LVCMOS33;
-NET "leds<3>" LOC = "N14" | IOSTANDARD = LVCMOS33;
-NET "leds<2>" LOC = "L12" | IOSTANDARD = LVCMOS33;
-NET "leds<1>" LOC = "P14" | IOSTANDARD = LVCMOS33;
-NET "leds<0>" LOC = "K12" | IOSTANDARD = LVCMOS33;
-
-# External SRAM
-NET "sa<17>" LOC = "L3" | IOSTANDARD = LVCMOS33;
-NET "sa<16>" LOC = "K5" | IOSTANDARD = LVCMOS33;
-NET "sa<15>" LOC = "K3" | IOSTANDARD = LVCMOS33;
-NET "sa<14>" LOC = "J3" | IOSTANDARD = LVCMOS33;
-NET "sa<13>" LOC = "J4" | IOSTANDARD = LVCMOS33;
-NET "sa<12>" LOC = "H4" | IOSTANDARD = LVCMOS33;
-NET "sa<11>" LOC = "H3" | IOSTANDARD = LVCMOS33;
-NET "sa<10>" LOC = "G5" | IOSTANDARD = LVCMOS33;
-NET "sa<9>" LOC = "E4" | IOSTANDARD = LVCMOS33;
-NET "sa<8>" LOC = "E3" | IOSTANDARD = LVCMOS33;
-NET "sa<7>" LOC = "F4" | IOSTANDARD = LVCMOS33;
-NET "sa<6>" LOC = "F3" | IOSTANDARD = LVCMOS33;
-NET "sa<5>" LOC = "G4" | IOSTANDARD = LVCMOS33;
-NET "sa<4>" LOC = "L4" | IOSTANDARD = LVCMOS33;
-NET "sa<3>" LOC = "M3" | IOSTANDARD = LVCMOS33;
-NET "sa<2>" LOC = "M4" | IOSTANDARD = LVCMOS33;
-NET "sa<1>" LOC = "N3" | IOSTANDARD = LVCMOS33;
-NET "sa<0>" LOC = "L5" | IOSTANDARD = LVCMOS33;
-
-#NET "sd1<15>" LOC = "R1" | IOSTANDARD = LVCMOS33;
-#NET "sd1<14>" LOC = "P1" | IOSTANDARD = LVCMOS33;
-#NET "sd1<13>" LOC = "L2" | IOSTANDARD = LVCMOS33;
-#NET "sd1<12>" LOC = "J2" | IOSTANDARD = LVCMOS33;
-#NET "sd1<11>" LOC = "H1" | IOSTANDARD = LVCMOS33;
-#NET "sd1<10>" LOC = "F2" | IOSTANDARD = LVCMOS33;
-#NET "sd1<9>" LOC = "P8" | IOSTANDARD = LVCMOS33;
-#NET "sd1<8>" LOC = "D3" | IOSTANDARD = LVCMOS33;
-NET "sd1<7>" LOC = "B1" | IOSTANDARD = LVCMOS33;
-NET "sd1<6>" LOC = "C1" | IOSTANDARD = LVCMOS33;
-NET "sd1<5>" LOC = "C2" | IOSTANDARD = LVCMOS33;
-NET "sd1<4>" LOC = "R5" | IOSTANDARD = LVCMOS33;
-NET "sd1<3>" LOC = "T5" | IOSTANDARD = LVCMOS33;
-NET "sd1<2>" LOC = "R6" | IOSTANDARD = LVCMOS33;
-NET "sd1<1>" LOC = "T8" | IOSTANDARD = LVCMOS33;
-NET "sd1<0>" LOC = "N7" | IOSTANDARD = LVCMOS33;
-
-NET "sramce1" LOC = "P7" | IOSTANDARD = LVCMOS33;
-NET "sramub1" LOC = "T4" | IOSTANDARD = LVCMOS33;
-NET "sramlb1" LOC = "P6" | IOSTANDARD = LVCMOS33;
-NET "sramwe" LOC = "G3" | IOSTANDARD = LVCMOS33;
-NET "sramoe" LOC = "K4" | IOSTANDARD = LVCMOS33;
Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v (nonexistent)
@@ -1,207 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: Dept. Architecture and Computing Technology. University of Seville
-// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
-//
-// Create Date: 19:13:39 4-Apr-2012
-// Design Name: ZX Spectrum
-// Module Name: ram32k
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 1.00 - File Created
-// Additional Comments: GPL License policies apply to the contents of this file.
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-/*
-This module generates a high level on "isfalling" when "a" changes from high to low.
-*/
-module getfedge (
- input clk,
- input a,
- output isfalling
- );
-
- reg sh = 1'b1;
- assign isfalling = sh & ~a;
- always @(posedge clk)
- sh <= a;
-endmodule
-
-
-/*
-This module implements a shared RAM controller. The Spartan 3 Starter Kit has two 256Kx16 SRAM chips.
-It uses half the size of one of these chips (8 bit data bus instead of 16).
-As the ZX Spectrum needs two independent memory banks, and bus cycles may happen to both at the same
-time, it's necessary to emulate those two banks with one chip.
-
-I tried a simple round-robin multiplexing, but didn't work as expected. This module is a bit more complicated
-as it implements a first-come-first-serve approach, with fixed priority scheme when several petitions happen
-at the same time.
-
-Each bank can be up to 64Kx8, so implementing a 128K memory scheme is very easy (I hope so) using this module
-and the external SRAM on board.
-
-This may be my first 100% synchronous implementation for a FPGA (that is, only one clock and all the ff's are
-activated at the same edge)
-
-*/
-module ram_controller (
- input clk,
- // Bank 1 (VRAM)
- input [15:0] a1,
- input cs1_n,
- input oe1_n,
- input we1_n,
- input [7:0] din1,
- output [7:0] dout1,
- // Bank 2 (upper RAM)
- input [15:0] a2,
- input cs2_n,
- input oe2_n,
- input we2_n,
- input [7:0] din2,
- output [7:0] dout2,
- // Outputs to actual SRAM on board
- output [17:0] sa,
- inout [7:0] sd,
- output sramce,
- output sramub,
- output sramlb,
- output sramoe,
- output sramwe
- );
-
- // Permanently enable SRAM and set it to use only LSB
- assign sramub = 1;
- assign sramlb = 0;
- assign sramce = 0;
- assign sramoe = 0;
-
- reg rsramwe = 1;
- assign sramwe = rsramwe;
-
- reg [17:0] rsa;
- reg [7:0] rsd;
- assign sa = rsa;
- assign sd = rsd;
-
- // set when there has been a high to low transition in the corresponding signal
- wire bank1read, bank1write, bank2read, bank2write;
- getfedge detectbank1read (clk, cs1_n | oe1_n, bank1read);
- getfedge detectbank2read (clk, cs2_n | oe2_n, bank2read);
- getfedge detectbank1write (clk, cs1_n | we1_n, bank1write);
- getfedge detectbank2write (clk, cs2_n | we2_n, bank2write);
-
- reg [15:0] ra1;
- reg [15:0] ra2;
- reg [7:0] rdin1;
- reg [7:0] rdin2;
-
- reg [7:0] rdout1;
- assign dout1 = rdout1;
- reg [7:0] rdout2;
- assign dout2 = rdout2;
-
- // ff's to store pending memory requests
- reg pendingreadb1 = 0;
- reg pendingwriteb1 = 0;
- reg pendingreadb2 = 0;
- reg pendingwriteb2 = 0;
-
- // ff's to store current memory requests
- reg reqreadb1 = 0;
- reg reqreadb2 = 0;
- reg reqwriteb1 = 0;
- reg reqwriteb2 = 0;
-
- reg state = 1;
- always @(posedge clk) begin
- // get requests from the two banks
- if (bank1read) begin
- ra1 <= a1;
- pendingreadb1 <= 1;
- pendingwriteb1 <= 0;
- end
- else if (bank1write) begin
- ra1 <= a1;
- rdin1 <= din1;
- pendingwriteb1 <= 1;
- pendingreadb1 <= 0;
- end
- if (bank2read) begin
- ra2 <= a2;
- pendingreadb2 <= 1;
- pendingwriteb2 <= 0;
- end
- else if (bank2write) begin
- ra2 <= a2;
- rdin2 <= din2;
- pendingwriteb2 <= 1;
- pendingreadb2 <= 0;
- end
-
- // reads from bank1 have the higher priority, then writes to bank1,
- // the reads from bank2, then writes from bank2.
- // Reads and writes to bank2 are mutually exclusive, though, as only the CPU
- // performs those operations. So they are with respect to bank1.
- case (state)
- 0 : begin
- if (reqreadb1 || reqwriteb1) begin
- rsa <= {2'b00,ra1}; // operation to bank1 accepted. We put the memory address on the SRAM address bus
- if (reqwriteb1) begin // if this is a write operation...
- pendingwriteb1 <= 0; // accept it, and mark pending operation as cleared
- rsd <= rdin1; // put the data to be written in the SRAM data bus
- rsramwe <= 0; // pulse /WE in SRAM to begin write
- end
- else begin
- pendingreadb1 <= 0; // else, this is a read operation...
- rsd <= 8'bzzzzzzzz; // disconnect the output bus from the data register to the SRAM data bus, so
- rsramwe <= 1; // we can read from the SRAM data bus itself. Deassert /WE to enable data output bus
- end
- state <= 1; // if either request has been accepted, proceed to next phase.
- end
- else if (reqreadb2 || reqwriteb2) begin // do the same with requests to bank 2...
- rsa <= {2'b01,ra2};
- if (reqwriteb2) begin
- pendingwriteb2 <= 0;
- rsd <= rdin2;
- rsramwe <= 0;
- end
- else begin
- pendingreadb2 <= 0;
- rsd <= 8'bzzzzzzzz;
- rsramwe <= 1;
- end
- state <= 1;
- end
- end
- 1 : begin
- if (reqreadb1) begin // for read requests, read the SRAM data bus and store into the corresponding data output register
- rdout1 <= sd;
- end
- else if (reqreadb2) begin
- rdout2 <= sd;
- end
- if (reqwriteb1) begin // for write requests, deassert /WE, as writting has already been happened.
- rsramwe <= 1;
- end
- else if (reqwriteb2) begin
- rsramwe <= 1;
- end
- reqreadb1 <= pendingreadb1; // current request has finished, so update current requests with pending requests to serve the next one
- reqreadb2 <= pendingreadb2;
- reqwriteb1 <= pendingwriteb1;
- reqwriteb2 <= pendingwriteb2;
- if (pendingreadb1 || pendingreadb2 || pendingwriteb1 || pendingwriteb2)
- state <= 0;
- end
- endcase
- end
-endmodule
Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v (nonexistent)
@@ -1,182 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a
-// copy of this software and associated documentation files (the "Software"),
-// to deal in the Software without restriction, including without limitation
-// the rights to use, copy, modify, merge, publish, distribute, sublicense,
-// and/or sell copies of the Software, and to permit persons to whom the
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// Negative-edge based wrapper allows memory wait_n signal to work
-// correctly without resorting to asynchronous logic.
-
-module tv80n (/*AUTOARG*/
- // Outputs
- m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
- // Inputs
- reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
- );
-
- parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
- parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-
-
- input reset_n;
- input clk;
- input wait_n;
- input int_n;
- input nmi_n;
- input busrq_n;
- output m1_n;
- output mreq_n;
- output iorq_n;
- output rd_n;
- output wr_n;
- output rfsh_n;
- output halt_n;
- output busak_n;
- output [15:0] A;
- input [7:0] di;
- output [7:0] dout;
-
- reg mreq_n;
- reg iorq_n;
- reg rd_n;
- reg wr_n;
- reg nxt_mreq_n;
- reg nxt_iorq_n;
- reg nxt_rd_n;
- reg nxt_wr_n;
-
- wire cen;
- wire intcycle_n;
- wire no_read;
- wire write;
- wire iorq;
- reg [7:0] di_reg;
- wire [6:0] mcycle;
- wire [6:0] tstate;
-
- assign cen = 1;
-
- tv80_core #(Mode, IOWait) i_tv80_core
- (
- .cen (cen),
- .m1_n (m1_n),
- .iorq (iorq),
- .no_read (no_read),
- .write (write),
- .rfsh_n (rfsh_n),
- .halt_n (halt_n),
- .wait_n (wait_n),
- .int_n (int_n),
- .nmi_n (nmi_n),
- .reset_n (reset_n),
- .busrq_n (busrq_n),
- .busak_n (busak_n),
- .clk (clk),
- .IntE (),
- .stop (),
- .A (A),
- .dinst (di),
- .di (di_reg),
- .dout (dout),
- .mc (mcycle),
- .ts (tstate),
- .intcycle_n (intcycle_n)
- );
-
- always @*
- begin
- nxt_mreq_n = 1;
- nxt_rd_n = 1;
- nxt_iorq_n = 1;
- nxt_wr_n = 1;
-
- if (mcycle[0])
- begin
- if (tstate[1] || tstate[2])
- begin
- nxt_rd_n = ~ intcycle_n;
- nxt_mreq_n = ~ intcycle_n;
- nxt_iorq_n = intcycle_n;
- end
- end // if (mcycle[0])
- else
- begin
- if ((tstate[1] || tstate[2]) && !no_read && !write)
- begin
- nxt_rd_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
- end
- if (T2Write == 0)
- begin
- if (tstate[2] && write)
- begin
- nxt_wr_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
- end
- end
- else
- begin
- if ((tstate[1] || (tstate[2] && !wait_n)) && write)
- begin
- nxt_wr_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
- end
- end // else: !if(T2write == 0)
- end // else: !if(mcycle[0])
- end // always @ *
-
- always @(negedge clk)
- begin
- if (!reset_n)
- begin
- rd_n <= #1 1'b1;
- wr_n <= #1 1'b1;
- iorq_n <= #1 1'b1;
- mreq_n <= #1 1'b1;
- end
- else
- begin
- rd_n <= #1 nxt_rd_n;
- wr_n <= #1 nxt_wr_n;
- iorq_n <= #1 nxt_iorq_n;
- mreq_n <= #1 nxt_mreq_n;
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
-
- always @(posedge clk)
- begin
- if (!reset_n)
- begin
- di_reg <= #1 0;
- end
- else
- begin
- if (tstate[2] && wait_n == 1'b1)
- di_reg <= #1 di;
- end // else: !if(!reset_n)
- end // always @ (posedge clk)
-
-endmodule // t80n
-
Index: zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v
===================================================================
--- zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v (revision 7)
+++ zx_ula/branches/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v (nonexistent)
@@ -1,333 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: Dept. Architecture and Computing Technology. University of Seville
-// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
-//
-// Create Date: 19:13:39 4-Apr-2012
-// Design Name: ZX Spectrum
-// Module Name: ula
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 1.00 - File Created
-// Additional Comments: GPL License policies apply to the contents of this file.
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-`define cyclestart(a,b) ((a)==(b))
-`define cycleend(a,b) ((a)==(b+1))
-
-module ula(
- input clk14, // 14MHz master clock
- // CPU interfacing
- input [15:0] a, // Address bus from CPU (not all lines are used)
- input [7:0] din, // Input data bus from CPU
- output [7:0] dout, // Output data bus to CPU
- input mreq_n, // MREQ from CPU
- input iorq_n, // IORQ from CPU
- input rd_n, // RD from CPU
- input wr_n, // WR from CPU
- input rfsh_n, // RFSH from CPU
- output clkcpu, // CLK to CPU
- output msk_int_n, // Vertical retrace interrupt, to CPU
- // VRAM interfacing
- output [13:0] va, // Address bus to VRAM (16K)
- input [7:0] vramdout,// Data from VRAM to ULA/CPU
- output [7:0] vramdin,// Data from CPU to VRAM
- output vramoe, //
- output vramcs, // Control signals for VRAM
- output vramwe, //
- // ULA I/O
- input ear, //
- output mic, // I/O ports
- output spk, //
- output [7:0] kbrows, // Keyboard rows
- input [4:0] kbcolumns, // Keyboard columns
- // Video output
- output r, //
- output g, // RGB TTL signal
- output b, // with separate bright
- output i, // and composite sync
- output csync //
- );
-
- reg [2:0] BorderColor = 3'b100;
-
- // Pixel clock
- reg clk7 = 0;
- always @(posedge clk14)
- clk7 <= !clk7;
-
- // Horizontal counter
- reg [8:0] hc = 0;
- always @(posedge clk7) begin
- if (hc==447)
- hc <= 0;
- else
- hc <= hc + 1;
- end
-
- // Vertical counter
- reg [8:0] vc = 0;
- always @(posedge clk7) begin
- if (hc==447) begin
- if (vc == 311)
- vc <= 0;
- else
- vc <= vc + 1;
- end
- end
-
- // HBlank generation
- reg HBlank_n = 1;
- always @(negedge clk7) begin
- if (`cyclestart(hc,320))
- HBlank_n <= 0;
- else if (`cycleend(hc,415))
- HBlank_n <= 1;
- end
-
- // HSync generation (6C ULA version)
- reg HSync_n = 1;
- always @(negedge clk7) begin
- if (`cyclestart(hc,344))
- HSync_n <= 0;
- else if (`cycleend(hc,375))
- HSync_n <= 1;
- end
-
- // VBlank generation
- reg VBlank_n = 1;
- always @(negedge clk7) begin
- if (`cyclestart(vc,248))
- VBlank_n <= 0;
- else if (`cycleend(vc,255))
- VBlank_n <= 1;
- end
-
- // VSync generation (PAL)
- reg VSync_n = 1;
- always @(negedge clk7) begin
- if (`cyclestart(vc,248))
- VSync_n <= 0;
- else if (`cycleend(vc,251))
- VSync_n <= 1;
- end
-
- // INT generation
- reg INT_n = 1;
- assign msk_int_n = INT_n;
- always @(negedge clk7) begin
- if (`cyclestart(vc,248) && `cyclestart(hc,0))
- INT_n <= 0;
- else if (`cyclestart(vc,248) && `cycleend(hc,31))
- INT_n <= 1;
- end
-
- // Border control signal (=0 when we're not displaying paper/ink pixels)
- reg Border_n = 1;
- always @(negedge clk7) begin
- if ( (vc[7] & vc[6]) | vc[8] | hc[8])
- Border_n <= 0;
- else
- Border_n <= 1;
- end
-
- // VidEN generation (delaying Border 8 clocks)
- reg VidEN_n = 1;
- always @(negedge clk7) begin
- if (hc[3])
- VidEN_n <= !Border_n;
- end
-
- // DataLatch generation (posedge to capture data from memory)
- reg DataLatch_n = 1;
- always @(negedge clk7) begin
- if (hc[0] & !hc[1] & Border_n & hc[3])
- DataLatch_n <= 0;
- else
- DataLatch_n <= 1;
- end
-
- // AttrLatch generation (posedge to capture data from memory)
- reg AttrLatch_n = 1;
- always @(negedge clk7) begin
- if (hc[0] & hc[1] & Border_n & hc[3])
- AttrLatch_n <= 0;
- else
- AttrLatch_n <= 1;
- end
-
- // SLoad generation (negedge to load shift register)
- reg SLoad = 0;
- always @(negedge clk7) begin
- if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
- SLoad <= 1;
- else
- SLoad <= 0;
- end
-
- // AOLatch generation (negedge to update attr output latch)
- reg AOLatch_n = 1;
- always @(negedge clk7) begin
- if (hc[0] & !hc[1] & hc[2])
- AOLatch_n <= 0;
- else
- AOLatch_n <= 1;
- end
-
- // First buffer for bitmap
- reg [7:0] BitmapReg = 0;
- always @(negedge DataLatch_n) begin
- BitmapReg <= vramdout;
- end
-
- // Shift register (second bitmap register)
- reg [7:0] SRegister = 0;
- always @(negedge clk7) begin
- if (SLoad)
- SRegister <= BitmapReg;
- else
- SRegister <= {SRegister[6:0],1'b0};
- end
-
- // First buffer for attribute
- reg [7:0] AttrReg = 0;
- always @(negedge AttrLatch_n) begin
- AttrReg <= vramdout;
- end
-
- // Second buffer for attribute
- reg [7:0] AttrOut = 0;
- always @(negedge AOLatch_n) begin
- if (!VidEN_n)
- AttrOut <= AttrReg;
- else
- AttrOut <= {2'b00,BorderColor,BorderColor};
- end
-
- // Flash counter and pixel generation
- reg [4:0] FlashCnt = 0;
- always @(negedge VSync_n) begin
- FlashCnt <= FlashCnt + 1;
- end
- wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
-
- // RGB generation
- reg rI,rG,rR,rB;
- assign r = rR;
- assign g = rG;
- assign b = rB;
- assign i = rI;
- always @(*) begin
- if (HBlank_n && VBlank_n)
- {rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
- else
- {rI,rG,rR,rB} = 4'b0000;
- end
-
- //CSync generation
- assign csync = HSync_n & VSync_n;
-
- // VRAM address and control line generation
- reg [13:0] rVA = 0;
- reg rVCS = 0;
- reg rVOE = 0;
- reg rVWE = 0;
- assign va = rVA;
- assign vramcs = rVCS;
- assign vramoe = rVOE;
- assign vramwe = rVWE;
- // Latches to hold delayed versions of V and H counters
- reg [8:0] v = 0;
- reg [8:0] c = 0;
- // Address and control line multiplexor ULA/CPU
- always @(negedge clk7) begin
- if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
- c <= hc;
- v <= vc;
- end
- end
- // Address and control line multiplexor ULA/CPU
- always @(*) begin
- if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
- rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
- rVCS = 1;
- rVOE = !hc[0];
- rVWE = 0;
- end
- else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
- rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
- rVCS = 1;
- rVOE = !hc[0];
- rVWE = 0;
- end
- else if (Border_n && hc[3:0]==4'b0000) begin
- rVA = a[13:0];
- rVCS = 0;
- rVOE = 0;
- rVWE = 0;
- end
- else begin // when VRAM is not in use by ULA, give it to CPU
- rVA = a[13:0];
- rVCS = !a[15] & a[14] & !mreq_n;
- rVOE = !rd_n;
- rVWE = !wr_n;
- end
- end
-
- // CPU contention
- reg CPUClk = 0;
- assign clkcpu = CPUClk;
- reg ioreqtw3 = 0;
- reg mreqt23 = 0;
- wire ioreq_n = a[0] | iorq_n;
- wire Nor1 = (~(a[14] | ~ioreq_n)) |
- (~(~a[15] | ~ioreq_n)) |
- (~(hc[2] | hc[3])) |
- (~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
- wire Nor2 = (~(hc[2] | hc[3])) |
- ~Border_n |
- ~CPUClk |
- ioreq_n |
- ~ioreqtw3;
- wire CLKContention = ~Nor1 | ~Nor2;
- always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
- if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
- CPUClk <= 0;
- else
- CPUClk <= 1;
- end
- always @(posedge CPUClk) begin
- ioreqtw3 <= ioreq_n;
- mreqt23 <= mreq_n;
- end
-
- // ULA-CPU interface
- assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
- (!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
- (Border_n)? AttrReg : // to emulate
- 8'hFF; // port FF
- assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
- assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
- a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
- a[9]? 1'bz : 1'b0, // there's no need to do this.
- a[12]? 1'bz : 1'b0,
- a[13]? 1'bz : 1'b0,
- a[8]? 1'bz : 1'b0,
- a[14]? 1'bz : 1'b0,
- a[15]? 1'bz : 1'b0 };
- reg rMic = 0;
- reg rSpk = 0;
- assign mic = rMic;
- assign spk = rSpk;
- always @(negedge clk7) begin
- if (!iorq_n & !a[0] & !wr_n)
- {rSpk,rMic,BorderColor} <= din[5:0];
- end
-endmodule
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.xise (revision 8)
@@ -0,0 +1,373 @@
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Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/sp48k_for_spartan3_starter_kit.ucf (revision 8)
@@ -0,0 +1,83 @@
+NET "clk50" LOC = "T9" | IOSTANDARD = LVCMOS33;
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+# NET "clk50" PERIOD = 20.0ns HIGH 40%;
+
+NET "reset" LOC = "L14" | IOSTANDARD = LVCMOS33;
+
+# I/O
+NET "r" LOC = "E7" | IOSTANDARD = LVCMOS33;
+NET "g" LOC = "D6" | IOSTANDARD = LVCMOS33;
+NET "b" LOC = "D5" | IOSTANDARD = LVCMOS33;
+NET "i" LOC = "D7" | IOSTANDARD = LVCMOS33;
+
+NET "csync" LOC = "D8" | IOSTANDARD = LVCMOS33;
+NET "audio_out" LOC = "D10" | IOSTANDARD = LVCMOS33;
+NET "ear" LOC = "T13" | IOSTANDARD = LVCMOS33;
+
+NET "kbd_rows<0>" LOC = "E6" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<1>" LOC = "C5" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<2>" LOC = "C6" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<3>" LOC = "C7" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<4>" LOC = "C8" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<5>" LOC = "C9" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<6>" LOC = "A3" | IOSTANDARD = LVCMOS33;
+NET "kbd_rows<7>" LOC = "A4" | IOSTANDARD = LVCMOS33;
+
+NET "kbd_columns<0>" LOC = "B4" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "kbd_columns<1>" LOC = "B5" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "kbd_columns<2>" LOC = "B6" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "kbd_columns<3>" LOC = "A7" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "kbd_columns<4>" LOC = "A8" | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# Debug LED's
+NET "leds<7>" LOC = "P11" | IOSTANDARD = LVCMOS33;
+NET "leds<6>" LOC = "P12" | IOSTANDARD = LVCMOS33;
+NET "leds<5>" LOC = "N12" | IOSTANDARD = LVCMOS33;
+NET "leds<4>" LOC = "P13" | IOSTANDARD = LVCMOS33;
+NET "leds<3>" LOC = "N14" | IOSTANDARD = LVCMOS33;
+NET "leds<2>" LOC = "L12" | IOSTANDARD = LVCMOS33;
+NET "leds<1>" LOC = "P14" | IOSTANDARD = LVCMOS33;
+NET "leds<0>" LOC = "K12" | IOSTANDARD = LVCMOS33;
+
+# External SRAM
+NET "sa<17>" LOC = "L3" | IOSTANDARD = LVCMOS33;
+NET "sa<16>" LOC = "K5" | IOSTANDARD = LVCMOS33;
+NET "sa<15>" LOC = "K3" | IOSTANDARD = LVCMOS33;
+NET "sa<14>" LOC = "J3" | IOSTANDARD = LVCMOS33;
+NET "sa<13>" LOC = "J4" | IOSTANDARD = LVCMOS33;
+NET "sa<12>" LOC = "H4" | IOSTANDARD = LVCMOS33;
+NET "sa<11>" LOC = "H3" | IOSTANDARD = LVCMOS33;
+NET "sa<10>" LOC = "G5" | IOSTANDARD = LVCMOS33;
+NET "sa<9>" LOC = "E4" | IOSTANDARD = LVCMOS33;
+NET "sa<8>" LOC = "E3" | IOSTANDARD = LVCMOS33;
+NET "sa<7>" LOC = "F4" | IOSTANDARD = LVCMOS33;
+NET "sa<6>" LOC = "F3" | IOSTANDARD = LVCMOS33;
+NET "sa<5>" LOC = "G4" | IOSTANDARD = LVCMOS33;
+NET "sa<4>" LOC = "L4" | IOSTANDARD = LVCMOS33;
+NET "sa<3>" LOC = "M3" | IOSTANDARD = LVCMOS33;
+NET "sa<2>" LOC = "M4" | IOSTANDARD = LVCMOS33;
+NET "sa<1>" LOC = "N3" | IOSTANDARD = LVCMOS33;
+NET "sa<0>" LOC = "L5" | IOSTANDARD = LVCMOS33;
+
+#NET "sd1<15>" LOC = "R1" | IOSTANDARD = LVCMOS33;
+#NET "sd1<14>" LOC = "P1" | IOSTANDARD = LVCMOS33;
+#NET "sd1<13>" LOC = "L2" | IOSTANDARD = LVCMOS33;
+#NET "sd1<12>" LOC = "J2" | IOSTANDARD = LVCMOS33;
+#NET "sd1<11>" LOC = "H1" | IOSTANDARD = LVCMOS33;
+#NET "sd1<10>" LOC = "F2" | IOSTANDARD = LVCMOS33;
+#NET "sd1<9>" LOC = "P8" | IOSTANDARD = LVCMOS33;
+#NET "sd1<8>" LOC = "D3" | IOSTANDARD = LVCMOS33;
+NET "sd1<7>" LOC = "B1" | IOSTANDARD = LVCMOS33;
+NET "sd1<6>" LOC = "C1" | IOSTANDARD = LVCMOS33;
+NET "sd1<5>" LOC = "C2" | IOSTANDARD = LVCMOS33;
+NET "sd1<4>" LOC = "R5" | IOSTANDARD = LVCMOS33;
+NET "sd1<3>" LOC = "T5" | IOSTANDARD = LVCMOS33;
+NET "sd1<2>" LOC = "R6" | IOSTANDARD = LVCMOS33;
+NET "sd1<1>" LOC = "T8" | IOSTANDARD = LVCMOS33;
+NET "sd1<0>" LOC = "N7" | IOSTANDARD = LVCMOS33;
+
+NET "sramce1" LOC = "P7" | IOSTANDARD = LVCMOS33;
+NET "sramub1" LOC = "T4" | IOSTANDARD = LVCMOS33;
+NET "sramlb1" LOC = "P6" | IOSTANDARD = LVCMOS33;
+NET "sramwe" LOC = "G3" | IOSTANDARD = LVCMOS33;
+NET "sramoe" LOC = "K4" | IOSTANDARD = LVCMOS33;
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80n.v (revision 8)
@@ -0,0 +1,182 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+// Negative-edge based wrapper allows memory wait_n signal to work
+// correctly without resorting to asynchronous logic.
+
+module tv80n (/*AUTOARG*/
+ // Outputs
+ m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
+ // Inputs
+ reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
+ );
+
+ parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
+ parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
+
+
+ input reset_n;
+ input clk;
+ input wait_n;
+ input int_n;
+ input nmi_n;
+ input busrq_n;
+ output m1_n;
+ output mreq_n;
+ output iorq_n;
+ output rd_n;
+ output wr_n;
+ output rfsh_n;
+ output halt_n;
+ output busak_n;
+ output [15:0] A;
+ input [7:0] di;
+ output [7:0] dout;
+
+ reg mreq_n;
+ reg iorq_n;
+ reg rd_n;
+ reg wr_n;
+ reg nxt_mreq_n;
+ reg nxt_iorq_n;
+ reg nxt_rd_n;
+ reg nxt_wr_n;
+
+ wire cen;
+ wire intcycle_n;
+ wire no_read;
+ wire write;
+ wire iorq;
+ reg [7:0] di_reg;
+ wire [6:0] mcycle;
+ wire [6:0] tstate;
+
+ assign cen = 1;
+
+ tv80_core #(Mode, IOWait) i_tv80_core
+ (
+ .cen (cen),
+ .m1_n (m1_n),
+ .iorq (iorq),
+ .no_read (no_read),
+ .write (write),
+ .rfsh_n (rfsh_n),
+ .halt_n (halt_n),
+ .wait_n (wait_n),
+ .int_n (int_n),
+ .nmi_n (nmi_n),
+ .reset_n (reset_n),
+ .busrq_n (busrq_n),
+ .busak_n (busak_n),
+ .clk (clk),
+ .IntE (),
+ .stop (),
+ .A (A),
+ .dinst (di),
+ .di (di_reg),
+ .dout (dout),
+ .mc (mcycle),
+ .ts (tstate),
+ .intcycle_n (intcycle_n)
+ );
+
+ always @*
+ begin
+ nxt_mreq_n = 1;
+ nxt_rd_n = 1;
+ nxt_iorq_n = 1;
+ nxt_wr_n = 1;
+
+ if (mcycle[0])
+ begin
+ if (tstate[1] || tstate[2])
+ begin
+ nxt_rd_n = ~ intcycle_n;
+ nxt_mreq_n = ~ intcycle_n;
+ nxt_iorq_n = intcycle_n;
+ end
+ end // if (mcycle[0])
+ else
+ begin
+ if ((tstate[1] || tstate[2]) && !no_read && !write)
+ begin
+ nxt_rd_n = 1'b0;
+ nxt_iorq_n = ~ iorq;
+ nxt_mreq_n = iorq;
+ end
+ if (T2Write == 0)
+ begin
+ if (tstate[2] && write)
+ begin
+ nxt_wr_n = 1'b0;
+ nxt_iorq_n = ~ iorq;
+ nxt_mreq_n = iorq;
+ end
+ end
+ else
+ begin
+ if ((tstate[1] || (tstate[2] && !wait_n)) && write)
+ begin
+ nxt_wr_n = 1'b0;
+ nxt_iorq_n = ~ iorq;
+ nxt_mreq_n = iorq;
+ end
+ end // else: !if(T2write == 0)
+ end // else: !if(mcycle[0])
+ end // always @ *
+
+ always @(negedge clk)
+ begin
+ if (!reset_n)
+ begin
+ rd_n <= #1 1'b1;
+ wr_n <= #1 1'b1;
+ iorq_n <= #1 1'b1;
+ mreq_n <= #1 1'b1;
+ end
+ else
+ begin
+ rd_n <= #1 nxt_rd_n;
+ wr_n <= #1 nxt_wr_n;
+ iorq_n <= #1 nxt_iorq_n;
+ mreq_n <= #1 nxt_mreq_n;
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+ always @(posedge clk)
+ begin
+ if (!reset_n)
+ begin
+ di_reg <= #1 0;
+ end
+ else
+ begin
+ if (tstate[2] && wait_n == 1'b1)
+ di_reg <= #1 di;
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk)
+
+endmodule // t80n
+
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v (revision 8)
@@ -0,0 +1,207 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Dept. Architecture and Computing Technology. University of Seville
+// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
+//
+// Create Date: 19:13:39 4-Apr-2012
+// Design Name: ZX Spectrum
+// Module Name: ram32k
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 1.00 - File Created
+// Additional Comments: GPL License policies apply to the contents of this file.
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+/*
+This module generates a high level on "isfalling" when "a" changes from high to low.
+*/
+module getfedge (
+ input clk,
+ input a,
+ output isfalling
+ );
+
+ reg sh = 1'b1;
+ assign isfalling = sh & ~a;
+ always @(posedge clk)
+ sh <= a;
+endmodule
+
+
+/*
+This module implements a shared RAM controller. The Spartan 3 Starter Kit has two 256Kx16 SRAM chips.
+It uses half the size of one of these chips (8 bit data bus instead of 16).
+As the ZX Spectrum needs two independent memory banks, and bus cycles may happen to both at the same
+time, it's necessary to emulate those two banks with one chip.
+
+I tried a simple round-robin multiplexing, but didn't work as expected. This module is a bit more complicated
+as it implements a first-come-first-serve approach, with fixed priority scheme when several petitions happen
+at the same time.
+
+Each bank can be up to 64Kx8, so implementing a 128K memory scheme is very easy (I hope so) using this module
+and the external SRAM on board.
+
+This may be my first 100% synchronous implementation for a FPGA (that is, only one clock and all the ff's are
+activated at the same edge)
+
+*/
+module ram_controller (
+ input clk,
+ // Bank 1 (VRAM)
+ input [15:0] a1,
+ input cs1_n,
+ input oe1_n,
+ input we1_n,
+ input [7:0] din1,
+ output [7:0] dout1,
+ // Bank 2 (upper RAM)
+ input [15:0] a2,
+ input cs2_n,
+ input oe2_n,
+ input we2_n,
+ input [7:0] din2,
+ output [7:0] dout2,
+ // Outputs to actual SRAM on board
+ output [17:0] sa,
+ inout [7:0] sd,
+ output sramce,
+ output sramub,
+ output sramlb,
+ output sramoe,
+ output sramwe
+ );
+
+ // Permanently enable SRAM and set it to use only LSB
+ assign sramub = 1;
+ assign sramlb = 0;
+ assign sramce = 0;
+ assign sramoe = 0;
+
+ reg rsramwe = 1;
+ assign sramwe = rsramwe;
+
+ reg [17:0] rsa;
+ reg [7:0] rsd;
+ assign sa = rsa;
+ assign sd = rsd;
+
+ // set when there has been a high to low transition in the corresponding signal
+ wire bank1read, bank1write, bank2read, bank2write;
+ getfedge detectbank1read (clk, cs1_n | oe1_n, bank1read);
+ getfedge detectbank2read (clk, cs2_n | oe2_n, bank2read);
+ getfedge detectbank1write (clk, cs1_n | we1_n, bank1write);
+ getfedge detectbank2write (clk, cs2_n | we2_n, bank2write);
+
+ reg [15:0] ra1;
+ reg [15:0] ra2;
+ reg [7:0] rdin1;
+ reg [7:0] rdin2;
+
+ reg [7:0] rdout1;
+ assign dout1 = rdout1;
+ reg [7:0] rdout2;
+ assign dout2 = rdout2;
+
+ // ff's to store pending memory requests
+ reg pendingreadb1 = 0;
+ reg pendingwriteb1 = 0;
+ reg pendingreadb2 = 0;
+ reg pendingwriteb2 = 0;
+
+ // ff's to store current memory requests
+ reg reqreadb1 = 0;
+ reg reqreadb2 = 0;
+ reg reqwriteb1 = 0;
+ reg reqwriteb2 = 0;
+
+ reg state = 1;
+ always @(posedge clk) begin
+ // get requests from the two banks
+ if (bank1read) begin
+ ra1 <= a1;
+ pendingreadb1 <= 1;
+ pendingwriteb1 <= 0;
+ end
+ else if (bank1write) begin
+ ra1 <= a1;
+ rdin1 <= din1;
+ pendingwriteb1 <= 1;
+ pendingreadb1 <= 0;
+ end
+ if (bank2read) begin
+ ra2 <= a2;
+ pendingreadb2 <= 1;
+ pendingwriteb2 <= 0;
+ end
+ else if (bank2write) begin
+ ra2 <= a2;
+ rdin2 <= din2;
+ pendingwriteb2 <= 1;
+ pendingreadb2 <= 0;
+ end
+
+ // reads from bank1 have the higher priority, then writes to bank1,
+ // the reads from bank2, then writes from bank2.
+ // Reads and writes to bank2 are mutually exclusive, though, as only the CPU
+ // performs those operations. So they are with respect to bank1.
+ case (state)
+ 0 : begin
+ if (reqreadb1 || reqwriteb1) begin
+ rsa <= {2'b00,ra1}; // operation to bank1 accepted. We put the memory address on the SRAM address bus
+ if (reqwriteb1) begin // if this is a write operation...
+ pendingwriteb1 <= 0; // accept it, and mark pending operation as cleared
+ rsd <= rdin1; // put the data to be written in the SRAM data bus
+ rsramwe <= 0; // pulse /WE in SRAM to begin write
+ end
+ else begin
+ pendingreadb1 <= 0; // else, this is a read operation...
+ rsd <= 8'bzzzzzzzz; // disconnect the output bus from the data register to the SRAM data bus, so
+ rsramwe <= 1; // we can read from the SRAM data bus itself. Deassert /WE to enable data output bus
+ end
+ state <= 1; // if either request has been accepted, proceed to next phase.
+ end
+ else if (reqreadb2 || reqwriteb2) begin // do the same with requests to bank 2...
+ rsa <= {2'b01,ra2};
+ if (reqwriteb2) begin
+ pendingwriteb2 <= 0;
+ rsd <= rdin2;
+ rsramwe <= 0;
+ end
+ else begin
+ pendingreadb2 <= 0;
+ rsd <= 8'bzzzzzzzz;
+ rsramwe <= 1;
+ end
+ state <= 1;
+ end
+ end
+ 1 : begin
+ if (reqreadb1) begin // for read requests, read the SRAM data bus and store into the corresponding data output register
+ rdout1 <= sd;
+ end
+ else if (reqreadb2) begin
+ rdout2 <= sd;
+ end
+ if (reqwriteb1) begin // for write requests, deassert /WE, as writting has already been happened.
+ rsramwe <= 1;
+ end
+ else if (reqwriteb2) begin
+ rsramwe <= 1;
+ end
+ reqreadb1 <= pendingreadb1; // current request has finished, so update current requests with pending requests to serve the next one
+ reqreadb2 <= pendingreadb2;
+ reqwriteb1 <= pendingwriteb1;
+ reqwriteb2 <= pendingwriteb2;
+ if (pendingreadb1 || pendingreadb2 || pendingwriteb1 || pendingwriteb2)
+ state <= 0;
+ end
+ endcase
+ end
+endmodule
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/ula.v (revision 8)
@@ -0,0 +1,333 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Dept. Architecture and Computing Technology. University of Seville
+// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
+//
+// Create Date: 19:13:39 4-Apr-2012
+// Design Name: ZX Spectrum
+// Module Name: ula
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 1.00 - File Created
+// Additional Comments: GPL License policies apply to the contents of this file.
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`define cyclestart(a,b) ((a)==(b))
+`define cycleend(a,b) ((a)==(b+1))
+
+module ula(
+ input clk14, // 14MHz master clock
+ // CPU interfacing
+ input [15:0] a, // Address bus from CPU (not all lines are used)
+ input [7:0] din, // Input data bus from CPU
+ output [7:0] dout, // Output data bus to CPU
+ input mreq_n, // MREQ from CPU
+ input iorq_n, // IORQ from CPU
+ input rd_n, // RD from CPU
+ input wr_n, // WR from CPU
+ input rfsh_n, // RFSH from CPU
+ output clkcpu, // CLK to CPU
+ output msk_int_n, // Vertical retrace interrupt, to CPU
+ // VRAM interfacing
+ output [13:0] va, // Address bus to VRAM (16K)
+ input [7:0] vramdout,// Data from VRAM to ULA/CPU
+ output [7:0] vramdin,// Data from CPU to VRAM
+ output vramoe, //
+ output vramcs, // Control signals for VRAM
+ output vramwe, //
+ // ULA I/O
+ input ear, //
+ output mic, // I/O ports
+ output spk, //
+ output [7:0] kbrows, // Keyboard rows
+ input [4:0] kbcolumns, // Keyboard columns
+ // Video output
+ output r, //
+ output g, // RGB TTL signal
+ output b, // with separate bright
+ output i, // and composite sync
+ output csync //
+ );
+
+ reg [2:0] BorderColor = 3'b100;
+
+ // Pixel clock
+ reg clk7 = 0;
+ always @(posedge clk14)
+ clk7 <= !clk7;
+
+ // Horizontal counter
+ reg [8:0] hc = 0;
+ always @(posedge clk7) begin
+ if (hc==447)
+ hc <= 0;
+ else
+ hc <= hc + 1;
+ end
+
+ // Vertical counter
+ reg [8:0] vc = 0;
+ always @(posedge clk7) begin
+ if (hc==447) begin
+ if (vc == 311)
+ vc <= 0;
+ else
+ vc <= vc + 1;
+ end
+ end
+
+ // HBlank generation
+ reg HBlank_n = 1;
+ always @(negedge clk7) begin
+ if (`cyclestart(hc,320))
+ HBlank_n <= 0;
+ else if (`cycleend(hc,415))
+ HBlank_n <= 1;
+ end
+
+ // HSync generation (6C ULA version)
+ reg HSync_n = 1;
+ always @(negedge clk7) begin
+ if (`cyclestart(hc,344))
+ HSync_n <= 0;
+ else if (`cycleend(hc,375))
+ HSync_n <= 1;
+ end
+
+ // VBlank generation
+ reg VBlank_n = 1;
+ always @(negedge clk7) begin
+ if (`cyclestart(vc,248))
+ VBlank_n <= 0;
+ else if (`cycleend(vc,255))
+ VBlank_n <= 1;
+ end
+
+ // VSync generation (PAL)
+ reg VSync_n = 1;
+ always @(negedge clk7) begin
+ if (`cyclestart(vc,248))
+ VSync_n <= 0;
+ else if (`cycleend(vc,251))
+ VSync_n <= 1;
+ end
+
+ // INT generation
+ reg INT_n = 1;
+ assign msk_int_n = INT_n;
+ always @(negedge clk7) begin
+ if (`cyclestart(vc,248) && `cyclestart(hc,0))
+ INT_n <= 0;
+ else if (`cyclestart(vc,248) && `cycleend(hc,31))
+ INT_n <= 1;
+ end
+
+ // Border control signal (=0 when we're not displaying paper/ink pixels)
+ reg Border_n = 1;
+ always @(negedge clk7) begin
+ if ( (vc[7] & vc[6]) | vc[8] | hc[8])
+ Border_n <= 0;
+ else
+ Border_n <= 1;
+ end
+
+ // VidEN generation (delaying Border 8 clocks)
+ reg VidEN_n = 1;
+ always @(negedge clk7) begin
+ if (hc[3])
+ VidEN_n <= !Border_n;
+ end
+
+ // DataLatch generation (posedge to capture data from memory)
+ reg DataLatch_n = 1;
+ always @(negedge clk7) begin
+ if (hc[0] & !hc[1] & Border_n & hc[3])
+ DataLatch_n <= 0;
+ else
+ DataLatch_n <= 1;
+ end
+
+ // AttrLatch generation (posedge to capture data from memory)
+ reg AttrLatch_n = 1;
+ always @(negedge clk7) begin
+ if (hc[0] & hc[1] & Border_n & hc[3])
+ AttrLatch_n <= 0;
+ else
+ AttrLatch_n <= 1;
+ end
+
+ // SLoad generation (negedge to load shift register)
+ reg SLoad = 0;
+ always @(negedge clk7) begin
+ if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
+ SLoad <= 1;
+ else
+ SLoad <= 0;
+ end
+
+ // AOLatch generation (negedge to update attr output latch)
+ reg AOLatch_n = 1;
+ always @(negedge clk7) begin
+ if (hc[0] & !hc[1] & hc[2])
+ AOLatch_n <= 0;
+ else
+ AOLatch_n <= 1;
+ end
+
+ // First buffer for bitmap
+ reg [7:0] BitmapReg = 0;
+ always @(negedge DataLatch_n) begin
+ BitmapReg <= vramdout;
+ end
+
+ // Shift register (second bitmap register)
+ reg [7:0] SRegister = 0;
+ always @(negedge clk7) begin
+ if (SLoad)
+ SRegister <= BitmapReg;
+ else
+ SRegister <= {SRegister[6:0],1'b0};
+ end
+
+ // First buffer for attribute
+ reg [7:0] AttrReg = 0;
+ always @(negedge AttrLatch_n) begin
+ AttrReg <= vramdout;
+ end
+
+ // Second buffer for attribute
+ reg [7:0] AttrOut = 0;
+ always @(negedge AOLatch_n) begin
+ if (!VidEN_n)
+ AttrOut <= AttrReg;
+ else
+ AttrOut <= {2'b00,BorderColor,BorderColor};
+ end
+
+ // Flash counter and pixel generation
+ reg [4:0] FlashCnt = 0;
+ always @(negedge VSync_n) begin
+ FlashCnt <= FlashCnt + 1;
+ end
+ wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
+
+ // RGB generation
+ reg rI,rG,rR,rB;
+ assign r = rR;
+ assign g = rG;
+ assign b = rB;
+ assign i = rI;
+ always @(*) begin
+ if (HBlank_n && VBlank_n)
+ {rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
+ else
+ {rI,rG,rR,rB} = 4'b0000;
+ end
+
+ //CSync generation
+ assign csync = HSync_n & VSync_n;
+
+ // VRAM address and control line generation
+ reg [13:0] rVA = 0;
+ reg rVCS = 0;
+ reg rVOE = 0;
+ reg rVWE = 0;
+ assign va = rVA;
+ assign vramcs = rVCS;
+ assign vramoe = rVOE;
+ assign vramwe = rVWE;
+ // Latches to hold delayed versions of V and H counters
+ reg [8:0] v = 0;
+ reg [8:0] c = 0;
+ // Address and control line multiplexor ULA/CPU
+ always @(negedge clk7) begin
+ if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
+ c <= hc;
+ v <= vc;
+ end
+ end
+ // Address and control line multiplexor ULA/CPU
+ always @(*) begin
+ if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
+ rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
+ rVCS = 1;
+ rVOE = !hc[0];
+ rVWE = 0;
+ end
+ else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
+ rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
+ rVCS = 1;
+ rVOE = !hc[0];
+ rVWE = 0;
+ end
+ else if (Border_n && hc[3:0]==4'b0000) begin
+ rVA = a[13:0];
+ rVCS = 0;
+ rVOE = 0;
+ rVWE = 0;
+ end
+ else begin // when VRAM is not in use by ULA, give it to CPU
+ rVA = a[13:0];
+ rVCS = !a[15] & a[14] & !mreq_n;
+ rVOE = !rd_n;
+ rVWE = !wr_n;
+ end
+ end
+
+ // CPU contention
+ reg CPUClk = 0;
+ assign clkcpu = CPUClk;
+ reg ioreqtw3 = 0;
+ reg mreqt23 = 0;
+ wire ioreq_n = a[0] | iorq_n;
+ wire Nor1 = (~(a[14] | ~ioreq_n)) |
+ (~(~a[15] | ~ioreq_n)) |
+ (~(hc[2] | hc[3])) |
+ (~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
+ wire Nor2 = (~(hc[2] | hc[3])) |
+ ~Border_n |
+ ~CPUClk |
+ ioreq_n |
+ ~ioreqtw3;
+ wire CLKContention = ~Nor1 | ~Nor2;
+ always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
+ if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
+ CPUClk <= 0;
+ else
+ CPUClk <= 1;
+ end
+ always @(posedge CPUClk) begin
+ ioreqtw3 <= ioreq_n;
+ mreqt23 <= mreq_n;
+ end
+
+ // ULA-CPU interface
+ assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
+ (!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
+ (Border_n)? AttrReg : // to emulate
+ 8'hFF; // port FF
+ assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
+ assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
+ a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
+ a[9]? 1'bz : 1'b0, // there's no need to do this.
+ a[12]? 1'bz : 1'b0,
+ a[13]? 1'bz : 1'b0,
+ a[8]? 1'bz : 1'b0,
+ a[14]? 1'bz : 1'b0,
+ a[15]? 1'bz : 1'b0 };
+ reg rMic = 0;
+ reg rSpk = 0;
+ assign mic = rMic;
+ assign spk = rSpk;
+ always @(negedge clk7) begin
+ if (!iorq_n & !a[0] & !wr_n)
+ {rSpk,rMic,BorderColor} <= din[5:0];
+ end
+endmodule
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.gise
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.gise (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/zx_spectrum_48k.gise (revision 8)
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/spectrum48k_tld.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/spectrum48k_tld.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/spectrum48k_tld.v (revision 8)
@@ -0,0 +1,278 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Dept. Architecture and Computing Technology. University of Seville
+// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
+//
+// Create Date: 19:13:39 4-Apr-2012
+// Design Name: ZX Spectrum
+// Module Name: tld_spartan3_sp48k
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 1.00 - File Created
+// Additional Comments: GPL License policies apply to the contents of this file.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module tld_spartan3_sp48k (
+ input clk50,
+ input reset,
+ output r,
+ output g,
+ output b,
+ output i,
+ output csync,
+ // ULA I/O
+ input ear,
+ output audio_out,
+ output [7:0] kbd_rows,
+ input [4:0] kbd_columns,
+ // diagnostics
+ output [7:0] leds,
+ // SRAM memory
+ output [17:0] sa,
+ inout [7:0] sd1,
+ output sramce1,
+ output sramub1,
+ output sramlb1,
+ output sramoe,
+ output sramwe
+ );
+
+ // CPU signals
+ wire [15:0] a;
+ wire [7:0] cpudout;
+ wire [7:0] cpudin;
+ wire clkcpu;
+ wire mreq_n;
+ wire iorq_n;
+ wire wr_n;
+ wire rd_n;
+ wire rfsh_n;
+ wire int_n;
+
+ // VRAM signals
+ wire [13:0] va;
+ wire [7:0] vramdin;
+ wire [7:0] vramdout;
+ wire vramoe;
+ wire vramcs;
+ wire vramwe;
+
+ // I/O
+ wire mic;
+ wire spk;
+ assign audio_out = spk;
+
+ // ULA data bus
+ wire [7:0] uladout;
+ wire [7:0] uladin;
+
+ // SRAM data bus
+ wire [7:0] sramdout;
+ wire [7:0] sramdin;
+
+ // ROM data bus
+ wire [7:0] romdout;
+
+ wire sram_cs = a[15] & !mreq_n;
+ wire ula_cs = !a[0] & !iorq_n;
+ wire vram_cs = !a[15] & a[14] & !mreq_n;
+ wire port255_cs = !iorq_n && a[7:0]==8'hFF && !rd_n;
+ wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
+
+ /////////////////////////////////////
+ // Master clock (14MHz) generation
+ /////////////////////////////////////
+ wire clk28mhz;
+ master_clock clock28mhz (
+ .CLKIN_IN(clk50),
+ .CLKFX_OUT(clk28mhz),
+ .CLKIN_IBUFG_OUT(),
+ .CLK0_OUT()
+ );
+ reg clk14 = 0;
+ always @(posedge clk28mhz) begin
+ clk14 = !clk14;
+ end
+ wire clkula = clk14;
+ wire clkmem = clk28mhz;
+
+ /////////////////////////////////////
+ // ROM
+ /////////////////////////////////////
+ rom the_rom (
+ .clka(clkmem),
+ .ena(rom_cs),
+ .addra(a[13:0]),
+ .douta(romdout)
+ );
+
+// /////////////////////////////////////
+// // VRAM (first 16K of RAM)
+// /////////////////////////////////////
+// vram lower_ram (
+// .clka(clkmem),
+// .addra(va),
+// .dina(vramdin),
+// .douta(vramdout),
+// .ena(vramcs),
+// .wea(vramwe)
+// );
+
+// /////////////////////////////////////
+// // SRAM (top 32K of RAM). External SRAM chip
+// /////////////////////////////////////
+// ram32k upper_ram (
+// .a(a[14:0]),
+// .cs_n(!sram_cs),
+// .oe_n(rd_n),
+// .we_n(wr_n),
+// .din(sramdin),
+// .dout(sramdout),
+// .sa(sa),
+// .sd(sd1),
+// .sramce(sramce1),
+// .sramub(sramub1),
+// .sramlb(sramlb1),
+// .sramoe(sramoe),
+// .sramwe(sramwe)
+// );
+
+ /////////////////////////////////////
+ // VRAM and upper RAM banks
+ /////////////////////////////////////
+ ram_controller vram_and_upper_ram (
+ .clk(clkmem),
+ // Bank 1 (VRAM)
+ .a1({2'b00,va}),
+ .cs1_n(!vramcs),
+ .oe1_n(!vramoe),
+ .we1_n(!vramwe),
+ .din1(vramdin),
+ .dout1(vramdout),
+ // Bank 2 (upper RAM)
+ .a2({1'b0,a[14:0]}),
+ .cs2_n(!sram_cs),
+ .oe2_n(rd_n),
+ .we2_n(wr_n),
+ .din2(sramdin),
+ .dout2(sramdout),
+ // Outputs to actual SRAM on board
+ .sa(sa),
+ .sd(sd1),
+ .sramce(sramce1),
+ .sramub(sramub1),
+ .sramlb(sramlb1),
+ .sramoe(sramoe),
+ .sramwe(sramwe)
+ );
+
+ /////////////////////////////////////
+ // The ULA
+ /////////////////////////////////////
+ ula the_ula (
+ .clk14(clkula),
+ .a(a),
+ .din(uladin),
+ .dout(uladout),
+ .mreq_n(mreq_n),
+ .iorq_n(iorq_n),
+ .rd_n(rd_n),
+ .wr_n(wr_n),
+ .rfsh_n(rfsh_n),
+ .clkcpu(clkcpu),
+ .msk_int_n(int_n),
+ .va(va),
+ .vramdout(vramdout),
+ .vramdin(vramdin),
+ .vramoe(vramoe),
+ .vramcs(vramcs),
+ .vramwe(vramwe),
+ .ear(ear),
+ .mic(mic),
+ .spk(spk),
+ .kbrows(kbd_rows),
+ .kbcolumns(kbd_columns),
+ .r(r),
+ .g(g),
+ .b(b),
+ .i(i),
+ .csync(csync)
+ );
+
+ /////////////////////////////////////
+ // The CPU Z80A
+ /////////////////////////////////////
+ tv80n cpu (
+ // Outputs
+ .m1_n(),
+ .mreq_n(mreq_n),
+ .iorq_n(iorq_n),
+ .rd_n(rd_n),
+ .wr_n(wr_n),
+ .rfsh_n(rfsh_n),
+ .halt_n(),
+ .busak_n(),
+ .A(a),
+ .dout(cpudout),
+ // Inputs
+ .reset_n(!reset),
+ .clk(clkcpu),
+ .wait_n(1'b1),
+ .int_n(int_n),
+ .nmi_n(1'b1),
+ .busrq_n(1'b1),
+ .di(cpudin)
+ );
+
+// T80s cpu (
+// // Outputs
+// .M1_n(),
+// .MREQ_n(mreq_n),
+// .IORQ_n(iorq_n),
+// .RD_n(rd_n),
+// .WR_n(wr_n),
+// .RFSH_n(rfsh_n),
+// .HALT_n(),
+// .BUSAK_n(),
+// .A(a),
+// .DO(cpudout),
+// // Inputs
+// .RESET_n(!reset),
+// .CLK_n(clkcpu),
+// .WAIT_n(1'b1),
+// .INT_n(int_n),
+// .NMI_n(1'b1),
+// .BUSRQ_n(1'b1),
+// .DI(cpudin)
+// );
+
+ /////////////////////////////////////
+ // Connecting all togther
+ /////////////////////////////////////
+ assign sramdin = cpudout;
+ assign uladin = cpudout;
+ assign cpudin = (rom_cs)? romdout :
+ (ula_cs | vram_cs | port255_cs)? uladout :
+ (sram_cs)? sramdout :
+ 8'hFF;
+
+ /////////////////////////////////////
+ // Diagnostics
+ /////////////////////////////////////
+ reg [7:0] rLeds = 8'b10000000;
+ assign leds = rLeds;
+ reg [1:0] cntleds = 2'b00;
+ always @(posedge int_n) begin
+ cntleds <= cntleds + 1;
+ if (cntleds == 2'b11) begin
+ rLeds <= { rLeds[0], rLeds[7:1] };
+ end
+ end
+
+endmodule
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.v (revision 8)
@@ -0,0 +1,158 @@
+/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
+* related to, arising under or in connection with these *
+* materials, including for any direct, or any indirect, *
+* special, incidental, or consequential loss or damage *
+* (including loss of data, profits, goodwill, or any type of *
+* loss or damage suffered as a result of any action brought *
+* by a third party) even if such damage or loss was *
+* reasonably foreseeable or Xilinx had been advised of the *
+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
+* systems, Class III medical devices, nuclear facilities, *
+* applications related to the deployment of airbags, or any *
+* other applications that could lead to death, personal *
+* injury, or severe property or environmental damage *
+* (individually and collectively, "Critical *
+* Applications"). Customer assumes the sole risk and *
+* liability of any use of Xilinx products in Critical *
+* Applications, subject only to applicable laws and *
+* regulations governing limitations on product liability. *
+* *
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
+* PART OF THIS FILE AT ALL TIMES. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file rom.v when simulating
+// the core, rom. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module rom(
+ clka,
+ ena,
+ addra,
+ douta);
+
+
+input clka;
+input ena;
+input [13 : 0] addra;
+output [7 : 0] douta;
+
+// synthesis translate_off
+
+ BLK_MEM_GEN_V4_3 #(
+ .C_ADDRA_WIDTH(14),
+ .C_ADDRB_WIDTH(14),
+ .C_ALGORITHM(1),
+ .C_BYTE_SIZE(9),
+ .C_COMMON_CLK(0),
+ .C_DEFAULT_DATA("0"),
+ .C_DISABLE_WARN_BHV_COLL(0),
+ .C_DISABLE_WARN_BHV_RANGE(0),
+ .C_FAMILY("spartan3"),
+ .C_HAS_ENA(1),
+ .C_HAS_ENB(0),
+ .C_HAS_INJECTERR(0),
+ .C_HAS_MEM_OUTPUT_REGS_A(0),
+ .C_HAS_MEM_OUTPUT_REGS_B(0),
+ .C_HAS_MUX_OUTPUT_REGS_A(0),
+ .C_HAS_MUX_OUTPUT_REGS_B(0),
+ .C_HAS_REGCEA(0),
+ .C_HAS_REGCEB(0),
+ .C_HAS_RSTA(0),
+ .C_HAS_RSTB(0),
+ .C_HAS_SOFTECC_INPUT_REGS_A(0),
+ .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+ .C_INITA_VAL("0"),
+ .C_INITB_VAL("0"),
+ .C_INIT_FILE_NAME("rom.mif"),
+ .C_LOAD_INIT_FILE(1),
+ .C_MEM_TYPE(3),
+ .C_MUX_PIPELINE_STAGES(0),
+ .C_PRIM_TYPE(1),
+ .C_READ_DEPTH_A(16384),
+ .C_READ_DEPTH_B(16384),
+ .C_READ_WIDTH_A(8),
+ .C_READ_WIDTH_B(8),
+ .C_RSTRAM_A(0),
+ .C_RSTRAM_B(0),
+ .C_RST_PRIORITY_A("CE"),
+ .C_RST_PRIORITY_B("CE"),
+ .C_RST_TYPE("SYNC"),
+ .C_SIM_COLLISION_CHECK("ALL"),
+ .C_USE_BYTE_WEA(0),
+ .C_USE_BYTE_WEB(0),
+ .C_USE_DEFAULT_DATA(0),
+ .C_USE_ECC(0),
+ .C_USE_SOFTECC(0),
+ .C_WEA_WIDTH(1),
+ .C_WEB_WIDTH(1),
+ .C_WRITE_DEPTH_A(16384),
+ .C_WRITE_DEPTH_B(16384),
+ .C_WRITE_MODE_A("WRITE_FIRST"),
+ .C_WRITE_MODE_B("WRITE_FIRST"),
+ .C_WRITE_WIDTH_A(8),
+ .C_WRITE_WIDTH_B(8),
+ .C_XDEVICEFAMILY("spartan3"))
+ inst (
+ .CLKA(clka),
+ .ENA(ena),
+ .ADDRA(addra),
+ .DOUTA(douta),
+ .RSTA(),
+ .REGCEA(),
+ .WEA(),
+ .DINA(),
+ .CLKB(),
+ .RSTB(),
+ .ENB(),
+ .REGCEB(),
+ .WEB(),
+ .ADDRB(),
+ .DINB(),
+ .DOUTB(),
+ .INJECTSBITERR(),
+ .INJECTDBITERR(),
+ .SBITERR(),
+ .DBITERR(),
+ .RDADDRECC());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of rom is "black_box"
+
+endmodule
+
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80_reg.v
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80_reg.v (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/tv80_reg.v (revision 8)
@@ -0,0 +1,77 @@
+//
+// TV80 8-Bit Microprocessor Core
+// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
+//
+// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+module tv80_reg (/*AUTOARG*/
+ // Outputs
+ DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
+ // Inputs
+ AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
+ );
+ input [2:0] AddrC;
+ output [7:0] DOBH;
+ input [2:0] AddrA;
+ input [2:0] AddrB;
+ input [7:0] DIH;
+ output [7:0] DOAL;
+ output [7:0] DOCL;
+ input [7:0] DIL;
+ output [7:0] DOBL;
+ output [7:0] DOCH;
+ output [7:0] DOAH;
+ input clk, CEN, WEH, WEL;
+
+ reg [7:0] RegsH [0:7];
+ reg [7:0] RegsL [0:7];
+
+ always @(posedge clk)
+ begin
+ if (CEN)
+ begin
+ if (WEH) RegsH[AddrA] <= DIH;
+ if (WEL) RegsL[AddrA] <= DIL;
+ end
+ end
+
+ assign DOAH = RegsH[AddrA];
+ assign DOAL = RegsL[AddrA];
+ assign DOBH = RegsH[AddrB];
+ assign DOBL = RegsL[AddrB];
+ assign DOCH = RegsH[AddrC];
+ assign DOCL = RegsL[AddrC];
+
+ // break out ram bits for waveform debug
+// synopsys translate_off
+ wire [7:0] B = RegsH[0];
+ wire [7:0] C = RegsL[0];
+ wire [7:0] D = RegsH[1];
+ wire [7:0] E = RegsL[1];
+ wire [7:0] H = RegsH[2];
+ wire [7:0] L = RegsL[2];
+
+ wire [15:0] IX = { RegsH[3], RegsL[3] };
+ wire [15:0] IY = { RegsH[7], RegsL[7] };
+// synopsys translate_on
+
+endmodule
+
Index: zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.ngc
===================================================================
--- zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.ngc (nonexistent)
+++ zx_ula/branches/xilinx/spectrum_48k_for_digilent_spartan3_starter_kit/rom.ngc (revision 8)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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