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/* $Id: aeMB2_edk62.v,v 1.2 2008-04-20 16:34:32 sybreon Exp $
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/* $Id: aeMB2_edk62.v,v 1.3 2008-04-21 12:11:38 sybreon Exp $
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**
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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**
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** This file is part of AEMB.
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** This file is part of AEMB.
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module aeMB2_edk62 (/*AUTOARG*/
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module aeMB2_edk62 (/*AUTOARG*/
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// Outputs
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// Outputs
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xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
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xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
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xwb_adr_o, iwb_wre_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o, iwb_adr_o,
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xwb_adr_o, iwb_wre_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o, iwb_adr_o,
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ich_stb, dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_cyc_o,
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dwb_cyc_o, dwb_adr_o,
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dwb_adr_o,
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// Inputs
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// Inputs
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_ena_i, sys_clk_i, iwb_dat_i,
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iwb_ack_i, dwb_dat_i, dwb_ack_i, alu_c
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iwb_ack_i, dwb_dat_i, dwb_ack_i
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);
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);
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_DWB = 32; ///< DATA bus width
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parameter AEMB_DWB = 32; ///< DATA bus width
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parameter AEMB_XWB = 3; ///< XSEL bus width
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parameter AEMB_XWB = 3; ///< XSEL bus width
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output [31:0] dwb_dat_o; // From memif0 of aeMB2_memif.v
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output [31:0] dwb_dat_o; // From memif0 of aeMB2_memif.v
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output [3:0] dwb_sel_o; // From memif0 of aeMB2_memif.v
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output [3:0] dwb_sel_o; // From memif0 of aeMB2_memif.v
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output dwb_stb_o; // From memif0 of aeMB2_memif.v
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output dwb_stb_o; // From memif0 of aeMB2_memif.v
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output dwb_tag_o; // From memif0 of aeMB2_memif.v
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output dwb_tag_o; // From memif0 of aeMB2_memif.v
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output dwb_wre_o; // From memif0 of aeMB2_memif.v
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output dwb_wre_o; // From memif0 of aeMB2_memif.v
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output ich_stb; // From iwbif0 of aeMB2_iwbif.v
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output [AEMB_IWB-1:2] iwb_adr_o; // From iwbif0 of aeMB2_iwbif.v
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output [AEMB_IWB-1:2] iwb_adr_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_cyc_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_cyc_o; // From iwbif0 of aeMB2_iwbif.v
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output [3:0] iwb_sel_o; // From iwbif0 of aeMB2_iwbif.v
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output [3:0] iwb_sel_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_stb_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_stb_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_wre_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_wre_o; // From iwbif0 of aeMB2_iwbif.v
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output xwb_tag_o; // From memif0 of aeMB2_memif.v
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output xwb_tag_o; // From memif0 of aeMB2_memif.v
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output xwb_wre_o; // From memif0 of aeMB2_memif.v
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output xwb_wre_o; // From memif0 of aeMB2_memif.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input alu_c; // To regs0 of aeMB2_regs.v
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input dwb_ack_i; // To memif0 of aeMB2_memif.v
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input dwb_ack_i; // To memif0 of aeMB2_memif.v
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input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v
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input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v
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input iwb_ack_i; // To pip0 of aeMB2_pipe.v, ...
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input iwb_ack_i; // To pip0 of aeMB2_pipe.v, ...
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input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ...
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input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ...
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input sys_clk_i; // To pip0 of aeMB2_pipe.v
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input sys_clk_i; // To pip0 of aeMB2_pipe.v
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_wre_o (iwb_wre_o),
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.iwb_wre_o (iwb_wre_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_cyc_o (iwb_cyc_o),
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.ich_stb (ich_stb),
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.fet_fb (fet_fb),
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.fet_fb (fet_fb),
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.rpc_if (rpc_if[31:2]),
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.rpc_if (rpc_if[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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// Inputs
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// Inputs
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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// Outputs
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// Outputs
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.opa_if (opa_if[31:0]),
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.opa_if (opa_if[31:0]),
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.opb_if (opb_if[31:0]),
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.opb_if (opb_if[31:0]),
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.opd_if (opd_if[31:0]),
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.opd_if (opd_if[31:0]),
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// Inputs
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// Inputs
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.alu_c (alu_c),
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.alu_mx (alu_mx[31:0]),
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.alu_mx (alu_mx[31:0]),
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.bsf_mx (bsf_mx[31:0]),
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.bsf_mx (bsf_mx[31:0]),
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.dena (dena),
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.dena (dena),
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.dwb_mx (dwb_mx[31:0]),
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.dwb_mx (dwb_mx[31:0]),
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.gclk (gclk),
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.gclk (gclk),
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.gpha (gpha),
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.gpha (gpha),
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.grst (grst),
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.grst (grst),
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.ich_dat (ich_dat[31:0]),
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.ich_dat (ich_dat[31:0]),
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.imm_of (imm_of[15:0]),
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.mul_mx (mul_mx[31:0]),
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.mul_mx (mul_mx[31:0]),
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.mux_ex (mux_ex[2:0]),
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.mux_ex (mux_ex[2:0]),
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.mux_of (mux_of[2:0]),
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.mux_of (mux_of[2:0]),
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.opa_of (opa_of[31:0]),
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.opc_of (opc_of[5:0]),
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.ra_of (ra_of[4:0]),
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.rd_ex (rd_ex[4:0]),
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.rd_ex (rd_ex[4:0]),
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.rd_of (rd_of[4:0]),
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.rd_of (rd_of[4:0]),
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.rpc_if (rpc_if[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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.sel_mx (sel_mx[3:0]),
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.sel_mx (sel_mx[3:0]),
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.sfr_mx (sfr_mx[31:0]),
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.sfr_mx (sfr_mx[31:0]),
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.xwb_mx (xwb_mx[31:0]));
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.xwb_mx (xwb_mx[31:0]));
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endmodule // aeMB2_edk62
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endmodule // aeMB2_edk62
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2008/04/20 16:34:32 sybreon
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// Basic version with some features left out.
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//
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// Revision 1.1 2008/04/18 00:21:52 sybreon
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// Revision 1.1 2008/04/18 00:21:52 sybreon
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// Initial import.
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// Initial import.
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//
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//
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No newline at end of file
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No newline at end of file
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