Line 1... |
Line 1... |
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// AltOR32
|
// AltOR32
|
// Alternative Lightweight OpenRisc
|
// Alternative Lightweight OpenRisc
|
// V2.0
|
// V2.1
|
// Ultra-Embedded.com
|
// Ultra-Embedded.com
|
// Copyright 2011 - 2013
|
// Copyright 2011 - 2014
|
//
|
//
|
// Email: admin@ultra-embedded.com
|
// Email: admin@ultra-embedded.com
|
//
|
//
|
// License: LGPL
|
// License: LGPL
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
Line 46... |
Line 46... |
`define ALU_ADDC 4'b0101
|
`define ALU_ADDC 4'b0101
|
`define ALU_SUB 4'b0110
|
`define ALU_SUB 4'b0110
|
`define ALU_AND 4'b0111
|
`define ALU_AND 4'b0111
|
`define ALU_OR 4'b1000
|
`define ALU_OR 4'b1000
|
`define ALU_XOR 4'b1001
|
`define ALU_XOR 4'b1001
|
|
`define ALU_COMPARE 4'b1010
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// ALU Instructions
|
// ALU Instructions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`define INST_OR32_ALU 8'h38
|
`define INST_OR32_ALU 8'h38
|
Line 104... |
Line 105... |
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Set Flag Instructions
|
// Set Flag Instructions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`define INST_OR32_SFXX 8'h39
|
`define INST_OR32_SFXX 8'h39
|
`define INST_OR32_SFXXI 8'h2F
|
`define INST_OR32_SFXXI 8'h2F
|
`define INST_OR32_SFEQ 16'h0720
|
`define INST_OR32_SFMASK 16'hFD3F
|
`define INST_OR32_SFEQI 16'h05E0
|
`define INST_OR32_SFEQ 16'h0520
|
`define INST_OR32_SFGES 16'h072B
|
`define INST_OR32_SFGES 16'h052B
|
`define INST_OR32_SFGESI 16'h05EB
|
`define INST_OR32_SFGEU 16'h0523
|
`define INST_OR32_SFGEU 16'h0723
|
`define INST_OR32_SFGTS 16'h052A
|
`define INST_OR32_SFGEUI 16'h05E3
|
`define INST_OR32_SFGTU 16'h0522
|
`define INST_OR32_SFGTS 16'h072A
|
`define INST_OR32_SFLES 16'h052D
|
`define INST_OR32_SFGTSI 16'h05EA
|
`define INST_OR32_SFLEU 16'h0525
|
`define INST_OR32_SFGTU 16'h0722
|
`define INST_OR32_SFLTS 16'h052C
|
`define INST_OR32_SFGTUI 16'h05E2
|
`define INST_OR32_SFLTU 16'h0524
|
`define INST_OR32_SFLES 16'h072D
|
`define INST_OR32_SFNE 16'h0521
|
`define INST_OR32_SFLESI 16'h05ED
|
|
`define INST_OR32_SFLEU 16'h0725
|
|
`define INST_OR32_SFLEUI 16'h05E5
|
|
`define INST_OR32_SFLTS 16'h072C
|
|
`define INST_OR32_SFLTSI 16'h05EC
|
|
`define INST_OR32_SFLTU 16'h0724
|
|
`define INST_OR32_SFLTUI 16'h05E4
|
|
`define INST_OR32_SFNE 16'h0721
|
|
`define INST_OR32_SFNEI 16'h05E1
|
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Misc Instructions
|
// Misc Instructions
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`define INST_OR32_MISC 8'h08
|
`define INST_OR32_MISC 8'h08
|
`define INST_OR32_SYS 8'h20
|
`define INST_OR32_SYS 8'h20
|
`define INST_OR32_TRAP 8'h21
|
`define INST_OR32_TRAP 8'h21
|
|
`define INST_OR32_CUST1 8'h1C
|
|
|
`define INST_OR32_BUBBLE 8'h3F
|
`define INST_OR32_BUBBLE 8'h3F
|
`define OPCODE_INST_BUBBLE 32'hFC000000
|
`define OPCODE_INST_BUBBLE 32'hFC000000
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|