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https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
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All notable changes to this project will be documented in this file.
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All notable changes to this project will be documented in this file.
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##[1.5.1] - 3-2-2017
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## changed
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- src_c/jtag_main.c: variable length memory support is added.
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- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
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-ssa: Now can work with fully adaptive routing.
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##[1.5.0] - 13-10-2016
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##[1.5.0] - 13-10-2016
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### Added
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### Added
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- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
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- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
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- NoC emulator.
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- NoC emulator.
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- Altor processor.
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- Altor processor.
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