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https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
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All notable changes to this project will be documented in this file.
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All notable changes to this project will be documented in this file.
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##[2.0.0] -15-10-2020
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## added
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- SMART, single cycle multi hop bypass
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- Selfloop suport
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- gui for UART terminal
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- gui for runtime memory controler
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- Suport Xilinx FPFAs
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- Software Auto-generation using CAL language (CAL2C)
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- Suport multitreading in Verilator-based NoC simulator
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- Intigrated netrace to NoC simulator
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- add new topologies: Fmesh
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- gui for custom noc topology generation
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- GTK3 support
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## changed
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- NoC codes are changing to systemVerilog. Now it uses struct for router connection interface.
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##[1.9.1] -24-07-2019
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##[1.9.1] -24-07-2019
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## changed
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## changed
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- Some bugs are fixed in jtag interface & mpsoc custom parameter setting.
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- Some bugs are fixed in jtag interface.
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##[1.9.0] -30-04-2019
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##[1.9.0] -30-04-2019
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## Added
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## Added
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- add single flit sized packet support
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- add single flit sized packet support
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- add new topologies: Fattree, tree, concentrated mesh (Cmesh)
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- add new topologies: Fattree, tree, concentrated mesh (Cmesh)
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##[1.7.0] - 15-7-2017
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##[1.7.0] - 15-7-2017
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## Added
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## Added
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- Software compilation text-editor
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- Software compilation text-editor
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- Processing tile Diagram Viewer
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- Processing tile Diagram Viewer
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- Modelsim/Verilator/QuartusII GUI compilation assist
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- Modelsim/Verilator/QuartusII GUI compilation assist
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- Multi-channel DMA
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- Multi-chanel DMA
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## changed
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## changed
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- New multi-channel DMA-based NI
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- New multi-chanel DMA-based NI
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##[1.6.0] - 6-3-2017
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##[1.6.0] - 6-3-2017
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## Added
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## Added
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- NoC GUI simulator (using Verilator)
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- NoC GUI simulator (using Verilator)
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