Line 33... |
Line 33... |
You should have received a copy of the GNU Lesser General
|
You should have received a copy of the GNU Lesser General
|
Public License along with this source; if not, download it
|
Public License along with this source; if not, download it
|
from http://www.opencores.org/lgpl.shtml.
|
from http://www.opencores.org/lgpl.shtml.
|
*/
|
*/
|
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
|
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
|
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;
|
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
|
--/* synthesis translate_off */
|
/* synthesis translate_off */
|
--library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
|
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
|
--/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
entity user is port(
|
entity user is port(
|
/* Comment-out for simulation. */
|
/* Comment-out for simulation. */
|
-- clk,reset:in std_ulogic;
|
-- clk,reset:in std_ulogic;
|
|
|
Line 73... |
Line 73... |
|
|
signal irq_write:std_ulogic; -- clock gating.
|
signal irq_write:std_ulogic; -- clock gating.
|
|
|
begin
|
begin
|
/* pipelines. */
|
/* pipelines. */
|
process(reset,clk) is begin
|
process(clk) is begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
next_readRequest<=readRequest;
|
next_readRequest<=readRequest;
|
next_writeRequest<=writeRequest;
|
next_writeRequest<=writeRequest;
|
next_readResponse<=readResponse;
|
next_readResponse<=readResponse;
|
next_writeResponse<=writeResponse;
|
next_writeResponse<=writeResponse;
|
Line 99... |
Line 99... |
|
|
symbolsPerTransfer=>symbolsPerTransfer,
|
symbolsPerTransfer=>symbolsPerTransfer,
|
outstandingTransactions=>outstandingTransactions
|
outstandingTransactions=>outstandingTransactions
|
);
|
);
|
|
|
|
/* Interrupt-request generator. */
|
|
irq_write<=clk when not reset else '0';
|
|
|
/* Simulation Tester. */
|
/* Simulation Tester. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
clk<=not clk after 10 ps;
|
clk<=not clk after 10 ps;
|
process is begin
|
process is begin
|
reset<='0'; wait for 1 ps;
|
reset<='0'; wait for 1 ps;
|
reset<='1'; wait for 500 ps;
|
reset<='1'; wait for 500 ps;
|
reset<='0';
|
reset<='0';
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
|
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
/* Hardware tester. */
|
/* Hardware tester. */
|
|
|
/* Interrupt-request generator. */
|
|
irq_write<=clk when not reset;
|
|
|
|
/* Stimuli sequencer. */
|
/* Stimuli sequencer. */
|
|
axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
|
|
|
sequencer: process(reset,irq_write) is
|
sequencer: process(reset,irq_write) is
|
/* Local procedures to map BFM signals with the package procedure. */
|
/* Local procedures to map BFM signals with the package procedure. */
|
procedure read(address:in t_addr) is begin
|
procedure read(address:in t_addr) is begin
|
read(readRequest,address);
|
read(readRequest,address);
|
end procedure read;
|
end procedure read;
|
|
|
procedure write(data:in t_msg) is begin
|
procedure write(data:in t_msg) is begin
|
write(request=>writeRequest, address=>(others=>'-'), data=>data);
|
write(request=>writeRequest, address=>(others=>'-'), data=>data);
|
end procedure write;
|
end procedure write;
|
|
|
-- procedure writeStream(
|
|
-- data:in t_msg
|
|
-- ) is begin
|
|
-- writeStream(writeRequest,data);
|
|
-- end procedure writeStream;
|
|
|
|
variable isPktError:boolean;
|
variable isPktError:boolean;
|
|
|
/* Simulation-only randomisation. */
|
/* Simulation-only randomisation. */
|
variable seed0,seed1:positive:=1;
|
variable rv0,rv1:RandomPType;
|
variable rand0:real;
|
-- variable seed0,seed1:positive:=1;
|
|
-- variable rand0:real;
|
|
|
begin
|
begin
|
if reset then
|
if reset then
|
seed0:=1; seed1:=1;
|
-- seed0:=1; seed1:=1;
|
|
-- uniform(seed0,seed1,rand0);
|
uniform(seed0,seed1,rand0);
|
--
|
symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
|
-- symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
|
|
|
|
rv0.InitSeed(rv0'instance_name);
|
|
rv1.InitSeed(rv1'instance_name);
|
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
elsif falling_edge(irq_write) then
|
elsif falling_edge(irq_write) then
|
if outstandingTransactions>0 then
|
if outstandingTransactions>0 then
|
uniform(seed0,seed1,rand0);
|
-- uniform(seed0,seed1,rand0);
|
write(to_unsigned(integer(rand0 * 2.0**31),64));
|
-- write(to_signed(integer(rand0 * 2.0**31),64));
|
|
|
|
write(rv1.RandSigned(axiMaster_out.tData'length));
|
else
|
else
|
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
|
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
|
--symbolsPerTransfer<=(others=>'0');
|
--symbolsPerTransfer<=(others=>'0');
|
|
|
/* Testcase 2: number of symbols per transfer is randomised. */
|
/* Testcase 2: number of symbols per transfer is randomised. */
|
uniform(seed0,seed1,rand0);
|
-- uniform(seed0,seed1,rand0);
|
symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
|
-- symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
|
report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
|
-- report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
|
|
|
|
/* Truncate symbolsPerTransfer to 8 bits, so that it uses a "small" value for simulation. */
|
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sequencer;
|
end process sequencer;
|
end architecture rtl;
|
end architecture rtl;
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|