Line 52... |
Line 52... |
wire [31:0] trig_data = trig_cond[31:0];
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wire [31:0] trig_data = trig_cond[31:0];
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reg trig_cond_ok,trig_cond_ok_d1;
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reg trig_cond_ok,trig_cond_ok_d1;
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// for capture storage
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// for capture storage
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wire [49:0] capture_in;
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wire [49:0] capture_in;
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wire capture_wr;
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wire capture_wr;
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// for pretrigger capture
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wire [9:0] pretrig_num;
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reg [9:0] pretrig_cnt;
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wire pretrig_full;
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wire pretrig_wr;
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reg pretrig_wr_d1,pretrig_rd;
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Capture logic main
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// Capture logic main
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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Line 116... |
Line 122... |
end
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end
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// trigger gate kept open until trigger stoped
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// trigger gate kept open until trigger stoped
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end
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end
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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// generate capture wr-in
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// generate capture wr_in
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
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assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
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// generate pre-trigger wr_in
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assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
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assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
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always @(posedge clk)
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begin
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if (!trig_en || (trig_en && !trig_set)) begin
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pretrig_cnt <= 10'd0;
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pretrig_wr_d1<= 1'b0;
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pretrig_rd <= 1'b0;
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end
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else if (!pretrig_full) begin
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pretrig_cnt <= pretrig_cnt + addr_mask_ok;
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pretrig_wr_d1<= 1'b0;
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pretrig_rd <= 1'b0;
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end
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else if (pretrig_full) begin
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pretrig_cnt <= pretrig_cnt;
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pretrig_wr_d1<= pretrig_wr;
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pretrig_rd <= pretrig_wr_d1;
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end
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end
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Instantiate vendor specific JTAG functions
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// Instantiate vendor specific JTAG functions
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// index 0, instantiate capture fifo, as output
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// index 0, instantiate capture fifo, as output
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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.clk(clk),
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.clk(clk),
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.wr_en(capture_wr),
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.wr_in(capture_wr || pretrig_wr),
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.data_in(capture_in)
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.data_in(capture_in),
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.rd_in(pretrig_rd)
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);
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);
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defparam
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defparam
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u_virtual_jtag_adda_fifo.data_width = 50,
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u_virtual_jtag_adda_fifo.data_width = 50,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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Line 165... |
Line 194... |
u_virtual_jtag_addr_mask.mask_enabl = 4,
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u_virtual_jtag_addr_mask.mask_enabl = 4,
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u_virtual_jtag_addr_mask.addr_width = 32;
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u_virtual_jtag_addr_mask.addr_width = 32;
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|
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// index 2, instantiate capture trigger, as input
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// index 2, instantiate capture trigger, as input
|
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
.trig_out(trig_cond)
|
.trig_out(trig_cond),
|
|
.pnum_out(pretrig_num)
|
);
|
);
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defparam
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defparam
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u_virtual_jtag_adda_trig.trig_width = 56;
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u_virtual_jtag_adda_trig.trig_width = 56,
|
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u_virtual_jtag_adda_trig.pnum_width = 10;
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|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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