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## Generated SDC file "fpmult.sdc"
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#************************************************************
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# THIS IS A WIZARD-GENERATED FILE.
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#
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# Version 10.1 Build 153 11/29/2010 SJ Web Edition
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#
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#************************************************************
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## Copyright (C) 1991-2010 Altera Corporation
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# Copyright (C) 1991-2010 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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# Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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# and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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# functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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# (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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# associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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# to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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# Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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# Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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# without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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# programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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# Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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# applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 10.1 Build 153 11/29/2010 SJ Web Edition"
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## DATE "Sun Jan 30 18:51:15 2011"
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# Clock constraints
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##
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create_clock -name "clk" -period 50.000ns [get_ports {clk}] -waveform {0.000 25.000}
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## DEVICE "EP2C20F484C7"
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##
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#**************************************************************
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# Automatically constrain PLL and other generated clocks
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# Time Information
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derive_pll_clocks -create_base_clocks
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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# Automatically calculate clock uncertainty to jitter and other effects.
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#derive_clock_uncertainty
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# Not supported for family Cyclone II
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# tsu/th constraints
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# tco constraints
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#**************************************************************
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set_output_delay -clock "clk" -max 40ns [get_ports {q.a q.b}]
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# Create Clock
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#**************************************************************
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create_clock -name {altera_reserved_tck} -period 20.000 -waveform { 0.000 10.000 } [get_ports { altera_reserved_tck }]
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# tpd constraints
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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